JP2007536629A - High-throughput images for processing inspection images - Google Patents

Abstract

【Task】
An image processing system for analyzing an image of a sample to determine whether the sample contains a defect is disclosed. The system receives a plurality of processors (202, 306) that receive image data from the sample and analyze one or more selected patches (s) of such image data to determine whether the sample has a defect. )including. System further bind together the processor, as a specification, includes a plurality of buses (206,450) having a per second 50 gigabits or more data rates and about 10 ^-16 less than the error rate. In one example, the bus is a low voltage differential signal bus, and in another embodiment, the bus is a hyper transport bus.
[Selection] Figure 3

Description

  The present invention relates to the field of semiconductor inspection, and more particularly to a technique for processing inspection images and the like.

  In general, the semiconductor manufacturing industry is involved in very complex techniques for manufacturing integrated circuits using semiconductor materials that are stacked and patterned on a substrate such as silicon. Due to the large scale of circuit integration and the reduced size of semiconductor devices, devices need to be free of defects prior to shipping the device to the end user or customer. Thus, the produced device or wafer needs to be inspected for defects. In addition, the reticle used to manufacture the wafer also needs to be inspected for defects.

  A reticle or photomask is an optical element that includes transparent and opaque regions, translucent regions, and phase shift regions that together define a pattern of coplanar features in an electronic device such as an integrated circuit. The reticle is used during photolithography to define designated areas of a semiconductor wafer for etching, ion implantation, or other manufacturing processes. In many modern integrated circuit designs, the features of the optical reticle are about 1 to about 5 times larger than the corresponding features on the wafer. In other exposure systems (eg, X-rays, electron beams, and extreme ultraviolet), a similar range of reduction ratios applies.

  Optical reticles are typically made from a transparent medium, such as borosilicate glass or quartz plate, deposited on an opaque and / or translucent layer of chromium or other suitable material. However, other mask techniques are used for direct electron beam exposure (eg, stencil mask), X-ray exposure (eg, absorption mask), and the like. The reticle pattern may be formed by, for example, a laser or electron beam direct writing technique that is widely used in this technology.

  After manufacture of each reticle or reticle group, each reticle is typically inspected by irradiating light emitted by a controlled illuminator. An optical image of one or more portions of the reticle is constructed based on a portion of the light reflected, transmitted, or otherwise transmitted to the photosensor. Such inspection techniques and devices are well known in the art and are implemented in a variety of commercial products, including many available from KLA-Tencor Corporation of San Jose, California.

  During a conventional inspection process, an optical image of a portion of the reticle under inspection is typically compared with a corresponding reference image. Conventionally, the reference image is generated from circuit pattern data used to manufacture the reticle, or from an optical image of a neighborhood area of the reticle itself. Either way, the features of the optical image are analyzed and compared with the corresponding features of the reference image. Next, the difference between each feature is usually compared with a threshold value. If the feature of the optical image is greater than a predetermined threshold and different from the test feature, it is determined to be a defect. A similar inspection process may be used to inspect a semiconductor wafer being manufactured using multiple reticles.

  A typical inspection process mechanism may include a number of serially coupled processors. The image data is supplied to the first processor and processed. After the first processor performs one step of the analysis, the result data is provided to the second processor for the next step of the analysis. Image data may be continuously supplied to any number of processors. Usually, each different processor executes a small part of the overall analysis algorithm (s). The algorithm is typically hard coded into a separate processor.

  While some continuous processing of image data is appropriate for some applications, under certain conditions it may be too slow and / or flexible. For example, as circuit patterns and corresponding reticle patterns increase in complexity, the image data of such reticles will contain a relatively large amount of data that needs to be accurately analyzed. A normal reticle can be converted to image data of 1 million × 1 million pixels. Therefore, processing such a large amount of image data may be very burdensome.

  In addition, conventional image processing often relies on the proper functioning of all processors. That is, if a single processor fails within a continuous chain of processors, the image data may not be analyzed properly. The likelihood of failing proper analysis is particularly high when no other processor performing the function of the failed processor is present in the continuous chain of processors.

  Finally, inspection systems that include processors with fixed or hard-coded algorithms often cannot handle all possible algorithms that can be useful for image processing, even if a new set of algorithms is desirable. Cannot upgrade or change. For example, if a new algorithm is desired, it may be necessary to replace the processor with a new processor having a new set of hard-coded algorithms. This procedure requires relatively much time and / or cost.

  Therefore, there is a need for improved inspection devices and techniques. More specifically, a mechanism that processes image data more efficiently and accurately is desirable.

In one embodiment, an image processing system is disclosed that analyzes an image of a sample to determine whether the sample contains a defect. The system is a plurality of processors that receive image data from a sample, and at least in part, select one or more selected patches (s) of such image data to determine if the sample has a defect. Each including a plurality of processors for analysis. The system further includes a plurality of buses that couple the processors together, and by ^design , a plurality of buses having a data rate of about 50 gigabits per second or more and an error rate of less than about ^10-16 . In one example, the bus is a low voltage differential signal bus, and in another embodiment, the bus is a hyper transport bus.

  In certain embodiments, the processors are coupled together as a continuous chain by a bus so that the processor continuously receives the image data and analyzes one or more selected patches (s) of such image data. Yes. The processor is further operable to analyze the selected patch (s) and then output one or more result signals (group) indicating whether the sample has a defect, the result signal of each processor (Group) is output together with the image data. In a further aspect, at least one bus connects between two boards each including one or more processors.

  In another embodiment, the processors are arranged in a two-level hierarchical arrangement such that one or more processors, each as a distributor, are associated with a set of processors as analysis processors. Each distributor is operable to distribute one or more selected patch (s) to an associated set of analysis processors for analysis of such distribution patch (s). In a further aspect, at least one bus spans between two boards each containing one or more processors. In a further aspect, the processor includes a single distributor that distributes one or more image patch (s) to each of a plurality of associated four analysis processors, each of the associated four analysis processors comprising: Receive a quarter of the image data from the sample.

  In a particular embodiment, the processor distributes one or more image patch (s) to each of a plurality of four associated analysis processors for analysis of such distribution patch (s). And a second distributor that distributes one or more image patch (s) to each of a plurality of four associated analysis processors for analysis of such distribution patch (s). . Each of the eight analysis processors receives one-eighth of the image data from the sample.

  In a further embodiment, the system further includes a host for analyzing and / or displaying the defect data, each analysis processor being operable to output one or more result signal (s) to the host. The result signal (s) indicates whether the sample has a defect. In another aspect, the system generates a master clock used by the processor and a pixel clock that defines pixels in the image data relative to the angle clock of the inspection tool used to collect the image data from the sample. Includes a clock module. In certain embodiments, the image data is collected from a rotating sample and the pixel clock and synchronization signal so that the pixel resolution is changed according to the radial position of the sample to obtain a substantially constant pixel resolution along the radius. Is generated. The synchronization signal indicates the relative position of the pixel clock with respect to the master clock.

  In one embodiment, the image data corresponds to a plurality of semiconductor dies, and at least one or more processors are operable to generate a reference die based on an average of a portion of the image data dies. The same or other processor is operable to compare the reference die with other dies in the image patch (s) to determine if the sample is defective.

  In another embodiment, the invention further relates to an image processing system that analyzes an image of a sample to determine whether the sample contains a defect. The system includes a plurality of inspection signal processors that receive different sets of optical signals acquired from an inspection tool during inspection of a sample. Each test signal processor is capable of converting the received set of optical signals into digital image data and, if there is a next test signal processor, a specific time slot of the master clock that is sent to the next test signal processor The operation of outputting such image data is possible. The system further includes a distributor processor that receives the image data from the plurality of inspection signal processors and divides the image data into a plurality of image patches, and a plurality of analysis processors associated with the distributor. The distributor is further operable to distribute the selected image patch to the selected analysis processor for parallel processing to determine if the sample is defective.

In a further aspect of this alternative embodiment, the distributor receives image data from at least one inspection signal processor after all inspection signal processors have contributed to the image data. In a particular embodiment, there are 12 test signal processors and 8 analysis processors. In a further aspect, there are two test signal processors per board, the distributor and the associated analysis processor are one on a single board, and the test signal processor and distributor are specified at about 50 per second. Coupled in series with each other by a high-speed bus having a data rate greater than gigabit and an error rate of less than about ^10-16 .

  In one aspect, each of the analysis processors further outputs the image data when the image data output speed of the inspection tool is greater than the speed at which each analysis processor can process the image patch (s) distributed to it. An operation is possible to send a signal to the inspection tool indicating that the speed needs to be reduced. In another aspect, the optical signal is received in the form of an annular region of the sample. The optical signal may also be received in the form of a rectangular region of the sample.

  These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying drawings that illustrate the principles of the invention.

  Reference will now be made in detail to specific embodiments of the invention. An example of this embodiment is illustrated in the accompanying drawings. While the invention will be described in conjunction with this specific embodiment, it will be understood that it is not intended to limit the invention to one embodiment. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention.

  FIG. 1 illustrates one system approach for processing image patches in multiple parallel processors. In this approach, multiple data routers 102 and 104 are arranged hierarchically with multiple processors 106. Some embodiments of such a hierarchical system are further described in US Patent Application No. 09 / 449,022, filed November 24, 1999, "Method and Apparatus for Inspecting Reticles Performing Parallel Processing" by Goldberg et al. The

  In this embodiment, the top-level router is configured to pass only a portion of the image data stream to the subordinate routers, which in turn are configured to pass individual image patches to the individual processors. . Each processor is capable of performing inspection analysis of its own received patches, for example, by comparing dies between dies positioned in one or more patches. For example, the router 102a receives a first patch set, and the router 102b receives a second patch set. The router 102a divides the patch set into two patch sets, and passes them to the lower routers 104a and 104b. Similarly, router 102b divides its patch set into first and second patch sets that are routed to underlying routers 104c and 104d, respectively. Finally, the subordinate router 104a transmits the selected patch to the processor 106a or 106b. The lower routers 104b, 104c, and 104d also transmit the selected patch to the lower layer processor.

  This arrangement may be a mesh system where routers are coupled together in a more complex manner. For example, the upper router 102a may be configured to route the image patch set to the lower router 104c. In addition to the connections illustrated in FIG. 1, other connections may exist between the upper and lower routers and between the lower routers and the processors.

  When the router and processor are general purpose programmable routers and processors, the data stream rate becomes a problem. Currently available general purpose routers and processors cannot perform data routing and processing at a high enough speed to accommodate the inspection data output rate from the scanner or inspection tool.

  Since the entire image data stream is passed between the highest routers, the bus rate between the highest routers generally needs to be increased. The bandwidth speed between the highest and lower routers and between the lower router and the processor can be kept low because only a part of the data stream is handled. Although a high speed bus is used on a single board (eg, 110 in FIG. 1), there is currently no solution for delivering high rate data between boards. As a result of the high speed bus being limited to a single board processor, this type of hierarchical mesh image processing system is usually fixed in terms of the number of processors on a single board and cannot be easily expanded. That is, to add processing power to the system, the processing board must be completely redesigned.

  Generally speaking, the present invention provides a scalable high-speed image processing system. This scalable high-speed image processing system efficiently passes image data between a set of expandable processors at a rate that is at least as fast as the output data rate of the inspection tool. In this specification, the system of the present invention is described in relation to inspection image processing, but the system of the present invention can also be applied to processing other types of image data such as data from a measurement tool or the like.

In one embodiment of the image processing system, image data is transmitted on multiple boards using a bus that can be transmitted at a data rate that is at least as fast as the rate of image data collected and output by the inspection tool. Pass between other processors or routers. Preferably, the bus allows image data to be transmitted over a low cost, high density signal line having minimal interference characteristics. Preferably, the bus has, by design, a data rate of about 50 Gigabits per second or higher and an error rate of less than about ^10-16 . One such bus is a low voltage differential signal (LVDS) bus. Also, a hyper transport bus or any suitable low interference high speed bus type may be used. The LVDS bus typically uses two lines for each signal (eg, image pixel), each signal having a low potential, such as 0.4V between each pair of lines, for a binary value of “1”, two It is represented by 0.0V with respect to the decimal value “0”. Embodiments of the system of the present invention further include other novel features described below, which can be used alone or in conjunction with this high speed bus feature.

  FIG. 2 is a diagram showing an imaging system 200 according to the first embodiment of the present invention. As shown, the image data is received by the first processor 202a of the first board 204a. The first processor analyzes the first portion of the image data and combines the entire image data and the processing results from the first image portion with the second processor 202b on the same first board 204a. To pass. Of course, each board may include any number of processors. Next, the second processor 202b of the first board 204a processes the second portion of the image data, and the result of this processing and all the image data are combined with the first processor 202c of the second board 204b. Send to. Next, the first processor 202c of the second board 204b processes the third image portion, and sends the processing result and all the image data to the second processor 202d of the second board 204b.

  The signal passes between the processor and the processor board using a high speed bus on the backplane 206, such as LVDS, which has at least the same data rate as the image data output from the inspection tool. The last processor 202d of the last board 202b sends the results to a host 208 that is configured to store the results data in one or more databases or persistent memory devices and / or display the results data to the user. Send. Host 208 may be configured to perform further analysis on the resulting data, such as, for example, defect classification, determination of the root cause of defects, and the like. Any number of processing boards may be added or combined to an existing series of processing boards to expand the processing capabilities of the system 200.

  The processor of the arrangement of FIG. 2 can be any suitable combination of hardware and / or software for processing a patch of image data and sending the image data and result data to the next processor. In one low cost embodiment, the processor is a general purpose processor such as the 6414 processor available from Texas Instruments of Dallas, Texas. In short, the processing and bus arrangement 200 provides a high speed parallel image processing system that can be easily expanded through the use of multiple processing boards and intervening high speed buses.

  FIG. 3 is a diagram illustrating an imaging system 300 according to a second embodiment of the present invention. In general, the system 300 is a two-stage daisy chain type system that utilizes multiple processing boards with a high speed bus between the processor and the board. As shown, the system 300 may include a plurality of scanner signal processors 301 to receive scanner signals output by a scanner or inspection tool. Each scanner signal processor 301 receives a specific number of scanner signals and, as will be described further below, an image data bus or the like that is passed to the next scanner signal processor that can perform the same operation on its own scanner signal etc. The received scanner signal is output in digital form at a specific time slot of the “Daisy Chain” bus.

  The system 300 further includes one or more distributors 302 that pass the image data. Each distributor is configured to obtain a different set of image patches from the image data for processing by the selected set of lower layer servers. In other words, each distributor performs an operation of buffering and distributing a part of the image data. For example, distributor 302a obtains an image from a first half of a semiconductor wafer for processing by a first set of servers, and distributor 302b acquires wafers for processing by a second set of servers. Get the image patch from the second half.

  In the illustrated embodiment, the server associated with each distributor includes a memory 304 and two processors 306, respectively. Of course, each server may include any number of memory devices and / or processors, and the illustrated example is not intended to limit the scope of the invention. Additionally, one or more memory devices may be shared by any number of processors. In one embodiment, each server processes a portion of the image data portion obtained by the distributor and provides any suitable host, such as Ethernet, to the host 312 that has the same function as the host 308 of FIG. The result is transmitted via the interface bus. For example, each processor 306a-306d processes a quarter of the image portion acquired by distributor 302a, and each processor 306e-306h processes a quarter of the image portion acquired by distributor 302b.

  To facilitate expansion, the distributor is preferably located on the board and the boards are coupled together on the backplane as further described below. The high-speed image data is transferred between the distributor boards using a high-speed bus such as an LVDS bus. Similarly, any number and type of servers may be placed on any number of boards. The result bus does not need to be fast because it only passes result data, which is generally low bandwidth.

  FIG. 4 is a diagram illustrating the scanner signal processor 301 of FIG. 3 and a clock board 402 that provides timing signals to such processor 301 in accordance with certain embodiments of the present invention. In one embodiment of the scanner or inspection tool, the rotating scanner collects image data from the wafer in a spiral pattern. That is, the optical signals detected from the wafer are collected by rotating the wafer with respect to the optical signals sent toward the wafer. The rotary scanner can include an optical encoder and PLL electronics to generate a high frequency signal or “angle clock”. An angle clock generally provides a mechanism for determining the current position of a wafer, for example, an angle clock generates a fixed number of pulses for a particular angle of wafer rotation. The number of angular clock pulses can be counted from the beginning of the scan to obtain the current angular position of the sample or wafer. Therefore, the clock board 402 may include a counter 404 that counts angular clock pulses and outputs a count corresponding to the angular position or the angular position of the sample.

  Furthermore, it may be desirable to define the pixels in the acquired image data at a known angular position of the wafer, not necessarily the position of the optical encoder. In one embodiment, a synthesizer is used to simulate a pixel clock that defines the pixels in the image data stream, where the pixel clock pulse corresponds to a specific angular wafer position. The pixel clock cycle is output to correspond to all or part of a known number of angle clock counts. Preferably, the pixel clock is generated in consideration of the difference in angular velocity at different radial positions of the wafer. For example, as the scanner moves from the outside to the inside of the wafer, the angular spacing block 406 operates to generate a small number of pixels for each particular angle. In other words, the pixel resolution is changed according to the radial position so that a substantially constant pixel resolution is obtained with respect to the radius.

  In one embodiment, the pixel clock is not in a known phase with respect to the master clock used by the imaging system. Thus, in this example, the pixel clock is converted to an enable signal sampled at a master clock rate (eg, 100 MHz). Note that the pixel clock may not be related in phase to the angle clock or the master clock. FIG. 6 shows an example of an angle clock, a master clock, and a pixel clock. Therefore, the clock board 402 may be configured to generate a synchronization signal indicating the relationship between the pixel clock and the master clock. As shown, the clock board 402 generates a pixel clock enable and pixel clock residual phase signal (see pixel clock enable and pixel clock residual phase signal in FIG. 6) to indicate the relative position of the pixel clock with respect to the master clock. A synthesizer 406 is included. The pixel clock enable signal samples the pixel clock when it is high. However, the pixel clock enable signal is preferably delayed for at least one complete master clock cycle from the rising edge of the pixel clock. The clock residual phase signal or “delta” represents the distance from the rising edge of the pixel clock to the next rising edge of the master clock, and this delta can be changed. In this embodiment, the pixel clock enable signal is centered on the next rising edge of the master clock that occurs after the addition of a complete master clock cycle to the delta.

  To further illustrate, the processor that analyzes the pixel (of course, unless the angle clock is used as the master clock or used to generate the master clock) is the master for the pixel clock generated from the angle clock of the inspection tool. It is necessary to know the position of the clock. Accordingly, the pixel clock enable and clock residual phase signals are input to the image processing component of the example system.

  An analog to digital converter (ADC) that processes the image stream may operate to sample the image stream when a pixel clock pulse occurs. However, it is difficult to synchronize multiple ADCs used in embodiments of the present invention. To circumvent this problem, the ADC that processes the image stream is operated to sample the image stream at any suitable frequency, such as a master clock rate of 100 MHz. It then interpolates (by a field programmable gate array or FPGA) to interpolate the stream of sample pixels, corresponding to what should occur if the scanner clock (eg, angle clock) is sampled according to the pixel clock. A 12-bit digital value is generated. If a master clock different from the scanner clock is used, the interpolator needs to know the nearest master clock rising edge and residual phase error. In this embodiment, a residual phase error or delta is output as a synchronization signal to the image processing component using a 4-bit bus.

  In one embodiment, the residual phase error and the pixel enable signal move the daisy chain between each set of processors, along with image data and results. In this example, the pixels output from the scanner require slightly fewer bits on the daisy chain, so the synchronization signal is placed on unused bits. Thus, each processor knows when the rising edge of the pixel clock occurs. Of course, there is a delay between each set of processors or boards, but this delay is fixed and known to each processor. Thus, even if the ADC is operated at different speeds, a sample of the image data can be acquired at the pixel clock. For comparison, if the closest sample is obtained instead of performing interpolation, a jitter of one clock cycle is generated.

  As shown in FIG. 4, each scanner signal processor board 301 receives 10 optical channels and provides 10 pixels on the daisy chain bus. Of course, each board 301 may process any number of light channels and corresponding pixels. As shown, each channel is input to a preamplifier 410 and passes through an analog-to-digital converter (ADC) that generates a digital signal from the input channel signal. The channel signal is then processed by any suitable type of hardware and / or software, such as FPGA 414, for the next signal processor board 301 of the image data output at the master clock rate on the daisy chain bus. A bitstream results. For example, the signal processor board 301a outputs image data to a daisy chain bus to the signal processor board 301b.

  In the present invention, a complete daisy chain bus that exists between each board holds 120 pixels. In one embodiment, one frame time is secured by a set of two boards. In the illustrated example, there are 12 boards using a total of 6 frames. Each master clock cycle may be used to hold one frame, so in six cycles, the entire image data of six frames is held. Each set of boards is configured so that it knows which half cycle it will output data to the daisy chain bus. Otherwise, each set of boards simply copies the image data received from the previous set of boards in the daisy chain bus in the cycle in which the image data was received. In other words, each set of boards adds their image data to the appropriate half cycle of the daisy chain bus.

  In contrast to the synchronous pixel processing embodiments described above, conventional image processing systems operate asynchronously. Each pixel transform generates an asynchronous packet that is output to the network. This type of system requires complex network protocols and is inherently slower than the preferred embodiment of the present invention. Asynchronous pixel processing systems require network transceivers and fibers, resulting in high associated costs.

  The daisy chain is output from the last scanner signal processor (eg, 301c in FIG. 3) to the first distributor 302a. FIG. 5 is a diagram illustrating a first distributor and associated processor, according to one embodiment of the present invention. In this embodiment, the output signal includes 64 bits at 400 MHz (or four times the master clock rate), which are divided into first and second sets of 32-bit buses. The pair of FPGAs 510 and 502 can then each receive one of the 32-bit buses. Each FPGA divides the image data into four 16-bit buses and transmits each 16-bit bus to one selected from the servers 304a, b, c, and d. As each FPGA receives 32-bit image data, the image data is deserialized for processing and then serialized before outputting the data back to the daisy chain, combining the two 32-bits into 64 Use a bit bus. In other words, the FPGA may be configured to process together the entire 128-bit data received by the FPGA in a format having four consecutive 64-bit image data at 400 MHz. That is, the image data is compressed from 256 bits at 100 MHz to four consecutive 64 bits at 400 MHz. As shown in the illustrated example, the FPGA 510 has a deserializer 508, and the FPGA 504 has a deserializer 502. Similarly, the FPGA 510 has a serializer 512, and the FPGA 504 has a serializer 506.

  Of course, in addition to the FPGA, any suitable mechanism may be used to distribute the data to separate servers or processors, and in addition to 16 bits, any suitable image segmentation, Serialization techniques may be used. In this embodiment, the 64-bit daisy chain bus is divided into two 32-bit buses because each FPGA has only 64 channels (32 for input and 32 for output). Of course, if an FPGA or other component having a different number of channels is used, the daisy chain bus may be partitioned differently. In addition, the 64-bit daisy chain was used because this number of LVDS lines can be easily grouped on the board used in the system of the present invention. Any suitable daisy chain size may be used.

  Each FPGA preferably has an associated memory for storing received image data. As shown, the FPGA 510 has an associated memory 518 and the FPGA has an associated memory 520. In one embodiment, image data for one wafer revolution is buffered in memories 518 and 520. A 1 Gbyte DDR SDRAM (Double Data Rate Synchronous Dynamic RAM) works well in current applications, but any suitable memory type and size may be utilized depending on the requirements of a particular application.

  The FPGA is programmed to divide the image data into patches that are sent to each selected server. Each patch may be formed to have any suitable size and shape that can be processed by the server to determine a defect. In one example, each patch has an area that is large enough to contain all dies that can be compared in a die comparison inspection procedure. In this example, the image data for the entire wafer may be divided into four sectors or quadrants, with each patch corresponding to a single quadrant. Each quadrant or patch of data may then be handled by a single distributor with four servers, each processing one of the quadrants. Further, the image data may be further divided into eight sectors each handled by two distributors each having four servers (as in the illustrated embodiment). Image data can be divided into any suitable number of sectors. In another embodiment, the image data is simply divided into rectangular patches.

  In the four quadrant example, each FPGA (504 or 510) uses an associated memory (520 or 518) to store a 32-bit portion of the image data as it is input to the distributor. In one embodiment, image data for one rotation is stored in two memories at a time by the FPGA. Each FPGA may have any suitable number of associated memories. In general, each FPGA (504 or 510) of each distributor 301 then outputs one or more specific patches (groups) (eg, half or two quadrants of wafer image data) to the appropriate server. Operation may be possible. Thus, the distributor FPGAs may need to communicate with each other (eg, via a 32-bit bus) to access and send image data stored in each other's memory. In the illustrated embodiment, each distributor FPGA orders image data for distribution to each server. For example, the ordering table is hard-coded into each distributor FPGA (eg, by host 312).

  If there are multiple distributors, the distributor board 302 may be coupled via a daisy chain on the backplane 450. Each distributor may be coupled to a plurality of servers 304 via a plurality of multiple bit buses on the backplane 450. Examples of high-speed buses that work well are the LVDS and hypertransport buses.

  Each server may include one or more memories and one or more processors. In the example shown in FIG. 5, each server includes a common memory and two processors. In addition, each distributor may be associated with any number of servers. In the illustrated embodiment, each distributor is associated with four servers. As shown in FIG. 5, distributor 302a is coupled to servers 304a-304d. Server 302a includes memory 304a and processors 306a and 306b, server 302b includes memory 304b and processors 306c and 306d, server 302c includes memory 304c and processors 306e and 306f, and server 302d includes memory 304d and processors 306g and 306h.

  Each processor is also given a pointer to the end of the image data when stored in server memory (eg, by a distributor FPGA). In the illustrated embodiment, the image data further includes a pixel clock and coordinate data indicating the angle and radial position of each pixel, and since each frame size is known, each processor is associated with a particular wafer location in server memory. You can determine where each image data set is located and analyze the part of your image patch (if you have enough image data to analyze).

  Each processor 306 typically processes its own image patches (eg, quadrants) to determine whether such patches are defective. The results may then be output to a host 312 capable of displaying the results, for example, graphically, as a table, or visually. The result may be in any suitable form that indicates that the particular patch is defective. For example, the result may include an image of the defect and its coordinates. The host 312 (or each processor) is further configured to perform defect analysis, such as defect classification, determination of lot disposal, determination of process deviations, determination of the root cause of defects, etc. May be.

  Each processor may be programmed to send a signal back to the scanner indicating whether the receipt of the image data is too fast for the processor to analyze the image data before the server memory is overwritten. Ideally, another distributor and an additional processor are utilized to speed up the analysis procedure and keep up with the scanner. At present, the four servers work well for conventional scanners.

  The memory of each server may be sized to hold any part of the image data, such as the entire quadrant or a size smaller than the quadrant. If the server's memory can hold only a portion of each quadrant, the memory is overwritten as each data set is processed. Therefore, in this example, the processor needs to process the image data before it is overwritten, or the image data output by the inspection tool needs to be reduced below the processing speed of the server. In one embodiment, detector rows are arranged along the radius of the wafer and scanned from the outside of the wafer to the inside (or vice versa) as the wafer rotates. Thus, the image data is generated as an annular region, beginning outside the wafer radius and ending inside. In addition, a rectangular area of the image data of the wafer is generated. Regardless of how image data is collected, the server processor waits for sufficient data to be generated to perform inspection analysis (eg, die comparison). In the die comparison example, sufficient image data from the wafer is collected to include two or more dies that are compared to each other.

  Preferably, each server has enough memory to store the majority of the allocated image data. In the present example, since the server memory is 8 Gbytes or more, most of the sample quadrant of the image data can be stored. In embodiments where each server receives less than a quadrant (eg, when two distributors and eight servers are used), the memory can be made even smaller. That is, the memory size depends on how much data is divided in the server.

  In another procedure, an ideal die or “golden die” is stored in each server memory and then compared to all dies on the wafer. The golden die may be obtained in any suitable manner. For example, the scanner may be run long enough to obtain four dies (or any other suitable number of dies) that average together to form a golden die. Then, the scanner is backed up and rescanned from the beginning. Also, if the golden die is generated and distributed to all servers fast enough to allow each server processor to analyze the image data before the server memory is overwritten (or if the scanner can be decelerated first) Scanner backup is not necessary. After obtaining the golden die, each server processor compares all the dies in its respective patch with the golden die. This procedure further divides the image data among more processors (1/8 or 1/16 of the wafer per 8 or 16 processors) and can be processed more quickly. That is, there is no need for two dies in each processing patch for die comparison inspection analysis.

  Embodiments of the present invention have several advantages. For example, by using a high speed bus in two hierarchical stages, a parallel processing system provides an efficient mechanism for determining defect information inline during semiconductor manufacturing. That is, the defect can be determined quickly and the wafer can be reworked prior to performing a costly subsequent process on the same wafer. In addition, such a simplified two-stage system provides a very low cost solution.

  Although the foregoing has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Thus, the described embodiments are to be considered illustrative rather than limiting, and the invention should not be limited to the details described herein, Should be defined by all its equivalents.

FIG. 3 illustrates one system approach for processing image patches in multiple parallel processors. 1 is a diagram showing an imaging system according to a first embodiment of the present invention. It is a figure which shows the imaging system by 2nd embodiment of this invention. 4 illustrates the scanner signal processor of FIG. 3 and a clock board that provides timing signals to such a processor, in accordance with certain embodiments of the present invention. FIG. 3 illustrates a first distributor and associated processor according to one embodiment of the invention. It is a figure which displays in graphical form an example of the timing signal used and / or produced | generated in embodiment of this invention.

Claims (20)

An image processing system for analyzing an image of a sample to determine whether the sample contains a defect,
A plurality of processors for receiving image data from a sample, wherein one or more selected patches of the image data are each in at least some of the processors to determine whether the sample has a defect; With multiple processors to analyze,
A system comprising a plurality of buses coupling the processors together, the specification having a plurality of buses having a data rate of about 50 gigabits per second or more and an error rate of less than about ^10-16 . The system of claim 1, comprising:
The system, wherein the bus is a low voltage differential signal bus. The system of claim 1, comprising:
The system, wherein the bus is a hyper transport bus. The system of claim 1, comprising:
At least one of the buses is a system for connecting two boards each including one or more processors. A system according to any one of claims 1 to 4,
The processors are coupled together in a continuous chain by the bus so that the processor continuously receives the image data and analyzes one or more selected patches of the image data;
The processor may further output one or more result signals indicating whether the sample has a defect after analyzing the selected patch;
The result signal of each processor is output together with the image data. A system according to any one of claims 1 to 4,
The processors are arranged in a two-level hierarchical arrangement such that one or more processors, each as a distributor, are associated with a set of processors as analysis processors,
A system in which each distributor can distribute selected one or more patches to an associated set of analysis processors for analysis of the distributed patch. A system according to any one of claims 1 to 4,
The processor includes a single distributor that distributes one or more image patches to each of a plurality of associated four analysis processors;
Each of the four analysis processors receives a quarter of the image data from the sample. A system according to any one of claims 1 to 4,
The processor is
A first distributor that distributes one or more image patches to each of a plurality of four associated analysis processors for analysis of the one or more patches;
A second distributor that distributes one or more image patches to each of a plurality of four associated analysis processors for analysis of the one or more patches;
Each of the eight analysis processors receives one-eighth of the image data from the sample. The system according to any one of claims 6 to 8, further comprising:
A host for analyzing and / or displaying defect data;
Each analysis processor can output one or more result signals to the host, wherein the result signals indicate whether the sample has a defect. The system according to any one of claims 1 to 9, further comprising:
A clock module that generates a master clock used by the processor and a pixel clock that defines pixels in the image data relative to an angle clock of the inspection tool used to collect the image data from the sample. A system comprising: The system of claim 10, wherein
The image data is collected from a rotating sample,
The pixel clock and synchronization signal are generated such that the pixel resolution is changed according to the radial position of the sample so as to obtain a substantially constant pixel resolution along the radius of the sample;
The system, wherein the synchronization signal indicates a relative position of the pixel clock with respect to the master clock. A system according to any of claims 1 to 11, comprising
The image data corresponds to a plurality of semiconductor dies,
At least one or more of the processors may generate a reference die based on an average of a portion of the die of the image data;
A system wherein one or more identical or other processors can compare the reference die with other dies in an image patch to determine if the sample has a defect. An image processing system for analyzing an image of a sample to determine whether the sample contains a defect,
A plurality of inspection signal processors that receive different sets of optical signals obtained from an inspection tool during inspection of a sample, each inspection signal processor being capable of converting the received sets of optical signals into digital image data; and A plurality of test signal processors capable of outputting the image data in a specific time slot of a master clock sent to the next test signal processor if there is a next test signal processor;
A distributor processor that receives the image data from the plurality of inspection signal processors and divides the image data into a plurality of image patches;
A plurality of analysis processors associated with the distributor;
The distributor is further capable of distributing selected image patches to selected analysis processors for parallel processing to determine if the sample is defective. 14. The system of claim 13, wherein
The distributor receives the image data from at least one of the inspection signal processors after all of the inspection signal processors contribute to the image data. 15. A system according to claim 13 or 14,
12 test signal processors;
A system in which there are eight analysis processors. The system of claim 15, comprising:
There are two test signal processors per board,
The distributor and associated analysis processor are one single board;
The system wherein the test signal processor and the distributor are coupled together in series by a high speed bus having a data rate greater than about 50 gigabits per second and an error rate of less than about ^10-16 as specifications. The system of claim 16, comprising:
The high speed bus is a low voltage differential signal bus. A system according to any of claims 13 to 17,
Each of the analysis processors further reduces the image data output rate of the inspection tool when the image data output rate of the inspection tool is greater than the rate at which each of the analysis processors can process the distributed image patch. A system that can send a signal to the inspection tool indicating that it is needed. The system of claim 18, comprising:
The system, wherein the optical signal is received in the form of an annular region of the sample. The system of claim 18, comprising:
The system, wherein the optical signal is received in the form of a rectangular region of the sample.

Images