JP2007523439A - Memory defect detection and self-healing technology - Google Patents

Abstract

  According to some embodiments, a memory device having a plurality of storage units includes one or more spare storage units. When an electrical characteristic indicative of a defective storage unit is detected, one of the spare storage units is used to replace the defective storage unit. The detection of the defective storage unit is performed by monitoring the current, voltage and / or resistance. When the monitored electrical characteristic exceeds a predetermined threshold, the storage unit is considered defective. The defective storage unit is removed from further use. The spare storage unit is programmed to be accessible at the memory address of the removed storage unit. The exchange occurs automatically (ie, without user intervention).

Description

  The present invention relates to memory defect detection and self-repair technology.

  Flash memory provides a non-volatile fast access storage media device that first erases old data and then rewrites in the circuit. A flash memory cell is a small storage unit using, for example, a modified metal oxide semiconductor (MOS) transistor structure. The charge is stored on an insulated gate located between the selected gate and channel of the transistor. The charge on the insulated gate that is in the data state during the read operation changes the threshold voltage (Vt) of the transistor. The flash memory cell can be electrically erased.

  A flash memory block is a grouping of individually addressable flash memory cells. Due to the nature of flash memory, data is erased in blocks, which are typically between 8 kilobytes (KB) and 256 KB in size. Once data is written to a particular byte location, it is always necessary to erase the byte first when changing data, but this requires erasing the entire block in which the byte is located. In order to erase a block, an erase pulse is applied. If the block is not completely erased, the erase pulse is applied again.

  Potential manufacturing defects that cannot be sorted out may be introduced during assembly of the device. These defects can cause failures and cause shorts in the flash memory array during customer use, for example, block erase operations are not possible. Current solutions attempt to minimize these potential defect densities during the silicon processing process and during manufacturing. Because current solutions are costly, for the most part, these defects are only partially reduced.

  The invention will be better understood by reference to the accompanying drawings, and many features and advantages will become apparent to those skilled in the art.

  The use of the same reference symbols in different drawings indicates the same or similar items.

  According to some embodiments, a memory device having a plurality of storage units includes one or more spare storage units. If an electrical characteristic indicative of a defective storage unit is detected, one of the spare storage units is used for replacement with a defective storage unit. The detection of the defective storage unit is performed by monitoring the current, voltage and / or resistance. If the monitored electrical characteristic exceeds a predetermined threshold, the storage unit is considered defective. The defective storage unit is removed from further use. The spare storage unit is programmed to be accessible at the memory address of the removed storage unit. The exchange occurs automatically (ie, without user intervention).

  In the following description, numerous specific details are set forth. However, it should be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

  Indications such as “one example”, “example”, “example of implementation”, “various examples” indicate that an embodiment of the present invention includes a particular function, structure or characteristic, Indicates that it does not necessarily include a specific function, structure, or characteristic. Furthermore, repeated use of the phrase “in one embodiment” does not necessarily refer to the same embodiment.

  As used herein, unless otherwise specified, the use of adjectives indicating the order of “first”, “second”, “third”, etc. to represent a common object is a different example of similar objects. Is intended only to indicate that the subject matter is quoted, and that the subject must be in the given order, whether temporally, spatially, rated, or otherwise is not.

  Unless otherwise stated, as will be apparent from the following discussion, discussions that use terms such as “process”, “compute”, “calculate”, etc. are used throughout the specification to refer to computers, computers Related to the operation or processing of a system or similar electronic computing device, which is understood as manipulating or converting data represented as physical quantities, such as electrons, quanta, etc., to other data represented in the same way as physical quantities The

  Similarly, the term “processor” refers to any device or device that processes electronic data from any device or register and / or memory and transforms the electronic data into other electronic data that can be stored in the register and / or memory. It is about a part of. A “computer platform” may include one or more processors.

  FIG. 1 illustrates a portion of a computer system 100 in accordance with an embodiment of the present invention. The processor 102 sends commands and data to the memory system 104 via the bus 106. The memory controller 108 receives the command, stores the address indicator, forms a control signal, and performs a block erase on the block selected from the blocks 110 (1)-(N). One or more blocks of block 110 are not immediately addressable by memory controller 108. These non-addressable blocks are colloquially referred to as spare blocks. The spare memory block can be exchanged with any one of the accessible blocks 110. When a defect is detected in an accessible block, the spare block is automatically swapped with the defective block, i.e. without user intervention. Swapping is performed by changing the access addresses of the spare block and defective block, for example. The defective block becomes inaccessible, and the spare block becomes accessible at the address position of the defective block. Thus, spare blocks are used to replace defective blocks without leaving the product failed.

  According to embodiments of the present invention, block replacement occurs during use of memory system 104. In other embodiments, block replacement occurs during manufacturing tests to automate device repair.

  In addition to erasing blocks, it will be understood that there are a variety of other commands sent from the processor 102 to the memory system 104 via the bus 106, such as write data, read data, read status, etc. I will. Most of these are not part of the present invention and will continue to operate in a conventional manner in at least one embodiment. Furthermore, defect detection is performed during these other commands as well as during or instead of erasing blocks.

  The memory system 104 includes, for example, flash memory, EEPROM, EPROM, ROM, ferromagnetic digital memory, phase change memory, polymer memory, RAM, and / or the like.

  The computer system 100 includes a mainframe, minicomputer, server, workstation, personal computer, notepad, personal digital information processing terminal, one or more antennas 112 and an embedded system, to name a few examples. It is intended to represent any number of computing and communication systems including, but not limited to, various wireless communication devices.

  FIG. 2 shows a block diagram of a portion of memory system 104 in accordance with an embodiment of the present invention. The memory system 104 includes a plurality of memory blocks 202 (1)-(N), one or more spare memory blocks 204 (1)-(N), a defect detector 206, and a spare block swap. A unit 208 is included. Memory block 202 is a currently addressable block. Spare memory block 204 is not currently addressable and is in an erased state.

  The defect detector 206 monitors the memory block 202 for one or more electrical characteristics to identify the defective block. The defect detection device 206 includes circuitry 210 that tests at least one subset of the memory block 202 during operation, for example, during block erase, for example, to test the current, voltage, and / or resistance of the memory block. . For example, current is detected on the internal power supply in use during erasure of the memory block. A block erase defect is detected during an erase operation through an inherent load on the system's internal power supply, which occurs when a potential defect eventually causes a failure, but becomes a hard short. Any number of electrical property monitoring circuits may be used, but no further explanation is necessary here.

  In one embodiment of the present invention, the defect detection device 206 includes a circuit 212 or software / firmware routine for counting the number of failed erase attempts. For example, if the threshold for failed erasure attempts, eg, 4 times, is found that the block has a defect.

  When a defect is detected during an erase operation, spare block swap unit 208 automatically enables available spare block 204 and removes the defective block from further use. Both the output of the defect detector 206 and the duration of the erase operation are monitored during block erase.

  In one embodiment, the microcode automatically replaces defective blocks with unused spare blocks by programming a set of spare block non-volatile status bits (see FIG. 3).

  The defect detection device 206 and / or the spare block swap unit 208 are part of the memory controller 108. Alternatively, defect detector 206 and / or spare block swap unit 208 are software routines operating on processor 102 or memory controller 108 that are enabled by detection of a defective block.

  The last element (eg, memory block) in a series of related or similar elements (eg, memory blocks 202 [1] -202 [N], spare memory blocks 204 [1] -204 [N], etc.) 202 [N], spare memory block 204 [N], etc.) is designated more simply by using the variable symbol “N” in some examples in FIG. 2 and other figures (and “m”). Note that other variables such as "", "x", "k" are used below). The repeated use of such variable symbols is not intended to imply a correlation between the size of such a series of elements. Use of such variable symbols does not require that each series of elements has the same number of elements as other series of elements that are scoped by the same variable symbol. More precisely, in each use case, a variable identified by “N” (or “m”, “x”, “k” etc.) has the same or different value compared to other examples of the same variable name. You may hold that. For example, the memory block 202 [N] may be the tenth memory block in the series of flash memory blocks, while the spare memory block [N] is 2 of the series of spare memory blocks. It may be the second spare memory block.

  FIG. 3 illustrates a portion of a spare memory block according to an embodiment of the present invention. Spare memory block 204 [X] includes an array 302 of memory cells and a set of one or more status bits, eg, address status bit 304, usage status bit 306, and factory test pass status Contains bit 308. The status bits are programmable devices such as flash memory cells, fuses, or the like. In other embodiments, address status bits 304, usage status bits 306, and / or factory test pass status bits 308 are coupled to spare memory block 204 [X], not necessarily spare memory block 204 [ X] need not be within.

  The address status bit 304 is used to store the address of the defective memory block that is to be replaced with the defective memory block, ie, the spare memory block 204 [X]. In the case of a memory block erase defect, the address status bits 304 are automatically programmed, for example, by microcode.

  Usage status bit 306 is used to record whether spare memory block 204 [X] has been used. The usage status bit 306 indicates that the spare block swap unit 208 has swapped the defective block and spare memory block 204 [X], or that the spare block has been previously repaired, eg, during manufacturing test. Programmed to indicate that it has been used.

  Factory test pass status bit 308 is used to indicate whether spare memory block 204 [X] passed the test during manufacturing. The factory test pass status bit 308 is checked by the microcode to determine if an unused spare memory block can function before it is used to replace a defective block.

  According to one embodiment of the present invention, one or more spare blocks can be used to replace defective blocks for reasons other than block erase defects. For example, block replacement can be used for any detected short circuit or write defect.

  FIG. 4 shows a flow chart of spare block swap according to an embodiment of the present invention. An erase pulse is applied (402). A determination is made whether a defect has been detected (404). For example, current, voltage, and / or resistance test results are verified. If no defect is detected, erasure is confirmed, for example, by reading a block (406). If a defect is detected, a determination is made whether there is an available spare block (408). For example, if the usage status bit is not set, the spare block is available. If the spare block is not available, erasure is confirmed (406). If a spare block is available, a determination is made as to whether the spare block is usable (410). For example, if the factory test pass status bit is set, the spare block is usable. If the spare block is not usable, erasure is confirmed (406). If a spare block is available, the defective block is replaced (412) with a spare block, for example, by programming a spare block status bit. For example, address status bits and usage status bits may be programmed. After the block exchange, the process ends with a successful erase state (414). After confirmation of erasure (406), a determination is made as to whether erasure has failed (416). If the erase did not fail, the process ends with a successful erase state (414). If the erase fails, a determination is made as to whether the maximum number of erase pulses has been applied (418). If not, the process returns to 402 and an additional erase pulse is applied. If the maximum number of erase pulses has been applied, a determination is made as to whether a block swap has been attempted (420). If not, the process proceeds to 408. If a block exchange has already been attempted, the process ends with an erase failure condition (422).

  In another embodiment, in addition to or instead of determining whether the maximum number of erase pulses has been applied (418), a determination is made according to the erase rate measurement after a fixed erase pulse count, eg, It is determined whether the block is approaching the erased state at the expected rate.

  The operations cited herein are modules or module parts (eg, software, firmware, or hardware modules). For example, the software modules described herein include scripts, batches, or other executable files, or combinations thereof, and / or portions of such files. A software module includes a computer program or subroutine encoded on a computer readable medium.

  Furthermore, those skilled in the art will appreciate that the boundaries between modules are merely exemplary, and in other embodiments, the modules can be combined or the functions of the modules can be separated separately. For example, the modules described herein can be broken down into sub-modules that are executed as multiple computer processes. For example, decisions 408 and 410 can be combined as a single decision, for example, as to whether a usable spare block is available. Furthermore, in other embodiments, multiple examples of specific modules or sub-modules can be combined. Moreover, those skilled in the art will appreciate that the operations described in various embodiments are merely exemplary. In accordance with the present invention, the operations can be combined, or the functions of the operations can be distributed over additional operations.

  Furthermore, other embodiments include functionally equivalent processes without departing from the invention. For example, instead of determining whether a block swap has already been attempted (420), it is determined whether an available spare block is available.

  Various embodiments of the present invention may be implemented in a circuit or as a method. Embodiments of the invention are also executed as instructions stored on a machine-readable medium, which are read and executed by at least one processor to perform the functions described herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine, eg, a computer. Computer readable media may be permanently or removable or remotely coupled to system 100 or other systems. Computer readable media can be, for example, any number of of the following media: magnetic storage media including disk and tape storage media, compact disk media (eg, CD-ROM, CD-R, etc.), and digital video Optical storage media such as disk storage media, holographic memory, eg non-volatile memory storage media including semiconductor-based storage units such as flash memory, EEPROM, EPROM, ROM, ferromagnetic digital memory, phase change Volatile storage media including memory, polymer memory, registers, buffers or caches, main memory, RAM, etc., and permanent and intermittent computer networks, point-to-point communication devices, carrier transmission media, the Internet, etc. Including data transmission media , But not limited to including. Other new and various types of computer readable media may be used to store and / or transmit the software modules described herein.

  Embodiments in accordance with the present invention have been described with reference to specific examples. These examples are intended to be illustrative and not limiting. Many changes, modifications, additions and improvements are possible. Thus, multiple instances may be provided for the components described herein as a single instance. The boundaries between the various components, operations, and data stores are somewhat arbitrary, and specific operations are shown with respect to specific example configurations. Other arrangements of functionality are envisioned and are within the scope of the appended claims. Finally, structures and functions shown as separate components in various configurations can be implemented as a combined structure or component. These and other changes, modifications, additions and improvements are within the scope of the invention as defined in the appended claims.

1 illustrates a portion of a system in accordance with an embodiment of the present invention. 1 shows a block diagram of a portion of a memory system in accordance with an embodiment of the present invention. Fig. 4 shows a portion of a spare memory block according to an embodiment of the present invention. Fig. 5 shows a flow chart of spare block swap according to an embodiment of the present invention.

Claims (31)

Detecting electrical characteristics to identify defects in the storage unit;
Replacing the storage unit with a replacement storage unit, wherein the replacement is performed while a user is operating a device having the storage unit and the replacement storage unit;
A method characterized by comprising. Detecting the electrical property comprises:
Monitoring the current during the erase attempt;
Identifying the defect when the current exceeds a predetermined current threshold;
The method of claim 1 comprising: Detecting the electrical property comprises:
Monitoring the voltage during the erase attempt;
Identifying the defect when the voltage exceeds a predetermined voltage threshold;
The method of claim 1 comprising: Detecting the electrical property comprises:
Monitoring resistance during an erase attempt;
Identifying the defect when the resistance exceeds a predetermined resistance threshold;
The method of claim 1 comprising:   The method of claim 1, wherein the monitoring is performed during an erase operation. Replacing the storage unit with the alternative storage unit comprises:
Making the storage unit inaccessible by memory address;
Making the alternative storage unit accessible at the memory address;
The method of claim 1 comprising: Making the alternate storage unit accessible comprises:
The method of claim 6 including programming the alternate storage unit address status bits with the memory address.   The method of claim 7, wherein the address status bits comprise non-volatile memory.   The method of claim 7, wherein the address status bits include a programmable fuse. Making the alternate storage unit accessible comprises:
The method of claim 6 including setting a usage status bit for the alternate storage unit.   The method of claim 1, wherein the storage unit is a flash memory block.   The method of claim 1, wherein the storage unit is a row of flash memory.   The method of claim 1, wherein the storage unit is a row of polymer memory. A plurality of accessible storage units;
One or more spare storage units;
Coupled to the plurality of accessible storage units, monitoring electrical characteristics in the plurality of accessible storage units and detecting an electrical characteristic identifying a defect of one of the plurality of accessible storage units A defect detection unit formed for
A spare block swap unit coupled to the plurality of accessible storage units and the one or more spare storage units, wherein one of the plurality of accessible storage units is the one or more The spare block swap unit configured for replacement with one of the above spare storage units;
A device characterized by comprising.   The apparatus of claim 14, wherein the defect detection unit includes a current detection unit for detecting current during an erase operation.   The apparatus of claim 14, wherein the defect detection unit includes a voltage detection unit for detecting a voltage during an erase operation.   The apparatus of claim 14, wherein the defect detection unit includes a resistance detection unit for detecting resistance during an erase operation. Each of the one or more spare storage units is
Multiple memory cells;
Address status bits;
Usage status bits, and
15. The spare block swap unit is configured to program the address status bits and the usage status bits so that the plurality of memory cells are accessible. The device described. Each of the one or more spare storage units includes a plurality of memory cells;
Address status bits;
A usage status bit, and
15. The spare block swap unit is configured to program the address status bits and the usage status bits so that the plurality of memory cells are accessible. The device described. A processor;
An antenna coupled to the processor;
A memory device coupled to the processor;
The memory device comprises:
A plurality of accessible storage units;
One or more spare storage units;
Coupled to the plurality of accessible storage units, monitors electrical characteristics in the plurality of accessible storage units, and detects electrical characteristics that identify defects in one of the plurality of accessible storage units A defect detection unit formed to
A spare block swap unit coupled to the accessible storage unit and the one or more spare storage units, wherein one of the plurality of accessible storage units is the one or more The spare block swap unit configured for replacement with one of the spare storage units;
A system characterized by including.   The system of claim 20, wherein the defect detection unit includes a current detection unit for detecting a current in one of the plurality of accessible storage units during an erase operation. Each of the one or more spare storage units is
Multiple memory cells;
Address status bits;
Usage status bits, and
The spare block swap unit is configured to program the address status bits and the usage status bits so that the plurality of memory cells are accessible.
The system of claim 21. Each of the one or more spare storage units includes a plurality of memory cells, the memory device comprising:
Address status bits;
A usage status bit, and
The spare block swap unit is formed to program the address status bits and the usage status bits so that the plurality of memory cells are accessible.
21. The system of claim 20, wherein: A computer-readable medium;
Instructions stored on the computer readable medium comprising:
Detect electrical characteristics that identify defects in the storage unit;
Replacing the storage unit with a replacement storage unit, the replacement being executed while a user operates the storage unit and a device having the replacement storage unit; and
A device characterized by comprising. The instructions for detecting the electrical characteristic are:
Monitoring current and
25. The apparatus of claim 24 including instructions for identifying a defect when the current exceeds a predetermined current threshold. The instructions for detecting the electrical characteristic are:
Monitor the voltage during the erase attempt, and
The apparatus of claim 24 including instructions for identifying a defect when the voltage exceeds a predetermined voltage threshold.   The apparatus of claim 24, wherein the electrical characteristic is detected during an erase operation. The instruction to replace the storage unit with an alternative storage unit is:
Making the storage unit inaccessible at a memory address; and
25. The apparatus of claim 24, comprising instructions for making the alternate storage unit accessible at the memory address. The instructions for making the alternate storage unit accessible are:
29. The apparatus of claim 28 including instructions for programming address status bits of the alternate storage unit with the memory address. The instructions for making the alternate storage unit accessible are:
29. The apparatus of claim 28, further comprising instructions for setting usage status bits for the alternate storage unit.   25. The apparatus of claim 24, wherein the storage unit is a flash block.

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