JP2007510376A - Non-blocking and deterministic unicast packet scheduling - Google Patents

Abstract

のスピードアップとサブネットワークを有する相互接続ネットワークとを有するシステムであって、各サブネットワークは、各サブネットワークは総数少なくともｒ_１個の第１内部リンクに対する各入力ポートに接続される、少なくとも１個の第１内部リンクを備え、各サブネットワークはさらに総数少なくともｒ_２個の第２内部リンクに対する各出力ポートに接続される、少なくとも１個の第２内部リンクを備える。本システムは、決定論的な方式で、かつパケットのセグメント化および再組立を要求することなく、ｒ_１≦ｒ_２のときは、スイッチングすべき各スイッチング時間において、多くともてｒ_１回のスイッチング時間だけ、多くともｒ_１個のパケットをスケジューリングし、ｒ_２≦ｒ_１のときは、スイッチングｓｙべき各スイッチング時間において、多くともｒ_１回のスイッチング時間だけ、多くともｒ_２個のパケットをスケジューリングすることで、本発明による厳密にノンブロッキング方式で動作する。本システムはさらに、１００％スループット、処理保存的、公正に、それでいてなお決定論的に動作し、それにより出力ポートを決して輻輳させない。本システムは調停に対して１度だけの繰り返しで、相互接続ネットワークにおいて数学的に最小のスピードアップで実行する。本システムは、相互接続ネットワークにおけるパケット再順序付けの問題と、パケットの内部バッファリングが全くなく動作し、従って真にカットスルーかつ分散した方式で動作する。一実施形態において、本システムは、唯一のサブネットワークで、かつそのサブネットワークを介して２倍のスイッチングレートで、厳密にノンブロッキング方式で動作する。別の実施形態において、本システムは、相互接続ネットワークにおいて、少なくとも式（II）

のスピードアップで、再配置可能なノンブロッキング方式で動作する。入力ポートの数ｒ_１が出力ポートの数ｒ_２に等しく、ｒ_１＝ｒ_２＝ｒのとき、少なくとも式（III）

のスピードアップを有する相互接続ネットワークが、スイッチングすべき各スイッチング時間において、多くともｒ回のスイッチング時間だけ決定論的な方式で、多くともｒ個のパケットをスケジューリングすることで、本発明による厳密にノンブロッキングで決定論的方式で動作する。そして相互接続ネットワーク内におきて、少なくとも式（IV）

のスピードアップで、システムは再配置可能なノンブロッキングで決定論的方式で動作する。本システムは、入力ポートから出力ポートへのパケットに対するエンドツーエンド保証帯域幅およびレイテンシを提供する。全ての実施形態において、相互接続ネットワークは、クロスバーネットワーク、共有メモリネットワーク、クロスネットワーク、ハイパーキューブネットワーク、任意の内部ノンブロッキング相互接続ネットワークまたはネットワークのネットワークであってよい。
【選択図】図１Ｈ【Task】
The present invention provides a system for scheduling a unicast packet via the interconnect network, and r ₁ input ports each having r ₂ inputs queues, r, each having _one output queue r ₂ output ports and at least the formula (I)

And an interconnect network with sub-networks, each sub-network having at least _one sub-network connected to each input port for a total of at least r ₁ first internal links And each sub-network further comprises at least one second internal link connected to each output port for a total of at least r ₂ second internal links. The system is deterministic and does not require packet segmentation and reassembly, and when r ₁ ≦ r ₂ , at most r ₁ switching at each switching time to be switched. only time, schedules r ₁ one packet at most, when the r ₂ ≦ r _1, at each switching time should switching sy, with r ₁ times the switching time much, schedules r ₂ pieces of packets at most Thus, the operation is strictly non-blocking according to the present invention. The system further operates 100% throughput, conservatively, fairly, yet still deterministic, thereby never congesting the output port. The system runs with only one iteration for arbitration and with minimal mathematical speedup in the interconnect network. The system operates without any packet reordering issues in the interconnect network and no internal buffering of the packets, and thus operates in a truly cut-through and distributed manner. In one embodiment, the system operates in a strictly non-blocking manner with only one sub-network and twice the switching rate through that sub-network. In another embodiment, the system comprises at least formula (II) in an interconnect network

It works in a non-blocking manner that can be rearranged at a speedup of. When the number of input ports r ₁ is equal to the number of output ports r ₂ and r ₁ = r ₂ = r, at least the formula (III)

An interconnected network with a speedup of strictly schedules at most r packets at each switching time to be switched in a deterministic manner at most r switching times. It works in a non-blocking and deterministic manner. And at least the formula (IV)

With speedup, the system operates in a relocatable non-blocking, deterministic manner. The system provides end-to-end guaranteed bandwidth and latency for packets from input ports to output ports. In all embodiments, the interconnect network may be a crossbar network, a shared memory network, a cross network, a hypercube network, any internal non-blocking interconnect network, or a network of networks.
[Selection] Figure 1H

Description

This application claims and claims priority to US Provisional Patent Application No. 60 / 516,057, filed Oct. 30, 2003. This application is a related US patent application entitled "NONBLOCKING AND DETERMINISTIC UNICAST PACKET SCHEDULING" by Venkat Konda, assigned to the same applicant as the present application, and a PCT application for agent serial number V-0005. Incorporated by reference in its entirety. This application is related to US patent application Ser. No. 09 / 967,815 entitled “REARRANGEABLY NON-BLOCKING MULTICAST MULTI-STAGE NETWORKS” by Venkat Konda, filed Sep. 27, 2001, assigned to the same applicant as the present application. With regard to PCT application number PCT / US03 / 27971, filed on September 6, 2003, which is a continuation-in-part application, the entirety is incorporated by reference. This application is assigned to the same applicant as this application and is related to US patent application Ser. No. 09 / 967,106 filed Sep. 27, 2001 and entitled “STRICTLY NON-BLOCKING MULTICAST MULTI-STAGE NETWORKS” by Venkat Konda. With regard to PCT application number PCT / US03 / 27972, filed on September 6, 2003, which is a part continuation application, the entirety is incorporated by reference.

  This application includes US Provisional Patent Application No. 60 / 500,790 filed September 6, 2003 and US Patent Application No. 10 / 933,899, and PCT Application No. 04/29043 filed September 5, 2004. Is incorporated by reference in its entirety. This application is related to US Provisional Patent Application No. 60 / 500,789, filed Sep. 6, 2003, and US Patent Application No. 10 / 933,900, and PCT Application No. 04/29027, filed Sep. 5, 2004. , Incorporated by reference in its entirety.

  This application is related to US Provisional Patent Application No. 60 / 516,265, filed Oct. 30, 2003, and its US Patent Application, Attorney Docket No. V-0006, and its concurrently filed PCT application, Attorney Docket No. S. -0006 is incorporated by reference in its entirety. This application includes US Provisional Patent Application No. 60 / 516,163, filed Oct. 30, 2003, US Patent Application, Attorney Docket No. V-0009, and its concurrently filed PCT application, Attorney Docket No. S-0009. Is incorporated by reference in its entirety. This application includes US Provisional Patent Application No. 60 / 515,985, filed Oct. 30, 2003, US Patent Application, Attorney Docket No. V-0010, and its simultaneously filed PCT application, Attorney Docket No. S-0010. Is incorporated by reference in its entirety.

  Today's ATM switches and IP routers typically use a variety of interconnected networks to switch packets from an input port (also referred to as an “ingress port”) to a desired output port (also referred to as an “egress port”). To switch packets through the interconnect network, they are queued at the input or output port, or both the input and output ports. The packet may be destined for one or more output ports. A packet destined for only one output port is called a unicast packet, a packet destined for more than one output port is called a multicast packet, and a packet destined for all output ports is called a broadcast packet.

  The output queue (OQ) switch employs a queue only at the output port. In the output queue switch, when a packet is received at the input port, the packet is immediately switched to the destination output port queue. Since packets are immediately transferred to the output port queue, r * r output queue switches require r speedups in the interconnect network. An input queue (IQ) switch employs a queue only at the input port. The input queue switch requires only one speedup in the interconnect network. Alternatively, no speed up is required in the IQ switch. However, the input queue switch does not remove head of line (HOL) blocking. This means that if the destination output port of the packet at the head of the input queue is busy at the switching time, even if the destination port of the next packet in the queue is free, this is also blocked.

  An input / output composite queue (CIOQ) switch employs queues at both its input and output ports. Such switches give the best results with both OQ and IQ switches by employing speedups between 1 and r in the interconnect network. Another type of switch called a virtual output queue (VOQ) switch is designed to have r queues corresponding to packets destined for one of the output ports at each input port. The VOQ switch removes HOL blocking.

  The VOQ switch has attracted much attention in recent years. Nick Mckeown's paper entitled “The iSLIP Scheduling Algorithm for Input-Queued Switches”, IEEE / ACM Transactions on Networking, April 1999, Vol. In this article, in the introductory pages from page 188 to page 190, a number of scheduling algorithms for crossbar-based interconnection networks are described.

  US Pat. No. 6,212,182 entitled “Combined Unicast and Multicast Scheduling” entitled “Nick Mckeown”, incorporated herein by reference as a background, describes r unicast queues and one multicast at each input port. A VOQ switching technique using a queue is described. Arbitrary arbitration is performed at each switching time, and one packet is switched to each output port.

  US Pat. No. 6,351,466 entitled “Switching System and Methods of Operation of Switching System”, which is entitled to Prabhakar et al., Incorporated herein by reference, has r unicasts for each input port. VOQ switching technology for crossbar interconnect networks such as queues and output queue switches that have precise control of packet latencies with one multicast queue for each output port requires at least 4 speedups Explained.

  However, there are many problems with prior art switch fabrics. First, HOL blocking for multicast packets is not removed. Second, the mathematical minimum speedup within the interconnect is unknown. Third, the use of speedup in the interconnect network floods the output port, which results in unnecessary packet congestion at the output port and a reduced rate for sending packets out of the egress port. Fourthly, a multicast packet that is arbitrarily fanned out cannot be scheduled in a non-blocking manner with respect to the output port. Fifth, packet arbitration is repeatedly performed at each switching time, which is expensive in terms of switching time, cost and power. Finally, sixthly, current technology requires segmentation and reassembly at the input and output ports to perform scheduling in the longest non-deterministic manner.

  A system for scheduling multi-rate multicast packets via an interconnection network having a plurality of input ports, a plurality of output ports, and a plurality of input queues, comprising unicast packets at each input port, according to the present invention, By scheduling at most as many packets as there are input queues to each output port, it operates in a non-blocking manner. The system operates at 100% throughput, is conservative, fair but deterministic, thereby never congesting the output port. The system performs arbitration with only one iteration with minimal mathematical speedup in the interaction network. The system operates in a truly cut-through and distributed manner with no packet reordering issues in the interconnect network and no internal packet buffering. In another embodiment, each output port also comprises a plurality of output queues, each packet being non-blocking and deterministic in the non-blocking and deterministic manner, up to the output queue in the destination output port, even if the packet size is different. Transfer without the need for segmentation and reassembly. In one embodiment, scheduling is performed in a strictly non-blocking manner with at least two speedups in the interconnect network. In another embodiment, scheduling is performed in a relocatable non-blocking manner with at least one speedup in the interconnected network. The system provides end-to-end guaranteed bandwidth and latency for packets from the input port to the output port. In all embodiments, the interconnect network may be a crossbar network, a shared memory network, a cross (Clos) network, a hypercube network, any internal non-blocking interconnect network, or a network of networks.

  The present invention relates to the design and operation of non-blocking, deterministic scheduling in a switch fabric comprising unicast packets, regardless of the nature of the traffic, where the unicast packets arrive at the input port. Specifically, the present invention relates to the following problems in a packet scheduling system. 1) strictly relocatable non-blocking scheduling of packets, 2) from input port to output port (if necessary, to a specific output queue of the output port) deterministically, ie without congesting the output port Switching packets, 3) not requiring packet segmentation and reassembly (SAR) implementation, 4) arbitration is done only once, 5) mathematics in the interconnect network 6) to operate in a fair manner with 100% throughput even if the packet size is variable.

  When more than one output port packet is destined for an output port, one-to-many packet transfer is required, which is called a multicast packet. When a packet of an input port is destined for only one output port, a one-to-one packet transfer is required, which is called a unicast packet. When a packet of an input port is destined for all output ports, a one-to-all packet transfer is required, which is called a broadcast packet. A set of multicast packets transferred over an interconnect network is called a multicast assignment.

  The type of switch fabric described here uses a virtual output queue (VOQ) of input ports. In one embodiment, packets received at each input port are placed in as many queues as there are at output ports. Each queue holds packets destined for only one of the output ports. The switch fabric may or may not have an output queue at the output port. If there are output queues, in one embodiment there are as many queues at each output port as there are at the input ports. Packets are switched to output queues such that each output queue holds packets switched from only one input port.

  In a switch fabric of the type described here, each input queue in all input ports has a uniform rate of unicast packets and allocates equal bandwidth in the output ports. The non-blocking, deterministic switch fabric with a constant rate of multicast packets and with each input queue in all input ports allocated equal bandwidth at the output ports was previously incorporated by reference. It is described in detail in US patent application, agent serial number V-0006 and PCT application, agent serial number S-0006. The non-blocking, deterministic switch fabric with constant rate multicast packets and each input queue in every input port allocates the same bandwidth at the output port is the US previously incorporated by reference This is described in detail in the patent application, agent serial number V-0009 and its PCT application, agent serial number S-0009. A non-blocking, deterministic switch fabric with a constant rate of multicast packets, with each input queue in every input port, allocates different bandwidth to the output ports, previously incorporated by reference This is described in detail in Person Reference Number V-0010 and its PCT application, Agent Reference Number S-0010.

  Referring to FIG. 1A, an input stage 110 consisting of four input ports 151-154 and four output ports go through an intermediate stage 130 which is a mutual network consisting of two 4 × 4 crossbar networks 131-132. An exemplary switch fabric 10 is shown having an output stage 120 comprised of 191-194. Each input port 151-154 receives a packet via an ingress link 141-144, respectively. Each output port 191-194 transmits a packet via an exit link 201-204, respectively. Each crossbar network 131-132 is connected to each of four input ports 151-154 via eight links (hereinafter referred to as "first internal links") FL1-FL8, It is connected to each of the four output ports 191 to 194 via links (hereinafter referred to as “second internal links”) SL1 to SL8. In the switch fabric 10 of FIG. 1A, each of the inlet links 141-144, the first internal links FL1-FL8, the second internal links SL1-SL8, and the outlet links 201-204 operate at the same rate.

  Packets destined for output ports 191-194 are received at each input port 151-154 via the ingress links 141-144 so that the packets are destined for each input port 151-154 at the respective input queues 171-174. The packets are sorted according to the destination output port into the same number of input queues 171-174 (4) as the existing output ports. In one embodiment, as shown in switch fabric 10 of FIG. 1A, packets may be placed in priority queues 161-164 before being placed in the input queue. Each priority queue 161-164 includes f queues that hold packets corresponding to the priority [1-f]. For example, a packet destined for the output port 191 is placed in the priority queue 161 based on the priority [1-f] of the packet, and the packet having the highest priority is first placed in the input queue 171. Put the next highest priority packet. Because the use of priority queues 161-164 is independent of the operation of switch fabric 10, switch fabric 10 of FIG. 1A may be implemented without priority queues 161-164 in another embodiment (priority queues Since use is irrelevant to all embodiments described in this invention, all embodiments can also be implemented in a non-blocking, deterministic manner without priority queues).

  The network also includes a scheduler that couples to each of input stage 110, output stage 120, and intermediate stage 130 and switches packets from input ports 151-154 to output ports 191-194. The scheduler maintains a list of available destinations in memory for paths through the interconnect network in the intermediate stage 130.

  In one embodiment, as shown in FIG. 1A, each output port 191-194 consists of the same number of output queues 181-184 as the existing input ports (4), and packets switched from the input ports 151-154 are transmitted. These are placed in output queues 181 to 184 in the output ports 191 to 194, respectively. Each of the input queues 171 to 174 in the four input ports 151 to 154 in the switch fabric 10 of FIG. 1A has A1 to A4 in the input queue 171 of the input port 151 and is in a state of being switched to the output port. Illustrative four packets with P1-P4 in the fourth input queue 174 of input port 164 are shown. The head-of-line packets in all 16 input queues in the four input ports 151-154 are designated by A1-P1, respectively.

  Table 1 shows exemplary packet assignments between input queues and output queues in the switch fabric 10 of FIG. 1A. Packets in the input queue 171 in the input port 151 indicated by I {1,1} are allocated and switched to the output queue 181 in the output port 191 indicated by O {1,1}. The packet in the input queue 172 in the input port 151 indicated by I {1, 2} is assigned to the output queue 181 in the output port 192 indicated by O {2, 1} and switched. Similarly, packets in the remaining 16 input queues are assigned to the remaining 16 output queues as shown in Table 1. In another embodiment, the assignment of input queues to output queues may be different from Table 1, but according to the present invention, in each input port assigned to switch packets to the output queue in each output port. There is only one input queue and vice versa.

  According to the present invention, all 16 packets A1-P1 are output from the input port via the interconnection network in the intermediate stage 130 in a non-blocking manner at the time of switching four times (hereinafter referred to as “fabric switching cycle”). Switched to the port. At each switching time, at most one packet is switched from each input port and at most one packet is switched to each output port. Since each input port can only receive 4 unicast packets, input port collisions never occur in the switch fabric 10 of FIG. 1A. Since each input queue from any input port is switched to only one designated output queue in each output port, output port collisions never occur in the switch fabric 10 of FIG. 1A. Accordingly, three steps of arbitration are required: generation of a request by the input port, issue of permission by the output port, and approval of permission by the input port. Applicant now considers the problem with deterministic and non-blocking scheduling of 16 packets A1-P1 to be switched to output ports 191-194 in the switch fabric 10 of FIG. 1A is the three-stage cross network shown in FIG. 1C. It has an important view that it relates to 14 non-blocking scheduling.

個に等しいとき、ユニキャスト接続要求に対して厳密なノンブロッキング方式で動作する（本発明の背景として参照により組み込んだ、Charles Closによる「A Study of Non-Blocking Switching Networks」、１９５３年１月、The Bell System Technical Journal発行、第３２巻、Ｎｏ，１、４０６−４２４頁を参照）。 Referring to FIG. 1C, an exemplary symmetric type operating in a 10-switch time-space-time (TST) configuration that satisfies the communication requirements between the input stage 110 and the output stage 120 via the intermediate stage 130. A three stage cross network 14 is shown. Here, the input stage 110 includes four 4 × 2 switches IS1 to IS4, the output stage 120 includes four 2 × 4 switches OS1 to OS4, and the intermediate stage 130 includes two 4 × 4 switches MS1. -Consist of MS2. The number of inlet links for each switch in the input stage 110 and the number of outlet links for each switch in the output stage 120 is represented by n, and the number of switches in the input stage 110 and the output stage 120 is represented by r. Each of the two intermediate switches MS1-MS2 is connected to each of the r input switches via r links (for example, the links FL1-FL4 are connected to the intermediate switch MS1 from each of the input switches IS1-IS4). ), Connected to each of the output switches via r second internal links (for example, the links SL1-SL4 are connected from the intermediate switch MS1 to each of the output switches OS1-OS4). The network has 16 ingress links: I {1,1} -I {4,4} and 16 egress links O {1,1} -O {4,4}. In the three-stage cross network 14 of FIG. 1C, all 16 input links are assigned to 16 output links, as shown in Table 1, just like the switch fabric 10 of FIG. 1A. In the network 14 of FIG. 1C, the number of switches in the intermediate stage 130 is

Behave in a strict non-blocking manner for unicast connection requests (“A Study of Non-Blocking Switching Networks” by Charles Clos, incorporated by reference as the background of the present invention, January 1953, The (See Bell System Technical Journal, Vol. 32, No. 1, pages 406-424).

  In accordance with the present invention, in one embodiment having two 4x4 crossbar networks 131-132 in the intermediate stage 130, ie, two speedups, the switch fabric 10 of FIG. 1A operates in a strictly non-blocking manner. . The detailed method used to implement the strictly non-blocking deterministic switching may be any of a number of different methods that will be apparent to those skilled in the art in view of the present disclosure. One such arbitration and scheduling method is described in FIG. 1B below.

  Table 2 shows, in one embodiment, the packet schedule for the packet requests, grants and grants of Table 1 at each of the four switching times, using the scheduling part of the arbitration and scheduling method 40 of FIG. 1B. Is calculated. 1D to 1H show the state of the switch fabric 10 of FIG. 1A after each switching time. FIG. 1D shows the state of the switch fabric 10 of FIG. 1A after a first switching time in which packets A1, K1, and P1 are switched to the output queue. The packet A1 from the input port 151 is switched to the output queue 181 of the output port 191 via the crossbar network 131. The packet F1 from the input port 152 is switched to the output queue 182 of the output port 192 via the crossbar network 131. The packet K1 from the input port 153 is switched to the output queue 183 of the output port 193 via the crossbar network 132. The packet P1 from the input port 154 is switched to the output queue 184 of the output port 194 via the crossbar network 132. It is clear that at the first switching time, only one packet is switched from each input port and each output port receives only one packet.

  FIG. 1E shows the state of the switch fabric 10 of FIG. 1A after a second switching time when packets D1, E1, and O1 are switched to the output queue. The packet D1 from the input port 151 is switched to the output queue 181 of the output port 194 via the crossbar network 131. The packet E1 from the input port 152 is switched to the output queue 182 of the output port 191 via the crossbar network 131. The packet J1 from the input port 153 is switched to the output queue 183 of the output port 192 via the crossbar network 132. The packet O1 from the input port 154 is switched to the output queue 184 of the output port 193 via the crossbar network 132. Again, at the second switching time, only one packet is switched from each input port, and each output port receives only one packet.

  FIG. 1F shows the state of the switch fabric 10 of FIG. 1A after a third switching time when packets C1, H1, I1, and N1 are switched to the output queue. The packet C1 from the input port 151 is switched to the output queue 181 of the output port 193 via the crossbar network 131. The packet H1 from the input port 152 is switched to the output queue 182 of the output port 194 via the crossbar network 131. The packet I1 from the input port 153 is switched to the output queue 183 of the output port 191 via the crossbar network 132. The packet N1 from the input port 154 is switched to the output queue 184 of the output port 192 via the crossbar network 132. Again, at the third switching time, only one packet is switched from each input port and each output port receives only one packet.

  FIG. 1G shows the state of the switch fabric 10 of FIG. 1A after a fourth switching time in which packets B2, G2, and L1 are switched to the output queue. The packet B2 from the input port 151 is switched to the output queue 181 of the output port 192 via the crossbar network 132. The packet G1 from the input port 152 is switched to the output queue 182 of the output port 193 via the crossbar network 131. The packet L1 from the input port 153 is switched to the output queue 183 of the output port 194 via the crossbar network 131. The packet M1 from the input port 154 is switched to the output queue 184 of the output port 191 via the crossbar network 132. It is clear that at the fourth switching time, only one packet is switched from each input port and each output port receives only one packet.

  FIG. 1H shows the packet after the fifth switching time when A2, F2, K2, and P2 are switched to the output queue in the same way that A1, F1, K1, and P1 are switched at the first switching time. The state of switch fabric 10 of Drawing 1A is shown. The packet A2 from the input port 151 is switched to the output queue 181 of the output port 191 via the crossbar network 131. The packet F2 from the input port 152 is switched to the output queue 182 of the output port 192 via the crossbar network 131. The packet K2 from the input port 153 is switched to the output queue 183 of the output port 193 via the crossbar network 132. The packet P2 from the input port 154 is switched to the output queue 184 of the output port 194 via the crossbar network 132. Accordingly, the arbitration and scheduling method 40 of FIG. 1B does not need to be rescheduled after scheduling for the first fabric switching cycle has been performed. Thus, packets from any particular input queue to the destination output queue are switched along the same path and move in the same order as the input ports receive them, thus never causing packet reordering problems .

  Since all 16 packets A1-P1 are switched to the destination output port in the fabric switching cycle, the switch is non-blocking and operates at 100% throughput according to the present invention. The switch fabric 10 of FIG. 1A is such that each output port receives at least one packet from any one of the input queues destined for that output port as long as there is at least one packet at the switching time. In operation, the switch fabric is hereinafter referred to as a “process conservative system”. It can easily be seen that the switch fabric is directly process conservative when it is non-blocking. In accordance with the present invention, the switch fabric 10 of FIG. 1A operates so that none of the packets at the beginning of each input queue are maintained more than the same number of switching times as the number of input queues (4) at each input port. The switch fabric is called a “fair system”. Since the virtual output queue is used at the beginning of a line, blocking is also removed.

  In accordance with the present invention, the arbitration and scheduling method 40 of FIG. 1B can be used to switch the switch fabric of FIG. 1A even when two packets can be switched in switching time using two speedups in the interconnect network. 10 operates so that each output port receives at most one packet when switching. The speedup is used strictly to operate the interconnect network in a non-blocking manner and is used to never congest the output port. Accordingly, the arbitration and scheduling method 40 of FIG. 1C for switching packets in the switch fabric 10 of FIG. 1A is deterministic. Each ingress link 141-144 receives packets at the same rate as each egress link 201-204 transmits, ie, one packet at each switching time. Since only one packet is deterministically switched from each input port 151-154 at each switching time and only one packet is switched to each output port 191-194, the switch fabric 10 of FIG. Do not congest the output port.

  A major advantage of deterministic switching according to the present invention is that packets are switched from the input port at the highest peak rate. This also means that packets are received at the output port at the highest peak rate. That means no traffic management is required at the output port and packets are sent deterministically from the output port. Accordingly, traffic management is only required at the input port in the switch fabric 10 of FIG. 1A.

  Another important characteristic of the switch fabric 10 of FIG. 1A is that all packets belonging to a special input queue are switched to the same output queue in the destination output port. Applicants point out three key advantages with output queues. 1) In the switching time, one byte or a certain number of bytes are switched from the input port to the output port. Alternatively, since the switching time of the switch fabric is variable, it is a flexible parameter at the design stage of the switch fabric. 2) Therefore, even if the packets A1-P1 are of arbitrary length and the size is variable, each packet in the input queue is switched to the same output queue in the destination output port, so that the complete packet There is no need to be switched in the switching time. Alternatively, the second advantage of the output queue is that long packets do not need to be physically segmented within the input port and need not be relocated within the output port. Packets are not physically segmented, but are logically switched to the output queue one segment at a time (the size of the packet segment is determined by the switching time). The packet segments within each packet are also switched over the same path from the input queue to the destination output queue. 3) A third advantage of the output queue is that packets and packet segments are switched in the same order that the input ports receive them, and never encounter packet reordering issues.

  FIG. 1I shows a switch fabric 16 that switches long packets. There is one packet in each input queue, which creates 16 packets in all 16 input queues. That is, the packet {A1-A4} is stored in the input queue 171 in the input port 151, the packet {B1-B4} is stored in the input queue 172 in the input port 151, and the packet {B1 is stored in the input queue 173 in the input port 151. C1-C4} and the like are created, and the input queue 174 in the input port 154 has a packet {P1-P4}. Each of these 16 packets consists of 4 equally sized packet segments. For example, packet {A1-A4} consists of four packet segments, namely A1, A2, A3 and A4. If the size of the packet is not completely four times the size of the packet segment, the size of the fourth packet is shorter. However, none of the four packet segments is longer than the maximum packet segment size. The size of the packet segment is determined by the switching time. That is, at each switching time, a unique packet segment is switched from any input port to any output port. Except for the longer packet size, the diagram of switch fabric 16 of FIG. 1I is the same as the diagram of switch fabric 10 of FIG. 1A.

  1J through 1M show the state of the switch fabric 16 of FIG. 1I after each fabric switching cycle. FIG. 1J shows the state of the switch fabric 16 of FIG. 1I after the first fabric switching cycle in which all leading packet segments A1-P1 are switched to the output ports. As shown in FIGS. 1D-1G, these packet segments are exactly the same as packets A1-P1 are switched to output queues in the switch fabric 10 of FIG. 1A using the arbitration and scheduling method 40 of FIG. 1B. In the manner switched to the output queue. FIG. 1K shows the state of switch fabric 16 of FIG. 1I after the second fabric switching cycle when all leading packet segments A1-P1 are switched to the output queue. FIG. 1L shows the state of switch fabric 16 of FIG. 1I after a third fabric switching cycle in which all leading packet segments A3-P3 are switched to the output queue. FIG. 1M shows the state of the switch fabric 16 of FIG. 1I after the fourth fabric switching cycle in which all leading packet segments A1-P1 are switched to the output queue. In each of the first, second, third, and fourth fabric switching cycles, packets A1-P1 are switched to output queues in switch fabric 10 of FIG. 1A, as shown in FIGS. 1D-1G. The packet segment is switched to the output queue in exactly the same way. Obviously, all packet segments are switched in the same order that each input port receives. Thus, there is no problem of packet reordering. Packets are further switched in a 100% throughput, process conservative and fair manner.

  In FIGS. 1J-1M, packets are logically segmented and switched to output ports. In one embodiment, the tag bit “1” is further padded to a specially designated bit position in each packet segment to indicate that the packet segment is the first packet segment in each packet. By reading the tag bit of “1”, the output port recognizes that the packet segment A1-P1 is the first packet segment in the new packet. Similarly, each packet segment is padded with a tag bit of “1” at the specified bit position, except for the last packet segment padded with “0” (eg, in the packet segment in switch fabric 16 of FIG. 1I). Packet segments A1-P1, A2-P2 and A3-P3 are padded with tag bits of “1” and packet segments A4-P4 are padded with tag bits of “0”). When the tag bit is detected as “0”, the output port then expects a packet segment or new packet for the new packet. If there is only one packet segment in the packet, it is represented by a tag bit of “0” by the input port. If the output port receives two consecutive packet segments with a designated tag bit of “0”, the output port determines that the second packet segment is the only packet segment of the new packet.

  In the switch fabric 16 of FIG. 1I, the packet is 4 segments long. However, in general, packets are of arbitrary length. In addition, different packets in the same queue can be of different sizes. In both cases, the arbitration and scheduling method of FIG. 1B operates the switch fabric in a non-blocking manner, and packets are switched in a 100% throughput, process conservative, and fair manner. In addition, the packets need not be physically segmented within the input port and reassembled within the output port. The switching time of the switch fabric is also a flexible design parameter, and is set to switch packets one byte or several bytes at each switching time.

  FIG. 1B illustrates a high-level flowchart of the arbitration and scheduling method 40 performed by the scheduler of FIG. 1A in one embodiment. At most r requests according to this embodiment are generated from each input port at act 41. Since each input port has r input queues with at most one request from each input queue, there will be at most r requests from each input port. Each of these r requests is also addressed to a different output port. In act 42, each output port will issue at most r permissions. Each request then corresponds to an associated output queue. Since each input port generates a unique request, it can easily be seen that each output port receives at most r requests from each input port. Each output port can then issue a grant to all r received requests. In Act 43, each input port accepts at most r permissions. Each output port issues at most r permissions to each input port, so each input port receives at most r permissions. Each input port then approves all r permissions.

At act 44, all r ² requests are scheduled without relocating the previously scheduled packet path. In accordance with the present invention, all r ² requests are scheduled in a strictly non-blocking manner with at least two speedups in the intermediate stage 130. Note that request generation arbitration, permission issuance, and approval generation are performed in a single iteration. After act 44, control returns to act 45. In act 45, it is checked whether there are new or different requests at the input port. If the result is “no”, control returns to Act 45. If there is a new request but the same request and has the same input queue for the output queue request, the same schedule is used to switch the next r ² requests. When there is a new request and a different request from the input port, control passes from act 45 to act 41. Acts 41-45 are then executed in the loop.

に等しいとき、ユニキャスト接続要求に対して再配置可能なノンブロッキング方式で動作することもできる。同様に本発明によると、中間ステージ１３０内で４×４クロスバーネットワーク１３１を１つだけ、即ち少なくとも１のスピードアップを有する別の実施形態において、図１Ｎのスイッチファブリック１８は、再配置可能なノンブロッキング方式で動作する。 In the network 14 of FIG. 1C, the number of switches in the intermediate stage 130 is

It is also possible to operate in a non-blocking manner that can be rearranged for unicast connection requests. Similarly, according to the present invention, in another embodiment having only one 4 × 4 crossbar network 131 in the intermediate stage 130, ie at least one speedup, the switch fabric 18 of FIG. 1N can be relocated. Operates in a non-blocking manner.

  In a strictly non-blocking network, once packets are scheduled at the beginning of all input queues, the packet path from the input queue to the destination output queue is routed through the network without disturbing the previously scheduled packet path. Scheduling is always possible, and if more than one such path is available, any path can be selected without worrying about scheduling the remaining packets. In a relocatable non-blocking network, once a packet is scheduled at the beginning of all input queues, scheduling the path of the packet from the input queue to the destination output queue is Satisfaction is guaranteed by relocating the path of previously scheduled packets by the scheduler. According to the present invention, the switch fabric 10 of FIG. 1A operates strictly in a non-blocking manner, whereas the switch fabric 18 of FIG. 1N operates in a relocatable non-blocking manner.

  Referring to FIG. 2A, the switch fabric 20 does not have an output queue. Otherwise, the switch fabric 20 of FIG. 2A is exactly the same as the view of the switch fabric 10 of FIG. 1A. In accordance with the present invention, the switch fabric 20 is strictly non-blocking, in all respects similar to that disclosed for the switch fabric 10 of FIG. 1A, except that a SAR is required in the input and output ports. Operates in a deterministic manner. The packet needs to be segmented within the input port as determined by the switching time, switched to the output port, and reassembled separately. However, the arbitration and scheduling method 40 of FIG. 1B is also used to switch packets within the switch fabric 20 of FIG. 2A. Further here, scheduling is performed simultaneously on all 16 first-line packets, assuming that there are virtually 16 output queues, the packets are switched in 4 switching times. However, during the switching time, packets are switched to the destination output port instead of the output queue. 2B-2F show the state of the switch fabric 20 of FIG. 2A after each switching time by scheduling the packet requests shown in Table 1 using the arbitration and scheduling method of FIG. 1B.

  FIG. 2B shows the state of the switch fabric 20 of FIG. 2A after the initial switching time when packets A1, F1, K1, and P1 are switched to the output queue. The packet A1 from the input port 151 is switched to the output port 191 via the crossbar network 131. The packet F1 from the input port 152 is switched to the output port 192 via the crossbar network 131. The packet K1 from the input port 153 is switched to the output port 193 via the crossbar network 132. The packet P1 from the input port 154 is switched to the output port 194 via the crossbar network 132. It is clear that at the first switching time, only one packet is switched from each input port and each output port receives only one packet.

  FIG. 2C shows the state of the switch fabric 20 of FIG. 2A after a second switching time in which packets D1, E1, J1 and O1 are switched to the output queue. The packet D1 from the input port 151 is switched to the output port 194 via the crossbar network 131. The packet E1 from the input port 152 is switched to the output port 191 via the crossbar network 131. The packet J1 from the input port 153 is switched to the output port 192 via the crossbar network 132. The packet O1 from the input port 154 is switched to the output port 193 via the crossbar network 132. Again, at the second switching time, only one packet is switched from each input port, and each output port receives only one packet.

  FIG. 2D shows the state of the switch fabric 20 of FIG. 2A after a third switching time when packets C1, H1, I1, and N1 are switched to the output queue. The packet C1 from the input port 151 is switched to the output port 193 via the crossbar network 131. The packet H1 from the input port 152 is switched to the output port 194 via the crossbar network 131. The packet I1 from the input port 153 is switched to the output port 191 via the crossbar network 132. The packet N1 from the input port 154 is switched to the output port 192 via the crossbar network 132. Again, at the third switching time, only one packet is switched from each input port, and each output port receives only one packet.

  FIG. 2E shows the state of the switch fabric 20 of FIG. 2A after a fourth switching time in which packets B1, G1, L1 and M1 are switched to the output queue. The packet B1 from the input port 151 is switched to the output port 192 via the crossbar network 132. The packet G1 from the input port 152 is switched to the output port 193 via the crossbar network 131. The packet L1 from the input port 153 is switched to the output port 194 via the crossbar network 131. The packet M1 from the input port 154 is switched to the output port 191 via the crossbar network 132. In the fourth switching time, it is clear that only one packet is switched from each input port and each output port receives only one packet.

  FIG. 2F shows a fifth switching time after packets A2, F2, K2 and P2 are switched to the output queue, just as A1, F1, K1 and P1 are switched in the first switching time. The state of the switch fabric 20 of FIG. 2A is shown. The packet A2 from the input port 151 is switched to the output port 191 via the crossbar network 131. The packet F2 from the input port 152 is switched to the output port 192 via the crossbar network 131. The packet K2 from the input port 153 is switched to the output port 193 via the crossbar network 132. The packet P2 from the input port 154 is switched to the output port 194 via the crossbar network 132.

  Also, the arbitration and scheduling method 40 of FIG. 1B operates the switch fabric 20 of FIG. 2A strictly in a non-blocking manner, and the packet operates in a 100% throughput, process conservative and fair manner. The switching time of the switch fabric is also a flexible design parameter and can be set to switch packets one byte or several bytes at each switching time. However, SAR is required for the switch fabric 20 and the packets need to be physically segmented in the input port and reassembled in the output port. Nevertheless, in switch fabric 20, packets and packet segments are switched to output ports in the same order that the input ports receive. Indeed, except for the SAR, the arbitration and scheduling method 40 of FIG. 1B operates the switch fabric 20 in the same manner in all respects as described with respect to the switch fabric 10 of FIG. 1A.

  The two speedups in the intermediate stage for the switch fabric to operate non-blocking are realized in two ways. That is, 1) parallel processing and 2) doubling of the switching rate. Parallel processing is realized by using two interconnected networks in the intermediate stage in parallel, as shown for example by the switch fabric 10 in FIG. 1A. Switching rate doubling is achieved by operating a single interconnect network, first and second internal links at twice the clock rate for each clock in the input and output ports. . At the first clock, the single interconnect network switches as the first interconnect of an equivalent switch fabric implemented with two parallel interconnect networks, for example, the interconnect network 131 in the switch fabric 10 of FIG. 1A. Works against. Similarly, at the second clock, the single interconnect network operates as an interconnect network 132 within the second interconnect network, eg, switch fabric 10 of FIG. 1A. Therefore, twice the rate is required for this implementation in the interconnect network clock speed and the first and second internal links. The arbitration and scheduling method 40 of FIG. 1B implements parallel processing or double rate speedup so that both switch fabrics are non-blocking and deterministic in all respects as described in the present invention. Make it work.

  Referring to FIG. 3A, FIG. 3A shows the switch fabric 30. The diagram of the switch fabric 10 of FIG. 1A except that the clock speed on the only crossbar interconnect network in the intermediate stage 130 is increased by 2 and the first and second internal links are increased by 2 Is the same. In another embodiment of the network of FIG. 1A, each interconnect network in the intermediate stage is a shared memory network. FIG. 3B shows the switch fabric 50. Same as the switch fabric 10 of FIG. 1A except that it speeds up the two shared memory interconnect networks in the intermediate stage 130. FIG. 3C shows the switch fabric 60. Exactly the same as switch fabric 30 of FIG. 3A, except that the clock speed of the only shared memory interconnect network in intermediate stage 130 is increased by 2 and the first and second internal links are increased by 2 It is.

  Similarly, FIG. 3D shows the switch fabric 70. Exactly the same as switch fabric 10 of FIG. 1A, except that two speedups speeds up the two hypercube interconnect networks in intermediate stage 130. FIG. 3E shows the switch fabric 60. The switch fabric 30 of FIG. 3A, except for speeding up the clock rate of the only hypercube-based interconnect network in the intermediate stage 130 by 2 and speeding up the first and second internal links by 2 Exactly the same.

  Inputs at switch fabric 10 of FIG. 1A, 16 of FIG. 1I, 18 of FIG. 1N, 20 of FIG. 2A, 30 of FIG. 3A, 50 of FIG. 3B, 60 of FIG. 3C, 70 of FIG. The number of ports 110 and the number of output ports 120 are generally represented by a variable r for each stage. The speed up in the intermediate stage is represented by s. The speed up in the intermediate stage is parallel processing, ie two interconnect networks (shown in FIGS. 4A, 4C and 4E), or twice the switching rate in one interconnect network (FIGS. 4B, 4D and 4). (Shown in FIG. 4F). Each input port size 151- {151 + r} is generally expressed in the notation of r * s (each input port has r input queues, s interconnect networks and s first internal links). The size of each output switch 191- {191 + r} is generally expressed in the notation of s * r (each output port has r output queues and s interconnects). It is connected to the network with s second internal links). Similarly, the size of each interconnect network in the intermediate stage 130 is denoted r * r. The interconnect network described here can be a crossbar network, a shared memory network, a network of sub-networks, each of which is a crossbar or shared memory network, a three-stage cross network, a hypercube, any internal non-blocking interconnect network, or It may be a network of networks. A three-stage switch fabric is represented by the notation of V (s, r).

  There need not be as many input queues 171-{171 + r} as there are output queues 181-{181 + r}, but they are the same in a symmetric network. Each of the s intermediate stage interconnect networks 131-132 is connected to each of the r input ports via r first internal links, and each of the output ports via r second internal links. Connected to. Each of the first internal links FL1-FLr and each of the second internal links SL1-SLr are either usable by new packets or not available if already acquired by another packet.

  The switch fabric 10 of FIG. 1A is an example of the general symmetric switch fabric of FIG. 4A and provides two speedups by using two crossbar interconnect networks in the intermediate stage 130. Referring to FIG. 4B, a typical symmetric switch fabric is shown. Same as the switch fabric 30 of FIG. 4A except that the clock speed of the only crossbar interconnect network in the intermediate stage 130 is increased by 2 and the first and second internal links are increased by 2 is there

  FIG. 4C shows a typical symmetric switch fabric. Using two shared memory interconnect networks in the intermediate stage 130 provides a 2 speedup. FIG. 4D shows a typical symmetric switch fabric. This provides a speedup of 2 by using 2 speedup of the clock speed of the only shared memory interconnect network in the intermediate stage 130 and 2 speedup of the first and second internal links. To do.

  FIG. 4E shows a typical symmetric switch fabric. Using two three-stage cross-interconnect networks in the intermediate stage 130 provides two speedups. FIG. 4F shows a typical symmetric switch fabric. Using two speedups of the only three-stage cross-connect network in the intermediate stage 130 and two speedups of the first and second internal links provides two speedups.

  In general, the interconnection network in the intermediate stage 130 may be any interconnection network, i.e., a hypercube, batcher vanian interconnection network, any internal non-blocking interconnection network, or a network of networks. In one embodiment, interconnect networks 131 and 132 may be two disparate networks. For example, the interconnect network 131 may be a crossbar network and the interconnect network 132 may be a shared memory network. In accordance with the present invention, regardless of the type of interconnect network used in the intermediate stage, at least two speedups in the intermediate stage are strictly non-blocking using the arbitration and scheduling method 40 of FIG. 1B. Operate the switch fabric. And at least one speedup in the intermediate stage causes the switch fabric to operate in a non-blocking manner that can be repositioned.

  Note that the speedup within the switch fabric is not related to the internal speedup of the interconnect network. For example, crossbar networks and shared memory networks are fully connected topologies and are internally non-blocking without any additional internal speedup. For example, the interconnect network 131-132 in either the switch fabric 10 of FIG. 1A or the switch fabric 50 of FIG. 3B is a crossbar network or a shared memory network, and the interconnect networks 131-132 to operate in a non-blocking manner. There is no speedup required for either. However, when the interconnection network 131-132 is a three-stage cross network, each three-stage cross network can operate strictly in a non-blocking system, and therefore requires an internal speedup of 2. In a switch fabric where the intermediate stage interconnect network 131-132 is a three stage cross network, a two speed up of the switch fabric is provided in the form of two different three stage cross networks, such as 131 and 132. In addition, each three-stage cross network 131 and 132 requires a further 2 speedup because it is strictly strictly non-blocking internally. Clearly, the switch fabric speedup is different from the internal speedup of the interconnect network.

Similarly, if the interconnection network in the intermediate stages 131 and 132 is a hypercube network, in one embodiment in a d-rank hypercube (comprising 2 ^d nodes), because it is a non-blocking network, It is necessary to increase the internal speed of d. In accordance with the present invention, the intermediate stage interconnect network 131 or 132 can operate in a strictly non-blocking manner, with the switch fabric speeding up 2 in the intermediate stage using the arbitration and scheduling method 40 of FIG. 1B. Yes, and can be any internal non-blocking interconnect network because it can operate in a relocatable non-blocking manner with at least one speedup in the intermediate stage.

  Referring to FIG. 4G, a 4 × 4 port (2 rank) hypercube based interconnect in one embodiment where the intermediate stage interconnect network 131 or 132 is in the switch fabric 70 of FIG. 3D and the switch fabric 80 of FIG. 3E. A detailed view of the network is shown. There are four nodes in the 4-node hypercube: 00, 01, 10 and 11. Node 00 is connected to node 01 by bidirectional link A. The node 01 is connected to the node 11 by a bidirectional link B. The node 11 is connected to the node 10 by a bidirectional link C. The node 10 is connected to the node 00 by a bidirectional link D. Each of the four nodes is connected to an input port and an output port of the switch fabric. The node 00 is connected to the first internal link FL1 and the second internal link SL1. The node 01 is connected to the first internal link FL2 and the second internal link SL1. The node 10 is connected to the first internal link FL3 and the second internal link SL3. The node 11 is connected to the first internal link FL4 and the second internal link SL4. Because the hypercube network 131 or 132 shown in FIG. 4G is internally non-blocking, in one embodiment, at the same rate as the switch fabric ingress link (or egress link) or depending on the hypercube network scheduling scheme. It is necessary to operate links A, B, C, and D in both directions due to some increase in speed. According to the present invention, the hypercube operates internally in a non-blocking manner, and the switch fabric can operate strictly in a non-blocking manner at a speedup of at least 2 using the arbitration and scheduling method 40 of FIG. 1B. And the switch fabric must be able to operate in a relocatable non-blocking manner with at least one speedup in the intermediate stage.

のスピードアップを有する相互接続ネットワークとを備え、各サブネットワークは総数少なくともｒ_１個の第１内部リンクに対する各入力ポートに接続される少なくとも１個の第１内部リンクを備え、各サブネットワークはさらに総数少なくともｒ_２個の第２内部リンクに対する各出力ポートに接続される少なくとも１個の第２内部リンクを備える。その非対称スイッチファブリックは、ｒ_１≦ｒ_２のときに、スイッチングすべき各スイッチング時間において、多くともｒ_２回のスイッチング時間だけ決定論的な方式で、かつパケットのセグメント化および再組立を要求することなく、多くともｒ_１個のパケットをスケジューリングすることで、本発明による厳密にノンブロッキング方式で動作する。別の実施形態においては、スイッチファブリックは、ｒ_２≦ｒ_１のときに、スイッチングすべき各スイッチング時間において、多くともｒ_１回のスイッチング時間だけ決定論的な方式で、かつパケットのセグメント化および再組立を要求することなく、多くともｒ_２個のパケットをスケジューリングすることで、本発明による厳密にノンブロッキング方式で動作する。 4A-4F show the same number of first and second internal links, but as in the case of a symmetric switch fabric, the invention extends to an asymmetric switch fabric. In general, be asymmetric switch fabric (r 1 _{* r 2),} the asymmetric switch fabric, and r ₁ input ports each input port having r ₂ inputs queues, each output port is _one r With at least r ₂ output ports having s output queues and s sub-networks

Each subnetwork comprising at least _one first internal link connected to each input port for a total of at least r ₁ first internal links, each subnetwork further comprising: A total of at least one second internal link connected to each output port for at least r ₂ second internal links. The asymmetric switch fabric requires packet segmentation and reassembly in a deterministic manner at most r ₂ switching times at each switching time to be switched when r ₁ ≦ r ₂ Without scheduling at most r ₁ packets, it operates in a strictly non-blocking manner according to the present invention. In another embodiment, the switch fabric is deterministic in each switching time to be switched when r ₂ ≦ r ₁ , and at most r ₁ switching time, and packet segmentation and By scheduling at most r ₂ packets without requiring reassembly, it operates in a strictly non-blocking manner according to the present invention.

Such a general asymmetric switch fabric is represented as V (s, r ₁ , r ₂ ). In one embodiment, the system performs only one iteration for arbitration with minimal mathematical speedup in the interconnect network. The system operates 100% throughput, conservative, fair, yet deterministic, thereby never congesting the output port. The arbitration and scheduling method 40 of FIG. 1B is also used to schedule packets in a V (s, r ₁ , r ₂ ) switch fabric.

In the arbitration and scheduling method 40 of FIG. 1B, a general V (s, r ₁ , r ₂ ) switch fabric is also operated in a non-blocking manner, and packets are switched in a 100% throughput, processing conservative and fair manner. The switching time of the switch fabric is also a flexible design parameter and can be set to switch packets one byte or several bytes at each switching time. Furthermore, there is no need for SAR as described in the present invention. In embodiments without an output queue, the packets must be physically segmented within the input port and reassembled at the output port.

のスピードアップで再配置可能なノンブロッキング方式で動作する。これは、ｒ_１≦ｒ_２のときに、スイッチングすべき各スイッチング時間において、多くともｒ_２回のスイッチング時間だけ決定論的な方式で、かつパケットのセグメント化および再組立を要求することなく、多くともｒ_１個のパケットをスケジューリングすることで動作する。別の実施形態において、非対称スイッチファブリックＶ（ｓ，ｒ_１，ｒ_２）は、相互接続ネットワークにおいて、少なくとも

のスピードアップで再配置可能なノンブロッキング方式で動作する。これは、ｒ_２≦ｒ_１のときに、スイッチングすべき各スイッチング時間において、多くともｒ_１回のスイッチング時間だけ決定論的な方式で、かつパケットのセグメント化および再組立を要求することなく、多くともｒ_２個のパケットをスケジューリングすることで動作する。 Similarly, in one embodiment, the asymmetric switch fabric V (s, r ₁ , r ₂ ) is at least in the interconnect network

It operates in a non-blocking method that can be relocated at a speedup of. This is a deterministic method for each switching time to be switched when r ₁ ≦ r ₂ and at most r ₂ switching times, and without requiring packet segmentation and reassembly, It works by scheduling at most r ₁ packets. In another embodiment, the asymmetric switch fabric V (s, r ₁ , r ₂ ) is at least in the interconnect network

It operates in a non-blocking method that can be relocated at a speedup of. This is in a deterministic manner at each switching time to be switched when r ₂ ≦ r ₁ , at most r ₁ switching time, and without requiring packet segmentation and reassembly, It works by scheduling r ₂ packets at most.

のスピードアップを有する相互接続ネットワークとを備え、各サブネットワークは、少なくとも総数ｒ_１個の第１内部リンクに対する各入力ポートに接続された、少なくとも１つの第１内部リンクを備え、各サブネットワークは、さらに少なくとも総数ｒ_２個の第２内部リンクに対する各出力ポートに接続された、少なくとも１つの第２内部リンクを備える。その非対称スイッチファブリックは、本発明に従い、スイッチングすべき各スイッチング時間において、多くともｒ_２回のスイッチング時間だけ決定論的な方式で、多くともｒ_１個のパケットをスケジューリングし、かつパケットのセグメント化および再組立を要求することで、厳密にノンブロッキング方式で動作する。図１Ｂの調停およびスケジューリング方法４０は、出力キューを使用せずに、Ｖ（ｓ，ｒ_１，ｒ_２）スイッチファブリックにおいてパケットをスイッチングするためにも使用される。 An asymmetric switch fabric V (s, r ₁ , r ₂ ), wherein the asymmetric switch fabric includes r ₁ input ports each having r ₂ input queues, r ₂ output ports, and , With at least s subnetworks

Each subnetwork comprising at least one first internal link connected to each input port for at least a total of r ₁ first internal links, wherein each subnetwork is , And at least one second internal link connected to each output port for at least a total of r ₂ second internal links. The asymmetric switch fabric according to the present invention schedules at most r ₁ packets and segments the packets in a deterministic manner at most r ₂ switching times at each switching time to be switched. And by requiring reassembly, it operates strictly in a non-blocking manner. The arbitration and scheduling method 40 of FIG. 1B is also used to switch packets in a V (s, r ₁ , r ₂ ) switch fabric without using an output queue.

のスピードアップを有する相互接続ネットワークとを備え、各サブネットワークは、少なくとも総数ｒ_１個の第１内部リンクに対する各入力ポートと接続された少なくとも１つの第１内部リンクを備え、各サブネットワークは、さらに少なくとも総数ｒ_２個の第２内部リンクに対する各出力ポートに接続された少なくとも１つの第２内部リンクを備える。その非対称スイッチファブリックは、本発明に従い、スイッチングすべき各スイッチング時間において、多くともｒ_２回のスイッチング時間だけ決定論的な方式で、多くともｒ_１個のパケットをスケジューリングし、かつパケットのセグメント化および再組立を要求することで、再配置可能なノンブロッキング方式で動作する。 An asymmetric switch fabric V (s, r ₁ , r ₂ ), wherein the asymmetric switch fabric includes r ₁ input ports each having r ₂ input queues, r ₂ output ports, and , With at least s subnetworks

Each sub-network comprising at least one first internal link connected to each input port for at least a total number r ₁ first internal links, each sub-network comprising: And at least one second internal link connected to each output port for at least a total of r ₂ second internal links. The asymmetric switch fabric according to the present invention schedules at most r ₁ packets and segments the packets in a deterministic manner at most r ₂ switching times at each switching time to be switched. And by requiring reassembly, it operates in a non-blocking manner that can be repositioned.

  Applicants note that all switch fabrics described in the present invention provide rate and latency guarantees from input ports to output ports. End-to-end guaranteed bandwidth, ie, bandwidth from any input port to any output port, is given based on the input queue to output queue allocation shown in Table 1. Guaranteed constant latency is provided for packets from multiple input ports to any output port. Since each input port switches packets to the assigned output queue in its destination output port, a packet from one input port does not interfere with another packet from a second input port that switches to the same output port, and therefore Enforce packet latency guarantees from all input ports. The switching time of the switch fabric determines the latency of packets in each flow, and further determines the latency of packet segments in each packet.

FIG. 5A shows an implementation of act 44 of the arbitration and scheduling method 40 of FIG. 1B. Scheduling r ² pieces of packets are executed by act 44. In act 44A, it is checked whether there are more packets to schedule. If there are more packets to schedule, ie if all r ² packets are not scheduled, control passes to act 44B. In act 44B, an open path through one of the two interconnected networks in the intermediate stage is selected by searching through r scheduling times. The packet is scheduled at act 44C via the selected path and the selected scheduling time. At 44D, the selected first and second internal links are marked as selected, and no other packet can select these links at the same scheduling time. Control then returns to act 44A so that act 44A, 44B, 44C, and 44D are executed in a loop to schedule each packet.

FIG. 5B is a low-level flowchart of a variation of Act 44 of FIG. 5A. Act 44A transfers control to Act 44B if there is a new packet request to be scheduled. Act 44B1 assigns the new packet request to c. In Act 44B2, sched_time_1 is assigned to the index variable i. Thereafter, act 44B3 checks whether i is less than or equal to scheduling time r. If the result is “yes”, control transfers to act 44B4. In Act 44B4, another index variable j is set in the interconnection network 1. Act 44B5 checks whether j is either interconnect network 1 or 2. If the result is “yes”, control transfers to act 44B6. Act 44B6 checks whether packet request c does not have a first internal link available for interconnect network j at scheduling time i. If the result is “no”, act 44B7 checks whether the interconnection network j does not have a second internal link available to the destination output port of packet request c at scheduling time i. If the result is “no”, control is transferred to Act 44C. At act 44C, the packet request c is scheduled via interconnect network j at scheduling time i, after which the first and second internal links correspond to interconnect network j at scheduling time i at act 44D. , Marked as used. Thereafter, control is transferred to Act 44A. In either Act 44B6 or Act 44B7, if the result is “yes”, control is transferred to Act 44B9, j is incremented by 1, and control is transferred to Act 44B5. If the result is “NO” in Act 44B5, control is transferred to Act 44B10. Act 44B10 increases i by 1, and control passes to Act 44B3. The result of act 44B3 is never “no”, which means that in r scheduling times, packet request c is guaranteed to be scheduled. The act 44B includes two loops. The inner loop consists of Acts 44B5, 44B6, 44B7, and 44B9. The outer loop consists of Acts 44B3, 44B4, 44B5, 44B6, 44B7, 44B9, and 44B10. Act 44, until all r ² pieces of packet requests are scheduled, is repeated for all the packets.

The following method shows pseudo code for one implementation of scheduling method 44 of FIG. 5A. This pseudo code uses r ² speedups of intermediate stage 130 in the switch fabric in FIGS. 4A-4F (due to 2 interconnected networks or 2 speedups of clock speed and link speed). Scheduling of packets strictly in a non-blocking manner.

Pseudo code for scheduling method:
Step 1: For each packet request to be scheduled do {
Step 2: c = Request packet schedule;
Step 3: for i = shed_time_1 to sched_time_r do {
Step 4: for j = inter_conn_net_1 to inter_conn_net_2 do {
Step 5: if (c has no first internal link available for j) continue;
Step 6: elseif (j has no second internal link available for destination output port of c) continue;
Step 7: else {
Scheduling c via interconnection network j at scheduling time i;
Marking links used to and from interconnection network j as unavailable;
}
}
}
}

  Step 1 starts a loop that schedules each packet. Step 2 labels the current packet request as “c”. Step 3 starts the second loop and goes through all r scheduling times. Step 4 starts the third loop and goes through the two interconnected networks. If the input port of packet request c does not have a first internal link available to interconnect network j at scheduling time i at step 5, control passes to step 4 where the next interconnect network is assigned i. Choose as. Step 6 checks whether the destination output port of packet request c does not have a second internal link available from interconnect network j at scheduling time i, and if so, control passes to step 4 and then Select i as the interconnection network. In step 7, a packet request c is set up via the interconnect network j at scheduling time i. The first and second internal links for interconnect network j at scheduling time i are marked unavailable for future packet requests. These steps are repeated for all two interconnected networks at all r scheduling times until an available first and second internal link is found. In accordance with the present invention, one interconnect network at one of the r scheduling times can always be found, through which the packet request c is scheduled. It is easy to understand that the number of steps to execute the scheduling method is proportional to s * r. Here, s is a speedup equal to 2, r is the number of scheduling times, and therefore the scheduling method is the time complexity O (s * r).

  Table 3 shows how steps 1-8 of the pseudo code above implement the flowchart of the method shown in FIG. 5B in one particular implementation.

  In the scheduling of strictly non-blocking switch fabrics, packet requests from the input queue to the output queue are scheduled so that the path through the interconnect network is discovered and the request is satisfied without obstructing the path of the already scheduled packet It is always possible, and if one or more such paths are available, any of them can be selected without worrying about scheduling the remaining packet requests. In strictly non-blocking networks, the cost of switch hardware is increased, but the time required to schedule packets is reduced compared to a relocatable non-blocking switch fabric. A strictly non-blocking switch fabric embodiment with 2 speedups in the intermediate stage uses the scheduling method 44 of FIG. 5A with time complexity O (s * r), and the switch fabric 10 and FIG. It is shown in the 1I switch fabric 16.

  In a relocatable non-blocking switch fabric, switch hardware costs are reduced at the cost of increased time required to schedule packets. Scheduling time increases in relocatable non-blocking networks. This is because, in addition to scheduling new packets, it is necessary to reschedule the paths of already scheduled packets that have been disturbed to implement relocation. For this reason, when scheduling new packets, it is desirable to minimize or eliminate the need to relocate already scheduled packets. When the need for relocation is eliminated, the network is strictly non-blocking, depending on the number of intermediate stage interconnect networks and the scheduling method. One embodiment of a relocatable non-blocking switch fabric that does not use speedup in an intermediate stage is shown in switch fabric 18 of FIG. 1N. Arbitration of request generation, authorization issuance, and approval generation is performed in a single iteration, regardless of whether the switch fabric operates strictly in non-blocking or relocatable non-blocking. Please note that.

  Applicants have made a few considerations regarding switches queued in the output queue. Applicant points out that a switch queued in the output queue congests the output port by immediately sending packets received at the input port to the destination output queue. For example, in an r * r OQ switch, if all input ports enter the same output port, the output port will receive r more packets than the output port designed to receive. Output port congestion creates the following unnecessary problems: 1) Additional packet prioritization and management is required in the output port 2) Extremely difficult to implement rate guarantee 3) The rate of each packet transmitted from the output port is reduced 4) Eliminating traffic congestion at the output port requires that packets be dropped randomly within the input port 5) All these factors lead to additional traffic management costs, power and memory requirements. Inherently, output queuing eliminates packet switching only locally by forwarding packets across the fabric, but the goal of deterministic flow of traffic at 100% throughput in a network device cannot be achieved. .

  Applicants now describe how the output ports in the VOQ switch fabric can potentially be congested. 6A and 6B show the state of the switch fabric 10 of FIG. 1A after each switching time, fully using speedup. That is, using speedup in the interconnect network in the intermediate stage, packets are sent at twice the rate that the output port can send by packets. FIG. 6A shows the state of the switch fabric 10 of FIG. 1A after a first switching time when packets A1, D1, E1, F1, J1, K1, O1, and P1 are switched to the output queue. The packet A1 from the input port 151 is switched to the output queue 181 of the output port 191 via the crossbar network 131. The packet D1 from the input port 151 is switched to the output queue 181 of the output port 194 via the crossbar network 132. The packet E1 from the input port 152 is switched to the output queue 182 of the output port 191 via the crossbar network 132. The packet F1 from the input port 152 is switched to the output queue 182 of the output port 192 via the crossbar network 131. The packet J1 from the input port 153 is switched to the output queue 183 of the output port 192 via the crossbar network 132. The packet K1 from the input port 153 is switched to the output queue 183 of the output port 193 via the crossbar network 131. The packet P1 from the input port 154 is switched to the output queue 184 of the output port 194 via the crossbar network 131. The packet O1 from the input port 154 is switched to the output queue 184 of the output port 193 via the crossbar network 132. Obviously, at the first switching time, two packets are switched from each input port and each output port receives two packets.

  FIG. 6B shows the state of the switch fabric 10 of FIG. 1A after a second switching time in which packets B1, C1, G1, H1, I1, L1, M1, and N1 are switched to the output queue. The packet B1 from the input port 151 is switched to the output queue 181 of the output port 192 via the crossbar network 131. The packet C1 from the input port 151 is switched to the output queue 181 of the output port 193 via the crossbar network 132. The packet G1 from the input port 152 is switched to the output queue 182 of the output port 193 via the crossbar network 131. The packet H1 from the input port 152 is switched to the output queue 182 of the output port 194 via the crossbar network 132. The packet I1 from the input port 153 is switched to the output queue 183 of the output port 191 via the crossbar network 132. The packet L1 from the input port 153 is switched to the output queue 183 of the output port 194 via the crossbar network 131. The packet M1 from the input port 154 is switched to the output queue 184 of the output port 191 via the crossbar network 131. The packet N1 from the input port 154 is switched to the output queue 184 of the output port 192 via the crossbar network 132. Again, at the second switching time, two packets are switched from each input port, and each output port receives two packets.

  However, it can be said that the output port only transmits one packet at each switching time. Furthermore, each input port receives only one packet at each switching time. Therefore, if there is not enough output queue area in the output port for the third and fourth switching times, the output port cannot receive a plurality of packets. Even if there is enough area, it cannot be sustained, and at some point the output queue area is full and switching from the input port must stop until the output port is cleared. Thus, full use of the speedup is not sustainable and creates unnecessary congestion at the output port.

  Furthermore, in accordance with the present invention, because the switch fabric operates in a non-blocking manner, a direct extension of the speedup required in the intermediate stage 130 can be achieved by adding additional control bits before the packet is switched to the output port. Proportionally adjusted by number. For example, if an additional control bit of 1% is added to any packet or packet segment that should be switched from input port to output port (these control bits switch packets from input port to output port The speedup required for the switch fabric in the intermediate stage 130, which is introduced only to do so, is 2.01 to operate strictly in a non-blocking manner and operates in a relocatable non-blocking manner 1.01 for this purpose.

  Similarly, when a packet is segmented and switched to an output port according to the present invention, the last packet segment may or may not be the same as that packet segment. Alternatively, if the packet size is not a perfect multiple of the packet segment size, the switch fabric throughput is less than 100%. If the last packet segment is often smaller than the size of that packet segment, the speedup in the intermediate stage needs to increase proportionally for the system to operate at 100% throughput.

  The present invention for non-blocking and deterministic switch fabrics can be directly extended to any number of input queues. That is, two or more input queues in each input port switch to two or more output queues in the destination output port and maintain a set of different unicast flows or unicast microflows in all input ports Each incoming queue provides one flow of QoS with rate and latency guarantees. End-to-end guaranteed bandwidth can be provided for multiple unicast flows to any destination output port, ie in different input queues of the input port. In addition, guaranteed constant latency is provided for packet flows from multiple input queues within an input port to any destination output port. Although each input queue within an input port maintains a different flow, packets are switched to the same destination output port, so longer packets from one input queue are the same for the same input port that switches to the same destination output port. 2 Do not block small separate packets from the input queue. Therefore, the packet flow latency guarantee from the input port is enforced. Here, the switching time of the switch fabric determines the packet latency in each flow, and also determines the packet segment latency in each packet.

  By increasing the number of flows that are switched separately from the input queue to the output port, end-to-end guaranteed bandwidth and latency can also be provided for fine-grained flows. In addition, each flow can be formed independently, and if necessary, tail-drop packets from the desired flow under oversubscription and provide a service provider to guarantee rate and latency. Can be formed by providing a separate flow and thus allowing additional revenue opportunities.

Numerous modifications and adaptations of the embodiments, implementations, and examples described herein will be apparent to those of skill in the art upon reviewing the present disclosure.

  The embodiments described in the present invention are also directly useful in parallel computers, video servers, load balancer applications, and grid computing applications. Furthermore, the embodiments described in the present invention are directly useful in hybrid switches and routers for switching both circuit-switched time slots and packet-switched packets or cells.

  Many such modifications and adaptations are encompassed by the appended claims.

FIG. 4 is an illustration of an exemplary 4 × 4 port switch fabric having input and output unicast queues with short packets and 2 speedups in a crossbar based interconnect network in accordance with the present invention. 4 is a high level flowchart of an arbitration and scheduling method 40 used to switch packets from an input port to an output port in accordance with the present invention. 1B is a diagram of a similar three-stage network in the scheduling of the switch fabric 10 of FIG. 1A. FIG. FIG. 1B shows the state of the switch fabric of FIG. 1A after non-blocking, deterministic packet switching in 5 consecutive switching times according to the present invention. FIG. 1B shows the state of the switch fabric of FIG. 1A after non-blocking, deterministic packet switching in 5 consecutive switching times according to the present invention. FIG. 1B shows the state of the switch fabric of FIG. 1A after non-blocking, deterministic packet switching in 5 consecutive switching times according to the present invention. FIG. 1B shows the state of the switch fabric of FIG. 1A after non-blocking, deterministic packet switching in 5 consecutive switching times according to the present invention. FIG. 1B shows the state of the switch fabric of FIG. 1A after non-blocking, deterministic packet switching in 5 consecutive switching times according to the present invention. FIG. 4 is an illustration of an exemplary 4 × 4 port switch fabric having input and output unicast queues with long packets and two speedups in a crossbar-based interconnect network in accordance with the present invention. FIG. 2 illustrates the state of the switch fabric 16 of FIG. 1I after non-blocking, deterministic packet switching without packet segmentation and reassembly after four consecutive fabric switching cycles in accordance with the present invention. FIG. 2 illustrates the state of the switch fabric 16 of FIG. 1I after non-blocking, deterministic packet switching without packet segmentation and reassembly after four consecutive fabric switching cycles in accordance with the present invention. FIG. 2 illustrates the state of the switch fabric 16 of FIG. 1I after non-blocking, deterministic packet switching without packet segmentation and reassembly after four consecutive fabric switching cycles in accordance with the present invention. FIG. 2 illustrates the state of the switch fabric 16 of FIG. 1I after non-blocking, deterministic packet switching without packet segmentation and reassembly after four consecutive fabric switching cycles in accordance with the present invention. FIG. 3 is an illustration of an exemplary 4 × 4 port switch fabric with input and output unicast queues and no speedup in a crossbar based interconnect network in accordance with the present invention. FIG. 4 is an illustration of an exemplary 4 × 4 port switch fabric with an input unicast queue and 2 speedups in a crossbar based interconnect network in accordance with the present invention. 2B shows the state of the switch fabric 20 of FIG. 2A after non-blocking, deterministic packet switching in 5 consecutive switching times, in accordance with the present invention. FIG. 2B shows the state of the switch fabric 20 of FIG. 2A after non-blocking, deterministic packet switching in 5 consecutive switching times, in accordance with the present invention. FIG. 2B shows the state of the switch fabric 20 of FIG. 2A after non-blocking, deterministic packet switching in 5 consecutive switching times, in accordance with the present invention. FIG. 2B shows the state of the switch fabric 20 of FIG. 2A after non-blocking, deterministic packet switching in 5 consecutive switching times, in accordance with the present invention. FIG. 2B shows the state of the switch fabric 20 of FIG. 2A after non-blocking, deterministic packet switching in 5 consecutive switching times, in accordance with the present invention. FIG. FIG. 4 is an illustration of an exemplary 4 × 4 port switch fabric having input and output unicast queues and a 2 speed up in link and clock speeds in a crossbar based interconnect network in accordance with the present invention. FIG. 3 is a diagram of an exemplary 4 × 4 port switch fabric with input and output unicast queues and two speedups in a shared memory based interconnect network in accordance with the present invention. FIG. 4 is an illustration of an exemplary 4 × 4 port switch fabric having input and output unicast queues and a two speed up in link and clock speeds in a shared memory based interconnect network in accordance with the present invention. FIG. 4 is an illustration of an exemplary 4 × 4 port switch fabric with input and output unicast queues and two speedups in a hypercube based interconnect network in accordance with the present invention. FIG. 3 is an illustration of an exemplary 4 × 4 port switch fabric having input and output unicast queues and a two speed up in link and clock speeds in a hypercube based interconnect network in accordance with the present invention. FIG. 3 is a diagram of a typical r * r port switch fabric with input and output unicast queues and two speedups in a crossbar based interconnect network in accordance with the present invention. FIG. 4 is a diagram of a generic r * r port switch fabric with input and output unicast queues and a 2 speed up in link and clock speeds in a crossbar based interconnect network in accordance with the present invention. FIG. 3 is a diagram of a generic r * r port switch fabric with input and output unicast queues and two speedups in a shared memory based interconnect network in accordance with the present invention. FIG. 3 is a diagram of a generic r * r port switch fabric with input and output unicast queues and a 2 speed up in link and clock speeds in a shared memory based interconnect network in accordance with the present invention. FIG. 2 is a diagram of a typical r * r port switch fabric with input and output unicast queues and two speedups in a three stage cross network based interconnect network in accordance with the present invention. FIG. 3 is a diagram of a typical r * r port switch fabric with input and output unicast queues and a two speed up in link and clock speeds in a three stage cross network based interconnect network in accordance with the present invention. . FIG. 3 illustrates in detail a 4 × 4 port (rank 2) hypercube-based interconnect network in one embodiment of an intermediate stage interconnect network 131 or 132 in switch fabric 70 of FIG. 3D and switch fabric 80 of FIG. 3E. It is. FIG. 1D illustrates an intermediate level implementation for act 44 of the arbitration and scheduling method 40 of FIG. 1C. 5B is a low-level flowchart for one variation of Act 44 of FIG. 5A. 1B is a diagram illustrating the state of the switch fabric 10 of FIG. 1A after switching packets using maximum speedup in two consecutive switching times. FIG. 1B is a diagram illustrating the state of the switch fabric 10 of FIG. 1A after switching packets using maximum speedup in two consecutive switching times. FIG.

Claims (112)

A system for scheduling unicast packets via an interconnection network having a plurality of input ports and a plurality of output ports, wherein each of the packets has a designated output port, the system comprising:
A plurality of input queues at each of the input ports, the input queue having an input queue having unicast packets;
Means for requesting service from the designated output port for each input port for at most as many packets as there are input queues at each input port;
Each output port allows a plurality of requests;
Means for each input port to approve at most as many permissions as the input queue;
Means for scheduling at most as many packets as there are input queues from each input port having an approved permission to each output port associated with the approved permission. A plurality of output queues at each output port, wherein the output queues receive output unicast packets via the interconnect network;
Means for each output port to grant at most as many requests as the output queue;
Scheduling at most as many packets as the number of input queues from each input port with approved grants and at most as many as the number of output queues to each output port associated with approved grants The system of claim 1, further comprising:   The system of claim 1, wherein the interconnect network is a non-blocking interconnect network.   The system of claim 3, wherein the non-blocking interconnect network comprises at least two speedups. The speed up is
Means of parallelism, ie means for physically replicating said interconnection network at least twice and connecting by means of separate links from said each input port and each said output port; or
Realized by means of speedup at least twice in the link bandwidth between the input port and the interconnect network, between the output port and the interconnect network, and also in the clock speed of the interconnect network The system according to claim 4, wherein: 5. The unicast packet path is always selectable through the non-blocking interconnect network by never changing the already selected path for another unicast packet. The system described in
The system, hereinafter referred to as the “strict non-blocking network”.   The system of claim 3, wherein the non-blocking interconnect network comprises at least one speedup. The unicast packet path can be always selected via the non-blocking interconnection network by changing an already selected path of another unicast packet, if necessary. 7. The system according to claim 7,
The system, hereinafter referred to as the “relocatable non-blocking network”.   The system of claim 1, further comprising a memory coupled to the scheduling means for holding a schedule of the packets already scheduled.   The system of claim 2, further comprising a memory coupled to the scheduling means for holding a schedule of the packets already scheduled.   Arbitration, that is, executing the request for the service by the input port, the permission for the request by the output port, and the approval of the permission by the input port in only one iteration. The system of claim 1.   Arbitration, that is, executing the request for the service by the input port, the permission for the request by the output port, and the approval of the permission by the input port in only one iteration. The system according to claim 2.   The system of claim 1, wherein the packets are substantially the same size.   The system of claim 1, wherein head of line blocking at the input port is completely eliminated.   The scheduling means schedules at most one packet at each switching time from each input queue having an approved grant to each output port associated with the approved grant. The system of claim 1.   The scheduling means includes, at switching time, at most one packet from each input queue having an approved grant and at most one packet to each output queue associated with the approved grant. The system according to claim 2, wherein the system is scheduled. As long as there is at least one packet, each output port is operative to receive at least one packet from any one of the input queues destined for that output port at switching time. The system of claim 1, wherein
Hereinafter, the system will be referred to as a “process conservation system”. As long as there is at least one packet, each output port is operative to receive at least one packet from any one of the input queues destined for that output port at switching time. The system according to claim 2, wherein
Hereinafter, the system will be referred to as a “process conservation system”. Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. Yes,
2. The system of claim 1, wherein the speedup is thereby utilized only to operate the interconnect network in a deterministic manner and the output port is never congested. Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. Yes,
3. The system of claim 2, wherein the speedup is thereby utilized only to operate the interconnect network in a deterministic manner and the output port is never congested. Packets from one of the input queues are always deterministically switched to the destination output port in the same path as they are received by the input port on the same path through the interconnect network, never Works to avoid packet sequencing issues,
2. The system of claim 1, wherein the switching time is variable at design time and provides room for selecting the switching time such that multiple bytes are switched at each switching time. Packets from one of the input queues are sent to one of the output queues in the destination output port in the same order as they are received by the input port on the same path through the interconnect network. Always switched deterministically and does not require segmentation of the packets in the input port nor reassembly of the packets in the output port, and never operates to cause packet sequencing problems;
3. The system according to claim 2, wherein the switching time is variable at the time of design and provides a room for selecting the switching time so that a plurality of bytes are switched at each switching time. 2. The operation according to claim 1, wherein any of the packets at the head of each of the input queues is operated so as not to be held beyond the same number of switching times as the number of input queues in each of the input ports. System,
Hereinafter, the system will be referred to as a “fair system”. 3. The operation according to claim 2, wherein any one of the packets at the head of each of the input queues is operated so as not to be held more than the same number of switching times as the number of input queues in each of the input ports. System,
Hereinafter, the system will be referred to as a “fair system”.   The system of claim 1, wherein the interconnect network is a crossbar network, a shared memory network, a cross network, a hypercube network, or any internal non-blocking interconnect network, or a network of networks.   The system of claim 1, wherein the system operates at 100% throughput.   The system of claim 2, wherein the system operates at 100% throughput.   The system of claim 1, wherein the system provides end-to-end guaranteed bandwidth from any input port to any output port.   The system of claim 2, wherein the system provides end-to-end guaranteed bandwidth from any input port to any output port.   The system of claim 1, wherein the system provides guaranteed constant latency for packets from multiple input ports to any output port.   3. The system of claim 2, wherein the system provides guaranteed constant latency for packets from multiple input ports to any output port.   The system of claim 1, wherein the system does not require a buffer in the interconnect network and is therefore a cut-through architecture.   The system of claim 2, wherein the system does not require a buffer in the interconnect network and is therefore a cut-through architecture. In a method for scheduling unicast packets via an interconnection network having a plurality of input ports and a plurality of output ports, each input port comprises a plurality of input queues, each packet having at least one designated output. Said method comprising a port, said method comprising:
Requesting service from each designated input port from the designated output port for at most as many packets as there are input queues in each input port;
Allowing a plurality of requests to each output port;
Approving each input port with at most as many permissions as the number of input queues;
Scheduling said packet at most as many as the number of input queues from said input port having an approved permission to each said output port associated with said approved permission. . A plurality of output queues for each output port;
Granting requests for each output port at most as many as the number of output queues at the output port;
Scheduling at most as many packets as the number of input queues from each input port with approved grants and at most as many as the number of output queues to each output port associated with approved grants The method of claim 34, further comprising the step of:   35. Arbitration, that is, the request for the service by the input port, the permission of the request by the output port, and the approval of the permission by the input port are executed only once. The system described in.   36. The arbitration, that is, the request for the service by the input port, the permission of the request by the output port, and the approval of the permission by the input port are executed only once. The system described in.   The method of claim 34, wherein the packets are substantially the same size.   35. The method of claim 34, wherein head of line blocking is completely eliminated at the input port.   The scheduling means schedules at most one packet at each switching time from each input queue having an approved grant to each output port associated with the approved grant. 35. The method of claim 34.   The scheduling means includes, at switching time, at most one packet from each input queue having an approved grant and at most one packet to each output queue associated with the approved grant. 36. The method of claim 35, wherein:   Each output port operates to receive at least one packet from any one of the input queues destined for that output port as long as there is at least one packet at switching time. 35. The method of claim 34, wherein:   Each output port operates to receive at least one packet from any one of the input queues destined for that output port as long as there is at least one packet at switching time. 36. The method of claim 35. Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. ,
35. The method of claim 34, whereby the speed up in the interconnect network is only utilized to operate the interconnect network in a deterministic manner, and the output port is never congested. Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. ,
36. The method of claim 35, whereby the speedup is only used to operate the interconnect network in a deterministic manner and the output port is never congested. Packets from one of the input queues are always deterministically switched to the destination output port in the same path as they are received by the input port on the same path through the interconnect network, never Works to avoid packet sequencing issues,
35. The method according to claim 34, wherein the number of times of switching becomes a variable at the time of design, giving room to select the number of times of switching so that a plurality of bytes are switched at each switching time. Packets from one of the input queues are sent to one of the output queues in the destination output port in the same order as they are received by the input port on the same path through the interconnect network. Always switched deterministically and does not require segmentation of the packets in the input port nor reassembly of the packets in the output port, and never operates to cause packet sequencing problems;
36. The method of claim 35, wherein the number of times of switching becomes a variable at design time and provides room for selecting the number of times of switching so that a plurality of bytes are switched at each switching time.   35. The method of claim 34, wherein the packet at the beginning of each input queue is operative not to be held beyond the same number of switching times as the number of input queues at each input port. .   36. The method of claim 35, wherein the packet at the beginning of each input queue is operative not to be held beyond the same number of switching times as the number of input queues at each input port. .   The method of claim 34, wherein the method schedules with 100% throughput.   36. The method of claim 35, wherein the method schedules with 100% throughput.   The method of claim 34, wherein the method operates to provide end-to-end guaranteed bandwidth from any input port to any output port.   36. The method of claim 35, wherein the method operates to provide end-to-end guaranteed bandwidth from any input port to any output port.   The method of claim 34, wherein the method operates to provide a guaranteed constant latency of packets from multiple input ports to any output port.   36. The method of claim 35, wherein the method operates to provide a guaranteed constant latency of packets from multiple input ports to any output port. A system for scheduling unicast packets over an interconnect network, the system comprising:
R ₁ input port and r ₂ output port, each packet having a designated output port;
R ₂ input queues comprising the packets at each of the r ₁ input ports;
said interconnect network comprising s ≧ 1 sub-networks, each sub-network having a total of at least one link connected to each input port for at least r ₁ first internal links (hereinafter, Each subnetwork further comprising at least one link connected to each output port for a total of at least r ₂ second internal links (hereinafter “second internal links”). Said interconnect network comprising a link);
Means for each input port to request service from the designated output port for at most r ₂ packets from each input port;
Each output port allows a plurality of requests;
Means for each of said input ports to approve permission of at most r ₂ packets;
Means for scheduling at most r ₁ packets to each of the output ports associated with the approved grant, having an approved grant at each switching time to be switched in at most r ₂ switchings; A system characterized by comprising. R ₁ output queues at each of the r ₂ output ports, the output queues receiving unicast packets via the interconnect network;
s ≧ 1 subnetworks, each subnetwork having a total of at least one link connected to each input port for at least r ₁ first internal links (hereinafter “first internal links”) Each sub-network further comprises at least one link connected to each output port for a total of at least r ₂ second internal links (hereinafter referred to as “second internal links”). The interconnection network;
Means for allowing each output port to accept at most r ₁ packets;
When r ₁ ≦ r ₂ , at most r ₁ packets in each switching time to be switched in at most r ₂ times switching, and when r ₂ ≦ r ₁ , at most r ₁ in each switching time to be switched in the times of switching, scheduling and r ₂ pieces of packets at most, the most r ₂ pieces of packets of said associated with permissions the approved to each output port has permission approved 57. The system of claim 56, further comprising means for performing.   57. The system of claim 56, wherein the interconnect network is a non-blocking interconnect network. The system

With sub-networks
Furthermore, a path can always be selected for a unicast packet by never changing a path already selected for another unicast packet via the non-blocking interconnection network. 59. The system of claim 58, wherein
Hereinafter, the interconnect network will be referred to as a “strict non-blocking network”. The system comprises s ≧ 1 subnetworks,
Both the first internal link and the second internal link operate at least twice as fast as the peak rate of each packet received in the input queue;
The subnetwork is a system that operates at least twice as fast as the peak rate of each packet received in the input queue;
The system further ensures that a path is always selectable for a unicast packet by never changing the already selected path for another unicast packet via the non-blocking interconnection network. 59. The system of claim 58, comprising:
Hereinafter, the interconnect network will be referred to as a “strict non-blocking network”. The system

With sub-networks
Both the first internal link and the second internal link operate at least as fast as the peak rate of each packet received in the input queue;
The sub-network is a system that operates at least as fast as the peak rate of each packet received in the input queue;
The system further allows a path to be always selected for a unicast packet by changing the already selected path of another unicast packet, if necessary, via the non-blocking interconnection network. 59. The system of claim 58, comprising:
Hereinafter, the interconnect network is referred to as a “relocatable non-blocking network”.   57. The system of claim 56, further comprising a memory coupled to the means for scheduling, wherein the system schedules the already scheduled packet.   58. The system of claim 57, further comprising a memory coupled to the means for scheduling, wherein the system schedules the already scheduled packets.   The arbitration, that is, the request for the service by the input port, the permission for the request by the output port, and the approval of the permission by the input port are executed only once. 56. The system according to 56.   The arbitration, that is, the request for the service by the input port, the permission for the request by the output port, and the approval of the permission by the input port are executed only once. 58. The system according to 57. r ₁ = r ₂ = r and the scheduling means has each approved output at each switching time to be switched in at most r times of switching and each output port associated with the approved grant 57. The system of claim 56, wherein at most r packets are scheduled. r ₁ = r ₂ = r and the scheduling means has each approved output at each switching time to be switched in at most r times of switching and each output port associated with the approved grant 58. The system of claim 57, wherein at most r packets are scheduled.   The system of claim 56, wherein the packets are substantially the same size.   57. The system of claim 56, wherein head-of-line blocking is completely eliminated at the input port.   The scheduling means schedules at most one packet at each switching time from each input queue having an approved grant to each output port associated with the approved grant. 57. The system of claim 56.   The scheduling means includes, at switching time, at most one packet from each input queue having an approved grant and at most one packet to each output queue associated with the approved grant. 58. The system of claim 57, wherein the system is scheduled. As long as there is at least one packet, each output port is operative to receive at least one packet from any one of the input queues destined for that output port at switching time. 57. The system of claim 56, comprising:
Hereinafter, the system will be referred to as a “process conservation system”. As long as there is at least one packet, each output port is operative to receive at least one packet from any one of the input queues destined for that output port at switching time. 58. The system of claim 57, wherein
Hereinafter, the system will be referred to as a “process conservation system”. Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. Yes,
57. The system of claim 56, whereby the speedup is only used to operate the interconnect network in a deterministic manner and the output port is never congested. Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. Yes,
58. The system of claim 57, whereby the speedup is only used to operate the interconnect network in a deterministic manner and the output port is never congested. Packets from one of the input queues are always deterministically switched to the destination output port in the same path as they are received by the input port on the same path through the interconnect network, never Works to avoid packet sequencing issues,
57. The system of claim 56, whereby the number of switchings is a variable at design time and provides room for selecting the number of switchings such that multiple bytes are switched at each switching time. Packets from one of the input queues are sent to one of the output queues in the destination output port in the same order as they are received by the input port on the same path through the interconnect network. Always switched deterministically and does not require segmentation of the packets in the input port nor reassembly of the packets in the output port, and never operates to cause packet sequencing problems;
58. The system according to claim 57, wherein the number of times of switching becomes a variable at the time of design, and gives a room for selecting the number of times of switching so that a plurality of bytes are switched at each switching time. 57. The operation of claim 56, wherein any packet at the beginning of each input queue is not retained beyond the same number of switching times as the number of input queues at each input port. System,
Hereinafter, the system will be referred to as a “fair system”. 58. The operation of claim 57, wherein any packet at the beginning of each input queue is not retained beyond the same number of switching times as the number of input queues at each input port. System,
Hereinafter, the system will be referred to as a “fair system”.   57. The system of claim 56, wherein the interconnect network is a crossbar network, shared memory network, cross network, hypercube network, or any internal non-blocking interconnect network, or network of networks.   The system of claim 56, wherein the system operates at 100% throughput.   58. The system of claim 57, wherein the system operates at 100% throughput.   57. The system of claim 56, wherein the system provides end-to-end guaranteed bandwidth from any input port to any output port.   58. The system of claim 57, wherein the system provides end-to-end guaranteed bandwidth from any input port to any output port.   57. The system of claim 56, providing guaranteed constant latency for packets from multiple input ports to any output port.   58. The system of claim 57, providing guaranteed constant latency for packets from multiple input ports to any output port.   57. The system of claim 56, wherein the system does not require a buffer in the interconnect network and is therefore a cut-through architecture.   58. The system of claim 57, wherein the system does not require a buffer in the interconnect network and is therefore a cut-through architecture. A method for scheduling unicast packets over an interconnect network, comprising:
R ₁ input port and r ₂ output port, each packet having at least one designated output port;
R ₂ input queues comprising the packets at each of the r ₁ input ports;
s ≧ 1 subnetworks, each subnetwork having a total of at least one link connected to each input port for at least r ₁ first internal links (hereinafter “first internal links”) Each sub-network further comprises at least one link connected to each output port for a total of at least r ₂ second internal links (hereinafter referred to as “second internal links”). Said method comprising said interconnect network, said method comprising:
Requesting service to each of the input ports from the designated output port for at most r ₂ of the packets;
Allowing a plurality of requests to each output port;
Approving the request to each input port in at most r ₂ of the packets;
Approving permission for each of said input ports in at most r ₂ packets;
Scheduling at most r ₁ packets to each of the output ports associated with the approved grant having an approved grant at each switching time to be switched in at most r ₂ switchings; Said method comprising the steps of: r ₁ output queue at each of the ₂ output ports, the output queue receiving multirate unicast packets via the interconnect network;
said interconnect network comprising s ≧ 1 sub-networks, each sub-network being connected for at least r ₁ first internal links in total for each input port (hereinafter referred to as Each sub-network is further connected to each output port for a total of at least r ₂ second internal links (hereinafter “second internal links”). An interconnect network comprising "internal links";
Allowing at most r ₁ packets for each output port;
When r ₁ ≦ r ₂ , at most r ₁ to the output port associated with the approved grant having an approved grant at each switching time to be switched in at most r ₂ times switching. The output associated with the approved grant having an approved grant at each switching time to be switched in at most r ₁ switching when r ₂ ≦ r ₁ the method of claim 89, further comprising the step of scheduling with r ₂ pieces of packet number of the port.   Arbitration, that is, executing the request for the service by the input port, the permission for the request by the output port, and the approval of the permission by the input port in only one iteration. 90. The method of claim 89.   Arbitration, that is, executing the request for the service by the input port, the permission for the request by the output port, and the approval of the permission by the input port in only one iteration. The method of claim 90. r ₁ = r ₂ = r and the scheduling means has each approved output at each switching time to be switched in at most r times of switching and each output port associated with the approved grant 90. The method of claim 89, wherein at most r packets are scheduled. r ₁ = r ₂ = r and the scheduling means has each approved output at each switching time to be switched in at most r times of switching and each output port associated with the approved grant The method of claim 90, wherein at most r packets are scheduled.   90. The method of claim 89, wherein the packets are substantially the same size.   90. The method of claim 89, wherein head of line blocking at the input port is completely eliminated.   The scheduling means schedules at most one packet at each switching time from each input queue having an approved grant to each output port associated with the approved grant. 90. The method of claim 89.   The scheduling means includes, at switching time, at most one packet from each input queue having an approved grant and at most one packet to each output queue associated with the approved grant. The method of claim 90, wherein scheduling is performed.   Each output port operates to receive at least one packet from any one of the input queues destined for that output port as long as there is at least one packet at switching time. 90. The method of claim 89, wherein:   Each output port operates to receive at least one packet from any one of the input queues destined for that output port as long as there is at least one packet at switching time. 92. The method of claim 90, wherein: Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. ,
90. The method of claim 89, whereby speedups in the interconnect network are only used to operate the interconnect network in a deterministic manner and the output port is never congested. Each output port is operable to receive at most one packet in switching time, regardless of the speed up in the interconnect network, even if more than one packet is destined for that output port. ,
93. The method of claim 90, whereby the speedup is only used to operate the interconnect network in a deterministic manner, and the output port is never congested. Packets from one of the input queues are always deterministically switched to the destination output port in the same path as they are received by the input port on the same path through the interconnect network, never Works to avoid packet sequencing issues,
90. The system of claim 89, wherein the number of switchings is a variable at design time and provides room for selecting the number of switchings so that multiple bytes are switched at each switching time. Packets from one of the input queues are sent to one of the output queues in the destination output port in the same order as they are received by the input port on the same path through the interconnect network. Always switched deterministically and does not require segmentation of the packets in the input port nor reassembly of the packets in the output port, and never operates to cause packet sequencing problems;
The system according to claim 90, wherein the number of times of switching becomes a variable at the time of design, and gives a room for selecting the number of times of switching so that a plurality of bytes are switched at each switching time.   90. The method of claim 89, wherein the packets at the beginning of each input queue are not retained beyond the same number of switching times as the number of input queues at each input port. .   93. The method of claim 90, wherein the packet at the beginning of each input queue is operative not to be held beyond the same number of switching times as the number of input queues at each input port. .   90. The method of claim 89, wherein the method operates at 100% throughput.   The method of claim 90, wherein the method operates at 100% throughput.   90. The method of claim 89, wherein the method operates to provide end-to-end guaranteed bandwidth from any input port to any output port.   The method of claim 90, wherein the method operates to provide end-to-end guaranteed bandwidth from any input port to any output port.   90. The method of claim 89, wherein the method operates to provide a guaranteed constant latency of packets from multiple input ports to any output port. The method of claim 90, wherein the method operates to provide a guaranteed constant latency of packets from multiple input ports to any output port.

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