JP2007503661A5 - - Google Patents

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Publication number
JP2007503661A5
JP2007503661A5 JP2006533522A JP2006533522A JP2007503661A5 JP 2007503661 A5 JP2007503661 A5 JP 2007503661A5 JP 2006533522 A JP2006533522 A JP 2006533522A JP 2006533522 A JP2006533522 A JP 2006533522A JP 2007503661 A5 JP2007503661 A5 JP 2007503661A5
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JP
Japan
Prior art keywords
read
write unit
address
memory
memory operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006533522A
Other languages
English (en)
Japanese (ja)
Other versions
JP5091481B2 (ja
JP2007503661A (ja
Filing date
Publication date
Priority claimed from US10/458,457 external-priority patent/US7165167B2/en
Application filed filed Critical
Publication of JP2007503661A publication Critical patent/JP2007503661A/ja
Publication of JP2007503661A5 publication Critical patent/JP2007503661A5/ja
Application granted granted Critical
Publication of JP5091481B2 publication Critical patent/JP5091481B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2006533522A 2003-06-10 2004-06-02 リプレイ機構を備えた読み出し／書き込みユニット Expired - Lifetime JP5091481B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/458,457 2003-06-10
US10/458,457 US7165167B2 (en) 2003-06-10 2003-06-10 Load store unit with replay mechanism
PCT/US2004/017096 WO2004111839A1 (en) 2003-06-10 2004-06-02 Load store unit with replay mechanism

Publications (3)

Publication Number Publication Date
JP2007503661A JP2007503661A (ja) 2007-02-22
JP2007503661A5 true JP2007503661A5 (https=) 2012-03-22
JP5091481B2 JP5091481B2 (ja) 2012-12-05

Family

ID=33510583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006533522A Expired - Lifetime JP5091481B2 (ja) 2003-06-10 2004-06-02 リプレイ機構を備えた読み出し／書き込みユニット

Country Status (8)

Country Link
US (1) US7165167B2 (https=)
EP (1) EP1644823B1 (https=)
JP (1) JP5091481B2 (https=)
KR (1) KR101093784B1 (https=)
CN (1) CN100367196C (https=)
DE (1) DE602004010265T2 (https=)
TW (1) TWI352311B (https=)
WO (1) WO2004111839A1 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050228971A1 (en) * 2004-04-08 2005-10-13 Samra Nicholas G Buffer virtualization
US7415597B2 (en) * 2004-09-08 2008-08-19 Advanced Micro Devices, Inc. Processor with dependence mechanism to predict whether a load is dependent on older store
US20100070730A1 (en) * 2008-09-17 2010-03-18 Sebastian Pop Minimizing memory access conflicts of process communication channels
US9996348B2 (en) 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
CN103744800B (zh) * 2013-12-30 2016-09-14 龙芯中科技术有限公司 面向重放机制的缓存操作方法及装置
US11068271B2 (en) 2014-07-28 2021-07-20 Apple Inc. Zero cycle move using free list counts
KR101837817B1 (ko) * 2014-12-14 2018-03-12 비아 얼라이언스 세미컨덕터 씨오., 엘티디. 비순차 프로세서에서 페이지 워크에 따라 로드 리플레이를 억제하는 메커니즘
WO2016097791A1 (en) * 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Apparatus and method for programmable load replay preclusion
US10387320B2 (en) * 2017-05-12 2019-08-20 Samsung Electronics Co., Ltd. Integrated confirmation queues
US10606603B1 (en) * 2019-04-08 2020-03-31 Ye Tao Methods and apparatus for facilitating a memory mis-speculation recovery
US11200062B2 (en) 2019-08-26 2021-12-14 Apple Inc. History file for previous register mapping storage and last reference indication
US10983801B2 (en) * 2019-09-06 2021-04-20 Apple Inc. Load/store ordering violation management
US11416254B2 (en) 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group
US11615043B2 (en) 2020-01-02 2023-03-28 Texas Instruments Incorporated Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems
US11360773B2 (en) 2020-06-22 2022-06-14 Microsoft Technology Licensing, Llc Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching
US11074077B1 (en) * 2020-06-25 2021-07-27 Microsoft Technology Licensing, Llc Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution
US11175917B1 (en) 2020-09-11 2021-11-16 Apple Inc. Buffer for replayed loads in parallel with reservation station for rapid rescheduling
US11983538B2 (en) * 2022-04-18 2024-05-14 Cadence Design Systems, Inc. Load-store unit dual tags and replays

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581719A (en) * 1992-11-12 1996-12-03 Digital Equipment Corporation Multiple block line prediction
US5828868A (en) * 1996-11-13 1998-10-27 Intel Corporation Processor having execution core sections operating at different clock rates
US6385715B1 (en) * 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US5966544A (en) * 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US6163839A (en) * 1998-09-30 2000-12-19 Intel Corporation Non-stalling circular counterflow pipeline processor with reorder buffer
US6484254B1 (en) * 1999-12-30 2002-11-19 Intel Corporation Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses
JP2003519833A (ja) 2000-01-03 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 依存性連鎖の発行および再発行が可能なスケジューラ
US6651161B1 (en) * 2000-01-03 2003-11-18 Advanced Micro Devices, Inc. Store load forward predictor untraining
WO2001061480A1 (en) * 2000-02-14 2001-08-23 Intel Corporation Processor having replay architecture with fast and slow replay paths
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
JP3729064B2 (ja) * 2000-11-29 2005-12-21 日本電気株式会社 データ依存関係検出装置

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