JP2007500936A - Field effect transistor having injection gate electrode with reduced gate depletion, and method of manufacturing the transistor - Google Patents

Abstract

Prior to defining the drain and source regions (208), an implantation mask (220) is formed to effectively separate the gate dopant density from the drain dopant density and the gate dopant density. Further, after removing the implantation mask (220), the lateral dimensions of the gate electrode (205) are defined by well-established sidewall spacer (207) technology. As a result, it offers an advantage in terms of device reduction over conventional methods based on photolithography and anisotropic etching.

Description

  The present invention relates to a configuration of an integrated circuit, and more specifically, an implantation gate region such as an implanted polysilicon gate electrode capable of controlling the implantation concentration independently of the implantation concentration of the drain region and the source region. The present invention relates to the manufacture of field effect transistors.

  The manufacture of integrated circuits requires the formation of a large number of circuit elements in a chip area according to a specific circuit layout. In general, multiple process technologies are used, for example, for microprocessors, storage chips and other logic circuits, CMOS technology is currently the most promising due to its advantageous features regarding processing speed and / or power consumption. It is an approach. In this technique, millions of complementary transistors, N-channel transistors and P-channel transistors, are formed on a suitable substrate. Here, the performance required for future transistors is a so-called SOI device, which is a suitable circuit configuration for a CMOS device that is highly advanced.

  SOI devices are formed in or on relatively thin semiconductor layers. This semiconductor layer is typically silicon (silicon formed in an oxide layer), and this silicon is formed on an insulating layer. According to the insulating structure that completely covers the circuit elements, complete electrical isolation from other circuit elements is achieved. This electrical isolation provides a number of advantages that cannot be readily achieved with conventional CMOS devices formed on large semiconductor substrates. Regardless of the circuit structure, a typical MOS transistor comprises PN junction regions separated from each other by a channel region. This channel region is controlled above the channel region by a gate electrode separated from the channel region by a thin insulating layer. The dimension of the channel region related to the distance between the two PN junction regions, also referred to as the drain and source regions, is referred to as the channel length and represents an excellent design feature of the MOS transistor. By shortening the channel length of the transistor, not only the size of the transistor but also the functional properties are specifically designed, and the desired performance of the transistor can be obtained. At present, a state-of-the-art CMOS device having a clock frequency of 2000 MHz or more employs a gate length of about 0.1 μm and much shorter. While continuous reduction in the size of transistor elements has provided significant advantages in terms of performance and / or power consumption, several issues have been addressed by several advantages brought about by reducing the dimensions of circuit elements. It must be treated so as not to unjustly offset the points. In particular, circuit element configurations having critical dimensions, such as the gate electrode of a transistor element that substantially determines the channel length, require a great deal of effort to be reliable and replicable. For example, forming a gate electrode having a gate length sufficiently shorter than the wavelength of UV radiation used to transfer the layout image from the reticle to the resist formed on the substrate is a very complex process.

  Another difficulty arises from the fact that PN junctions are defined by the properties of the dopant. This dopant property is generated, at least in part, by ion implantation and successive annealing cycles. Typically, as the cross-sectional area becomes smaller, complex implant cycles are required because the reduced feature size requires higher dopant density to compensate for the reduced conductivity. Here, the properties of the vertical and lateral dopants must be accurately controlled to achieve the desired transistor performance. Since implanted dopants are diffused during the manufacturing process with the device at elevated temperature, a thermal budget describing the dopant diffusivity over time meets very stringent requirements. There must be. For example, state-of-the-art transistor devices require very high implantation levels in the drain and source regions. This very high implantation level has also been imparted to the gate electrode that functions as an implantation mask during the implantation cycle in conventional process technology. Here, in particular, in a P-type transistor into which boron is implanted, serious diffusion of boron into the gate insulating layer occurs, resulting in serious reliability restrictions for the device.

  In order to shorten the gate length of the transistor and maintain the desired controllability in the channel conductivity, the problem arises that the PN junction needs to be very shallow. Accordingly, in the SOI device, the thickness of the silicon layer must be reduced accordingly, but this makes it possible to form a highly implanted semiconductor region and a metal silicide region formed in the drain region and the source region. Since the junction surface becomes small, the contact resistance with respect to the drain region and the source region increases.

  A typical conventional process sequence for forming a state-of-the-art SOIMOS transistor will be described using FIGS. 1a-1d to discuss some of the problems in state-of-the-art devices. In FIG. 1a, a transistor 100 includes a substrate 101 on which an insulating layer 102, also referred to as a buried oxide layer, is formed, and a crystalline silicon layer 104. The thickness of the silicon layer 104 is selected according to the overall device dimensions and is specifically adapted to the length of the gate electrode 105 formed on the silicon layer 104 and separated by the gate insulating layer 106. Typically, the gate electrode 105 is composed of polysilicon, and the gate insulating layer 106 is composed of silicon dioxide, silicon oxynitride, or other similar composition. Insulating structure 103 substantially defines the dimensions of the transistor and electrically insulates transistor 100 from adjacent circuit elements. The side spacer 107 is formed on the side surface of the gate electrode 105, and the drain region and the source region 108 having a specific lateral dopant characteristic are formed in the silicon layer 104.

  A typical process sequence for forming the transistor 100 shown in FIG. 1a includes the following processes. The substrate 101 having the insulating layer 102 and the silicon layer 104 may have a desired thickness of the silicon layer 104 or the thickness of the silicon layer 104 obtained by simultaneously polishing and adapting the substrate 101 from the same substrate manufacturer. Obtained with. In this other case, the substrate 101 having the insulating layer 102 and the silicon layer 104 can also be manufactured by well-known wafer-bonding techniques. Thereafter, the insulating structure 103 is formed by using a photolithography technique, an etching technique, a film forming technique, and a polishing technique established in this technical field. Further, a dielectric thin film layer having desired characteristics for the gate insulating layer 106 is then formed by, for example, a state-of-the-art oxidation process and / or film formation process. Thereafter, a polycrystalline silicon layer is formed on the dielectric thin film layer, and this stack is formed by a state-of-the-art photolithography process followed by an anisotropic etch process to obtain the desired gate length, i.e. horizontal in FIG. Patterned to obtain a gate electrode 105 and a gate insulating layer 106 having a length in the direction. Subsequently, a first ion implantation sequence is performed to form an extension of the dopant characteristics for the drain and source regions 108. Here, the polycrystalline silicon gate electrode 105 functions as an implantation mask. Thereafter, the side spacers 107 are formed in accordance with the process definition that two or more spacers are formed sequentially. In addition, an ion implantation cycle is performed to obtain the final required dopant density in the drain and source regions 108. Again, the same dopant dose is applied to the gate electrode 105. Thereafter, an annealing cycle is performed to activate the dopant, and at least partially recrystallize the drain region and the source region 108 damaged by the previous implantation sequence. In the manufacture of P-type transistors, boron is frequently used as a dopant to form drain and source regions 108 that exhibit high diffusivity. Therefore, boron penetration into the gate insulating layer 106 occurs during the implantation cycle and the subsequent annealing cycle, greatly increasing the reliability of the gate insulating layer 106, ie, long-term resistance to electrical breakdown. descend. When the boron implantation rate is very high, the dopant density in the channel region formed between the drain region and the source region 108 may also have an adverse effect.

  FIG. 1b shows a conventional transistor 100 that needs further consideration regarding device scaling. In FIG. 1b, a metal silicide region 109 is formed in the gate electrode 105, and a plurality of associated metal silicide regions 110 are formed in the drain region and the source region 108, respectively. The metal silicide regions 109 and 110 are made of, for example, cobalt silicide that exhibits a resistivity much lower than that of silicon even when implanted at a very high density of a state-of-the-art MOS transistor. However, it is preferable for the metal silicide region 109 to occupy as much space as possible in the gate electrode 105 in order to efficiently reduce the resistivity. The metal silicide regions 109 and 110 include, for example, a process for depositing a refractory metal layer, a first annealing cycle process for forming cobalt monosilicide, a process for selectively removing unreacted cobalt, and an arrow for cobalt monosilicide. It is formed by a common silicidation process that includes converting to ohmic cobalt disilicide. The requirement to increase the thickness of the metal silicide region 109 will completely use the vertical extension of the drain and source regions 108. This vertical extension of the drain and source regions 108, on the other hand, flows through the drain and source regions 108 because the horizontal bottom interface of the metal silicide region 110 is no longer useful for charge carrier movement. When the flowing current flows into the silicide region 110 only through the lateral interface, the contact resistance between the drain region and the source region 108 is increased. Following this, an alternative approach is described using FIG. 1c.

  FIG. 1c shows the transistor 100 before forming the metal silicide region. In FIG. 1c, a silicon region 111 is formed on the drain and source regions 108 and the gate electrode 105 by selective epitaxial growth. Typically, the silicon region 111 is grown after the first implantation step, and the extension of the drain region and the source region 108 is formed. Depending on process requirements, the silicon region 111 is grown to form the drain and source regions 108 before or after the first implantation cycle.

  FIG. 1d shows the transistor 100 after formation of enlarged gate electrodes, drain and source regions 108, and silicide regions 109 and 110 therein. As shown, the silicidation process is controlled until the metal silicide region 110 reaches the slave and source regions 108, but nevertheless the process does not use up the silicon completely. The interface for charge carrier transfer to the channel region is increased. This congested transistor design may avoid some of the problems described with respect to FIG. 1b, but nevertheless lithography and subsequent anisotropic etch processes substantially reduce the gate length. That is, it determines the potential for transistor scaling, resulting in physical gate length constraints caused by conventional photolithography. Further, as pointed out with respect to FIG. 1 a, the dopant density of the gate electrode 105 is directly related to the dopant density in the drain and source regions 108. Here, the dopant density in the drain and source regions 108 can be adjusted to produce minimal contact and minimal sheet resistance in these regions. However, especially for the highly diffusive boron of P-type transistors, the gate dopant density, which leads to inconsistencies in selecting the implantation parameters used to generate the drain / source dopant characteristics, is completely controlled. Thus, dopants that penetrate the gate insulating layer 106 and the channel region below the gate insulating layer 106 must be minimized.

  In view of the above-mentioned challenges, there remains a need for improved techniques that can further scale the gate length without substantially compromising the performance of the transistor, particularly the performance of the P-type transistor.

DISCLOSURE OF THE INVENTION The present invention generally reduces the coupling between gate dopant density and drain and source dopant density, while allowing gate length to be shortened beyond the limits provided by currently useful lithography techniques. It relates to enabling technology.

  According to an exemplary embodiment of the present invention, a method of forming a field effect transistor includes forming an implantation mask over a crystalline semiconductor region, and forming a drain region and a source region using the implantation mask. The drain region and the source region each have an upper surface located on the surface of the crystalline semiconductor region. Thereafter, the implantation mask is removed to expose the surface of the crystalline semiconductor region, and a gate insulating layer is formed on the exposed surface region. A gate electrode is formed on the gate insulating layer, and this gate electrode is implanted.

  According to yet another exemplary embodiment of the present invention, a field effect transistor has a substrate with a semiconductor region formed thereon. The drain region extends in the lateral direction and the height direction, and the source region is disposed so as to extend along the lateral direction and the height direction. Further, the gate electrode extends along the horizontal direction and the height direction. Here, the gate electrode is disposed laterally between the drain region and the source region, and is separated from the semiconductor region by the gate insulating layer. Here, the drain region and the source region extend along the height direction to at least the upper surface of the gate electrode.

  The present invention will be understood by the following detailed description and the accompanying drawings. In this description, the same or equivalent components are denoted by the same or equivalent reference numerals.

  While the invention is susceptible to various modifications and alternative forms, specific forms have been disclosed by way of example in the drawings and will be described in detail below. However, the detailed description set forth herein is not intended to limit the invention to the particular form disclosed, but rather is intended to be within the spirit and scope of the invention as defined by the appended claims. All improvements, equivalents, and alternatives that come in are included.

Modes for Implementing the Invention Hereinafter, exemplary embodiments of the invention will be described.
In order to clarify the content of the present invention, description of all features of the actual configuration is avoided here. In configuring the actual configuration, identify a number of configurations to achieve the practitioner's specific objectives, such as compliance associated with systems that have different configurations, and business related constraints. A decision must be made. Further, such achievement efforts are complex and time consuming, but nevertheless have become routines imposed on those skilled in the art who enjoy the benefit of this disclosure.

  The present invention will be described with reference to the accompanying drawings. While various regions and structures of semiconductor devices are shown in the figures as very precise and unambiguous configurations and features, those skilled in the art understand that these areas and structures are actually not as accurate as shown in the figures. It will be possible. In addition, the relative sizes of the various features and implant regions shown in the figures are exaggerated or reduced relative to the features or regions of the device being manufactured. Nevertheless, the attached drawings are intended to describe and explain illustrative aspects of the present invention. The words and phrases used herein should be understood and interpreted to have the same meaning as the words and phrases understood by those skilled in the art. No special terms or phrases are intended to be implied by the uniform use of the terms or phrases herein. That is, the unified use of terms or phrases herein is not intended to imply definitions that depart from the usual and customary meanings understood by those skilled in the art. To the extent that a term or phrase is intended to have a special meaning, i.e., other than the meaning understood by one of ordinary skill in the art, such special definitions may be questioned in addition to winning directly in the detailed description below. It is clearly defined so that it does not clearly define the special meaning of the term or phrase.

Since SOI circuit structures are currently considered as the most promising candidates for manufacturing state-of-the-art CMOS devices, a detailed description of yet another exemplary form of the present invention will be presented on an SOI substrate. Reference is made to the transistor element formed. However, the essence of the invention can be readily applied to transistor devices formed on large semiconductor substrates such as silicon substrates or other suitable III-V or II-VI semiconductors, for example. You can understand.
Accordingly, the invention is not limited to silicon-based SOI devices unless explicitly indicated in the appended claims.

Still another exemplary configuration is shown in detail with respect to FIGS. 2a-2i.
In FIG. 2 a, the transistor 200 includes a substrate 201. The substrate 201 may include, for example, a silicon substrate or other substrate such as glass, sapphire, and other equivalents. Here, the insulating layer 202 and the substantial crystalline semiconductor layer 204 are formed on the substrate 201. The semiconductor layer 204 is composed of silicon, silicon / germanium, or other suitable semiconductor material. In the following exemplary form, the thickness of the semiconductor layer 204, which is considered to be composed of silicon, is selected to match the requirements of an extremely reduced SOI transistor device. The overall dimensions of transistor 200 are defined by an insulating structure 203 comprised of an insulating material such as, for example, silicon dioxide and / or silicon nitride. An implantation mask 220 having a lateral dimension 221 is formed on the semiconductor layer 204. The implantation mask 220 is similar to the outer shape of the gate electrode to be formed. For the implantation mask 220, a selective etching method can be applied or selected so that the implantation mask 220 can be efficiently removed selectively with respect to the semiconductor layer 204 in a state-of-the-art manufacturing process described later. For example, it is constructed of a suitable material such as silicon dioxide, silicon nitride and other equivalents so that a suitable etch method can be established. In one form, the lateral direction of the implantation mask 220 provides the possibility of dramatically reducing the actual dimensions of the gate electrode without being constrained by the resolution of currently available photolithography techniques. The dimension 221 is selected to exceed the lateral length of the gate electrode, ie, the designed gate length, so that the implantation mask 220 can be easily formed by well-established lithography and anisotropic etch techniques. Is done. In other forms, critical transistor dimensions, i.e., gate length, are within the resolution of currently available lithographic techniques, and the lateral dimensions of implantation mask 220 are substantially the gates that are subsequently formed. Represents the gate length of the electrode.

  A typical process sequence for forming the device 200 shown in FIG. 2a comprises the following process. After providing the substrate 201 by state-of-the-art wafer bond technology, or after forming the substrate 201, the insulating structure 203 is formed by well-established lithography technology, anisotropic etch technology, deposition (film formation) technology and polishing technology. Is formed. Thereafter, an available implantation sequence is performed to establish the desired vertical dopant characteristics (not shown) for the operation of the transistors in the semiconductor layer 204. Thereafter, a layer made of a suitable insulating material is deposited by, for example, plasma enhanced chemical vapor deposition. The thickness of this layer is set to such an extent that a desired ion blocking effect can be exhibited in a subsequent implantation sequence. For example, when the main component of the dielectric layer is silicon nitride, a thin film silicon dioxide layer is deposited before depositing the silicon nitride, and functions as an etch stop layer in the step of patterning the dielectric layer. As described above, the process of patterning the dielectric layer to form the implantation mask 220 is performed by well established lithographic techniques and anisotropic etch techniques. This is because, in one exemplary form, the lateral dimension 221 and the size in the width dimension of the transistor may exceed the dimensions of the associated gate when attempting to reduce the transistor element extremely. Because there is.

  FIG. 2b exemplarily shows the device 200 where the anisotropic etch process for patterning the implantation mask 220 has been completed and the implantation sequence shown at 222 has been performed. Here, a high dopant density is formed which is laterally defined by the implantation mask 220, ie self-aligned. The dopant density formed in the semiconductor layer 204 represents the desired density of the extension region 208a for the associated source and drain regions to be formed. The implantation sequence 222 may comprise a plurality of implantation steps necessary to achieve the desired dopant characteristics 208a. Here, depending on the lateral dimension 221 of the implantation mask 220, an implantation step may be provided to obtain implanted dopant characteristics that extend under the implantation mask 220 as necessary. In one form, heat treatment is then performed by means of a rapid temperature annealing cycle to recrystallize the amorphous semiconductor region. This amorphous semiconductor region has been damaged in the previous implantation sequence 222. Compared to conventional methods, annealing cycle parameters are selected to recrystallize the semiconductor layer 204 continuously and ultimately. Here, in order to provide the desired lateral expansion of the dopant characteristics 208a, thermal diffusion of the dopant may be performed in advance. Subsequently, the lateral dimension 221 of the implantation mask 220 is determined by the combination of the elevated temperature with the time of the current annealing cycle and the time of the next annealing cycle, similar to the previously performed implantation sequence 222. The dopant characteristics 208a and the desired channel length are designed. The dopant behavior during the associated implantation and annealing steps is calculated by the associated simulation program. The results of this simulation allow for the establishment of appropriate design values for the lateral dimension 221 and the process parameters of the annealing sequence for recrystallization of the implantation sequence 222 and the amorphous semiconductor region.

FIG. 2c is a diagram exemplarily showing the transistor 200 in a later processing step. The transistor 200 includes a semiconductor region 211 epitaxially grown on the semiconductor layer 204.
Since the height of the semiconductor region 211 substantially determines the height of the gate electrode to be formed, the thickness or height of the semiconductor region 211 is selected in view of device requirements. For example, the height of the semiconductor region 2311 is selected in the range of 20-100 nm.

  The epitaxial growth of the semiconductor material on the semiconductor layer (underlying semiconductor layer), for example, is carried out by an established process on the silicon layer, and a detailed description thereof will be omitted. Since the rest of transistor 200 is covered by a dielectric material, the growth in region 211 is limited to the exposed silicon region (not covered by the dielectric). Thereafter, the transistor 200 is further implanted 223 to produce the final required dopant density in the drain region 208 and the source region 208. In other forms, the pre-implantation sequence 222 and associated annealing cycle may be omitted and integrated into the implantation cycle 223. In this case, a low energy implantation sequence due to an increased thickness of the semiconductor region into which the dopant is implanted can be substantially avoided. After this, an annealing sequence is performed, the damage due to implantation is substantially repaired, and the dopant is activated. As a result, dopant diffusion during the anneal cycle, together with the dopant migration obtained during the previous anneal cycle, ultimately forms the required lateral dopant properties and reduces channel length 224. Form. In contrast to conventional methods, the annealing parameters, along with the implantation parameters and the lateral dimension 221 of the implantation mask 220, are optimal for the drain region 208 and the source region 208 without risking adversely affecting other transistor components. Selected to give unique characteristics. Such adverse effects include diffusion of activated dopants in the gate electrode and gate implant layer in conventional methods.

  FIG. 2 d exemplarily shows the transistor 200 with the implantation mask 220 removed and sidewall spacers 207 formed on the inner and outer sidewalls of the semiconductor region 221. Sidewall spacer 207 is comprised of silicon oxide, silicon nitride, and other equivalents. Implant mask 220 is selectively removed by an isotropic etch process. As this isotropic etching process, there is an isotropic dry etching process or an isotropic wet etching process which shows high selectivity with respect to surrounding semiconductor materials without causing inappropriate damage.

  Here, in one form, if the insulating structure 223 does not exhibit high selectivity, for example, a lithography reticle (not shown) used to pattern the implantation mask 220 such that the resist mask exposes the implantation mask 220. The photolithography process performed by the same reticle as that in (1) may be further performed. Thereafter, the implant mask 220 is removed by an associated isotropic etch process with or separately from the resist mask. After removal of the implantation mask 220, preferably after removal of the implantation mask 220 and resist mask, a layer of one or more materials is deposited to a specific thickness, followed by a layer of these one or two layers. Excess portions are removed by an anisotropic etching process to form sidewall spacers 207. Since the related sidewall spacer technology is a well-established technology, its details are omitted. However, since the lateral length 221 of the implantation mask 220 (see FIG. 2c) can be twice as short as the spacer width 207A, the width 207A of the sidewall spacer 207 is sufficiently controllable, and therefore the final The gate length obtained can be determined. Subsequently, when the implantation mask 220 is formed by cutting-edge photolithography, a reduction advantage twice as large as the spacer width 207A can be obtained by a known technique.

  FIG. 2 e is a diagram illustrating the device 200 in a later process, in which a gate insulating layer 206 is formed between the sidewall spacers 207. In the embodiment shown here, the gate insulating layer 206 is formed by an oxidation treatment performed in advance. In this oxidation treatment, part of the semiconductor in the layer 204 and the top of the region 211 are used to form an oxide layer having a desired thickness. In another form, the gate insulating layer 206 may be formed by a well-known volume technique performed in advance.

  FIG. 2f exemplarily shows the transistor 200 and the gate electrode material layer 205A formed thereon. The gate electrode material layer 205A may be made of polysilicon, for example, when the transistor is silicon-based. The polysilicon layer 205A may be deposited by a well-established chemical vapor deposition technique. Here, the thickness of the polysilicon layer 205A is sufficient to fill the space between the regions 211 with the amount of gate electrode material. As long as it is selected. Thereafter, the surplus portion of the polysilicon layer 205A is removed by chemical mechanical polishing (CMP) and / or etching. When the polysilicon layer 205A is substantially removed by etching, it is effective to planarize the upper surface of the layer 205A by chemical mechanical polishing before performing the etching process. In one form, the excess is removed by CMP, where the polishing process is monitored to expose the gate silicon layer 206 on top of the semiconductor region 211. Thereafter, the polishing process is continued, the thin-film gate insulating layer 206 on the top of the semiconductor region 211 is surely removed, and the upper side of the side spacer 207 is planarized.

  FIG. 2g exemplarily shows the transistor 200, and shows a state in which the gate electrode 205 is formed after the surplus portion of the layer 205A is removed by CMP. The planarized portion 207B of the sidewall spacer 207 provides sufficient electrical insulation of the gate electrode 205 with respect to the semiconductor region 211. In another form, if most of the excess portion of layer 205A is removed by etching, the etch process is stopped leaving the gate insulating layer 206 at the top of the semiconductor region 211 (see FIG. 2f) as a clearance. This is followed by a selective etch process to remove the exposed gate insulating layer 206. If this is appropriate, a further semiconductor material etch process is performed to reduce the height of the semiconductor region 211 and the gate electrode 205. As a result, the sidewall spacer 207 ensures sufficient electrical insulation between these semiconductor regions. This is because the height of the gate electrode 205 and the region 211 is sufficiently lower than the top of the sidewall spacer.

  FIG. 2h is a diagram illustrating transistor 200 in which a further ion implantation sequence 225 is performed. This ion implantation sequence is designed to increase the conductivity of the gate electrode 205, while at the same time substantially avoiding any harmful effects known in the prior art. That is, the implantation parameters during the ion implantation sequence 225 are such that the dopant penetration in the gate insulation layer 206 is kept to a minimum and, at the same time, that the gate depletion is minimized. The dopant density in the vicinity of 206 is selected to be increased. The ion implantation sequence 225 is configured to obtain superior gate characteristics instead of obtaining superior drain / source characteristics or compromise characteristics at both the gate and drain / source as in the conventional method. The performance of the transistor can be improved.

  In another form, for example, a resist mask (not shown) is formed using the same lithography reticle used to form the implantation mask 220. This provides a high degree of flexibility in selecting an appropriate dopant for use in the implantation sequence 225. For example, if the transistor device 200 is a P-type semiconductor, the dopant density in the drain region 208 and the source region 208 is formed by boron that exhibits high diffusivity during the implantation process. Accordingly, in some cases, it may be more appropriate to use another dopant of the opposite conductivity type to boron for the gate implant 225. Other dopants, particularly those of the opposite conductivity type, unduly affect the dopant density in region 211, and the additional resist mask substantially blocks ions from entering during implantation sequence 225.

  Thereafter, if the transistor 200 is silicon-based, the silicidation process is performed to increase the conductivity of the region 211 and the gate electrode 205, similar to conventional devices.

  FIG. 2i shows the transistor 200 after the silicidation process is complete. This silicidation process is performed as a self-aligned reaction of silicon with a refractory metal such as cobalt. Subsequently, an unreacted metal removing step and an annealing step for transferring cobalt monosilicide to stable and highly conductive cobalt disilicide are performed. Thus, the metal silicide region 209 is formed into a gate electrode. 205 and the associated metal silicide region 210 in the drain region 208 and the source region 208 are formed.

As a result, the transistor 200 shown in FIG. 2i includes the highly conductive gate electrode 205 having the metal silicide region 209 and the injection portion 205c, and the gate density is optimized by the dopant density of the injection portion 205c. , Dopant penetration into the gate insulating layer 206 is suppressed. On the other hand, the desired high dopant density is established in the drain region 208 and the source region 208 including the semiconductor region 211, where at the same time by the increased interface of the known drain region 208 and source region 208 with the metal silicide region 210. Sufficient charge carrier transport from the metal silicide region 21 to the extension region and channel region of the transistor 200 is provided. Thus, an SOI transistor with a very reduced channel region can be fabricated in a thickness range of about 5-50 nm, which eliminates undue compromise of source-drain contact and sheet resistance.
Furthermore, the effective gate and channel lengths are not limited by the effective resolution of currently existing cutting edge photolithography, and are shortened based on established sidewall spacer technology.

  Still another exemplary configuration is shown with respect to FIGS. 3a-3e. In this mode, the epitaxial growth process described in the above mode is not necessary. Constituent elements similar to those shown in FIGS. 2a to 2i are given the same reference numerals, but the first numerals (numbers in hundreds) of the reference numerals are changed. Also, the description of the same components as those in FIGS. 2a to 2i is omitted.

  In FIG. 3 a, the transistor 300 includes a substrate 301 on which a semiconductor layer 304 covered with an insulating layer 302 and an insulating structure 303 is formed. The resist mask 330 is formed on the semiconductor layer 304 and includes an opening 320 </ b> A having a lateral dimension 321. The opening 320 </ b> A is partially formed in a portion without the semiconductor layer 304, and the opening 320 </ b> A exposes the semiconductor region of the semiconductor layer 304 having a thickness 304 </ b> A required for the channel region of the transistor 300.

  The substrate 301 having the insulating structure 303 is formed by a process similar to that previously described with respect to FIG. The resist mask 330 is formed by lithography, and the same evaluation as described for the implantation mask 220 in FIG. The opening 320A in the semiconductor layer 304 is formed by an anisotropic etch process similar to the process performed in forming the insulating structure 303. Following this, the relevant process technology is well established. It should be noted that the initial thickness of the semiconductor layer 304 is selected to represent the final height of the transistor element 300. Here, the anisotropic etch process is controlled to provide the desired shallow thickness 304A required for proper transistor performance. Since the etch rate of the associated anisotropic etch process is determined very accurately in advance, the etch process is reliably stopped according to the design value of thickness 304A.

  FIG. 3B is a diagram illustrating a transistor 300 having a dielectric layer 320B formed thereon. Here, the thickness of the dielectric layer 320 </ b> B is selected so that the opening 320 </ b> A can be sufficiently embedded in the semiconductor layer 304. The formation of the configuration shown in FIG. 3b is accomplished by removing the resist mask 330 and then depositing layer 320B by a CVD method with a suitable material comprised of, for example, silicon oxide, silicon nitride, and other equivalents. .

  FIG. 3c exemplarily shows the configuration of device 300 after planarizing the top surface of layer 320B to form an implantation mask in opening 320A. As shown in FIG. 3c, the CMP process may be designed to leave a thin layer on the top surface of the semiconductor layer 304, and in other portables, the CMP process substantially completely removes all excess material. May be continued until is removed from the semiconductor layer 304. Thereafter, an ion implantation process 322 is performed to form a portion having a desired ion density over a specific depth 322A. Thanks to the implantation mask 320 formed in the opening 320A, the channel region 340 is substantially unaffected by the implantation sequence 322. Thereafter, the implant mask 320 is removed by a selective etch process designed as an isotropic dry etch process or an isotropic wet etch process. Related selective etch processes are well established in the art. Therefore, the detailed description is abbreviate | omitted. Next, an anneal cycle is performed to recrystallize any amorphous semiconductor regions, and to activate and diffuse the dopants implanted by the previous implantation sequence 322. The annealing cycle parameters are selected to provide the desired dopant transfer into the channel region 340. As a result, a specific channel length is defined. For the appropriate implantation and annealing parameters, the same evaluation as described above with respect to FIGS. 2b and 2c applies, as well as the lateral dimensions of the opening 320A.

  FIG. 3d is a diagram exemplarily illustrating the transistor 300 in a state where the annealing cycle for forming the drain region and the source region 308 is completed. A channel length 324 is defined between the drain region and the source region 308. By removing the implantation mask prior to the annealing process, diffusion from the upper layer into the channel region 340 is substantially suppressed.

  FIG. 3e exemplarily shows the transistor 300 in which the sidewall spacer 307 is formed on the sidewall of the opening 320A and the gate insulating layer 306 is formed over the channel region 340 and the semiconductor region 304. The width of the side wall spacer 307 defines the finally obtained gate length 305B. The gate length 305B is that of the gate electrode formed in the opening 320A. The process sequence for forming the sidewall spacer 307 and the gate insulating layer 306 is the same as previously described with respect to FIGS. 2d and 2e.

  Subsequent processing, i.e., formation of the gate electrode in the opening 320A, including a specifically designed gate implantation cycle, is performed in a manner similar to that already described with respect to FIGS. 2f-2i.

  Following this, the desired thin channel region 340 is formed without the need for an epitaxial growth step. As a result, the complexity of the process can be significantly reduced. Nevertheless, high compatibility with the aforementioned mobile phone is ensured. Omitting the epitaxial growth process results in increased throughput and significantly reduced production costs.

  As a result, the present invention provides a transistor element, particularly an SOI device, having a gate length that is shorter than the associated gate length of presently useful cutting edge devices. Here, the manufacturing process used in the present invention is similar to that well established for manufacturing such presently useful cutting devices. Further, effectively separating the dopant density in the gate electrode from the dopant density in the drain and source regions results in improved channel junction and increased sheet resistance, but at the same time, the gate electrode characteristics are improved. Improved. Thus, the present invention offers the possibility to aggressively shrink transistor elements by using currently well-established manufacturing methods. As is apparent from the above-described embodiments, the present invention is not limited to SOI devices, and its application to SOI devices is very advantageous, but it is also applicable to devices formed on a large semiconductor substrate. It is possible.

The particular forms described above are exemplary only, and the invention is capable of equivalent modifications and implementations of different forms but obvious to those skilled in the art having the benefits suggested herein. For example, the process steps described above can be performed in a different order.
Furthermore, no limitations are intended to the structural or design specifications shown herein, and the invention is defined by the appended claims. Accordingly, the specific forms described above can be substituted or modified, and all such variations are included within the scope and spirit of the invention.
Accordingly, the scope of protection sought by the present invention is defined by the appended claims.

It is a figure which shows illustratively the cross-section of the SOI transistor produced by the conventional method. It is a figure which shows illustratively the cross-section of the SOI transistor produced by the conventional method. It is a figure which shows illustratively the cross-section of the SOI transistor produced by the conventional method. It is a figure which shows illustratively the cross-section of the SOI transistor produced by the conventional method. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. It is a figure which shows the structure of the transistor device in one stage of the manufacturing process of this invention. FIG. 5 is a diagram illustrating the structure of a transistor device in one stage of another form of the invention that does not require epitaxial growth. FIG. 5 is a diagram illustrating the structure of a transistor device in one stage of another form of the invention that does not require epitaxial growth. FIG. 5 is a diagram illustrating the structure of a transistor device in one stage of another form of the invention that does not require epitaxial growth. FIG. 5 is a diagram illustrating the structure of a transistor device in one stage of another form of the invention that does not require epitaxial growth. FIG. 5 is a diagram illustrating the structure of a transistor device in one stage of another form of the invention that does not require epitaxial growth.

Claims (15)

A method of manufacturing a field effect transistor,
Forming an implantation mask 220 on the crystalline semiconductor region 204;
Forming a drain region 208 and a source region 208, each having an upper surface located on the surface of the crystalline semiconductor region, using the implantation mask;
Removing the implantation mask to expose a surface region of the crystalline semiconductor region;
Forming a gate insulating layer 206 on the exposed surface region;
Forming a gate electrode 205 on the gate insulating layer 206; and
Doping the gate electrode 205;
A method comprising:   The step of forming the gate electrode 205 includes a step of depositing a gate electrode material amount on the gate insulating layer 206, and a step of removing excess of the gate electrode to form the gate electrode 205. The method of claim 1, wherein   The method according to claim 1, wherein a lateral size of the implantation mask is larger than a design value of a gate length of the gate electrode.   The method of claim 1, wherein forming the drain region and the source region includes epitaxially growing a crystalline semiconductor layer next to the implantation mask.   A first implantation sequence for forming the drain region and the source region is performed before the semiconductor layer is epitaxially grown, and a second implantation for forming the drain region 208 and the source region 208 after the semiconductor layer is epitaxially grown. The method of claim 4, wherein the sequence is performed.   The method of claim 5, further comprising performing an annealing process to activate the dopant.   The method of claim 6, wherein the annealing process is controlled based on a desired channel length defined by a lateral distance between the drain region and the source region.   The annealing treatment includes a first annealing cycle that is performed after the first implantation sequence is performed and before the second implantation sequence is performed, and the first annealing cycle includes the semiconductor region. The method of claim 7, wherein the method is performed to substantially completely recrystallize the amorphized portion.   The method of claim 3, further comprising forming sidewall spacers 207 on the sidewalls of the drain and source regions 208 exposed by removing the implantation mask 220.   The method of claim 9, wherein the width 207A of the sidewall spacer 207 is controlled based on a target gate length of the gate electrode.   The step of forming the implantation mask 220 includes a step of forming a recess in a semiconductor layer including the crystalline semiconductor region 204, and a step of filling the recess with a mask material to form the implantation mask 220. The method of claim 1 comprising:   The step of filling the concave portion includes a step of depositing the mask material by a thickness sufficient to completely fill the concave portion, and a step of removing surplus by chemical mechanical polishing. The method described.   The method of claim 11, wherein a lateral dimension of the recess is longer than a target gate length of the gate electrode. A substrate on which a semiconductor region 204 is formed;
Drain regions 208 extending in the lateral and height directions,
A source region 208 extending in the lateral direction and the height direction; and
A gate electrode 205 extending in the lateral direction and the height direction;
The gate electrode 205 is disposed laterally between the drain region and the source region, and is separated from the semiconductor region by a gate insulating layer 206. The drain region and the source region are A field effect transistor extending in a height direction to at least the upper surface of the gate electrode.   The gate electrode 205 is at least partially composed of a doped semiconductor material, and the peak density of the dopant in the gate electrode is higher than the peak density of the dopant in the drain region 208 and the source region 208. 15. The field effect transistor according to claim 14, wherein the field effect transistor is low.

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