JP2007335980A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simplified semiconductor integrated circuit device capable of estimating the number of delay cycles for obtaining an appropriate operation result from a combinational logic circuit. <P>SOLUTION: At least one of logic cells has: a standard cell composed of a MIS transistor; a first MIS transistor of a first conductivity type that is provided between the output terminal of a standard cell and a first supply voltage, and sets the standard cell to be in an operation stop state; a second MIS transistor of a second conductivity type that is provided between the standard cell and a second supply voltage, and breaks the leak current of the MIS transistor for composing the standard cell to set the standard cell to be in an operation stop state; a flip-flop circuit to which an output signal from the combinational logic circuit is inputted; a master latch circuit; a data input terminal to which the output signal from the master latch circuit is inputted; and a control terminal to which a clock signal is inputted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a combinational logic circuit.

  Uvighara et al. Show a method for reducing leakage current in ISSCC 2004 Digest of Technical Papers (23.3) Feb, 2004 and Slide Supplements (23.3) [Non-Patent Document 1].

  In the leakage current reducing method disclosed in Non-Patent Document 1, two types of logic cells are prepared: a normal logic cell and a logic cell with a foot switch. A normal logic cell is composed only of a transistor with a high threshold voltage (HVT), but a logic cell with a foot switch is a standard cell composed of a transistor with a low threshold voltage (LVT) and a high threshold (HVT). It is comprised with the foot switch comprised by this transistor.

  At this time, a logic cell with a foot switch can operate at a higher speed than a normal logic cell composed of only transistors with a high threshold voltage, but the leakage current when the foot switch is on is Larger than normal logic cell.

  In Non-Patent Document 1, a combinational logic circuit is configured by mixing these normal logic cells and logic cells with foot switches. At that time, an attempt is made to use a normal logic cell as much as possible, and a logic cell with a foot switch is used only when the speed requirement cannot be satisfied.

  In general, a semiconductor integrated circuit has a plurality of clock domains. The supply of clock signals in the clock domain corresponding to the parts that do not need to be operated is stopped to reduce power consumption. Such a technique is called gated clock or clock gating. ing.

  Control of whether or not to supply a clock signal to a specific clock domain is performed by a control circuit provided in the middle of the clock tree. When the supply of the clock signal is stopped, the combinational logic circuit of the clock domain is also stopped. If this combinational logic circuit has a logic cell with a footswitch, turn this footswitch off. Leakage current can be reduced. In order to turn on / off the foot switch of the logic cell with the foot switch, the control circuit needs to supply the control signal to the foot switch.

  However, if the foot switch of the combinational logic circuit is turned off before the combinational logic circuit finishes the operation, an appropriate operation result may not be obtained. The foot switch is turned off several cycles after the stop, and a clock signal is supplied several cycles after the foot switch is turned on.

  In Non-Patent Document 1, the number of delay cycles is configured to be adjustable afterwards. That is, when designing a combinational logic circuit, it is difficult to predict how long a delay cycle number will be required, which suggests setting the value of the delay cycle number after manufacturing. This is because the setting of the number of delay cycles corresponds to a waiting time during the operation of the integrated circuit, and thus it is desired to make the required minimum length.

As can be seen from these, Non-Patent Document 1 has three main problems. First, a relatively long delay cycle is required for switching between active / standby for supplying / stopping a clock signal, and complicated hardware is required for the control. Second, in the design stage, it is difficult to estimate the number of delay cycles required to obtain an appropriate operation result from the combinational logic circuit, and it is necessary to adjust the number of delay cycles after manufacturing. Third, the number of delay cycles to be set may vary from product to product due to variations in the manufacturing process, and the burden required for the adjustment becomes extremely large.
ISSCC2004 Digest of Technical Papers (23.3) Feb, 2004 and Slide Supplements (23.3)

  Therefore, the present invention has been made in view of the above problems, and provides a semiconductor integrated circuit device capable of estimating the number of delay cycles required to obtain an appropriate operation result from a combinational logic circuit in a design stage. However, an object is to simplify the circuit.

In order to solve the above problems, a semiconductor integrated circuit device according to the present invention provides:
A semiconductor integrated circuit device comprising a combinational logic circuit having one or more logic cells connected in series,
At least one of the logic cells is
An input terminal composed of a MIS transistor, to which an output signal from the previous stage is input as an input signal, and an output terminal that performs a predetermined logical operation based on the input signal and outputs the logical operation result as an output signal A standard cell having
A control terminal is provided between the output terminal of the standard cell and the first power supply voltage and receives a circuit control signal. The standard cell is put into an operation stop state based on the circuit control signal. For this purpose, a first MIS transistor of a first conductivity type that supplies the first power supply voltage to the output terminal of the standard cell;
The standard cell is provided between the standard cell and a second power supply voltage and has a control terminal to which the circuit control signal is input. Based on the circuit control signal, the standard cell is placed in a computation stop state. A second MIS transistor of a second conductivity type that cuts off a leakage current of the MIS transistor constituting the cell;
With
The semiconductor integrated circuit device includes:
A flip-flop circuit to which an output signal from the combinational logic circuit is input;
The flip-flop circuit is
A master latch circuit having a data input terminal to which an output signal from the combinational logic circuit is input, and a control terminal to which an AND signal obtained by ANDing the circuit control signal and a clock signal is input;
A data input terminal to which an output signal from the master latch circuit is input; a control terminal to which the clock signal is input;
It is characterized by providing.

  According to the present invention, it is possible to simplify a circuit while providing a semiconductor integrated circuit device capable of estimating the number of delay cycles necessary for obtaining an appropriate operation result from a combinational logic circuit at a design stage. Can do.

[First Embodiment]
FIG. 1 is a diagram illustrating an example of a circuit configuration of a combinational logic circuit in the semiconductor integrated circuit device according to the present embodiment, and FIG. 2 is a diagram illustrating an operation timing chart of the semiconductor integrated circuit device in FIG.

  As shown in FIG. 1, the clock operation circuit in the semiconductor integrated circuit device according to the present embodiment includes a flip-flop circuit FF10, a combinational logic circuit COM10, and a flip-flop circuit FF11.

  An input signal IN, which is a data signal, is input to the data input terminal D of the flip-flop circuit FF10, and is output as an output signal from the data output terminal Q in synchronization with the clock signal CLK1 input from the clock input terminal. The output signal output from the flip-flop circuit FF10 is input to the combinational logic circuit COM10.

  The combinational logic circuit COM10 performs a predetermined logical operation that is determined in advance, and the logical operation result is output as an output signal from the combinational logic circuit COM10. An output signal from the combinational logic circuit COM10 is input to the data input terminal D of the flip-flop circuit FF11, and is output from the data output terminal Q as the output signal OUT in synchronization with the clock signal CLK2 input from the clock input terminal. .

  As specific operations of the flip-flop circuits FF10 and FF11, when the clock signals CLK1 and CLK2 are switched from the low level to the high level, the data signal input to the data input terminal D is taken in and the data output terminal Q is output as an output signal, but when the clock signals CLK1 and CLK2 are in other states, the output signals are maintained.

  Further, the combinational logic circuit COM10 includes one or a plurality of logic cells in order to perform a predetermined logic operation. For example, the combinational logic circuit COM10 includes four logic cells LC10 to LC13 in FIG. Each logic cell includes a P-type MOS transistor, a logic circuit, and an N-type MOS transistor.

  In each logic cell, when the circuit control signal EN is at a high level, the N-type MOS transistor is turned on, the P-type MOS transistor is turned off, and the logic level of the logic circuit is output to its output terminal. , Input to the logic cell in the subsequent stage. On the other hand, when the circuit control signal EN is at a low level, the N-type MOS transistor is turned off, the P-type MOS transistor is turned on, and the output signal is pulled high regardless of the logic level of the logic circuit. And input to the logic cell in the subsequent stage.

  As shown in FIG. 1, in this embodiment, a P-type MOS transistor PM10, a NAND circuit NA10, and an N-type MOS transistor NM10 constitute one logic cell LC10. The transistor PM11, the NOR circuit NR10, and the N-type MOS transistor NM11 constitute one logic cell LC11. The P-type MOS transistor PM12, the NAND circuit NA11, and the N-type MOS transistor NM12 One logic cell LC12 is configured, and one logic cell LC13 is configured by the P-type MOS transistor PM13, the NAND circuit NA12, and the N-type MOS transistor NM13. As can be seen from this, in the present embodiment, all of the logic cells LC10 to LC13 constitute a logic cell with a foot switch.

  The first reference signal VDD is input to the source terminals of the P-type MOS transistors PM10 to PM13, and the circuit control signal EN is input to these control terminals. The output signal of the flip-flop circuit FF10 and the input signal IN1 are input to the two input terminals of the NAND circuit NA10. The output terminal of the NAND circuit NA10 and the drain terminal of the P-type MOS transistor PM10 are connected to one input terminal of the NOR circuit NR10. The input signal IN2 is input to the other input terminal of the NOR circuit NR10.

  The output terminal of the NOR circuit NR10 and the drain terminal of the P-type MOS transistor PM11 are connected to one input terminal of the NAND circuit NA11. The input signal IN3 is input to the other input terminal of the NAND circuit NA11. The output terminal of the NAND circuit NA11 and the drain terminal of the P-type MOS transistor PM12 are connected to one input terminal of the NAND circuit NA12. The other input terminal of the NAND circuit NA12 is connected to the output terminal of the NAND circuit NA10 and the drain terminal of the P-type MOS transistor PM10.

  The output terminal of the NAND circuit NA12 and the drain terminal of the P-type MOS transistor PM13 are connected to the data input terminal D of the flip-flop circuit FF11. The ground voltage second reference signal GND is input to the source terminals of the N-type MOS transistors NM10 to NM13, and the circuit control signal EN is input to the control terminals. The circuit control signal EN is also input to the control terminals of the P-type MOS transistors PM10 to PM13, respectively. The illustrated COM 10 is an example of a combinational logic circuit, and can be applied to a combinational logic circuit using a general CMOS standard cell.

  As can be seen from FIG. 2, when the clock signals CLK1 and CLK2 are supplied, the circuit control signal EN becomes high level in synchronization with the rising edges, and when the clock signals CLK1 and CLK2 are stopped, This signal becomes a low level in synchronization with the original rising edge. In the present embodiment, an operation enable state in which the circuit control signal EN is at a high level is defined as an active mode, and an operation stop state in which the circuit control signal EN is at a low level is defined as a sleep mode.

  The P-type MOS transistors PM10 to PM13 correspond to the first conductivity type MOS transistors in the present embodiment, and the N-type MOS transistors NM10 to NM13 are the second conductivity type MOS transistors in the present embodiment. It corresponds to. The voltage of the first reference signal VDD input to the source terminals of the P-type MOS transistors PM10 to PM13 corresponds to the first power supply voltage in the present embodiment, and the source terminals of the N-type MOS transistors NM10 to NM13. The voltage of the second reference signal GND input to is equivalent to the second power supply voltage in this embodiment.

  In the present embodiment, each of the NAND circuits NA10 to NA12 and the NOR circuit NR10 is an example of a standard cell that performs a predetermined logical operation, and is configured by a MOS transistor. The NAND circuit can be composed of, for example, a MOS transistor as shown in FIG. In the example of FIG. 3, a NAND circuit is configured by P-type MOS transistors PM20 and PM21 connected in parallel with each other and N-type MOS transistors NM20 and -21 connected in series with each other in series. Has been.

  FIG. 3 illustrates the configuration of the logic cell LC10 including the NAND circuit NA10. For this reason, a pull-up MOS transistor PM10 is provided in parallel with the P-type MOS transistor PM21. A MOS transistor NM10 which is a foot switch is provided between the MOS transistor NM21 and the signal line of the second reference signal GND. As is apparent from this configuration, when the pull-up MOS transistor PM10 is turned on, the output signal becomes high regardless of the logic output of the NAND circuit NA10. Further, when the MOS transistor NM10 that is a foot switch is turned off, the leakage current is cut off regardless of the state of the internal MOS transistor that constitutes the NAND circuit NA10.

  The NOR circuit can be configured by, for example, a MOS transistor as shown in FIG. In the example of FIG. 4, a NOR circuit is constituted by P-type MOS transistors PM30 and PM31 connected in series with each other and N-type MOS transistors NM30 and NM31 connected in parallel with each other in series. Has been.

  FIG. 4 illustrates the configuration of the logic cell LC11 including the NOR circuit NR10. For this reason, a pull-up MOS transistor PM11 is provided in parallel with the P-type MOS transistors PM30 and PM31. A MOS transistor NM11 that is a foot switch is provided between the N-type MOS transistors NM30 and NM31 and the signal line of the second reference signal GND. As is apparent from this configuration, when the pull-up MOS transistor PM11 is turned on, the output signal becomes a high level regardless of the logical output of the NOR circuit NR10. Further, when the MOS transistor NM11 which is a foot switch is turned off, the leakage current is cut off regardless of the state of the internal MOS transistor constituting the NOR circuit NR10.

  The threshold voltages of the MOS transistors NM10 to NM13 are determined based on the MOS transistors PM20, PM21, NM20, NM21 constituting the NAND circuits NA10 to NA12 and the MOS transistors PM30, PM31, NM30, NM31 constituting the NOR circuit NR10. You may comprise so that it may become higher than the threshold voltage of a transistor. With this configuration, it is possible to increase the operating speed of the NAND circuit and the NOR circuit that are standard cells, and to more reliably cut off the leakage current with the N-type MOS transistors NM10 to NM13. In this case, the threshold voltage of the P-type MOS transistors PM10 to PM13 may be the same threshold voltage as that of the N-type MOS transistor NM10, or may be a threshold voltage lower than this.

  Next, the operation of the combinational logic circuit COM10 shown in FIG. 1 will be described in detail with reference to FIG. At this time, it is assumed that the first reference signal (VDD) is at a high level and the second reference signal (GND) is at a low level. Here, it is assumed that the same clock signal CLK is input to CLK1 and CLK2. It is assumed that the first reference signal (VDD) is input to IN1 and IN3, and the second reference signal (GND) is input to IN2.

  First, in the first clock cycle between time T1 and time T2, since the circuit control signal EN is at a high level, the combinational logic circuit COM10 operates in the same manner as a normal logic circuit.

  In the second clock cycle between the next time T2 and time T3, after the clock signal CLK rises, the circuit control signal EN changes from the high level to the low level, and the sleep mode is entered. As a result, the four nodes of the node B, the node C, the node D, and the node E are pulled up by the P-type MOS transistors PM10 to PM13, respectively, and become high level. That is, in the sleep mode, the output signals of the logic cells LC10 to LC13 are at a high level regardless of the outputs of the NAND circuits NA10 to NA12 and the NOR circuit NR10 which are standard cells of the logic cells LC10 to LC13. For this reason, the input signal to the data input terminal D of the flip-flop circuit FF11 is also fixed at a high level.

  In the third clock cycle from the next time T3 to time T4, the low level of the circuit control signal EN is maintained, and the clock gating state in which the supply of the clock signal CLK is stopped is maintained.

  In the fourth clock cycle from the next time T4 to the time T5, immediately after the start of this clock cycle, the circuit control signal EN changes from the low level to the high level and changes to the active mode. When the circuit control signal EN becomes high level, the P-type MOS transistors PM10 to PM13 are turned off and the N-type MOS transistors NM10 to NM13 are turned on, so that the NAND circuits NA10 to NA12, which are standard cells, and the NOR circuit NR10. Operates to perform a predetermined logical operation, and outputs the logical operation result to the output terminal. That is, the nodes A to E sequentially return to the values immediately before entering the sleep mode. In the present embodiment, the value of the node E returns to the value immediately before entering the sleep mode during the fourth clock cycle, that is, before the time T5.

  In the fifth clock cycle from the next time T5 to the time T6, when the clock signal CLK changes from the low level to the high level at the time T5, the flip-flop circuit FF11 has the value of the node E input to the data input terminal D. And output as an output signal OUT from the data output terminal Q. As a result, the flip-flop circuit FF11 takes in the value immediately before entering the sleep mode and can be normally output as the output signal OUT. In addition, the combinational logic circuit COM10 is in a state in which a normal operation synchronized with the clock signal CLK is possible.

  The gate width of the pull-up MOS transistor may be smaller than the gate width of other MOS transistors. This is because, in the active mode, the pull-up MOS transistor remains off, so that the size should be small from the viewpoint of parasitic capacitance. In addition, the size affects the switching time when switching from the active mode to the sleep mode, but since the time may be about the clock cycle, the gate width can be reduced as compared with other MOS transistors.

  Next, the operation of the logic cell in the sleep mode, that is, when the circuit control signal EN is at a low level will be described. For example, the logic cell LC13 formed of a NAND circuit has the circuit configuration shown in FIG. 3, and in the sleep mode, that is, when the circuit control signal EN is at a low level, the input signal 1 (node B) and the input signal 2 (node D). ) Goes high. Further, the output signal (node E) also becomes high level. At this time, the source potential of the MOS transistors NM20 and NM21 is a potential that is lower than the power supply voltage VDD by the threshold voltage of the MOS transistor NM20 (NM21).

  Most of the gate leakage current in the logic cell LC13 flows from the drain of the MOS transistor NM10 to the gate. This is because the potentials of all the terminals of the transistors constituting the NAND circuit are at a high level and there is no potential difference, and the potential difference between the gate and source of the MOS transistors NM20 and NM21 is a small value about the threshold voltage. Further, since the MOS transistor PM10 can be designed with a relatively small gate width as compared with other transistors, the gate leakage current is small.

  Therefore, most of the gate leakage current when the circuit control signal EN is at the low level is in the MOS transistor NM10, and the potential difference between the gate and the drain in the MOS transistor NM10 is not from the power supply voltage VDD but from the power supply voltage VDD. Since the voltage is reduced by the threshold voltage, the gate leakage current can be reduced.

  As described above, according to the semiconductor integrated circuit device of the present embodiment, when the circuit control signal EN is switched from the low level to the high level in order to switch from the sleep mode to the active mode, from the next clock cycle, The combinational logic circuit COM10 can perform a normal operation in synchronization with the clock signal CLK. That is, in the example of FIG. 2, the circuit control signal EN is set to the high level in the fourth clock cycle from the time T4 to the time T5, and from the next time T5, the combinational logic circuit COM10 sets the normal logic operation result as the logic level. It becomes possible to output. Therefore, in the sleep mode, the time during which the circuit control signal EN can be set to the low level can be lengthened, and the power consumption due to the leakage current of the combinational logic circuit COM10 can be reduced.

  Further, according to the semiconductor integrated circuit device according to the present embodiment, the gate leakage current in the sleep mode can be reduced. In the embodiments described later, the same effect can be obtained in the logic cell including the pull-up transistor when the circuit control signal EN is at the low level and the other input signals are at the high level.

  Further, according to the semiconductor integrated circuit device of the present embodiment, since the output signals of the logic cells LC10 to LC13 in the sleep mode can be determined to be at a high level, when shifting from the sleep mode to the active mode (circuit) The operation timing of the logic cells LC10 to LC13 after the control signal EN is switched from the low level to the high level can be analyzed using an existing analysis tool. If an existing analysis tool is used, the time required until the value of the node E is determined after the circuit control signal EN becomes high level can be obtained, and until the clock signal CLK next becomes high level. It can be verified whether the value of the node E is fixed. In other words, at the design stage of this semiconductor integrated circuit device, it is possible to verify whether or not the output logic level of the combinational logic circuit COM10 is determined by the next clock cycle when the circuit control signal EN becomes high level. Thus, there is no need to adjust the number of delay cycles after product manufacture as before.

[Second Embodiment]
In the second embodiment, the gated clock signal CLK is generated by an OR circuit and a flip-flop circuit. Hereinafter, a different part from 1st Embodiment mentioned above is demonstrated.

  FIG. 5 is a diagram showing an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 6 is a diagram showing an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 5, the semiconductor integrated circuit device according to this embodiment is configured by adding a flip-flop circuit FF20, an OR circuit OR20, and an inverter circuit IN20 to the semiconductor integrated circuit device of the first embodiment described above. ing.

  The system clock signal SysCLK is input to the clock input terminal of the flip-flop circuit FF20, and the clock control data signal EnCLKD is input to the data input terminal D. As can be seen from FIG. 6, this flip-flop circuit FF20 outputs the value of the clock control data signal EnCLKD when the system clock signal SysCLK is switched from the low level to the high level as the clock control signal EnCLK. Even when the clock control data signal EnCLKD changes during the clock cycle of the system clock signal SysCLK by the flip-flop circuit FF20, only when the system clock signal SysCLK changes from low level to high level, the clock control signal EnCLK Can be changed. The clock control signal EnCLK is a control signal for controlling whether the clock signal is supplied or stopped.

  The OR circuit OR20 receives the clock control signal EnCLK and the system clock signal SysCLK, and outputs the gated clock signal CLK to the flip-flop circuit FF11. Therefore, the gated clock signal CLK is a signal synchronized with the system clock signal SysCLK when the clock control signal EnCLK is at a low level, but is high when the clock control signal EnCLK is at a high level. Fixed to.

  The clock control signal EnCLK output from the flip-flop circuit FF20 is inverted by the inverter IN20 to become the circuit control signal EN, and is input to the control terminals of the N-type MOS transistors NM10 to NM13 and the P-type MOS transistors PM10 to PM13. The

  The clock signal CLK1 is input to the clock input terminal of the flip-flop circuit FF10. The clock signal CLK1 may be a clock signal of another system generated from the system clock SysCLK, or an OR circuit. The clock signal CLK2 output from the OR 20 may be used. Here, description will be made assuming that CLK2 is also input to the clock signal CLK1.

  In the example of the operation timing chart shown in FIG. 6, the clock control data signal EnCLKD changes from the low level to the high level in the middle of the first clock cycle from the time T1 to the time T2. For this reason, the clock control signal EnCLK changes from the low level to the high level at the time T2 when the next system clock signal SysCLK rises. For this reason, the circuit control signal EN changes from the high level to the low level at the time T2. The clock signal CLK2 is kept at a high level.

  On the other hand, when the clock control data signal EnCLKD changes from the high level to the low level in the middle of the third clock cycle between the time T3 and the time T4, the opposite operation is performed. The clock signal CLK2 falls between T4 and T5.

  With the configuration described above, the gated clock signal CLK can be generated from the clock control data signal EnCLKD and the system clock signal SysCLK.

  Note that if there is a timing shift between the circuit control signal EN and the clock signal CLK2, the flip-flop circuit FF11 may take in erroneous data. In particular, when shifting from the active mode to the sleep mode, if the circuit control signal EN falls before the rising edge of the clock signal CLK2, the flip-flop circuit FF11 takes in erroneous data. For this reason, it is necessary to take into consideration that there is no deviation in the timing between the circuit control signal EN and the clock signal CLK2 in design.

  In the semiconductor integrated circuit device according to this embodiment, as shown in FIG. 7, the output of the OR circuit OR20 is input to the flip-flop circuit FF10 as the clock signal CLK1, and the clock signal CLK2 of another system is input to the flip-flop circuit F11. Can also be entered.

[Third Embodiment]
In the third embodiment, the above-described second embodiment is modified so that the gated clock signal CLK2 is generated by a flip-flop circuit, a low-through latch circuit, and an AND circuit. Hereinafter, a different part from 2nd Embodiment mentioned above is demonstrated.

  FIG. 8 is a diagram illustrating an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 9 is a diagram illustrating an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 8, in the semiconductor integrated circuit device according to the present embodiment, a low-through latch circuit LTL30 is provided at the subsequent stage of the flip-flop circuit FF20, and an AND circuit AN30 is disposed at the subsequent stage of the low-through latch circuit LTL30. Is provided. The low-through latch circuit LTL30 outputs the input of the data input terminal D from the data output terminal Q while the signal input to the clock input terminal is low level, but the signal input to the clock input terminal is high. During the level, it is a circuit that holds and outputs the previous state.

  A system clock signal SysCLK is input to clock input terminals of the flip-flop circuit FF20 and the low-through latch circuit LTL30. The clock control data signal EnCLKD is input to the data input terminal D of the flip-flop circuit FF20, and the clock control signal EnCLK output from the data output terminal Q of the flip-flop circuit FF20 is the data input of the low-through latch circuit LTL30. Input to terminal D. A signal output from the data output terminal Q of the low-through latch circuit LTL30 is input to one input terminal of the AND circuit AN30. The system clock signal SysCLK is input to the other input terminal of the AND circuit AN30. The gated clock signal CLK2 is output from the output terminal of the AND circuit AN30, and is input to the clock input terminal of the flip-flop circuit FF11.

  However, in the present embodiment, as shown in FIG. 9, when the clock control data signal EnCLKD switches from the active mode to the sleep mode, the clock control data signal EnCLKD switches from the high level to the low level, and conversely, from the sleep mode to the active mode. In this case, the signal is switched from the low level to the high level. Therefore, the clock control signal EnCLK can be used as it is as the circuit control signal EN.

  With the configuration described above, the gated clock signal CLK2 can be generated from the clock control data signal EnCLKD and the system clock signal SysCLK.

  Note that if there is a timing shift between the circuit control signal EN and the clock signal CLK2, the flip-flop circuit FF11 may take in erroneous data. In particular, when shifting from the active mode to the sleep mode, if the circuit control signal EN falls before the rising edge of the clock signal CLK2, the flip-flop circuit FF11 takes in erroneous data. For this reason, it is necessary to take into consideration that there is no deviation in the timing between the circuit control signal EN and the clock signal CLK2 in design.

  Further, as shown in FIG. 10, in the semiconductor integrated circuit device according to the present embodiment, the output of the AND circuit AN30 is input to the flip-flop circuit FF10 as the clock signal CLK1, and the clock signal CLK2 of another system is input to the flip-flop circuit F11. Can also be entered.

[Fourth Embodiment]
In the fourth embodiment, the first embodiment described above is modified so that among the logic cells LC10 to LC13, the logic cell LC13, which is a part of the logic cells, is not a logic cell with a foot switch but a normal logic cell. It is configured. Specifically, even if the circuit control signal EN is at a low level, a standard cell is provided for a part of the logic cells in which the logic level of the output signal output from the previous stage as an input signal does not become indefinite. A switch MOS transistor and a pull-up MOS transistor are not provided. Hereinafter, a different part from 1st Embodiment mentioned above is demonstrated.

  FIG. 11 is a diagram illustrating an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 12 is a diagram illustrating an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 11, in the combinational logic circuit COM40 of the semiconductor integrated circuit device according to this embodiment, the logic cell LC13 is provided with a NAND circuit NA12, but a P-type MOS transistor PM13 and an N-type transistor are provided. The MOS transistor NM13 is not provided. For this reason, in the present embodiment, the logic cell LC13 is configured by a NAND circuit NA12 which is a standard cell.

  The inputs of the NAND circuit NA12 are the output signal of the NAND circuit NA10 and the output signal of the NAND circuit NA11. However, in the sleep mode, as shown in FIG. 12, the first reference signal VDD is supplied to one input terminal of the NAND circuit NA12 via the P-type MOS transistor PM10 (node B). The first reference signal VDD is also supplied to the other input terminal via the P-type MOS transistor PM12 (node D). For this reason, the input signal of the NAND circuit NA12 is fixed at a high level, and a large leak current does not flow. In this way, it can be seen that the foot switch of the NAND circuit NA12 can be omitted. By omitting the N-type MOS transistor NM13, which is a foot switch, the P-type MOS transistor PM13 can also be omitted, thereby reducing the number of transistors. If the timing constraint is satisfied, the leakage current of the NAND circuit NA12 can be reduced by forming the NAND circuit NA12 with a high threshold transistor.

  In the example of FIG. 11, the logic cell in which the foot switch is omitted is the last stage logic cell. However, the logic cell in which the foot switch can be omitted is not limited to the last stage. As long as it is a logic cell composed of standard cells whose inputs are fixed in the sleep mode, they may be in any position.

  As a method for generating the clock signals CLK1 and CLK2 and the circuit control signal EN, any of the methods of the second embodiment and the third embodiment described above may be used.

[Fifth Embodiment]
In the fifth embodiment, the above-described first embodiment is modified so that some of the logic cells LC10 to LC13 are not pulled up in the sleep mode. Specifically, an output signal is input only to a logic cell having a foot switch. For a logic cell, a standard cell and a foot switch are provided, but a pull-up MOS transistor is not provided. is there. Hereinafter, a different part from 1st Embodiment mentioned above is demonstrated.

  FIG. 13 is a diagram showing an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 14 is a diagram showing an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 13, in the combinational logic circuit COM50 of the semiconductor integrated circuit device according to the present embodiment, all logic cells LC10 to LC13 are provided with N-type MOS transistors NM10 to NM10 which are foot switches, respectively. ing. That is, all standard cells are provided with foot switches. For this reason, in the sleep mode, even if inputs to the NAND circuits NA10 to NA12 and the NOR circuit NR10 which are these standard cells become indefinite, a large leak current does not flow from these standard cells.

  On the other hand, as a pull-up transistor, only the P-type MOS transistor PM13 is provided, and other MOS transistors PM10 to PM12 are not provided. For this reason, in the sleep mode between time T2 and time T4, as shown in FIG. 14, the output signal of the NAND circuit NA12 is pulled up to a high level (node E), but is a standard cell other than this. The output signals of the NAND circuits NA10 and NA11 and the NOR circuit NR10 are indefinite (node B, node C, node D).

  However, since only the output of the NAND circuit NA12 is inputted to the data input terminal D of the flip-flop circuit FF11 in the subsequent stage, if the output of the NAND circuit NA12 can be pulled up to a high level, the combinational logic circuit COM50 has The indefinite state does not affect the flip-flop circuit FF11.

  With this configuration as well, the number of MOS transistors in the combinational logic circuit COM50 can be reduced.

  As a method for generating the clock signals CLK1 and CLK2 and the circuit control signal EN, any of the methods of the second embodiment and the third embodiment described above may be used.

[Sixth Embodiment]
In the sixth embodiment, the fourth embodiment described above is modified so that a logic cell in which an output signal is input only to a logic cell of a cell with a foot switch is not pulled up in the sleep mode. Hereinafter, a different part from 4th Embodiment mentioned above is demonstrated.

  FIG. 15 is a diagram illustrating an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 16 is a diagram illustrating an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 15, the combinational logic circuit COM60 of the semiconductor integrated circuit device according to the present embodiment is different from the combinational logic circuit COM40 according to the fourth embodiment described above in that the pull-up MOS transistor PM11 in the logic cell LC11. Is omitted. The output signal of the logic cell LC11 becomes indefinite in the sleep mode (node C in FIG. 16), but is only input to the NAND circuit NA11. Here, since the NAND circuit NA11 is provided with the MOS transistor NM12 which is a foot switch, the leakage current from the NAND circuit NA11 is cut off. Further, the output signal of the NOR circuit NR10 is not output to the outside. Therefore, no problem occurs even if the output signal of the NOR circuit NR10 is indefinite.

  With this configuration as well, the number of MOS transistors in the combinational logic circuit COM60 can be reduced.

  As a method for generating the clock signals CLK1 and CLK2 and the circuit control signal EN, any of the methods of the second embodiment and the third embodiment described above may be used.

[Seventh Embodiment]
In the seventh embodiment, the above-described first embodiment is modified so that the semiconductor integrated circuit device has a scan test mode. Hereinafter, a different part from 1st Embodiment mentioned above is demonstrated.

  FIG. 17 is a diagram illustrating an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment. As shown in FIG. 17, the circuit of the semiconductor integrated circuit device according to the present embodiment is provided with an OR circuit OR70. A circuit control signal EN and a test enable signal TE are input to the OR circuit OR70. Has been. The circuit control internal signal ENI output from the OR circuit OR70 is input to the control terminals of the MOS transistors NM10 to NM13 and the MOS transistors PM10 to PM13.

  For this reason, in the scan test mode, by setting the test enable signal TE to the high level, the MOS transistors NM10 to NM13 which are foot switches can be turned on, and the MOS transistors PM10 to PM13 can be turned off. . That is, by setting the test enable signal TE to the high level, the MOS transistors NM10 to NM13 can be turned on and the MOS transistors PM10 to PM13 can be turned off regardless of the value of the circuit control signal EN.

  With this configuration, in the scan test mode, the logic cells LC10 to LC13 can be tested as logic cells configured from normal standard cells.

[Eighth Embodiment]
In the eighth embodiment, the above-described first embodiment is modified and a high-through latch circuit is additionally inserted between the combinational logic circuit COM10 and the flip-flop circuit FF11. Hereinafter, a different part from 1st Embodiment mentioned above is demonstrated.

  18 is a diagram illustrating an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 19 is a diagram illustrating an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 18, the circuit of the semiconductor integrated circuit device according to the present embodiment is provided with a control signal generation circuit GEN. A system clock signal SysCLK and a clock control signal EnCLK are input to the control signal generation circuit GEN. The control signal generation circuit GEN generates and outputs the clock signals CLK1 and CLK2 and the circuit control signal EN based on the input system clock signal SysCLK and the clock control signal EnCLK. As can be seen from this, a transition of the circuit control signal EN occurs after the transition of the clock control signal EnCLK occurs.

  Further, as shown in FIG. 18, in the circuit of the semiconductor integrated circuit device according to the present embodiment, a high-through latch circuit HTL80 is additionally inserted between the combinational logic circuit COM10 and the flip-flop circuit FF11. The high-through latch circuit HTL80 outputs the data signal input from the data input terminal D as it is from the data output terminal Q while the input signal to the clock input terminal is at the high level, but the input signal to the clock input terminal. While the signal is at low level, the previous state is maintained and output from the data output terminal Q.

  Therefore, as shown in FIG. 19, the data signal input to the data input terminal of the high-through latch circuit HTL80 is output from the data output terminal while the circuit control signal EN is at the high level. During the low level, the previous state is maintained without being output (node E and node F). By inserting such a high-through latch circuit HTL80, the circuit control signal EN is set to the high level in the next clock cycle when the clock control signal EnCLK is switched from the high level to the low level in order to shift from the active mode to the sleep mode. You can switch from level to low level. Further, in order to shift from the sleep mode to the active mode, the circuit control signal EN can be switched from the low level to the high level in the next clock cycle when the clock control signal EnCLK is switched from the low level to the high level.

  This is because, while the circuit control signal EN is at a low level, the high-through latch circuit HTL80 holds the previous state and outputs it from the data output terminal Q. Therefore, no matter what timing the circuit control signal EN is switched to This is because the flip-flop circuit FF11 is not affected. For this reason, it becomes possible to quickly switch between the active mode and the sleep mode.

  In the present embodiment, the timing at which the clock control signal EnCLK can be switched in one clock cycle is not limited, so that the clock control signal EnCLK is switched immediately before the end of one clock cycle. However, active / standby switching is possible during the next clock cycle. In other words, after the transition of the clock control signal EnCLK occurs, the circuit control signal EN transitions. However, regardless of the timing of the clock control signal EnCLK, the circuit control signal EN is transitioned in the next clock cycle. Can do it.

  In this example, the EN signal is input to the high-through latch, but an inverted signal of the EN signal may be input to the low-through latch.

[Ninth Embodiment]
In the ninth embodiment, the above-described second embodiment is applied to the above-described eighth embodiment, and the gated clock signal CLK2 is generated by an OR circuit. Hereinafter, a different part from 2nd Embodiment and 8th Embodiment mentioned above is demonstrated.

  20 is a diagram illustrating an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 21 is a diagram illustrating an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 20, in the circuit of the semiconductor integrated circuit device according to the present embodiment, an OR circuit OR90, a flip-flop circuit FF90, and an inverter IN90 are added to the semiconductor integrated circuit device of the eighth embodiment described above. It is configured. The OR circuit 90 receives a clock control signal EnCLK and a system clock signal SysCLK. The output signal of the OR circuit OR90 is input to the flip-flop circuit FF11 as the gated clock signal CLK2.

  The clock control signal EnCLK is input to the data input terminal D of the flip-flop circuit FF90 via the inverter IN90. The system clock signal SysCLK is input to the clock input terminal of the flip-flop circuit FF90. Therefore, as shown in FIG. 21, a circuit control signal EN obtained by inverting the clock control signal EnCLK in synchronization with the system clock signal SysCLK is output from the data output terminal Q of the flip-flop circuit FF90. The circuit control signal EN is input to the control terminals of the P-type MOS transistors PM10 to PM13, the control terminals of the N-type MOS transistors NM10 to NM13, and the high-through latch circuit HTL80.

  A clock signal CLK1 is input to the flip-flop circuit FF10. This clock signal CLK1 may be a clock signal of another system generated from the system clock SysCLK, or is output from the OR circuit OR90. Alternatively, the clock signal CLK2 may be used.

  With the configuration described above, the gated clock signal CLK2 can be generated from the clock control signal EnCLK and the system clock signal SysCLK.

  In the present embodiment, the clock control signal EnCLK needs to be guaranteed to change while the system clock signal SysCLK is at a high level. This is because if the clock control signal EnCLK changes from the low level to the high level while the system clock signal SysCLK is at the low level, the clock signal CLK2 changes from the low level to the high level at that time.

  In addition, if there is a timing shift between the circuit control signal EN input to the logic cells LC10 to LC13 and the circuit control signal EN input to the high-through latch circuit HTL80, the high-through latch circuit HTL80 generates erroneous data. May be taken in. In particular, when the circuit control signal EN input to the logic cells LC10 to LC13 falls before the circuit control signal EN input to the high-through latch circuit HTL80 during the transition from the active mode to the sleep mode, The through latch circuit HTL80 takes in erroneous data. For this reason, it is necessary to take into consideration that there is no deviation in the timing between the circuit control signal EN input to the logic cells LC10 to LC13 and the circuit control signal EN input to the high-through latch circuit HTL80. is there.

  In the semiconductor integrated circuit device according to the present embodiment, as shown in FIG. 22, the output of the OR circuit OR90 is input to the flip-flop circuit FF10 as the clock signal CLK1, and the clock signal CLK2 of another system is input to the flip-flop circuit F11. Can also be entered.

[Tenth embodiment]
In the tenth embodiment, the above-described eighth embodiment is applied to the above-described eighth embodiment, and the gated clock signal CLK2 is generated by the low-through latch circuit and the AND circuit. Hereinafter, a different part from 3rd Embodiment and 8th Embodiment which were mentioned above is demonstrated.

  FIG. 23 is a diagram illustrating an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 24 is a diagram illustrating an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 23, in the circuit of the semiconductor integrated circuit device according to the present embodiment, a low-through latch circuit LTL100, an AND circuit AN100, and a flip-flop circuit FF100 are added to the semiconductor integrated circuit device of the eighth embodiment described above. It is comprised by doing.

  The clock control data signal EnCLKD is input to the data input terminal D of the low-through latch circuit LTL100, and the system clock signal SysCLK is input to the clock input terminal. Therefore, as shown in FIG. 24, while the system clock signal SysCLK is at the low level, the low through latch circuit LTL100 outputs the clock control data signal EnCLKD as it is from the data output terminal Q, but the system clock signal SysCLK is at the high level. During the level, a value holding the previous state is output from the data output terminal Q.

  The clock control signal EnCLK output from the low through latch circuit LTL100 is input to one input terminal of the AND circuit AN100. The system clock signal SysCLK is input to the other input terminal of the AND circuit AN100. Therefore, as shown in FIG. 24, the clock signal CLK2 output from the AND circuit AN100 is stopped while the clock control signal EnCLK is at the low level.

  Further, the clock control signal EnCLK is input to the data input terminal of the flip-flop circuit FF100, and the system clock signal SysCLK is input to the clock input terminal. Therefore, the flip-flop circuit FF100 outputs a circuit control signal EN synchronized with the system clock signal SysCLK as shown in FIG. As shown in FIG. 25, the clock control data signal EnCLKD may be input to the data input terminal of the flip-flop circuit FF100.

  In the present embodiment, the clock control data signal EnCLKD may change when the system clock signal SysCLK is at a high level or at a low level. Therefore, the clock control data signal EnCLKD is changed to a complicated combinational logic circuit. Can also be generated.

  Note that if there is a timing difference between the circuit control signal EN input to the logic cells LC10 to LC13 and the circuit control signal EN input to the high-through latch circuit HTL80, the high-through latch circuit HTL80 generates erroneous data. May be taken in. In particular, when the circuit control signal EN input to the logic cells LC10 to LC13 falls before the circuit control signal EN input to the high-through latch circuit HTL80 during the transition from the active mode to the sleep mode, The through latch circuit HTL80 takes in erroneous data. For this reason, it is necessary to take into consideration that there is no deviation in the timing between the circuit control signal EN input to the logic cells LC10 to LC13 and the circuit control signal EN input to the high-through latch circuit HTL80. is there.

  In the semiconductor integrated circuit device according to the present embodiment, as shown in FIG. 26, the output of the AND circuit AN100 is input to the flip-flop circuit FF110 as the clock signal CLK1, and the clock signal CLK2 of another system is input to the flip-flop circuit F11. Can also be entered.

[Eleventh embodiment]
In the eleventh embodiment, the fourth embodiment described above is applied to the eighth embodiment described above, and among the logic cells LC10 to LC13, the logic cell LC13, which is a part of the logic cells, is replaced with a logic cell with a foot switch. Instead, it is configured by a normal logic cell. Specifically, even if the circuit control signal EN is at a low level, a standard cell is provided for a part of the logic cells in which the logic level of the output signal output from the previous stage as an input signal does not become indefinite. A switch MOS transistor and a pull-up MOS transistor are not provided. Hereinafter, a different part from 4th Embodiment and 8th Embodiment mentioned above is demonstrated.

  FIG. 27 is a diagram showing an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 28 is a diagram showing an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 27, the circuit of the semiconductor integrated circuit device according to this embodiment is provided with a control signal generation circuit GEN. A system clock signal SysCLK and a clock control signal EnCLK are input to the control signal generation circuit GEN. The control signal generation circuit GEN generates and outputs the clock signals CLK1 and CLK2 and the circuit control signal EN based on the input system clock signal SysCLK and the clock control signal EnCLK. As can be seen from this, a transition of the circuit control signal EN occurs after the transition of the clock control signal EnCLK occurs.

  As shown in FIG. 27, in the circuit of the semiconductor integrated circuit device according to this embodiment, in the semiconductor integrated circuit device of the above-described fourth embodiment, a high through rate is provided between the logic cell LC13 and the flip-flop circuit FF11. A latch circuit HTL80 is provided. That is, the output signal of the NAND circuit NA12 is input to the data input terminal D of the high-through latch circuit HTL80. A circuit control signal EN is input to the clock input terminal of the high-through latch circuit HTL80.

  Therefore, as shown in FIG. 28, while the circuit control signal EN is at a high level, the output signal of the NAND circuit NA12 is output from the high-through latch circuit HTL80, but while the circuit control signal EN is at a low level, The high-through latch circuit HTL80 holds the previous state and outputs from the data output terminal Q (node E and node F).

  As in the fourth embodiment described above, in the sleep mode, the input signal of the NAND circuit NA12 is fixed at a high level, and a large leakage current does not flow. For this reason, the foot switch of the NAND circuit NA12 can be omitted. By omitting the N-type MOS transistor NM13, which is a foot switch, the P-type MOS transistor PM13 can also be omitted, thereby reducing the number of transistors.

  Further, similarly to the above-described eighth embodiment, the circuit control signal EN can be switched in the next clock cycle after the clock control signal EnCLK is switched, so that the active mode and the sleep mode can be quickly switched. it can.

  In the example of FIG. 27, the logic cell in which the foot switch is omitted is the last stage logic cell. However, the logic cell in which the foot switch can be omitted is not limited to the last stage. As long as it is a logic cell composed of standard cells whose inputs are fixed in the sleep mode, they may be in any position.

  As a method for generating the clock signals CLK1 and CLK2 and the circuit control signal EN, any of the methods of the ninth embodiment and the tenth embodiment described above may be used.

[Twelfth embodiment]
In the twelfth embodiment, the fifth embodiment described above is applied to the eighth embodiment described above, and some of the logic cells LC10 to LC13 are not pulled up in the sleep mode. Is. Specifically, an output signal is input only to a logic cell having a foot switch. For a logic cell, a standard cell and a foot switch are provided, but a pull-up MOS transistor is not provided. is there. Hereinafter, a different part from 5th Embodiment and 8th Embodiment which were mentioned above is demonstrated.

  FIG. 29 is a diagram showing an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 30 is a diagram showing an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 29, a control signal generation circuit GEN is provided in the circuit of the semiconductor integrated circuit device according to the present embodiment. A system clock signal SysCLK and a clock control signal EnCLK are input to the control signal generation circuit GEN. The control signal generation circuit GEN generates and outputs the clock signals CLK1 and CLK2 and the circuit control signal EN based on the input system clock signal SysCLK and the clock control signal EnCLK. As can be seen from this, a transition of the circuit control signal EN occurs after the transition of the clock control signal EnCLK occurs.

  Further, as shown in FIG. 29, in the circuit of the semiconductor integrated circuit device according to this embodiment, in the semiconductor integrated circuit device of the fifth embodiment described above, a high through rate is provided between the logic cell LC13 and the flip-flop circuit FF11. A latch circuit HTL80 is provided. That is, the output signal of the NAND circuit NA12 is input to the data input terminal D of the high-through latch circuit HTL80. A circuit control signal EN is input to the clock input terminal of the high-through latch circuit HTL80.

  Therefore, as shown in FIG. 29, while the circuit control signal EN is at the high level, the output signal of the NAND circuit NA12 is output from the high-through latch circuit HTL80, but while the circuit control signal EN is at the low level, The high-through latch circuit HTL80 holds the previous state and outputs from the data output terminal Q (node E and node F).

  As in the fifth embodiment described above, in the sleep mode, the circuit control signal EN is at a low level and the MOS transistors NM10 to NM13 are turned off, so that the NAND circuit which is a standard cell constituting the logic cells LC10 to LC13 A large leak current does not flow from NA10 to NA12 or the NOR circuit NR10.

  Further, as shown in FIG. 30, since the pull-up MOS transistors PM10 to PM12 are omitted, the nodes B to D which are the outputs of the logic cells LC10 to LC12 become indefinite, but the output of the combinational logic circuit COM10. The output of the logic cell LC13 is pulled up to a high level when the MOS transistor PM13 is turned on. Therefore, even if the NAND circuits NA10 and NA11 and the pull-up MOS transistors PM10 to PM12 of the NOR circuit NR10 that do not affect the output of the combinational logic circuit COM10 are omitted, the data input terminal D of the high-through latch circuit HTL80 is omitted. It is possible to avoid the input becoming indefinite.

  If a latch circuit that does not flow a leak current even when the state of the data input terminal D becomes floating (undefined) is used instead of the high-through latch circuit HTL80, the P-type MOS transistor PM13 is also omitted. Is possible.

  As a method for generating the clock signals CLK1 and CLK2 and the circuit control signal EN, any of the methods of the ninth embodiment and the tenth embodiment described above may be used.

[Thirteenth embodiment]
In the thirteenth embodiment, the sixth embodiment described above is applied to the eighth embodiment described above, and the logic cell in which the output signal is input only to the logic cell with the foot switch is pulled up in the sleep mode. This is what I did not. In other words, the eleventh embodiment described above is further modified. Hereafter, a different part from 6th Embodiment, 8th Embodiment, and 11th Embodiment mentioned above is demonstrated.

  FIG. 31 is a diagram showing an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment, and FIG. 32 is a diagram showing an operation timing chart of the semiconductor integrated circuit device of FIG.

  As shown in FIG. 31, the control signal generation circuit GEN is provided in the circuit of the semiconductor integrated circuit device according to the present embodiment. A system clock signal SysCLK and a clock control signal EnCLK are input to the control signal generation circuit GEN. The control signal generation circuit GEN generates and outputs the clock signals CLK1 and CLK2 and the circuit control signal EN based on the input system clock signal SysCLK and the clock control signal EnCLK. As can be seen from this, a transition of the circuit control signal EN occurs after the transition of the clock control signal EnCLK occurs.

  Further, as shown in FIG. 31, in the circuit of the semiconductor integrated circuit device according to this embodiment, in the semiconductor integrated circuit device of the sixth embodiment described above, a high-throughput is provided between the logic cell LC13 and the flip-flop circuit FF11. A latch circuit HTL80 is provided. That is, the output signal of the NAND circuit NA12 is input to the data input terminal D of the high-through latch circuit HTL80. A circuit control signal EN is input to the clock input terminal of the high-through latch circuit HTL80.

  Therefore, as shown in FIG. 32, while the circuit control signal EN is at the high level, the output signal of the NAND circuit NA12 is output from the high-through latch circuit HTL80, but while the circuit control signal EN is at the low level, The high-through latch circuit HTL80 holds the previous state and outputs from the data output terminal Q (node E and node F).

  As shown in FIG. 32, the node C, which is the output of the logic cell LC11, becomes indefinite during the sleep mode, but the output of the logic cell LC11 is only input to the logic cell LC12 with a foot switch. It is. Therefore, even if the output of the logical cell LC11 becomes indefinite, a large leak current does not flow.

  With this configuration as well, the number of MOS transistors in the combinational logic circuit COM60 can be reduced.

  As a method for generating the clock signals CLK1 and CLK2 and the circuit control signal EN, any of the methods of the ninth embodiment and the tenth embodiment described above may be used.

[Fourteenth embodiment]
In the fourteenth embodiment, the seventh embodiment described above is applied to the eighth embodiment described above, so that the semiconductor integrated circuit device has a scan test mode. Hereinafter, parts different from the seventh embodiment and the eighth embodiment described above will be described.

  FIG. 33 is a diagram showing an example of a circuit configuration of the semiconductor integrated circuit device according to the present embodiment. As shown in FIG. 33, in the circuit of the semiconductor integrated circuit device according to this embodiment, in the semiconductor integrated circuit device of the seventh embodiment described above, a high-through latch is provided between the logic cell LC13 and the flip-flop circuit FF11. A circuit HTL80 is provided. That is, the output signal of the NAND circuit NA12 is input to the data input terminal D of the high-through latch circuit HTL80. The flip-flop is a so-called scan flip-flop. When TE goes high, the flip-flop enters test mode.

  Similarly to the seventh embodiment, the circuit of the semiconductor integrated circuit device according to the present embodiment is provided with an OR circuit OR70. The OR circuit OR70 includes a circuit control signal EN, a test enable signal TE, and Is input, and the inverted hold signal HOLDX is output. The inverted hold signal HOLDX is input to the control terminals of the MOS transistors NM10 to NM13 and the MOS transistors PM10 to PM13, and is also input to the clock input terminal of the high-through latch circuit HTL80.

  For this reason, in the scan test mode, by setting the test enable signal TE to the high level, the MOS transistors NM10 to NM13 which are foot switches can be turned on, and the MOS transistors PM10 to PM13 can be turned off. . That is, by setting the test enable signal TE to the high level, the MOS transistors NM10 to NM13 can be turned on and the MOS transistors PM10 to PM13 can be turned off regardless of the value of the circuit control signal EN. Further, in the scan test mode, by setting the test enable signal TE to the high level, the high through latch circuit HTL80 outputs the data input to the data input terminal D as it is from the data output terminal Q.

  With this configuration, in the scan test mode, the logic cells LC10 to LC13 can be tested as logic cells configured from normal standard cells.

[Fifteenth embodiment]
The configurations of the high-through latch circuit HTL80 and the flip-flop circuit FF11 according to the fourteenth embodiment will be described in more detail.

  FIG. 34 is a diagram for explaining the circuit configuration of the latch circuit with a test function and the flip-flop circuit to which the output is input according to the present embodiment. As shown in FIG. 34, the latch circuit according to this embodiment includes inverter circuits IN150, IN152, IN154, IN156, IN158, IN159, and a slave latch circuit SL. Among these inverter circuits, the inverter circuits IN150, IN152, IN154, IN160, and IN156 are constituted by clocked inverters having a gate function. Further, the inverter IN154, the inverter IN158, and the inverter IN159 constitute the master latch circuit ML in the present embodiment. The inverter circuits IN150, IN152, and IN156, the master latch circuit ML, and the slave latch circuit SL constitute the high-through latch circuit HTL80 and the flip-flop circuit FF11 in the fourteenth embodiment.

  A test signal TI is input to the inverter circuit IN150 and is gated by a logical product of the test enable signal TE and the inverted hold signal HOLDX. The data signal IN is input to the inverter circuit IN152 and gated by the logical product of the inverted test enable signal TEX and the inverted hold signal HOLDX.

  Therefore, when the test enable signal TE is at a low level, the data signal IN is selected by the inverter circuit IN152, and when the test enable signal TE is at a high level, the test signal TI is selected by the inverter circuit IN150. In either case, when the inverted hold signal HOLDX is at a high level (that is, when the hold HOLD is at a low level), the signals input to the inverter circuits IN150 and IN152 are inverted and passed, but the inverted hold When the signal HOLDX is at a low level (that is, when the hold HOLD is at a high level), the signal HOLDX is cut off.

  When the inverted hold signal HOLDX is at a low level (that is, when the hold HOLD is at a high level), the inverter circuit IN156 operates and inverts and outputs the input signal. For this reason, in this embodiment, the inverter circuit IN150, IN152, IN156 constitutes a multiplexer.

  Furthermore, in the latch circuit according to the present embodiment, the inverter circuit IN154 and the inverter IN156 constitute one latch circuit, and the inverter circuit IN158 and the inverter IN159 constitute one latch circuit.

  With this configuration, it is possible to realize a high-through latch circuit HTL80 that holds data only by adding three inverter circuits IN150, IN152, and IN156 to the configuration of the normal master latch ML. Further, the number of stages of the inverter circuit from IN to OUT during normal operation is the same as that of a normal scan input / output flip-flop circuit, and it can be considered that there is almost no decrease in operation speed due to the addition of the hold function. .

[Sixteenth Embodiment]
The latch circuit according to the fifteenth embodiment described above is configured on the premise that the clock signal CLK is guaranteed to be low when the hold state is entered. However, this embodiment does not have this guarantee. Even if it is working properly. Hereinafter, a different part from 15th Embodiment mentioned above is demonstrated.

  FIG. 35 is a diagram for explaining the circuit configuration of the latch circuit according to the present embodiment. As shown in FIG. 35, in the latch circuit according to the present embodiment, the inverter circuit IN154 is configured by a normal inverter, and an inverter circuit IN160 is additionally inserted between the inverter circuit IN154 and the inverter IN158. Has been.

  The inverter circuit IN160 is a clocked inverter to which the inverted clock signal CLKX is input.

  With this configuration, when the clock signal CLK is at a high level when the hold state is entered, the inverter circuit IN160 is cut off, and the latch function of the inverter circuits IN158 and IN159 operates. For this reason, even if the clock signal CLK at the time of entering the hold state is at a high level or a low level, it functions normally.

[Seventeenth embodiment]
The latch circuit according to the fifteenth embodiment described above is configured to hold the data signal even during the scan test. However, in the present embodiment, it is assumed that the data signal does not need to be held during the scan test. is there. Hereinafter, a different part from 15th Embodiment mentioned above is demonstrated.

  FIG. 36 is a diagram illustrating the circuit configuration of the latch circuit according to the present embodiment. As shown in FIG. 36, in the latch circuit according to the present embodiment, the inverter circuit IN150 is gated by the test enable signal TE. By doing so, the control signal of the input multiplexer can be simplified.

  As shown in FIG. 37, this embodiment can be constituted by three inverter circuits IN170, IN172, and IN174 when it is constituted by a flip-flop circuit FF170. These inverter circuits IN170, IN172, and IN174 are all constituted by clocked inverters.

  A test signal TI is input to the inverter circuit IN170 and is gated by the test enable signal TE. The data signal IN is input to the inverter circuit IN172 and is gated by the logical product of the test enable signal TE and the inverted hold signal HOLDX. The inverter circuits IN172 and IN174 form a latch circuit, and the output is input to the data input terminal D of the flip-flop circuit FF170. With such a configuration, the control signal of the input multiplexer can be simplified.

[Eighteenth Embodiment]
In the eighteenth embodiment, a technique for simplifying the high-through latch circuit and the flip-flop circuit will be described from a viewpoint different from the above-described embodiments. FIG. 38 is a diagram illustrating a high-through latch circuit HTL200 to which an output of the combinational logic circuit is input and a flip-flop circuit FF200. The flip-flop circuit FF200 further includes a master latch circuit ML200 and a slave latch circuit SL200.

  As shown in FIG. 38, a node on the data input terminal D side of the high-through latch circuit HTL200 is a node B, and a node on the data output terminal Q side is a node C. A node on the data output terminal Q side of the master latch circuit ML200 having the data input terminal D connected to the node C is referred to as a node D. A signal output from the data output terminal Q of the slave latch circuit SL200 having the data input terminal D connected to the node D is defined as an output signal OUT.

  As shown in FIG. 38, a circuit control signal EN is input to the control terminal of the high-through latch circuit HTL200, and a clock signal CLK is input to the control terminal of the slave latch circuit SL200. Further, an inverted clock signal CLKB obtained by inverting the clock signal CLK is input to the control terminal of the master latch circuit ML200.

  FIG. 39 is a table collectively showing the logic levels of the circuit control signal EN and the clock signal CLK and the logic levels of the nodes B, C and D and the output signal OUT. As shown in FIG. 39, (1) when the circuit control signal EN is at a high level and the clock signal CLK is also at a high level, the high-through latch circuit HTL200 is in the through state, the master latch circuit ML200 is in the hold state, and the slave latch The circuit SL200 enters a through state. Therefore, if the logical level of node B is Q, the logical level of node C is also Q. However, the logical level of the node D is a logical level R that is unrelated to the logical level Q of the node C. The logic level of the output signal OUT is R.

  (2) When the circuit control signal EN is at a high level and the clock signal CLK is at a low level, the high-through latch circuit HTL200 is in a through state, the master latch circuit ML200 is in a through state, and the slave latch circuit SL200 is in a hold state. Therefore, if the logical level of node B is Q, the logical level of node C is also Q, and the logical level of node D is also Q. However, the logic level of the output signal OUT is a logic level R that is unrelated to the logic level Q of the node D.

  (3) When the circuit control signal EN is at a low level and the clock signal CLK is at a high level, the high-through latch circuit HTL200 is in a hold state, the master latch circuit ML200 is in a hold state, and the slave latch circuit SL200 is in a through state. For this reason, if the logical level of the node B is Q, the logical level of the node C is a logical level R that is unrelated to the logical level Q. Further, the logical level of the node D is a logical level S that is unrelated to the logical level R of the node C. The logic level of the output signal OUT is S.

  (4) When the circuit control signal EN is at the low level and the clock signal CLK is also at the low level, the high through latch circuit HTL200 is in the hold state, the master latch circuit ML200 is in the through state, and the slave latch circuit SL200 is in the hold state. For this reason, if the logical level of the node B is Q, the logical level of the node C is a logical level R that is unrelated to the logical level Q. The logical level of node D is also R. However, the logic level of the output signal OUT is a logic level S that is unrelated to the logic level R of the node D.

  If the high-through latch circuit HTL200 is omitted based on the table of FIG. 39, a circuit configuration as shown in FIG. 40 is obtained. That is, an output from the combinational logic circuit is input to the master latch circuit ML200, and a signal obtained by ANDing the circuit control signal EN and the inverted clock signal CLKB is input to the control terminal of the master latch circuit ML200. The

  FIG. 41 is a diagram collectively showing the relationship between the logic levels of the circuit control signal EN and the clock signal CLK and the logic levels of the nodes B and D and the output signal OUT in the flip-flop circuit FF200 of FIG. is there. As can be seen by comparing FIG. 41 with FIG. 39 described above, the logic levels of the nodes B and C and the output signal OUT with respect to the logic levels of the circuit control signal EN and the clock signal CLK are the same between the two diagrams. It has become. From this, it is understood that the high-through latch circuit HTL200 can be omitted by inputting a signal obtained by ANDing the circuit control signal EN and the inverted clock signal CLKB to the control terminal of the master latch circuit ML200.

  FIG. 42 shows a circuit diagram in which the output signal of the combinational logic circuit COM200 is input to the flip-flop circuit FF200 shown in FIG. Although the configuration of the logic cell of the combinational logic circuit COM200 is arbitrary, FIG. 42 shows an example in which the logic cell is configured by N-type MOS transistors NM200 and NM202 and P-type MOS transistors PM200 and PM202. The N-type MOS transistor NM202 constitutes a foot switch, and the P-type MOS transistor PM202 constitutes a pull-up transistor.

  A flip-flop circuit FF202 is provided in the preceding stage of the combinational logic circuit COM200. An input signal IN is input to the data input terminal D of the flip-flop circuit 202. The clock signal CLK1 is input to the control terminal, and the input signal IN is output from the data output terminal Q in synchronization with the clock signal CLK1 and input to the combinational logic circuit COM200.

  The clock signal CLK1 is generated by a clock gating circuit as shown in FIG. That is, a clock including a low-through latch circuit LTL200 to which the clock control signal EnCLK1 and the system clock signal SysCLK are input, and an AND circuit AN200 to which the output signal of the low-through latch circuit LTL200 and the system clock signal SysCLK are input. Generated by a gating circuit.

  In the combinational logic circuit COM200 of FIG. 42, an operation for inverting the input signal is executed as a predetermined operation, and the output signal is input to the flip-flop circuit FF200. In the flip-flop circuit FF200, the clock signal CLK2 is input to the control terminal of the slave latch circuit SL200. A signal obtained by ANDing the circuit control signal EN and the inverted clock signal CLK2B obtained by inverting the clock signal CLK2 is input to the control terminal of the master latch circuit ML200.

  The clock signal CLK2 is generated by a clock gating circuit as shown in FIG. That is, a clock including a low-through latch circuit LTL202 to which the clock control signal EnCLK2 and the system clock signal SysCLK are input, and an AND circuit AN202 to which the output signal of the low-through latch circuit LTL202 and the system clock signal SysCLK are input. Generated by a gating circuit. Here, it is assumed that the clock control signal EnCLK1 and the clock control signal EnCLK2 are separate control signals.

  FIG. 45 shows an operation timing chart of the semiconductor integrated circuit shown in FIG. As shown in FIG. 45, the normal output signal OUT is output from the flip-flop circuit FF200 even though the high-through latch circuit HTL200 is omitted. That is, when the logic level of the node B changes, the logic level of the output signal OUT changes in the next clock cycle. When the circuit control signal EN becomes low level and the sleep mode is entered, the output signal of the flip-flop circuit FF200 is fixed at low level.

  46 is a circuit diagram in which the high-through latch circuit HTL200 is not omitted in the semiconductor integrated circuit shown in FIG. 42, and FIG. 47 is a diagram showing an operation timing chart of the semiconductor integrated circuit shown in FIG. is there. As shown in these drawings, the output signal OUT of the semiconductor integrated circuit without the high-through latch circuit HTL200 is the same as the output signal OUT of the semiconductor integrated circuit without the high-through latch circuit HTL200. Therefore, it can be seen that there is no problem in circuit operation even if the high-through latch circuit HTL200 is omitted.

  Here, in the operation timing chart of FIG. 45, the case where the clock signal CLK1 and the clock signal CLK2 are different signals and have different waveforms in the semiconductor integrated circuit of FIG. 42 has been described as an example. There may be a case where the clock signal CLK2 has the same waveform. That is, the clock signal CLK2 may be a signal that enters the sleep mode similarly to the clock signal CLK1. Therefore, next, the operation when the clock signal CLK1 and the clock signal CLK2 are the same is verified.

  FIG. 48 is an operation timing chart when the clock signal CLK1 and the clock signal CLK2 having the same operation waveform are used in the semiconductor integrated circuit of FIG. 49 is an operation timing chart when the clock signal CLK1 and the clock signal CLK2 having the same operation waveform are used in the semiconductor integrated circuit of FIG.

  As is clear from comparison between FIGS. 48 and 49, even when the clock signal CLK1 and the clock signal CLK2 having the same operation waveform are used, the output signal OUT of the semiconductor integrated circuit of FIG. It becomes the same as the output signal OUT. Therefore, it can be seen that there is no problem in circuit operation even when the clock signal CLK1 and the clock signal CLK2 have the same operation waveform even if the high-through latch circuit HTL200 is omitted as in the semiconductor integrated circuit of FIG.

  FIG. 50 shows an example of a specific circuit configuration of flip-flop circuit FF200 in the semiconductor integrated circuit shown in FIG. As shown in FIG. 50, in the flip-flop circuit 200, the master latch circuit ML200 includes a transfer gate T220, an inverter IN220, and a clocked inverter IN222. The slave latch circuit SL200 includes a transfer gate T230, a transfer gate T232, and inverters IN230, IN232, and IN234.

  A signal obtained by ANDing the circuit control signal EN and the inverted clock signal CLK2B is input to the transfer gate T220 of the master latch circuit ML200. On the other hand, a signal obtained by logically summing a signal obtained by inverting the circuit control signal EN and the clock signal CLK2 is input to the inverter IN222. In other words, the inverter IN222 receives a signal obtained by inverting a signal obtained by ANDing the circuit control signal EN and the inverted clock signal CLK2B.

  The clock signal CLK2 is input to the transfer gate T230 of the slave latch circuit SL200. The inverted clock signal CLK2B is input to the transfer gate T232.

  In the flip-flop circuit FF200 having such a configuration, as described above, the input signal IN output from the combinational logic circuit COM200 is input to the transfer gate T220 via the node B, and the output signal OUT is output from the inverter IN234. Is output.

  FIG. 51 is a diagram illustrating an example of a circuit configuration of the flip-flop circuit FF200 when a test function is added to the flip-flop circuit FF200 of FIG. As shown in FIG. 51, a flip-flop circuit FF200 to which a test function is added is provided with a multiplexer MX220 in front of the master latch circuit ML200.

  The multiplexer MX220 includes clocked inverters IN240 and IN242. A test enable signal TE is input to the clocked inverter IN242, and an inverted test enable signal / TE obtained by inverting the test enable signal TE is input to the clocked inverter IN240. Therefore, clocked inverters IN240 and IN242 are alternatively gated by test enable signal TE and test enable signal / TE.

  The clocked inverter IN240 receives the input signal IN output from the combinational logic circuit COM200, and the clocked inverter IN242 receives the test signal TI. Therefore, when the test enable signal TE is high level (that is, in the case of a test), the test signal TI input to the clocked inverter IN242 is input to the master latch circuit ML200, and the test enable signal TE is low level ( That is, in the case of normal operation), the input signal IN from the combinational logic circuit COM200 input to the clocked inverter IN240 is input to the master latch circuit ML200. Thus, it can be seen that the flip-flop circuit FF200 having the test function can be realized.

  As described above, according to the semiconductor integrated circuit of this embodiment, the high-through latch circuit HTL200 can be omitted as shown in FIG. Therefore, the number of transistors can be reduced and the circuit area can be reduced. Further, since the master latch circuit ML200 of the flip-flop circuit FF200 also serves as a function for maintaining the level of the input signal, a test signal similar to a normal test for the flip-flop circuit can be applied when testing the semiconductor integrated circuit. Good. Therefore, testability is improved as compared with the case where the high-through latch circuit HTL200 exists.

[Nineteenth Embodiment]
In the embodiment described above, the output of the combinational logic circuit is fixed at a high level in the sleep mode. For example, in the first embodiment described above, as illustrated in FIGS. 1 and 2, the node E that is the output of the combinational logic circuit COM10 is in the sleep mode (while the circuit control signal EN is at the low level). The P-type MOS transistor PM13 is forcibly set to a high level.

  However, when the output destination of the combinational logic circuit COM10 is a clock gating circuit for controlling the supply and stop of the clock signal, the output of the node E is at a high level. Since the mode is the mode, the supply of the clock signal is continued without being stopped even though the supply of the clock signal should be stopped. That is, the pull-up of the P-type MOS transistor PM13 causes the clock gating circuit to supply a clock signal unconditionally.

  Therefore, in this embodiment, as shown in FIG. 52, the logical product of the output of the combinational logic circuit COM10 and the circuit control signal EN is taken, and the control of the clock gating circuit CGC is performed with the signal obtained by the logical product. Do.

  That is, as shown in FIG. 52, in this embodiment, the clock gating circuit CGC includes AND circuits AN300 and AN302 and a low-through latch circuit LTL300. The combinational logic circuit COM10 is composed of various combinations of logic cells. In FIG. 52, a pull-up P-type MOS transistor PM13 and an N-type foot switch in the final stage of the combinational logic circuit COM10 are used. The MOS transistor NM13 is illustrated. The combinational logic circuit COM10 is configured as shown in FIG. 1, for example.

  As shown in FIG. 52, in the AND circuit AN300 of the clock gating circuit CGC, the signal of the node E that is the output of the logic circuit COM10 and the circuit control signal that is also input to the control terminal of the N-type MOS transistor NM13. EN is input. The output signal of the AND circuit 300 is input to the data input terminal D of the low through latch circuit LTL300. The AND circuit AN300 constitutes the first gating logic circuit in the present embodiment, and the AND circuit is an example of the first gating logic circuit.

  The system clock signal SysCLK is input to the control terminal of the low-through latch circuit LTL300. Therefore, while the system clock signal SysCLK is at the low level, the clock control signal EnCLK input from the data input terminal D is output from the data output terminal Q, but when the system clock signal SysCLK is at the high level, the data From the output terminal Q, a clock control signal EnCLK holding the previous level is output.

  This clock control signal EnCLK is input to the AND circuit AN302. A system clock signal SysCLK is also input to the AND circuit AN302. The output of the AND circuit AN302 is supplied to the clock tree CLTR at the subsequent stage as the clock signal CLK. The AND circuit AN302 constitutes the second gating logic circuit in the present embodiment, and the AND circuit is an example of the second gating logic circuit.

  As can be seen from this configuration, when the clock gating circuit CGC of FIG. 52 is used, when the circuit control signal EN is at a high level (that is, in the active mode), the same logical value as the output of the combinational logic circuit COM10 is obtained. The data is input to the data input terminal D of the low-through latch circuit LTL300. Therefore, the AND circuit AN302 outputs a clock signal CLK synchronized with the system clock signal SysCLK.

  On the other hand, when the circuit control signal EN is at the low level (ie, in the sleep mode), the output of the AND circuit AN300 is at the low level regardless of the output of the combinational logic circuit COM10, and the low level signal is in the low through latch. The data is input to the data input terminal D of the circuit LTL300. For this reason, the output of the low-through latch circuit LTL300 is also fixed at a low level, and the output of the clock gating circuit CGC is also fixed at a low level. Therefore, the supply of the clock signal to the subsequent clock tree CLTR can be stopped.

  As can be seen from this, this embodiment is effective when the combinational logic circuit COM10 is set to the sleep mode and the clock signal CLK is stopped in a low level state.

[20th embodiment]
In the above embodiment, the sleep mode is effective when there is regularity that the input and output to the low-through latch circuit LTL300 are at a low level and the output of the clock gating circuit CGC is also in a low level. However, there are cases where there is no such regularity. Therefore, in the present embodiment, the configuration of the clock gating circuit CGC when there is no such regularity will be described.

  FIG. 53 shows a combinational logic circuit COM10 according to the present embodiment, a clock gating circuit CGC that performs gating of the system clock signal SysCLK using the output of the combinational logic circuit COM10, and a clock signal from the clock gating circuit CGC. It is a figure which shows clock tree CLTR which receives supply of CLK.

  To explain the difference from the above embodiment, the clock gating circuit CGC includes a multiplexer MX300 instead of the AND circuit AN300. The multiplexer MX300 receives an output signal from the combinational logic circuit COM10 and a clock control signal EnCLK that is an output signal from the low-through latch circuit LTL300. The circuit control signal EN is input to the control terminal of the multiplexer MX300. The AND circuit AN302 constitutes the third gating logic circuit in the present embodiment, and the AND circuit is an example of a third gating logic circuit.

  As can be seen from this configuration, when the clock gating circuit CGC of FIG. 53 is used, the multiplexer MX300 receives the input from the combinational logic circuit COM10 when the circuit control signal EN is at a high level (that is, in the active mode). Since it is output to the low-through latch circuit LTL300, the same logical value as the output of the combinational logic circuit COM10 is input to the data input terminal D of the low-through latch circuit LTL300. Therefore, the AND circuit AN302 outputs a clock signal CLK synchronized with the system clock signal SysCLK.

  On the other hand, when the circuit control signal EN is at the low level (that is, in the sleep mode), the multiplexer MX300 outputs the clock control signal EnCLK input from the low through latch circuit LTL300 to the low through latch circuit LTL300. For this reason, the output of the low-through latch circuit LTL300 becomes the input of the low-through latch circuit LTL300, and the output of the low-through latch circuit LTL300 remains unchanged.

  Therefore, in the sleep mode, the present embodiment can be applied even when there is no regularity that the clock control signal EnCLK is always stopped in a low level state. When the clock control signal EnCLK is at a low level and the sleep mode is entered, the supply of the clock signal CLK to the clock tree CLTR can be stopped.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, in each of the above-described embodiments, the present invention is realized by a pull-up configuration using an N-type MOS transistor. However, the present invention is realized by a pull-down configuration using a P-type MOS transistor. May be. When the present invention is realized by a pull-down configuration, for example, the semiconductor integrated circuit device of the first embodiment described above has a circuit configuration as shown in FIG. The operation timing chart in this case is as shown in FIG. That is, in the sleep mode between the time T2 and the time T4, the P-type MOS is applied so that the nodes B to E, which are the outputs of the logic cells LC10 to LC13, are pulled down to a low level and no leakage current flows. Transistors PM10 to PM13 are turned off.

  In addition, the MOS transistor configuring the combinational logic circuit in the above-described embodiment is an example of a MIS transistor (Metal Insulator Semiconductor Transistor), and may be configured by other types of MIS transistors.

1 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a first embodiment. FIG. 3 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 1. FIG. 2 is a diagram showing an example of a circuit configuration of a NAND circuit used in the semiconductor integrated circuit device shown in FIG. 1. FIG. 2 is a diagram showing an example of a circuit configuration of a NOR circuit used in the semiconductor integrated circuit device shown in FIG. 1. The figure which shows an example of the circuit structure of the semiconductor integrated circuit device which concerns on 2nd Embodiment. FIG. 6 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 5. The figure which shows the modification of the semiconductor integrated circuit device which concerns on 2nd Embodiment. FIG. 10 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a third embodiment. FIG. 9 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 8. The figure which shows the modification of the semiconductor integrated circuit device which concerns on 3rd Embodiment. FIG. 10 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a fourth embodiment. FIG. 12 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 11. FIG. 10 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a fifth embodiment. FIG. 14 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 13. FIG. 10 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a sixth embodiment. FIG. 16 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 15. FIG. 10 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a seventh embodiment. FIG. 16 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to an eighth embodiment. FIG. 19 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 18. FIG. 20 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a ninth embodiment. FIG. 21 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 20. The figure which shows the modification of the semiconductor integrated circuit device which concerns on 9th Embodiment. FIG. 20 is a diagram illustrating an example of a circuit configuration of a semiconductor integrated circuit device according to a tenth embodiment. FIG. 24 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 23. FIG. 16 is a view showing a modification of the semiconductor integrated circuit device according to the tenth embodiment. The figure which shows another modification of the semiconductor integrated circuit device which concerns on 10th Embodiment. FIG. 20 is a diagram showing an example of a circuit configuration of a semiconductor integrated circuit device according to an eleventh embodiment. FIG. 28 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 27. A figure showing an example of circuit composition of a semiconductor integrated circuit device concerning a 12th embodiment. FIG. 30 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 29. A figure showing an example of circuit composition of a semiconductor integrated circuit device concerning a 13th embodiment. FIG. 32 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 31. A figure showing an example of circuit composition of a semiconductor integrated circuit device concerning a 14th embodiment. The figure which shows an example of the circuit structure of a low through latch circuit. The figure which shows another example of the circuit structure of a low through latch circuit. The figure which shows another example of the circuit structure of a low through latch circuit. The figure which shows another example of the circuit structure of a low through latch circuit. 2 is a diagram showing a high-through latch circuit provided in a semiconductor integrated circuit and a flip-flop circuit connected to the high-through latch circuit. FIG. The figure which shows the input / output signal of FIG. 38, and the logic level of each node as a table | surface. FIG. 39 is a diagram showing a circuit configuration in which a high-through latch circuit is omitted from the circuit of FIG. The figure which shows the input / output signal of FIG. 40, and the logic level of each node as a table | surface. FIG. 41 is a diagram showing a circuit configuration of a semiconductor integrated circuit using the flip-flop circuit of FIG. FIG. 43 is a diagram showing an example of a circuit configuration of a clock gating circuit that generates a clock signal in the semiconductor integrated circuit of FIG. 42. FIG. 43 is a diagram showing an example of a circuit configuration of a clock gating circuit that generates a clock signal in the semiconductor integrated circuit of FIG. 42. FIG. 43 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit of FIG. 42. FIG. 39 is a diagram showing a circuit configuration of a semiconductor integrated circuit using the high-through latch circuit and the flip-flop circuit of FIG. 38 in the subsequent stage of the combinational logic circuit. 47 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit of FIG. 46. FIG. FIG. 43 is a diagram showing an example of an operation timing chart when clock signals having the same waveform are used in the semiconductor integrated circuit of FIG. FIG. 47 is a diagram showing an example of an operation timing chart when clock signals having the same waveform are used in the semiconductor integrated circuit of FIG. 46. FIG. 41 is a diagram showing an example of a specific circuit configuration of the flip-flop circuit in FIG. 40. FIG. 51 is a diagram showing an example of a circuit configuration when a test function is added to the flip-flop circuit of FIG. 50. The figure which shows an example of the circuit structure of the clock gating circuit into which the signal output from the combinational logic circuit provided with the transistor for pullups is input. FIG. 53 is a diagram showing a modification of the clock gating circuit of FIG. 52. FIG. 3 is a diagram showing an example in which the pull-up type semiconductor integrated circuit device shown in FIG. 1 is modified to a pull-down type. FIG. 55 is a diagram showing an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 54.

Explanation of symbols

LC10-LC13 Logic cells NA10-NA12 NAND circuit NOR10 NOR circuit PM10-PM13 P-type MOS transistors NM10-NM13 N-type MOS transistors FF10, FF11 Flip-flop circuits CLK, CLK1, CLK2 Clock signal EN Circuit control signal

Claims (5)

A semiconductor integrated circuit device comprising a combinational logic circuit having one or more logic cells connected in series,
At least one of the logic cells is
An input terminal composed of a MIS transistor, to which an output signal from the previous stage is input as an input signal, and an output terminal that performs a predetermined logical operation based on the input signal and outputs the logical operation result as an output signal A standard cell having
A control terminal is provided between the output terminal of the standard cell and the first power supply voltage and receives a circuit control signal. The standard cell is put into an operation stop state based on the circuit control signal. For this purpose, a first MIS transistor of a first conductivity type that supplies the first power supply voltage to the output terminal of the standard cell;
The standard cell is provided between the standard cell and a second power supply voltage and has a control terminal to which the circuit control signal is input. Based on the circuit control signal, the standard cell is placed in a computation stop state. A second MIS transistor of a second conductivity type that cuts off a leakage current of the MIS transistor constituting the cell;
With
The semiconductor integrated circuit device includes:
A flip-flop circuit to which an output signal from the combinational logic circuit is input;
The flip-flop circuit is
A master latch circuit having a data input terminal to which an output signal from the combinational logic circuit is input, and a control terminal to which an AND signal obtained by ANDing the circuit control signal and a clock signal is input;
A data input terminal to which an output signal from the master latch circuit is input; a control terminal to which the clock signal is input;
A semiconductor integrated circuit device comprising: A clock gating circuit to which an output signal from the combinational logic circuit is input;
The clock gating circuit is
When the output signal of the combinational logic circuit and the circuit control signal are input, and when the circuit control signal is high level, the output signal of the combinational logic circuit is output, and when the circuit control signal is low level Includes a first gating logic circuit that outputs a low-level output signal;
A latch circuit that receives an output signal from the first gating logic circuit and outputs an output signal from the first gating logic circuit in synchronization with a system clock signal;
A second gating logic circuit that receives an output signal from the latch circuit and outputs an output signal from the latch circuit in synchronization with the system clock signal;
The semiconductor integrated circuit device according to claim 1, comprising: The first gating logic circuit outputs a logical product of the output signal of the combinational logic circuit and the circuit control signal,
The second gating logic circuit outputs a signal obtained by ANDing the output signal from the first gating logic circuit and the system clock signal.
The semiconductor integrated circuit device according to claim 2. A clock gating circuit to which an output signal from the combinational logic circuit is input;
The clock gating circuit is
A multiplexer to which the circuit control signal is input, wherein an output signal of the combinational logic circuit and an output signal of the multiplexer are input, and when the circuit control signal is at a high level, an output of the combinational logic circuit A multiplexer that outputs a signal and outputs an output signal of the multiplexer when the circuit control signal is at a low level;
A latch circuit that receives an output signal from the multiplexer and outputs an output signal from the multiplexer in synchronization with a system clock signal;
A third gating logic circuit that receives an output signal from the latch circuit and outputs an output signal from the latch circuit in synchronization with the system clock signal;
The semiconductor integrated circuit according to claim 1, comprising:   5. The semiconductor integrated circuit device according to claim 1, wherein the first MIS transistor is provided in a logic cell at a final stage in the combinational logic circuit. 6.

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