JP2007335548A - Mos field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing leakage current of a MOS field effect transistor in a high-temperature environment. <P>SOLUTION: A source offset region 7 having concentration higher than that of a semiconductor substrate is provided between a source region 3 and a channel forming region 4, and a gate oxide film on the source offset region 7 is made to be thinned. In this way, the leakage current is reduced while keeping a threshold voltage at low. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to leakage current suppression of a MOS field effect transistor.

  When trying to achieve low power consumption by suppressing the leakage current of MOS field effect transistors, the simplest method is to increase the threshold voltage by increasing the concentration of the semiconductor substrate. .

However, if the threshold voltage is increased, it becomes an obstacle when the MOS field effect transistor is operated at high speed. As a further improvement measure, a pn junction diode formed in the semiconductor substrate region by the source region and the semiconductor substrate region. For example, a method of applying a forward voltage smaller than the built-in voltage was considered.
JP 9-252125 A

  In the case of the above method, the voltage that can be applied to the semiconductor substrate region is up to the build-in voltage of the pn junction diode. However, when the MOS field effect transistor is used in a high temperature environment, the build-in voltage increases as the temperature rises. The voltage drops and a sufficient effect cannot be exhibited.

  Further, when a high breakdown voltage is required, it is necessary to reduce the concentration of the semiconductor substrate region, so that it is difficult to increase the concentration of the semiconductor substrate region itself.

  In consideration of using a high voltage MOS field effect transistor in a high temperature environment, the present invention keeps the threshold voltage of the MOS field effect transistor low, that is, reduces the concentration of the semiconductor substrate. It is still another object to provide a semiconductor device that suppresses leakage current.

  A source offset region having a concentration higher than that of the substrate having the same conductivity type as that of the substrate is formed between the source electrode and the channel forming region of the MOS field effect transistor formed on the semiconductor substrate, and gate oxidation on the source offset region is performed. By making the film thin, the leakage current of the MOS field effect transistor is suppressed while the threshold voltage of the MOS field effect transistor is kept low.

  One of the main causes of the leakage current of MOS field-effect transistors due to an increase in temperature environment is that the potential barrier near the surface of the pn junction formed at the interface between the source region and the semiconductor substrate region (well region) By going down by rising.

  If a source offset region is provided between the source region and the channel forming region as in the present invention, the concentration of the source offset region is made higher than that of the substrate, and the oxide film on the source offset region is made thin, the MOS field effect transistor While the threshold voltage is kept low, the potential barrier of the pn junction at the interface between the source region and the source offset region can be set high in advance, and leakage current due to an increase in temperature environment can be suppressed.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of a semiconductor device 100 according to the first embodiment of the present invention.

  The semiconductor device 100 includes a first conductivity type (for example, P type) semiconductor substrate region (well region) 1 and a second conductivity type (for example, N type) source region 3 and drain region 2 that are spaced apart from each other. Between the source region 3 and the drain region 2, the channel formation region 4 of the semiconductor substrate region (well region) 1, and the first conductivity type provided in part of the source region 3 in contact with the channel formation region 4. A source offset region 7 having the same conductivity type as that of the semiconductor substrate region (well region) 1 and having a higher concentration than the semiconductor substrate region (well region) 1 of the first conductivity type, and one of the drain regions 2 in contact with the channel formation region 4 A low-concentration drain region 9 provided in the region, a gate oxide film 5 provided on the channel formation region 4, a source gate oxide film 8 thinner than the gate oxide film 5 provided on the source offset region 7, , Low concentration A high breakdown voltage insulating film 10 thicker than the gate oxide film provided on the drain region 9, a source gate oxide film 8, a gate oxide film 5, and a source offset region 7, a channel formation region 4, and a low concentration drain region 9 This is a MOS field effect transistor having a gate electrode 6 provided through an insulating film 10 for high withstand voltage.

  Hereinafter, a mechanism for suppressing the leakage current will be described by taking an N-type MOS field effect transistor as an example. 2 to 5 are band diagrams in the vicinity of the surface of the pn junction formed at the interface between the source region 3 and the source offset region 7, and FIGS. 2 to 3 show the concentration of the source offset region 7 in the semiconductor substrate region (well region) 1. A conventional MOS field effect transistor having the same concentration.

  FIG. 6 depicts the Fermi level position versus temperature for donor or acceptor concentrations, and is quoted from Andrew S. Grove, “Physics and Technology of Semiconductor Device”. In general, when the environmental temperature of an impurity semiconductor is raised, the Fermi level approaches the Fermi level of the intrinsic semiconductor regardless of the conductivity type as shown in FIG. If FIG. 2), it becomes like 102 (FIG. 3) in a high temperature environment, and the potential barrier 11 of the pn junction becomes lower and the leakage current increases as the temperature rises.

  If the concentration of the source offset region 7 is made higher than the concentration of the semiconductor substrate region (well region) 1 as in the present invention, the potential barrier 11 in the band diagram 103 (FIG. 4) of the pn junction in the room temperature environment is conventional. The MOS field effect transistor can be made larger than the potential barrier 11 in the band diagram 101 (FIG. 2). In a high temperature environment, the potential barrier 11 shown in the band diagram 104 (FIG. 5) is larger than the potential barrier 11 in the band diagram 102 (FIG. 3) of the conventional MOS field effect transistor, so that the leakage current is suppressed. The

  Furthermore, in the present invention, by increasing the thickness of the source offset region 7 by reducing the thickness of the oxide film on the source offset region 7, the increase in threshold value of the MOS field effect transistor is suppressed, and the threshold voltage is increased. Leakage current can be suppressed while maintaining low.

  FIG. 7 is a cross-sectional view of a semiconductor device 105 according to the second embodiment of the present invention.

  The semiconductor device 105 includes a source region 3 and a drain region 2 of a second conductivity type (for example, N type) provided on the surface of a semiconductor substrate region (well region) 1 of a first conductivity type (for example, P type) at a distance from each other. Between the source region 3 and the drain region 2, a channel formation region 4 of the semiconductor substrate region (well region) 1, and a low concentration drain region 9 provided in a part of the drain region 2 in contact with the channel formation region 4 A source offset region 7 of the first conductivity type having a concentration higher than that of the semiconductor substrate region (well region) 1 provided in part of the source region 3 in contact with the channel forming region 4, and the channel forming region 4 and the source offset Gate oxide film 5 provided on region 7, high-voltage insulating film 10 thicker than gate oxide film 5 provided on lightly doped drain region 9, channel forming region 4 and lightly doped drain region A gate electrode 6 provided on the gate oxide film 5 and the high breakdown voltage insulating film 10 on the gate electrode 6 and a second gate electrode 16 on the source offset region 7 via the gate oxide film 5 are provided. This is a MOS field effect transistor.

  The mechanism for suppressing the leakage current is the same as in the first embodiment. In the second embodiment, the second gate electrode 16 for controlling the source offset region 7 is provided separately from the gate electrode 6. Leakage current during standby can be reduced by controlling the second gate electrode 16 to be turned off when the MOS field effect transistor is in standby. Alternatively, if the second gate electrode 16 and the drain region 2 are connected, the area where the source region 3 and the semiconductor substrate region (well region) 1 are in contact with each other is reduced, so that the leakage current is reduced accordingly.

  FIG. 8 is a cross-sectional view of a semiconductor device 106 according to the third embodiment of the present invention.

  A semiconductor between the source region 3 and the drain region 2 of the second conductivity type and the source region 3 and the drain region 2 which are spaced from each other on the surface of the first conductivity type semiconductor substrate region (well region) 1. A channel formation region 4 in the substrate region (well region) 1, a low-concentration drain region 9 provided in a part of the drain region 2 in contact with the channel formation region 4, and a source region 3 in contact with the channel formation region 4 Source offset region 7 provided in the region, first gate oxide film 17 provided on channel formation region 4 and source offset region 7, and first gate oxide film provided on lightly doped drain region 9 The first gate electrode 18 provided on the channel formation region 4 and the low-concentration drain region 9 with the first gate oxide film 17 and the high breakdown voltage insulating film 10 being interposed therebetween. The second gate oxide film 19 provided on the first gate electrode 18, the first gate oxide film 17 and the second gate oxide film 19 on the source offset region 7 and the first gate electrode 18 through the first gate oxide film 19. The MOS field effect transistor is characterized in that two gate electrodes 16 are provided and the first gate electrode 18 is in a floating state.

  The mechanism for suppressing the leakage current is the same as in the first embodiment. In the third embodiment, the voltage applied to the second gate electrode 16 for controlling the source offset region 7 is applied to the first gate electrode 18 which is floated via the second gate oxide film 19 via capacitive coupling. Configured.

  If a voltage is applied to the second gate electrode 16, a voltage lower than the applied voltage is applied to the first gate electrode 17 as a result of capacitive coupling, so that the concentration of the semiconductor substrate region (well region) 1 is kept low. The leakage current of the MOS field effect transistor can be suppressed.

Sectional drawing of the semiconductor device 100 which concerns on the 1st Embodiment of this invention. Energy band diagram at the interface between the source region and the channel formation region in a conventional MOS field effect transistor (room temperature environment) Energy band diagram of the interface between the source region and the channel formation region in a conventional MOS field effect transistor (high temperature environment) Energy band diagram of the interface between the source offset region and the channel forming region in the MOS field effect transistor of the present invention (room temperature environment) Energy band diagram of source offset region and channel forming region interface in MOS field effect transistor of the present invention (high temperature environment) Diagram showing the relationship between temperature and Fermi level for impurity semiconductors with different concentrations Sectional drawing of the semiconductor device 105 which concerns on the 2nd Embodiment of this invention. Sectional drawing of the semiconductor device 106 concerning the 3rd Embodiment of this invention.

Explanation of symbols

1 Semiconductor substrate area (well area)
2 drain region 3 source region 4 channel formation region 5 gate oxide film 6 gate electrode 7 source offset region 8 source gate oxide film 9 low concentration drain region 10 high breakdown voltage insulating film 11 potential barrier 12 conduction band 13 Fermi level of intrinsic semiconductor 14 Fermi level 15 Valence band 16 Second gate electrode 17 First gate oxide film 18 First gate electrode 19 Second gate oxide film 101 Energy band diagram of interface between source offset region and channel formation region in room temperature environment of conventional MOS transistor 102 Energy band diagram of interface between source offset region and channel forming region in high temperature environment of conventional MOS transistor 103 Energy band diagram of interface of source offset region and channel forming region in room temperature environment according to the embodiment of the present invention 104 In the high temperature environment of the embodiment of the present invention Energy band diagram of interface between source offset region and channel forming region

Claims (4)

A source region and a drain region of a second conductivity type provided on the surface of the semiconductor substrate region of the first conductivity type and spaced from each other;
A channel formation region provided in the semiconductor substrate region between the source region and the drain region;
A low concentration drain region provided in part of the drain region in contact with the channel formation region;
A source offset region of a first conductivity type having a concentration higher than that of the semiconductor substrate region provided between the channel formation region and the source region;
A gate oxide film provided on the channel formation region;
A source gate oxide film thinner than the gate oxide film provided on the source offset region;
A high breakdown voltage insulating film thicker than the gate insulating film provided on the low concentration drain region;
A MOS field effect transistor having a gate electrode provided on the gate oxide film, the source gate oxide film, and the high breakdown voltage insulating film. A source region and a drain region of a second conductivity type provided on the surface of the semiconductor substrate region of the first conductivity type and spaced from each other;
A channel forming region provided in the semiconductor substrate region between the source region and the drain region;
A low concentration drain region provided in part of the drain region in contact with the channel formation region;
A source offset region of a first conductivity type having a concentration higher than that of the semiconductor substrate region provided between the channel formation region and the source region;
A gate oxide film provided on the channel formation region and the source offset region;
A high breakdown voltage insulating film thicker than the gate insulating film provided on the low concentration drain region;
A first gate electrode provided on the channel formation region and the low-concentration drain region via the gate oxide film and the high breakdown voltage insulating film;
A MOS field effect transistor having a second gate electrode provided on the source offset region via the gate oxide film.   3. The MOS field effect transistor according to claim 2, wherein the second gate electrode and the drain region have the same potential. A source region and a drain region of a second conductivity type provided on the surface of the semiconductor substrate region of the first conductivity type and spaced from each other;
A channel forming region provided in the semiconductor substrate region between the source region and the drain region;
A low concentration drain region provided in part of the drain region in contact with the channel formation region;
A source offset region of a first conductivity type having a concentration higher than that of the semiconductor substrate region provided between the channel formation region and the source region;
A first gate oxide film provided on the channel formation region and the source offset region;
A high breakdown voltage insulating film thicker than the first gate oxide film provided on the low-concentration drain region;
A first gate electrode provided on the channel formation region and the low-concentration drain region via the first gate oxide film and the high breakdown voltage insulating film;
A second gate oxide film provided on the first gate electrode;
A second gate electrode provided on the source offset region and the first gate electrode via the first gate oxide film and the second gate oxide film, and the first gate electrode is set in a floating state. MOS field effect transistor.

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