JP2007335479A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007335479A
JP2007335479A JP2006162943A JP2006162943A JP2007335479A JP 2007335479 A JP2007335479 A JP 2007335479A JP 2006162943 A JP2006162943 A JP 2006162943A JP 2006162943 A JP2006162943 A JP 2006162943A JP 2007335479 A JP2007335479 A JP 2007335479A
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semiconductor element
substrate
connection
semiconductor device
connection electrodes
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Takatoshi Osumi
貴寿 大隅
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress curving of a semiconductor element due to a difference in thermal expansion coefficient between the semiconductor element and a substrate to which the semiconductor element is mounted, can reduce the internal stress of the semiconductor element, and can improve the degree of freedom in structural design of the semiconductor element. <P>SOLUTION: A substrate 5 to which a flip-chip connection type semiconductor element 1 is mounted has an opening 8 reaching one surface of the substrate 5 from the other surface thereof to suppress an influence of curving of the substrate 5 on the semiconductor element 1, due to a difference in thermal expansion coefficient between the substrate 5 and the semiconductor element 1. The opening 8 is entirely formed inside by a half or more of pitch of connection electrodes 4 from the innermost row of the connection electrodes 4 on the substrate 5 under the semiconductor element 1. Due to the opening 8, the curving of semiconductor element 1 is reduced that occurs due to a difference of thermal expansion coefficient between the semiconductor element 1 and the substrate 5, the connectability of the semiconductor element 1 can be improved, and the degree of freedom in assembling process increases as a result. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明はＬＳＩチップの集積回路部を保護し、かつ外部装置とＬＳＩチップの電気的接続を安定的に確保し、さらに高密度な実装を可能とした半導体装置に係り、特に接続端子の多い半導体素子を搭載する半導体装置に関するものである。   The present invention relates to a semiconductor device that protects an integrated circuit portion of an LSI chip, stably secures an electrical connection between an external device and the LSI chip, and enables high-density mounting, and particularly a semiconductor having many connection terminals. The present invention relates to a semiconductor device on which an element is mounted.

近年、情報通信機器、事務用電子機器、家庭用電子機器、測定装置、組み立てロボット等の産業用電子機器、医療用電子機器、電子玩具等の分野は、小型軽量化が進み、半導体装置には実勢面積の小型化が強く求められてきた。これらの要求に応えるものの一つとしてＢＧＡ（ボールグリッドアレイ）等が用いられている。一方、ＢＧＡに搭載される半導体素子は高密度化に伴い、小チップ且つ多ピン化への対応が求められている。   In recent years, fields such as information and communication equipment, office electronic equipment, household electronic equipment, measuring equipment, assembly robots, and other industrial electronic equipment, medical electronic equipment, and electronic toys have become smaller and lighter. There has been a strong demand for downsizing the actual area. A BGA (ball grid array) or the like is used as one of those that meet these requirements. On the other hand, the semiconductor elements mounted on the BGA are required to cope with a small chip and a large number of pins as the density increases.

以下、このような要求を実現した、従来のＢＧＡタイプの半導体装置（半導体パッケージ）の構成の一例を、図９に基づいて説明する。
図９に示すように、ＢＧＡタイプの半導体装置は、一方の面に接続電極４を含む配線回路を有し、他方の面に前記接続電極４と内部のビア６を介して接続された外部端子７を有する基板５と、基板５の一方の面上にフェイスダウンに搭載され、その接続端子２が基板５の接続電極４と電気的に接続されるフリップチップ接続型の半導体素子１と、接続電極４と接続端子２と半導体素子１の回路部表面を覆うアンダーフィル樹脂３を備えて構成されている。 Hereinafter, an example of the configuration of a conventional BGA type semiconductor device (semiconductor package) that realizes such a requirement will be described with reference to FIG.
As shown in FIG. 9, the BGA type semiconductor device has a wiring circuit including a connection electrode 4 on one surface, and an external terminal connected to the other surface via the connection electrode 4 and an internal via 6. 7, a flip-chip connection type semiconductor device 1 that is mounted face down on one surface of the substrate 5, and whose connection terminals 2 are electrically connected to the connection electrodes 4 of the substrate 5, The electrode 4, the connection terminal 2, and the underfill resin 3 that covers the circuit portion surface of the semiconductor element 1 are provided.

またＢＧＡタイプの半導体装置の他の一例が、特許文献１に開示されている。
半導体装置（半導体パッケージ）に、ポリイミドなどの樹脂フィルムを絶縁ベース基板として利用すると、セラミックスなどと比較して吸湿しやすく、絶縁ベース基板側からの水の浸入を防止することは困難である。したがって、外部接続端子としてはんだボールをＩＲリフローさせる工程や半導体パッケージをプリント配線基板にはんだ実装する際に、絶縁ベース基板や半導体チップ接着材界面付近にトラップされた水に起因されるふくれや剥がれ、あるいは封止樹脂のクラックなどが発生しやすく、半導体チップと配線パターンとの接続部が剥離して電気的接続不良を引き起こすという問題が発生する。 Another example of the BGA type semiconductor device is disclosed in Patent Document 1.
When a resin film such as polyimide is used as an insulating base substrate in a semiconductor device (semiconductor package), it is easier to absorb moisture than ceramics and it is difficult to prevent water from entering from the insulating base substrate side. Therefore, when the solder balls are IR reflowed as external connection terminals or when the semiconductor package is solder-mounted on the printed wiring board, blistering or peeling caused by water trapped near the interface between the insulating base substrate and the semiconductor chip adhesive, Or the crack of sealing resin etc. generate | occur | produce easily and the problem that the connection part of a semiconductor chip and a wiring pattern peels and causes an electrical connection defect generate | occur | produces.

この特許文献１に開示されている半導体装置（半導体パッケージ）は、この問題を解決するものであり、絶縁ベース基板の一方の面に配線パターンが形成され、他方の面に外部接続端子が形成された半導体チップ搭載用基板と、半導体チップ搭載用基板に接着材を介して接着された半導体チップと、半導体チップを封止する封止樹脂とにより成り、半導体パッケージ中央領域の絶縁ベース基板及び接着材を予め除去し、絶縁ベース基板及び接着材を貫通し半導体チップに達する凹部を設けている。   The semiconductor device (semiconductor package) disclosed in Patent Document 1 solves this problem, and a wiring pattern is formed on one surface of an insulating base substrate, and an external connection terminal is formed on the other surface. A semiconductor chip mounting substrate, a semiconductor chip bonded to the semiconductor chip mounting substrate via an adhesive, and a sealing resin for sealing the semiconductor chip. Is removed in advance, and a recess is provided that penetrates the insulating base substrate and the adhesive and reaches the semiconductor chip.

この凹部により、絶縁ベース基板や半導体チップ接着材界面付近にトラップされた水を蒸気として逃すことができ、トラップされた水に起因して半導体チップと配線パターンとの接続部が剥離して電気的接続不良を引き起こすという問題を解決している。
特開平０９−１４８４７５号公報 This recess allows water trapped near the interface between the insulating base substrate and the semiconductor chip adhesive to escape as vapor, and the connection between the semiconductor chip and the wiring pattern is peeled off due to the trapped water, and the electrical It solves the problem of causing poor connection.
JP 09-148475 A

しかしながら、図９に示すフリップチップ接続型半導体素子１を搭載した半導体装置の構造では、はんだ実装される際等で半導体装置が加熱される状態となると、半導体素子１とこの半導体素子１が搭載される基板５との熱膨張係数の差により、基板５が半導体素子１より大きく伸び、このとき基板５の中央部が半導体素子１により抑えられているため、図８（ａ）に示すように、基板５の両端が下方側（半導体素子１とは反対側）に反り、この基板５の反りの作用により半導体素子１に反りが発生する。そして、この反りに起因する半導体素子１の内部応力により、半導体素子１の配線破壊やトランジスタの特性変動が発生する可能性が高まる。   However, in the structure of the semiconductor device on which the flip-chip connection type semiconductor element 1 shown in FIG. 9 is mounted, when the semiconductor device is heated, such as when solder mounting, the semiconductor element 1 and the semiconductor element 1 are mounted. Due to the difference in thermal expansion coefficient with the substrate 5, the substrate 5 extends larger than the semiconductor element 1, and at this time, the central part of the substrate 5 is suppressed by the semiconductor element 1. Both ends of the substrate 5 warp downward (on the side opposite to the semiconductor element 1), and the warp of the semiconductor element 1 is generated by the warping action of the substrate 5. Then, the internal stress of the semiconductor element 1 resulting from the warpage increases the possibility of the wiring destruction of the semiconductor element 1 and the transistor characteristic fluctuation occurring.

また特許文献１に開示されている半導体装置は、半導体チップを封止樹脂により封止し半導体チップと基板を堅固に固定しているため、上記熱膨張係数の差により発生する半導体チップの反りを、封止樹脂が抑えようとする。したがって、反って半導体チップの内部応力による半導体チップの配線破壊やトランジスタの特性変動が発生しやすくなる。   In addition, since the semiconductor device disclosed in Patent Document 1 is sealed with a sealing resin and the semiconductor chip and the substrate are firmly fixed, the warp of the semiconductor chip that occurs due to the difference in the thermal expansion coefficient is avoided. The sealing resin tries to suppress. Therefore, warpage of the semiconductor chip due to internal stress of the semiconductor chip and transistor characteristic variation are likely to occur.

このように、反りに起因する半導体素子の内部応力により半導体素子の配線破壊やトランジスタの特性変動が発生しやすくなることによって、自由なプロセス設計が阻害され、半導体素子の配線破壊やトランジスタの特性変動に対応してファインプロセス化、チップ薄化の観点から電気的接続に必要な接続電極の平坦度の減少に対応しうる構造設計が困難となる。   As described above, the internal stress of the semiconductor element caused by the warpage is likely to cause the breakdown of the wiring of the semiconductor element and the characteristic fluctuation of the transistor, thereby hindering the free process design and the breakdown of the wiring of the semiconductor element and the characteristic fluctuation of the transistor. Therefore, it is difficult to design a structure that can cope with a decrease in the flatness of the connection electrode necessary for electrical connection from the viewpoint of fine processing and chip thinning.

そこで、本発明は、半導体素子の実装性を向上させるとともに、半導体素子とこの半導体素子が搭載される基板との熱膨張係数の差に起因する半導体素子の反りを抑制でき、半導体素子の内部応力を低減し、半導体素子の構造設計自由度の向上を可能とする半導体装置を提供することを目的としたものである。   Therefore, the present invention improves the mountability of the semiconductor element and can suppress the warpage of the semiconductor element due to the difference in thermal expansion coefficient between the semiconductor element and the substrate on which the semiconductor element is mounted. It is an object of the present invention to provide a semiconductor device that can improve the structural design freedom of semiconductor elements.

前記課題を解決するために、本発明の半導体装置は、一方の面に接続電極を含む配線回路を有し、他方の面に前記接続電極と接続された外部端子を有する基板と、前記基板の一方の面上にフェイスダウンに搭載され、その接続端子が前記基板の接続電極と電気的に接続される半導体素子と、前記基板に前記他方の面から前記一方の面までに到るまで設けられ、前記基板と前記半導体素子の熱膨張率の差による基板の反りの作用が半導体素子に及ぶことを抑制する開口と、前記接続電極と前記接続端子と前記半導体素子の回路部表面を覆い、且つ前記溝に充填しないアンダーフィル樹脂を備え、前記基板および半導体素子の上方が開放されていることを特徴とする。   In order to solve the above problems, a semiconductor device of the present invention has a wiring circuit including a connection electrode on one surface and a substrate having an external terminal connected to the connection electrode on the other surface; The semiconductor device is mounted face down on one surface, and its connection terminal is electrically connected to the connection electrode of the substrate, and is provided on the substrate from the other surface to the one surface. An opening that suppresses the effect of warping of the substrate due to a difference in thermal expansion coefficient between the substrate and the semiconductor element on the semiconductor element, covers the connection electrode, the connection terminal, and the surface of the circuit portion of the semiconductor element, and An underfill resin that does not fill the groove is provided, and the substrate and the semiconductor element are open above.

上記構成によれば、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子と半導体素子が搭載される基板との熱膨張係数の差による基板の反りの作用が半導体素子へ及ぶことが開口により抑制され、かつ基板および半導体素子の上方が開放されていることにより、前記熱膨張係数の差に起因する半導体素子の反りが抑制される。よって、半導体素子の内部応力が低減され、半導体素子の配線破壊やトランジスタの特性変動を抑制することができる。   According to the above configuration, when the semiconductor device is heated during solder mounting or the like, the warping action of the substrate due to the difference in thermal expansion coefficient between the semiconductor element and the substrate on which the semiconductor element is mounted may reach the semiconductor element. The warpage of the semiconductor element due to the difference in the thermal expansion coefficient is suppressed by being suppressed by the opening and the upper part of the substrate and the semiconductor element being opened. Therefore, the internal stress of the semiconductor element is reduced, and the wiring breakdown of the semiconductor element and the transistor characteristic fluctuation can be suppressed.

上記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、全面に形成される。
あるいは前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の矩形開口が格子状に配置されて形成される。この開口の構成によると、開口が前記全面に形成されることと比較して、配線自由度を向上させることができる。 The opening is formed on the entire surface on the inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes.
Alternatively, the opening is formed by arranging a plurality of rectangular openings in a grid pattern on the inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. According to the configuration of this opening, the degree of freedom of wiring can be improved as compared with the case where the opening is formed on the entire surface.

あるいは前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の円形開口が格子状に配置されて形成される。この開口の構成によると、開口が前記全面に形成されることと比較して、配線自由度を向上させることができる。   Alternatively, the openings are formed by arranging a plurality of circular openings in a lattice pattern on the inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. According to the configuration of this opening, the degree of freedom of wiring can be improved as compared with the case where the opening is formed on the entire surface.

あるいは前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の溝が列状に配置されて形成される。この開口の構成によると、開口が前記全面に形成されることと比較して、配線自由度を向上させることができる。   Alternatively, the opening is formed by arranging a plurality of grooves in a row inside the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance that is half or more the pitch of the connection electrodes. According to the configuration of this opening, the degree of freedom of wiring can be improved as compared with the case where the opening is formed on the entire surface.

あるいは前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の溝が前記半導体素子の中心から放射状に配置されて形成される。この開口の構成によると、開口が前記全面に形成されることと比較して、配線自由度を向上させることができる。   Alternatively, the opening has a plurality of grooves arranged radially from the center of the semiconductor element at an inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. It is formed. According to the configuration of this opening, the degree of freedom of wiring can be improved as compared with the case where the opening is formed on the entire surface.

あるいは前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、全面に配置され且つ前記半導体素子の幅を超える領域が存在する溝により形成される。   Alternatively, the opening is located on the entire surface of the innermost row of the connection electrodes of the substrate below the semiconductor element and more than half the pitch of the connection electrodes, and there is a region exceeding the width of the semiconductor element. It is formed by the groove | channel which carries out.

また本発明の半導体装置は、一方の面に接続電極を含む配線回路を有し、他方の面に前記接続電極と接続された外部端子を有する４枚の基板と、各基板同士を平面的に間隔を開けて配置することにより生じる溝と、前記溝を中心として前記４枚の基板の一方の面上にフェイスダウンに搭載され、前記各基板の接続電極とその接続端子が電気的に接続される半導体素子と、前記接続電極と前記接続端子と前記半導体素子の回路部表面を覆い且つ前記溝に充填しないアンダーフィル樹脂を備え、前記基板および半導体素子の上方が開放されていることを特徴とする。   The semiconductor device of the present invention has a wiring circuit including a connection electrode on one surface, four substrates having external terminals connected to the connection electrode on the other surface, and each substrate in a plane. A groove formed by disposing them at intervals, and mounted face down on one surface of the four substrates around the groove, and the connection electrodes of the substrates and their connection terminals are electrically connected A semiconductor element, an underfill resin that covers a surface of a circuit part of the semiconductor element and does not fill the groove, and the upper side of the substrate and the semiconductor element is open. To do.

上記構成によれば、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子と半導体素子が搭載される４枚の基板との熱膨張係数の差による４枚の基板の反りの作用が半導体素子へ及ぶことが各基板同士間の溝により抑制され、かつ４枚の基板および半導体素子の上方が開放されていることにより、前記熱膨張係数の差に起因する半導体素子の反りが抑制される。よって、半導体素子の内部応力が低減され、半導体素子の配線破壊やトランジスタの特性変動を抑制することができる。   According to the above configuration, when the semiconductor device is heated during solder mounting or the like, the warping action of the four substrates due to the difference in the thermal expansion coefficient between the semiconductor element and the four substrates on which the semiconductor element is mounted. The warpage of the semiconductor element due to the difference in the thermal expansion coefficient is suppressed by extending to the semiconductor element by the grooves between the substrates and by opening the upper part of the four substrates and the semiconductor element. The Therefore, the internal stress of the semiconductor element is reduced, and the wiring breakdown of the semiconductor element and the transistor characteristic fluctuation can be suppressed.

本発明の半導体装置は、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子と半導体素子が搭載される基板との熱膨張係数の差による半導体素子の反りを抑制し、半導体素子の内部応力を低減することにより、半導体素子の配線破壊やトランジスタの特性変動を抑制でき、よって組立プロセスの自由度を増大させることができ、またアンダーフィル樹脂をパッケージ裏面から注入することができることにより、アンダーフィル樹脂のボイドを低減することができ、その結果、半導体素子接続部の信頼性を向上できる、という効果を有している。   The semiconductor device of the present invention suppresses the warpage of the semiconductor element due to the difference in thermal expansion coefficient between the semiconductor element and the substrate on which the semiconductor element is mounted when the semiconductor device is heated during solder mounting or the like. By reducing the internal stress, it is possible to suppress the breakdown of the wiring of the semiconductor element and the characteristic variation of the transistor, thereby increasing the degree of freedom of the assembly process, and by being able to inject the underfill resin from the back of the package, The voids of the underfill resin can be reduced, and as a result, the reliability of the semiconductor element connection portion can be improved.

以下、本発明の実施の形態を、図面を参照しながら説明する。なお、従来の半導体装置の構成と同一の構成には同一の符号を付して説明を省略する。
［実施の形態１］
図１は本発明の実施の形態１における半導体装置の構造を示す断面図および半導体装置を構成する基板の平面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components as those of the conventional semiconductor device are denoted by the same reference numerals, and the description thereof is omitted.
[Embodiment 1]
FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to Embodiment 1 of the present invention and a plan view of a substrate constituting the semiconductor device.

図１に示すように、基板５に、半導体素子１の下部の基板５の接続電極４の最内列より接続電極４のピッチの半分の距離以上内側に、全面に、他方の面から一方の面までに到達する開口８が新たに設けられている。   As shown in FIG. 1, the substrate 5 has one surface from the other surface to the inner side of the innermost row of the connection electrodes 4 of the lower substrate 5 of the semiconductor element 1, more than half the pitch of the connection electrodes 4. An opening 8 reaching the surface is newly provided.

また半導体素子１と基板５の間に、接続端子２と接続電極４と半導体素子１の回路部表面を覆い、且つ開口８に充填しないようアンダーフィル樹脂３を介在させ、アンダーフィル樹脂３を熱硬化させて接続部を保護している。   In addition, the underfill resin 3 is interposed between the semiconductor element 1 and the substrate 5 so as to cover the connection terminal 2, the connection electrode 4, and the circuit portion surface of the semiconductor element 1 and not to fill the opening 8. The connection is protected by curing.

また半導体素子１と基板５の上方を開放して基板５の自由度を確保している。
このような構成の半導体装置は、下記の手順で製造される。
まず、めっき法やボール搭載法、印刷法などによって半導体素子１上のパッドに接続端子２を形成する。 Further, the upper portions of the semiconductor element 1 and the substrate 5 are opened to ensure the degree of freedom of the substrate 5.
The semiconductor device having such a configuration is manufactured by the following procedure.
First, the connection terminals 2 are formed on the pads on the semiconductor element 1 by plating, ball mounting, printing, or the like.

次に、接続端子２を有する半導体素子１をフェイスダウンにし、接続端子２をフラックスや導電性ペーストなどに転写し、基板５に接続端子２あたり５ｇｆ以上の加圧力により押圧して搭載したのち、接続端子２の融点を超える温度を付加して半導体素子１と基板５を接合して接続端子２と接続電極４を電気的に接続する。   Next, the semiconductor element 1 having the connection terminal 2 is face-downed, the connection terminal 2 is transferred to a flux or a conductive paste, and mounted on the substrate 5 by pressing with a pressure of 5 gf or more per connection terminal 2. The semiconductor element 1 and the substrate 5 are joined by applying a temperature exceeding the melting point of the connection terminal 2 to electrically connect the connection terminal 2 and the connection electrode 4.

次に、半導体素子１と基板５の間に接続端子２と接続電極４と半導体素子１の回路部表面を覆い、且つ開口８に充填しないようアンダーフィル樹脂３を介在させ、アンダーフィル樹脂３を熱硬化させて接続部を保護する。   Next, the underfill resin 3 is interposed between the semiconductor element 1 and the substrate 5 so as to cover the connection terminal 2, the connection electrode 4, and the circuit portion surface of the semiconductor element 1 and not to fill the opening 8. Heat cure to protect the connection.

なお、上記接続端子２の材質は半田であるが、Cu、樹脂バンプなどを用いてもよい。更なる接続特性の向上を図る場合には、低温で溶融するベースレジンの採用等の方法が考えられる。また上記アンダーフィル樹脂３は半導体素子１を搭載する前に塗布または貼付してもよいし、搭載した後でもよい。搭載した後の場合、アンダーフィル樹脂３を半導体素子１の側面から塗布してもよいし、基板５の開口８から注入してもよい。また上記外部端子８は、はんだボール等が一般的であるが、はんだ以外の金属ボールやボール形状をとらないランドやバンプでもよい。   The connecting terminal 2 is made of solder, but Cu, resin bumps, or the like may be used. In order to further improve the connection characteristics, a method such as the use of a base resin that melts at a low temperature can be considered. The underfill resin 3 may be applied or pasted before mounting the semiconductor element 1 or after mounting. After mounting, the underfill resin 3 may be applied from the side surface of the semiconductor element 1 or may be injected from the opening 8 of the substrate 5. The external terminal 8 is generally a solder ball or the like, but may be a metal ball other than solder or a land or bump that does not take the shape of a ball.

さて、上記基板５の材質は、ガラス布積層エポキシ（ガラエポ）やアラミド不織布などの繊維強化樹脂層などの繊維強化樹脂層が用いられる。また基板の層数は要求される配線密度によって４〜１２層基板が適宜用いられる。基板５の配線回路の厚みは５μｍ〜２０μｍ程度であり、内層の配線材料はＣｕやＣｕ−Ｎｉなど、表面の配線材料はＣｕ−Ｎｉ−Ａｕなどが用いられる。   As the material of the substrate 5, a fiber reinforced resin layer such as a fiber reinforced resin layer such as a glass cloth laminated epoxy (glass epoxy) or an aramid nonwoven fabric is used. As the number of layers of the substrate, a 4 to 12 layer substrate is appropriately used depending on the required wiring density. The thickness of the wiring circuit of the substrate 5 is about 5 μm to 20 μm, Cu or Cu—Ni is used as the inner layer wiring material, and Cu—Ni—Au or the like is used as the surface wiring material.

また半導体素子１の厚みは３０μｍ以上３００μｍ以下の範囲で多く用いられ、また基板５の厚みは２６０μｍ以上１０００μｍ以下の範囲で多く用いられる。
また基板５の接続端子２のピッチはチップ外周部に配置（一列配列、格子配列）された場合５０μｍ〜８０μｍであり、チップ全面に配置（格子配列）された場合１５０〜２５０μｍである。 The thickness of the semiconductor element 1 is often used in the range of 30 μm to 300 μm, and the thickness of the substrate 5 is frequently used in the range of 260 μm to 1000 μm.
Further, the pitch of the connection terminals 2 of the substrate 5 is 50 μm to 80 μm when arranged on the outer periphery of the chip (single line arrangement, grid arrangement), and 150 to 250 μm when arranged on the entire surface of the chip (grid arrangement).

以上のように本実施の形態１によれば、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子１と半導体素子１が搭載される基板５との熱膨張係数の差による基板５の反りの作用が半導体素子１へ及ぶことが、図８（ｂ）に示すように、開口８により抑制され、かつ基板５および半導体素子１の上方が開放されていることにより、基板５と半導体素子１の熱膨張係数の差に起因する半導体素子１の反りを抑制することができ、よって、半導体素子１の内部応力が低減され、半導体素子１の配線破壊やトランジスタの特性変動を抑制することができ、またアンダーフィル樹脂３をパッケージ裏面から注入することができ、アンダーフィル樹脂３のボイドを低減することができ、その結果、半導体素子１の接続部の信頼性を向上できる。
［実施の形態２，３］
図２、図３はそれぞれ、本発明の実施の形態２，３における半導体装置の構造を示す断面図および半導体装置を構成する基板の平面図である。 As described above, according to the first embodiment, when the semiconductor device is heated during solder mounting or the like, the substrate 5 due to the difference in thermal expansion coefficient between the semiconductor element 1 and the substrate 5 on which the semiconductor element 1 is mounted. As shown in FIG. 8B, the warping action of the substrate 5 is suppressed by the opening 8 and the upper side of the substrate 5 and the semiconductor element 1 is opened. The warpage of the semiconductor element 1 due to the difference in the thermal expansion coefficient of the element 1 can be suppressed, so that the internal stress of the semiconductor element 1 is reduced and the wiring breakdown of the semiconductor element 1 and the transistor characteristic fluctuation are suppressed. The underfill resin 3 can be injected from the back surface of the package, and voids in the underfill resin 3 can be reduced. As a result, the reliability of the connection portion of the semiconductor element 1 can be improved.
[Embodiments 2 and 3]
2 and 3 are a sectional view showing the structure of the semiconductor device according to the second and third embodiments of the present invention and a plan view of a substrate constituting the semiconductor device, respectively.

この実施の形態２，３では、前記実施の形態１の半導体装置の開口８、すなわち半導体素子１の下部の基板５の接続電極４の最内列より接続電極４のピッチの半分の距離以上内側に、全面に形成された開口８に代えて、図２、図３に示すように、半導体素子１の下部の基板５の接続電極４の最内列より接続電極４のピッチの半分の距離以上内側に、複数の矩形開口１０（実施の形態２）または円形開口１１（実施の形態３）を格子状に配置して形成された開口１２を設けている。   In the second and third embodiments, the opening 8 of the semiconductor device of the first embodiment, that is, the inner side of the innermost row of the connection electrodes 4 of the substrate 5 below the semiconductor element 1 is more than the distance of half the pitch of the connection electrodes 4. In addition, instead of the openings 8 formed on the entire surface, as shown in FIGS. 2 and 3, the distance from the innermost row of the connection electrodes 4 of the substrate 5 on the lower side of the semiconductor element 1 to a distance equal to or more than half the pitch of the connection electrodes 4. Inside, a plurality of rectangular openings 10 (Embodiment 2) or circular openings 11 (Embodiment 3) are provided in an opening 12 formed in a lattice pattern.

なお、複数の矩形開口１０または円形開口１１の格子ピッチは面内で変則的でもよく、また格子配置はフルマトリクスに配置してもよいし、一部配置しなくてもよい。複数の矩形開口１０または円形開口１１の各サイズは全て均一でもよいし、不均一でもよい。   Note that the lattice pitch of the plurality of rectangular openings 10 or the circular openings 11 may be irregular in the plane, and the lattice arrangement may be arranged in a full matrix or may not be partially arranged. Each size of the plurality of rectangular openings 10 or circular openings 11 may be uniform or non-uniform.

またこの半導体装置の製造方法、接続端子２の材質・ピッチ、アンダーフィル樹脂３の塗布方法、外部端子７の形状、半導体素子１の厚さ、基板５の材質・厚さ等は、実施の形態１と同様であり、説明を省略する。   Further, the manufacturing method of the semiconductor device, the material / pitch of the connection terminals 2, the coating method of the underfill resin 3, the shape of the external terminal 7, the thickness of the semiconductor element 1, the material / thickness of the substrate 5, etc. 1 and is not described here.

以上のように本実施の形態２，３によれば、実施の形態１と同様に、基板５に開口１２を備えていることから、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子１と基板５との熱膨張係数の差による基板５の反りの作用が半導体素子１へ及ぶことが抑制され、かつ基板５および半導体素子１の上方が開放されていることにより、基板５と半導体素子１の熱膨張係数の差に起因する半導体素子１の反りを抑制することができ、よって、半導体素子１の内部応力が低減され、半導体素子１の配線破壊やトランジスタの特性変動を抑制することができ、またアンダーフィル樹脂３をパッケージ裏面から注入することができ、アンダーフィル樹脂３のボイドを低減することができ、その結果、半導体素子１の接続部の信頼性を向上できる。   As described above, according to the second and third embodiments, since the substrate 5 includes the opening 12 as in the first embodiment, when the semiconductor device is heated during solder mounting, the semiconductor The warping action of the substrate 5 due to the difference in thermal expansion coefficient between the element 1 and the substrate 5 is suppressed from reaching the semiconductor element 1 and the upper side of the substrate 5 and the semiconductor element 1 is opened. The warpage of the semiconductor element 1 due to the difference in the thermal expansion coefficient of the semiconductor element 1 can be suppressed, so that the internal stress of the semiconductor element 1 is reduced and the breakdown of the wiring of the semiconductor element 1 and the fluctuation of the transistor characteristics are suppressed. The underfill resin 3 can be injected from the back surface of the package, and voids in the underfill resin 3 can be reduced. As a result, the reliability of the connection portion of the semiconductor element 1 can be improved.

また開口１２は、実施の形態１に開示した開口８と比較して配線自由度を向上させることができる。これにより、半導体素子１の内部応力を低減することがより可能となり、半導体素子１の配線破壊やトランジスタの特性変動を抑制させるとともに、組立プロセスの自由度を増大させることができる。
［実施の形態４，５］
図４、図５はそれぞれ、本発明の実施の形態４，５における半導体装置の構造を示す断面図および半導体装置を構成する基板の平面図である。 Further, the opening 12 can improve the degree of freedom of wiring as compared with the opening 8 disclosed in the first embodiment. As a result, the internal stress of the semiconductor element 1 can be further reduced, wiring breakdown of the semiconductor element 1 and transistor characteristic fluctuations can be suppressed, and the degree of freedom of the assembly process can be increased.
[Embodiments 4 and 5]
4 and 5 are a sectional view showing the structure of the semiconductor device according to the fourth and fifth embodiments of the present invention and a plan view of a substrate constituting the semiconductor device, respectively.

この実施の形態４，５では、前記実施の形態１の半導体装置の開口８、すなわち半導体素子１の下部の基板５の接続電極４の最内列より接続電極４のピッチの半分の距離以上内側に、全面に形成された開口８に代えて、図４、図５に示すように、半導体素子１の下部の基板５の接続電極４の最内列より接続電極４のピッチの半分の距離以上内側に、他方の面から一方の面まで到達する複数の溝９が列状（実施の形態４）または放射状（実施の形態５）に配置されて形成された開口１３を設けている。   In the fourth and fifth embodiments, the opening 8 of the semiconductor device of the first embodiment, that is, the inner side of the innermost row of the connection electrodes 4 of the substrate 5 below the semiconductor element 1 is more than the distance of half the pitch of the connection electrodes 4. In addition, instead of the openings 8 formed on the entire surface, as shown in FIGS. 4 and 5, the distance from the innermost row of the connection electrodes 4 of the substrate 5 below the semiconductor element 1 to a distance equal to or more than half the pitch of the connection electrodes 4. A plurality of grooves 9 reaching from the other surface to the one surface are provided on the inner side, and the openings 13 are formed in a row (Embodiment 4) or radial (Embodiment 5).

なお、溝９のピッチは面内で変則的でもよく、また溝９のサイズは全て均一でもよいし、不均一でもよい。
またこの半導体装置の製造方法、接続端子２の材質・ピッチ、アンダーフィル樹脂３の塗布方法、外部端子７の形状、半導体素子１の厚さ、基板５の材質・厚さ等は、実施の形態１と同様であり、説明を省略する。 The pitch of the grooves 9 may be irregular within the plane, and the sizes of the grooves 9 may be all uniform or non-uniform.
Further, the manufacturing method of the semiconductor device, the material / pitch of the connection terminals 2, the coating method of the underfill resin 3, the shape of the external terminal 7, the thickness of the semiconductor element 1, the material / thickness of the substrate 5, etc. 1 and is not described here.

以上のように本実施の形態４，５によれば、実施の形態１と同様に、基板５に複数の溝９からなる開口１３を備えていることから、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子１と基板５との熱膨張係数の差による基板５の反りの作用が半導体素子１へ及ぶことが抑制され、かつ基板５および半導体素子１の上方が開放されていることにより、基板５と半導体素子１の熱膨張係数の差に起因する半導体素子１の反りを抑制することができ、よって、半導体素子１の内部応力が低減され、半導体素子１の配線破壊やトランジスタの特性変動を抑制することができ、またアンダーフィル樹脂３をパッケージ裏面から注入することができ、アンダーフィル樹脂３のボイドを低減することができ、その結果、半導体素子１の接続部の信頼性を向上できる。   As described above, according to the fourth and fifth embodiments, as in the first embodiment, the substrate 5 is provided with the openings 13 formed of the plurality of grooves 9, so that the semiconductor device is mounted by soldering or the like. When heated, the warping action of the substrate 5 due to the difference in thermal expansion coefficient between the semiconductor element 1 and the substrate 5 is suppressed from reaching the semiconductor element 1, and the upper side of the substrate 5 and the semiconductor element 1 is opened. As a result, the warpage of the semiconductor element 1 due to the difference in the thermal expansion coefficient between the substrate 5 and the semiconductor element 1 can be suppressed, so that the internal stress of the semiconductor element 1 is reduced, the wiring breakdown of the semiconductor element 1 and the transistor Variation in the characteristics of the underfill resin 3 can be suppressed, and the underfill resin 3 can be injected from the back surface of the package, and voids in the underfill resin 3 can be reduced. -Reliability can be improved.

また開口１３は、実施の形態１に開示した開口８と比較して配線自由度を向上させることができる。これにより、半導体素子１の内部応力を低減することがより可能となり、半導体素子１の配線破壊やトランジスタの特性変動を抑制させるとともに、組立プロセスの自由度を増大させることができる。
［実施の形態６］
図６は、本発明の実施の形態６における半導体装置の構造を示す断面図および半導体装置を構成する基板の平面図である。 Further, the opening 13 can improve the degree of freedom of wiring as compared with the opening 8 disclosed in the first embodiment. As a result, the internal stress of the semiconductor element 1 can be further reduced, wiring breakdown of the semiconductor element 1 and transistor characteristic fluctuations can be suppressed, and the degree of freedom of the assembly process can be increased.
[Embodiment 6]
FIG. 6 is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment of the present invention and a plan view of the substrate constituting the semiconductor device.

この実施の形態６では、前記実施の形態１の半導体装置の開口８、すなわち半導体素子１の下部の基板５の接続電極４の最内列より接続電極４のピッチの半分の距離以上内側に、全面に形成された開口８に代えて、図６に示すように、半導体素子１の下部の基板５の接続電極４の最内列より接続電極４のピッチの半分の距離以上内側に、全面に配置され且つ半導体素子１の幅を超える領域が存在する他方の面から一方の面まで到達する溝１４からなる開口１５が設けられている。   In the sixth embodiment, the opening 8 of the semiconductor device of the first embodiment, that is, the inner side of the innermost row of the connection electrodes 4 of the substrate 5 below the semiconductor element 1 is more than a distance half the pitch of the connection electrodes 4, Instead of the openings 8 formed on the entire surface, as shown in FIG. 6, the entire surface is more than a distance half the pitch of the connection electrodes 4 from the innermost row of the connection electrodes 4 of the substrate 5 below the semiconductor element 1. An opening 15 including a groove 14 is provided which reaches the one surface from the other surface where the region that is disposed and exceeds the width of the semiconductor element 1 exists.

なお、溝１４は半導体素子１の幅を越える部分の大きさは均一でもよいし、不均一でもよい。また溝９は単数でもよいし、複数でもよい。
またこの半導体装置の製造方法、接続端子２の材質・ピッチ、アンダーフィル樹脂３の塗布方法、外部端子７の形状、半導体素子１の厚さ、基板５の材質・厚さ等は、実施の形態１と同様であり、説明を省略する。 The size of the portion of the groove 14 that exceeds the width of the semiconductor element 1 may be uniform or non-uniform. Further, the groove 9 may be single or plural.
Further, the manufacturing method of the semiconductor device, the material / pitch of the connection terminals 2, the coating method of the underfill resin 3, the shape of the external terminal 7, the thickness of the semiconductor element 1, the material / thickness of the substrate 5, etc. 1 and is not described here.

以上のように本実施の形態６によれば、実施の形態１と同様に、基板５に溝１４からなる開口１５を備えていることから、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子１と基板５との熱膨張係数の差による基板５の反りの作用が半導体素子１へ及ぶことが抑制され、かつ基板５および半導体素子１の上方が開放されていることにより、基板５と半導体素子１の熱膨張係数の差に起因する半導体素子１の反りを抑制することができ、よって、半導体素子１の内部応力が低減され、半導体素子１の配線破壊やトランジスタの特性変動を抑制することができ、またアンダーフィル樹脂３をパッケージ裏面から注入することができ、アンダーフィル樹脂３のボイドを低減することができ、その結果、半導体素子１の接続部の信頼性を向上できる。
［実施の形態７］
図７は、本発明の実施の形態７における半導体装置の構造を示す断面図および半導体装置を構成する基板の平面図である。 As described above, according to the sixth embodiment, as in the first embodiment, the substrate 5 is provided with the opening 15 formed of the groove 14, so that the semiconductor device is heated during solder mounting or the like. The action of warping of the substrate 5 due to the difference in thermal expansion coefficient between the semiconductor element 1 and the substrate 5 is suppressed from reaching the semiconductor element 1 and the upper side of the substrate 5 and the semiconductor element 1 is opened, whereby the substrate 5 and the semiconductor element 1 can be prevented from warping due to the difference in thermal expansion coefficient. Therefore, the internal stress of the semiconductor element 1 is reduced, and the wiring breakdown of the semiconductor element 1 and the transistor characteristic fluctuation are reduced. The underfill resin 3 can be injected from the back surface of the package, and voids in the underfill resin 3 can be reduced. As a result, the reliability of the connection portion of the semiconductor element 1 can be improved. It can be above.
[Embodiment 7]
FIG. 7 is a cross-sectional view showing the structure of the semiconductor device according to the seventh embodiment of the present invention and a plan view of the substrate constituting the semiconductor device.

図７に示すように、４枚の基板５を「田」の字の形状に、平面的に間隔を開けて配置し、各基板５同士間に十字状の溝１６を形成している。この各基板５の間隔である溝１６は均一の幅でもよいし、不均一の幅でもよい。   As shown in FIG. 7, four substrates 5 are arranged in the shape of a “rice” with a space therebetween in a plane, and a cross-shaped groove 16 is formed between the substrates 5. The groove 16 that is the interval between the substrates 5 may have a uniform width or a non-uniform width.

このように形成された溝１６を中心として４枚の基板５の中央部分に、半導体素子１がフェイスダウンに搭載されて、半導体素子１と４枚の基板５は接合され、接続端子２と接続電極４が電気的に接続されている。また十字状に形成された溝１６が、半導体装置の開口１７を形成している。   The semiconductor element 1 is mounted face-down on the central portion of the four substrates 5 centering on the groove 16 formed in this way, and the semiconductor element 1 and the four substrates 5 are joined and connected to the connection terminal 2. The electrode 4 is electrically connected. Moreover, the groove | channel 16 formed in the cross shape forms the opening 17 of a semiconductor device.

また半導体素子１と基板５の間に接続端子２と接続電極４と半導体素子１の回路部表面を覆い、且つ開口１７に充填しないようアンダーフィル樹脂３を介在させ、アンダーフィル樹脂３を熱硬化させて接続部を保護している。   Further, the underfill resin 3 is interposed between the semiconductor element 1 and the substrate 5 so as to cover the connection terminal 2, the connection electrode 4, and the circuit portion surface of the semiconductor element 1 and not to fill the opening 17. To protect the connection.

なお、この半導体装置の製造方法、接続端子２の材質・ピッチ、アンダーフィル樹脂３の塗布方法、外部端子７の形状、半導体素子１の厚さ、基板５の材質・厚さ等は、実施の形態１と同様であり、説明を省略する。   The manufacturing method of the semiconductor device, the material / pitch of the connection terminals 2, the coating method of the underfill resin 3, the shape of the external terminal 7, the thickness of the semiconductor element 1, the material / thickness of the substrate 5, etc. It is the same as that of form 1, and description is abbreviate | omitted.

以上のように本実施の形態７によれば、実施の形態１と同様に、基板５に溝１６からなる開口１７を備えていることから、半導体装置がはんだ実装の際等で加熱されるとき、半導体素子１と基板５との熱膨張係数の差による基板５の反りの作用が半導体素子１へ及ぶことが抑制され、かつ基板５および半導体素子１の上方が開放されていることにより、基板５と半導体素子１の熱膨張係数の差に起因する半導体素子１の反りを抑制することができ、よって、半導体素子１の内部応力が低減され、半導体素子１の配線破壊やトランジスタの特性変動を抑制することができ、またアンダーフィル樹脂３をパッケージ裏面から注入することができ、アンダーフィル樹脂３のボイドを低減することができ、その結果、半導体素子１の接続部の信頼性を向上できる。また組立プロセスの自由度を増大させることができる。   As described above, according to the seventh embodiment, as in the first embodiment, the substrate 5 is provided with the opening 17 formed of the groove 16, so that the semiconductor device is heated during solder mounting or the like. The action of warping of the substrate 5 due to the difference in thermal expansion coefficient between the semiconductor element 1 and the substrate 5 is suppressed from reaching the semiconductor element 1 and the upper side of the substrate 5 and the semiconductor element 1 is opened, whereby the substrate 5 and the semiconductor element 1 can be prevented from warping due to the difference in thermal expansion coefficient. Therefore, the internal stress of the semiconductor element 1 is reduced, and the wiring breakdown of the semiconductor element 1 and the transistor characteristic fluctuation are reduced. The underfill resin 3 can be injected from the back surface of the package, and voids in the underfill resin 3 can be reduced. As a result, the reliability of the connection portion of the semiconductor element 1 can be improved. It can be above. Moreover, the freedom degree of an assembly process can be increased.

本発明にかかる半導体装置は、半導体素子の接続部の信頼性が高く、情報通信機器、事務用電子機器、家庭用電子機器、測定装置、組み立てロボット等の産業用電子機器、医療用電子機器、電子玩具等の分野で有用である。   The semiconductor device according to the present invention has a high reliability of the connection portion of the semiconductor element, industrial communication equipment such as information communication equipment, office electronic equipment, home electronic equipment, measuring device, assembly robot, medical electronic equipment, Useful in the field of electronic toys.

本発明の実施の形態１における半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device in Embodiment 1 of this invention, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device. 本発明の実施の形態２における半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。It is a figure which shows the semiconductor device in Embodiment 2 of this invention, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device. 本発明の実施の形態３における半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。It is a figure which shows the semiconductor device in Embodiment 3 of this invention, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device. 本発明の実施の形態４における半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。It is a figure which shows the semiconductor device in Embodiment 4 of this invention, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device. 本発明の実施の形態５における半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。It is a figure which shows the semiconductor device in Embodiment 5 of this invention, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device. 本発明の実施の形態６における半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。It is a figure which shows the semiconductor device in Embodiment 6 of this invention, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device. 本発明の実施の形態７における半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。It is a figure which shows the semiconductor device in Embodiment 7 of this invention, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device. 従来の半導体装置の課題と本発明の半導体装置の効果を示す図であり、（ａ）は従来の半導体装置の断面図、（ｂ）は本発明の実施の形態１における半導体装置の断面図である。It is a figure which shows the subject of the conventional semiconductor device, and the effect of the semiconductor device of this invention, (a) is sectional drawing of the conventional semiconductor device, (b) is sectional drawing of the semiconductor device in Embodiment 1 of this invention. is there. 従来の半導体装置を示す図であり、（ａ）は断面図、（ｂ）は半導体装置を構成する基板の平面図である。It is a figure which shows the conventional semiconductor device, (a) is sectional drawing, (b) is a top view of the board | substrate which comprises a semiconductor device.

符号の説明Explanation of symbols

１ 半導体素子
２ 接続端子
３ アンダーフィル樹脂
４ 接続電極
５ 基板
６ ビア
７ 外部端子
８，１２，１３，１５，１７ 開口
９，１４，１６ 溝
１０ 矩形開口
１１ 円形開口 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Connection terminal 3 Underfill resin 4 Connection electrode 5 Substrate 6 Via 7 External terminal 8, 12, 13, 15, 17 Open 9, 14, 16 Groove 10 Rectangular opening 11 Circular opening

Claims (8)

一方の面に接続電極を含む配線回路を有し、他方の面に前記接続電極と接続された外部端子を有する基板と、
前記基板の一方の面上にフェイスダウンに搭載され、その接続端子が前記基板の接続電極と電気的に接続される半導体素子と、
前記基板に前記他方の面から前記一方の面までに到るまで設けられ、前記基板と前記半導体素子の熱膨張率の差による基板の反りの作用が半導体素子に及ぶことを抑制する開口と、
前記接続電極と前記接続端子と前記半導体素子の回路部表面を覆い、且つ前記溝に充填しないアンダーフィル樹脂
を備え、
前記基板および半導体素子の上方が開放されていること
を特徴とする半導体装置。 A substrate having a wiring circuit including a connection electrode on one surface and an external terminal connected to the connection electrode on the other surface;
A semiconductor element mounted face-down on one surface of the substrate, the connection terminal of which is electrically connected to the connection electrode of the substrate;
An opening that is provided in the substrate from the other surface to the one surface, and that suppresses the action of warping of the substrate due to a difference in thermal expansion coefficient between the substrate and the semiconductor element from reaching the semiconductor element;
An underfill resin that covers the connection electrode, the connection terminal, and the circuit portion surface of the semiconductor element and does not fill the groove,
A semiconductor device, wherein an upper portion of the substrate and the semiconductor element is open. 前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、全面に形成されること
を特徴とする請求項１に記載の半導体装置。 2. The opening according to claim 1, wherein the opening is formed on the entire surface on the inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. Semiconductor device. 前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の矩形開口が格子状に配置されて形成されること
を特徴とする請求項１に記載の半導体装置。 The openings are formed by arranging a plurality of rectangular openings arranged in a grid pattern on the inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. The semiconductor device according to claim 1. 前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の円形開口が格子状に配置されて形成されること
を特徴とする請求項１に記載の半導体装置。 The openings are formed by arranging a plurality of circular openings in a grid pattern on the inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. The semiconductor device according to claim 1. 前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の溝が列状に配置されて形成されること
を特徴とする請求項１に記載の半導体装置。 The opening is formed by arranging a plurality of grooves in a row inside the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. The semiconductor device according to claim 1. 前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、複数の溝が前記半導体素子の中心から放射状に配置されて形成されること
を特徴とする請求項１に記載の半導体装置。 The opening is formed with a plurality of grooves arranged radially from the center of the semiconductor element at an inner side of the innermost row of the connection electrodes of the substrate below the semiconductor element by a distance equal to or more than half the pitch of the connection electrodes. The semiconductor device according to claim 1, wherein: 前記開口は、前記半導体素子の下部の前記基板の前記接続電極の最内列より前記接続電極のピッチの半分の距離以上内側に、全面に配置され且つ前記半導体素子の幅を超える領域が存在する溝により形成されること
を特徴とする請求項１に記載の半導体装置。 The opening is located on the entire surface of the innermost row of the connection electrodes of the substrate under the semiconductor element and more than half the distance of the pitch of the connection electrodes, and there is a region exceeding the width of the semiconductor element. The semiconductor device according to claim 1, wherein the semiconductor device is formed by a groove. 一方の面に接続電極を含む配線回路を有し、他方の面に前記接続電極と接続された外部端子を有する４枚の基板と、
各基板同士を平面的に間隔を開けて配置することにより生じる溝と、
前記溝を中心として前記４枚の基板の一方の面上にフェイスダウンに搭載され、前記各基板の接続電極とその接続端子が電気的に接続される半導体素子と、
前記接続電極と前記接続端子と前記半導体素子の回路部表面を覆い且つ前記溝に充填しないアンダーフィル樹脂
を備え、
前記基板および半導体素子の上方が開放されていること
を特徴とする半導体装置。 Four substrates having a wiring circuit including a connection electrode on one surface and having an external terminal connected to the connection electrode on the other surface;
A groove formed by arranging each substrate with a space in a plane, and
A semiconductor element mounted face down on one surface of the four substrates around the groove, and the connection electrodes of the substrates and the connection terminals thereof are electrically connected;
An underfill resin that covers the connection electrode, the connection terminal, and the circuit portion surface of the semiconductor element and does not fill the groove,
A semiconductor device, wherein an upper portion of the substrate and the semiconductor element is open.
JP2006162943A 2006-06-13 2006-06-13 Semiconductor device Pending JP2007335479A (en)

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