JP2007323227A - Power monitoring control circuit and image forming apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reset circuit connecting at least two ICs operable on different supply voltages and a reset generation means which prevents an infinite loop of resets even when either power supply fails. <P>SOLUTION: In the power monitoring control circuit, when receiving from a supply voltage monitoring circuit 105 a signal representing an anomaly in the supply voltage of 3.3 V for operating the second control means 102, the first control means 101 outputs to the reset signal generation means 103 a watchdog timer control signal to disable a watchdog timer function and stop outputting reset signals. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply monitoring control circuit in which at least two ICs each operating with different power supply voltages are connected to a reset generation unit, and an image forming apparatus using the same.

Conventionally, as shown in FIG. 6, in power supply monitoring, as a circuit that can detect instability of a supplied power supply voltage and that can be realized with a simple configuration, a WDT circuit 221 and power supply monitoring circuits 222 and 223 for each power supply. Is output to the power supply monitoring circuit 222 when the WDT circuit 221 receives the WDT signal and detects a system runaway, and is provided for each power supply. The power supply monitoring circuits 222 and 223 are provided with input terminals for receiving the above signals, and when the power supply voltage is lowered or the above signals are input, a reset signal for resetting the system is output. The power monitoring circuit 223 is input to the subsequent stage, and the reset signal of the power monitoring circuit 223 is output to the outside. There is invention constructed by the series connection.
JP 2000-339069 A

  However, in the conventional technique, for example, when the 5V power supply becomes abnormal due to disconnection or disconnection of the connector, the 5V power supply monitoring circuit 223 of the power supply monitoring device 220 operates to output a reset signal. The reset signal resets the CPU 212 and the communication device 213, but since the 3.3V power source that is the power source of the CPU 212 and the communication device 213 is normal, the reset is immediately released. However, since the 5V power supply monitoring circuit 223 of the power supply monitoring device 220 continues to output the reset signal, the CPU 212 and the communication device 213 fall into an infinite loop of reset and reset release.

  SUMMARY OF THE INVENTION The present invention solves the above-described problem, and in a power supply monitoring control circuit in which at least two ICs each operating at different power supply voltages and reset generation means are connected and an image forming apparatus using the same, one power supply is abnormal. An object of the present invention is to provide a power supply monitoring and control circuit that does not fall into an infinite loop of reset and reset release, and an image forming apparatus using the same.

  The present invention solves the above-described problem, and includes a clock signal generation unit that generates a clock signal at a constant frequency, a first control unit that inputs the clock signal from the clock signal generation unit, and the first The second control means that operates with a power source different from the control means and inputs the clock signal from the first control means, and the clock from the second control means that is connected to the second control means and is normally input. When the signal is not input for a predetermined time, if there is an abnormality in the reset signal generating means with a watchdog timer function that outputs a reset signal to the first control means and the power source that operates the second control means, the first A power supply monitoring control circuit comprising: a power supply voltage monitoring circuit that outputs a signal indicating an abnormality of a power supply that operates the second control means to the control means; The control means invalidates the watchdog timer function for the reset signal generating means when a signal indicating an abnormality of the power supply voltage of the power supply operating the second control means is input from the power supply voltage monitoring circuit, A watchdog timer control signal for controlling so as not to output a reset signal is output.

  Furthermore, the power monitoring control circuit is applied to an image forming apparatus.

  According to the present invention, even when an abnormality occurs in one of the power supplies, it does not fall into an infinite loop of reset and reset release, and the first control means can give an appropriate response.

  Further, by applying the power monitoring control circuit to the image forming apparatus, the first control unit can give an appropriate response, so that the user can grasp the error state by the display unit and take an appropriate response. Can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a power supply monitoring control circuit of the present invention. The power monitoring and control circuit includes a CPU 101 as an example of first control means that operates with a 5V power supply, an ASIC 102 as an example of second control means that operates with a 3.3V power supply, and a watchdog timer function that operates with a 5V power supply. A watchdog circuit 103 as an example of a reset generation unit with a mark is connected in series to form a loop.

  A CPU 101 and an application specific integrated circuit (ASIC) 102 are ICs that perform load control, and communicate data, addresses, and the like with each other. The watchdog circuit 103 monitors the clock signal for the watchdog timer generated from the crystal oscillator 104 and is input via the CPU 101 and the ASIC 102 when it is valid. If the clock signal is not input for a predetermined time, that is, the CPU 101 and the ASIC 102 are abnormal. A watchdog timer function is provided for outputting a reset signal to the CPU 101 when it occurs. The watchdog timer function is controlled by a watchdog timer control signal output from the CPU 101 to be valid or invalid.

  The power supply voltage monitoring circuit 105 monitors the 3.3V and 24V power supplies, and when both are below the respective predetermined voltages, a 3.3V power supply OFF detection signal and a 24V power supply OFF detection signal indicating a voltage abnormality are provided. The data is output to the CPU 101.

  The 24V power supply control FET 106 divides the power supply system into a plurality of power supply systems. The purpose is to distribute the inrush current generated by the 24V power supply ON switch and to save energy / safety. The FET control signal is sent to the ASIC 102. Output. Reference numeral 107 denotes a non-volatile FRAM (registered trademark) (Ferroelectric Random Access Memory) that temporarily stores calculation results in the CPU 101 and other load data, and outputs FRAM communication signals to the ASIC 102. .

  The operation of such a reset circuit will be described with reference to the flowchart of FIG. The start is a state in which there is some abnormality in the circuit, the CPU 101 is reset, the 5V power supply is turned on, and the reset of the CPU 101 is released.

  First, in step 1 (ST1), it is determined whether or not the voltage of the 24V power supply has dropped. If the 24V power supply has not dropped and is normal, the process proceeds to step 2 (ST2). If the 24V power supply drops and is abnormal, access to the FRAM 107 is prohibited in step 11 (ST11), and the 24V system power supply control FET 106 is turned off in step 12 (ST12). Execute a service call.

  Next, when the 24V power supply is normal, it is determined in step 2 (ST2) whether or not the voltage of the 3.3V power supply has dropped. If the 3.3V power supply is not lowered and is normal, the process proceeds to step 3 (ST3). If the 3.3V power supply drops and is abnormal, in step 21 (ST21), the CPU 101 that inputs the 3.3V power supply abnormality from the power supply monitoring circuit 105 disables the watchdog timer function of the watchdog circuit 103. In step 22 (ST22), access to the FRAM 107 is prohibited, and in step 23 (ST23), the ASIC 102 is reset and the circuit is stopped.

  Next, when the 3.3V power supply is normal, in step 4 (ST4), the watchdog timer function of the watchdog circuit 103 is enabled by the watchdog timer control signal output from the CPU 101 and performs normal operation. .

  As described above, when the 3.3V power supply is lowered and abnormal, the CPU 101 that has input the 3.3V power supply abnormality from the power supply monitoring circuit 105 invalidates the watchdog timer function of the watchdog circuit 103, and then the ASIC 102 Is reset and the circuit is stopped, so that the CPU 101 does not fall into an infinite loop of reset and reset release.

  Next, an embodiment in which this power supply monitoring control circuit is applied to an image forming apparatus will be described. FIG. 3 is a longitudinal side view showing an embodiment of an image forming apparatus to which the power supply monitoring control circuit of this embodiment is applied. FIG. 4 is a block diagram showing an electrical configuration of the image forming apparatus of FIG. This image forming apparatus forms a full color image by superposing four color toners of yellow (Y), cyan (C), magenta (M), and black (K), or uses only black (K) toner. A monochrome image is formed.

  In the image forming apparatus 1 applied to this embodiment, an image signal is given to the main controller 12 from an external device such as a host computer in response to an image formation request from a user. At this time, a command signal is transmitted from the main controller 12 to the engine controller 10. In response to this command signal, the engine controller 10 controls each part of the engine unit EG to form an image corresponding to the image signal on the sheet S (recording medium).

  In the engine unit EG, a photosensitive member 2 functioning as an “image carrier” is provided to be rotatable in an arrow direction D1 in FIG. Further, a charging unit 3, a rotary developing unit 4 and a cleaning unit 5 are arranged around the photoreceptor 2 along the rotation direction D1. The charging unit 3 is applied with a charging bias from the charging controller 108 and uniformly charges the outer peripheral surface of the photoreceptor 2 to a predetermined surface potential.

  Then, the light beam L is irradiated from the exposure unit 6, that is, the optical device, toward the outer peripheral surface of the photosensitive member 2 charged by the charging unit 3. The exposure unit 6 exposes the light beam L onto the photosensitive member 2 in accordance with a control command given from the exposure control unit 109 to form an electrostatic latent image corresponding to the image signal. The exposure unit 6 is provided with appropriate optical elements such as a lens and a mirror.

  The exposure unit 6 includes a scanner motor using a DC motor, and drives an optical element such as a rotating polygon mirror. Each unit such as the charging unit 3, the rotary developing unit 4, and the exposure unit 6 used for image formation is configured to be replaceable. The life management information of each unit is stored in FRAM (registered trademark) 107 described later.

  When an image signal is given from an external device such as a host computer to the CPU 121 of the main controller 12 via the interface 122, the CPU 101 of the engine controller 10 sends a control signal corresponding to the image signal to the exposure control unit 109 at a predetermined timing. Output. In response to this control signal, the exposure unit 6 irradiates the photosensitive member 2 with the light beam L, and an electrostatic latent image corresponding to the image signal is formed on the photosensitive member 2.

  The electrostatic latent image formed in this way is developed with toner by the rotary developing unit 4. That is, in this embodiment, the rotary developing unit 4 is provided with members such as a support frame 40 that is rotatably provided about the axis, and a rotary drive unit that is not shown. Further, a yellow developing device 4Y, a cyan developing device 4C, a magenta developing device 4M, and a black developing device which are configured to be detachable from the support frame 40 and incorporate respective color toners. It has 4K. Each of the developing devices 4Y, 4C, 4M, and 4K is mounted as a toner cartridge so as to be replaceable.

  The rotary developing unit 4 is controlled by a developing device controller 110 as shown in FIG. Based on the control command from the developing device controller 110, the rotary developing unit 4 is driven to rotate. Further, these developing devices 4Y, 4C, 4M, and 4K are selectively positioned at a predetermined developing position facing the photoconductor 2 to apply toner of the selected color to the surface of the photoconductor 2. As a result, the electrostatic latent image on the photoreceptor 2 is visualized with the selected toner color.

  In this image forming apparatus, the developing roller 44 provided in the developing device (yellow developing device 4Y in the example of FIG. 3) positioned at the developing position is in contact with the photosensitive member 2 or a predetermined gap. Are arranged opposite to each other. The developing roller 44 functions as a toner carrier that carries the frictionally charged toner on its surface. Then, as the developing roller 44 rotates, the toner is sequentially conveyed to a position facing the photoreceptor 2 on which an electrostatic latent image is formed.

  Here, a developing bias in which a DC voltage and an AC voltage are superimposed is applied from the developing device controller 110 to the developing roller 44. Due to such a developing bias, the toner carried on the developing roller 44 partially adheres to each part of the surface of the photoconductor 2 according to the surface potential, and thus the electrostatic latent image on the photoconductor 2 becomes the toner. It is visualized as a color toner image. The toner image developed by the developing unit 4 as described above is primarily transferred onto the intermediate transfer belt (intermediate transfer member) 71 of the transfer unit 7 in the primary transfer region TR1. The transfer unit 7 includes an intermediate transfer belt 71 stretched over a plurality of rollers 72 to 75, and a drive unit (not shown) that rotates the intermediate transfer belt 71 in a predetermined rotation direction D2 by rotationally driving the roller 73. It has. Further, a secondary transfer roller 78 is provided at a position facing the roller 73 with the intermediate transfer belt 71 interposed therebetween, and is configured to be able to contact and separate from the surface of the belt 71 by an electromagnetic clutch (not shown). It has been.

  When the color image is transferred to the sheet S (recording medium), the color toner images formed on the photoreceptor 2 are superimposed on the intermediate transfer belt 71 to form a color image. Then, the color image is secondarily transferred onto the sheet S taken out from the paper supply unit 8 and conveyed to the secondary transfer region TR2 between the intermediate transfer belt 71 and the secondary transfer roller 78. Further, the sheet S on which the color image is formed in this way is conveyed via the fixing unit 9 to a discharge tray portion provided on the upper surface portion of the apparatus main body. The rotary developing unit 4 is used as means for forming each color image on the same amount of recording medium.

  Note that the surface potential of the photoreceptor 2 after the toner image is primarily transferred to the intermediate transfer belt 71 is reset by a charge eliminating unit (not shown). Further, after the toner remaining on the surface of the photoreceptor 2 is removed by the cleaning unit 5, the charging unit 3 receives the next charge. The toner removed by the cleaning unit 5 is collected in a toner tank (not shown).

  Further, a cleaner 76, a density sensor 60, and a vertical synchronization sensor 77 are disposed in the vicinity of the roller 75. Among these, the cleaner 76 can be moved toward and away from the roller 75 by a motor (not shown). Then, the blade of the cleaner 76 abuts on the surface of the intermediate transfer belt 71 that is stretched over the roller 75 while moving to the roller 75 side, and the toner that remains on the outer peripheral surface of the intermediate transfer belt 71 after the secondary transfer. Remove. The toner removed by the blade of the cleaner 76 is collected in the transfer waste toner tank.

  The vertical synchronization sensor 77 is a sensor for detecting the reference position of the intermediate transfer belt (intermediate transfer member) 71, and outputs a synchronization signal output in association with the rotational drive of the intermediate transfer belt 71, that is, a vertical synchronization signal Vsync. Functions as a vertical synchronization sensor to obtain. In this apparatus, the operation of each part of the apparatus is controlled based on the vertical synchronization signal Vsync in order to align the operation timing of each part and accurately superimpose the toner images formed in the respective colors. Further, the density sensor 60 is provided to face the surface of the intermediate transfer belt 71, and measures the optical density of the patch image formed on the outer peripheral surface of the intermediate transfer belt 71 in the density control process.

  As shown in FIG. 4, each developing device (toner cartridge) 4Y, 4C, 4M, 4K is a “storage element” that stores data relating to the manufacturing lot and usage history of the developing device, the remaining amount of built-in toner, and the like. Certain memories 41Y, 41C, 41M, and 41K are provided. Further, connectors 49Y, 49C, 49M, and 49K are provided in the developing devices 4Y, 4C, 4M, and 4K, respectively.

  If necessary, these connectors 49Y, 49C, 49M, and 49K are selectively connected to the connector 112 provided on the main body side. For this reason, data is transmitted and received between the CPU 101 of the engine controller 10 and each of the memories 41Y, 41C, 41M, and 41K via the interface 111, and various information such as consumable management regarding the developing device (toner cartridge). Management.

  In this embodiment, the main body side connector 112 and each developing device side connector 49K and the like are mechanically fitted to each other to exchange data. However, for example, electromagnetic means such as wireless communication is used. Data transmission / reception may be performed without contact. Further, the memory 41 that stores data unique to each of the developing devices 4Y, 4C, 4M, and 4K may be a non-volatile memory that can store the data even when the power is off or the developing device is removed from the main body. desirable.

  Although not shown in FIG. 3, the image forming apparatus is provided with a display unit 13 as shown in FIG. And a required message is notified to a user by displaying a predetermined message according to a control command given from CPU121 if needed. For example, when an abnormality such as a device failure or a paper jam occurs, a message is displayed informing the user to that effect.

  As the display unit 13, for example, a display device such as a liquid crystal display can be used, but in addition to this, a warning lamp that is lit or blinks as necessary may be used. Further, in addition to visually informing the user by displaying a message, a voice alarm such as a pre-recorded voice message or a buzzer may be used, or a combination thereof may be used as appropriate.

  The controller 12 is provided with an image memory 123 for storing an image given from an external device such as a host computer via the interface 122. Reference numeral 113 denotes a ROM for storing a calculation program executed by the CPU 101, control data for controlling the engine unit EG, and the like. The FRAM 107 stores life management information of toner cartridges and other replaceable units and various adjustment information such as density adjustment.

  FIG. 5 is an explanatory diagram showing the connection between the circuit board and the load of the present invention. This circuit board shows an example used for a control unit of an image forming apparatus. However, for the sake of simplicity, the conductive connection between the circuit board and the load is not shown. In addition, a large number of loads connected to the circuit board are arranged around the circuit board for easy understanding, but the loads are not actually connected to the circuit board in such a form. 5, in addition to the CPU 101 and FRAM 107 described with reference to FIG. 1, the circuit board 50 includes drive circuits 51 and 52 for driving system components such as a motor, an A / D converter, a D / A converter 114, and the like. Is provided.

  Around the circuit board 50, the main controller 12 described in FIG. 4, the cartridge memory (CS memory) 41 provided in the rotary developing unit 4, and the wiring terminals of the laser exposure device 6 are arranged. Also, each motor terminal such as a scanner motor, electromagnetic power means 80 such as a solenoid and a clutch, measuring means 81 such as a fixing thermistor and patch sensor, each sensor 82 such as a rotary position detection sensor, and each wiring terminal of a photoreceptor old / old discrimination fuse 84 Is arranged.

  Furthermore, each fan 85 such as a fixing fan, eraser 86, 24V power supply, 5V power supply interlock switch 87, high voltage power supply 88 connected to the developing device, 3.3V power supply, 5V power supply, 24V power supply low voltage power supply 89, wiring terminals of the fixing heater 90 are arranged. As described above, wiring terminals connected to a large number of components are arranged around the circuit board 50.

  The wiring terminals of the circuit board 50 and each component are connected by cables or lead wires. In FIG. 5, a thick line 53a is a signal transmission path through which a current of 100 mA or more flows, and a thin line 54a is a signal transmission path through which a current of several mA flows. Thus, since the signal transmission paths having different current capacities are wired, a wiring pattern having a current capacity corresponding to the current capacity of each signal transmission path is formed on the circuit board.

  When the power supply monitoring control circuit as shown in FIG. 1 is applied to such an image forming apparatus 1, if the 3.3V power supply drops and is abnormal, the power supply monitoring circuit 105 reports an abnormality in the 3.3V power supply. The input CPU 101 disables the watchdog timer function of the watchdog circuit 103 without going through the ASIC 102, and then resets the ASIC 102 and stops the circuit, so that the CPU 101 does not fall into an infinite loop between reset and reset release. Even when the function of the image forming apparatus 1 is stopped, it is possible to notify the abnormality of the power supply voltage by displaying on the display means.

  Note that the power supplies used for the CPU 101 and the watchdog circuit 103 and the ASIC 102 may be any voltage as long as they are different voltages.

Block diagram of one embodiment of the present invention Control flow diagram of one embodiment 1 is a diagram illustrating an image forming apparatus to which a circuit according to an embodiment is applied. Block diagram of the image forming apparatus shown in FIG. The figure which shows the connection of the circuit board and load of the image forming apparatus shown in FIG. Diagram showing conventional technology

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 2 ... Photoconductor (image carrier), 3 ... Charging unit, 4 ... Rotary developing unit, 40 ... Support frame, 4Y ... Yellow developing device, 4C ... Cyan developing device, 4M ... Developer for magenta, 4K ... developer for black, 44 ... developing roller, 5 ... cleaning unit, 6 ... exposure unit, 60 ... density sensor,
DESCRIPTION OF SYMBOLS 7 ... Transfer unit, 71 ... Intermediate transfer belt, 72-75 ... Roller, 76 ... Cleaner, 77 ... Vertical synchronization sensor, 78 ... Secondary transfer roller, 101 ... CPU (first control means), 102 ... ASIC (second) Control means), 103 ... watchdog circuit (reset generation means), 104 ... crystal oscillator, 105 ... power supply voltage monitoring circuit, 106 ... 24V system power supply control FET, 107 ... FRAM

Claims (2)

  The clock signal generating means for generating a clock signal at a constant frequency, the first control means for inputting the clock signal from the clock signal generating means, and the first control means are operated with a different power source, and the first control means A second control unit that inputs the clock signal from the control unit; and the first control unit that is connected to the second control unit and is normally input when the clock signal from the second control unit is not input for a predetermined time. When there is an abnormality in the power supply for operating the second control means and the reset signal generating means having a watchdog timer function for outputting a reset signal to the first control means, the power supply for operating the second control means A power supply voltage monitoring circuit that outputs a signal indicating an abnormality, wherein the first control means includes the second control circuit from the power supply voltage monitoring circuit. Watchdog timer control for controlling the reset signal generation means to disable the watchdog timer function and not to output a reset signal when a signal indicating an abnormality in the power supply voltage of the power supply operating the control means is input. A power supply monitoring control circuit characterized by outputting a signal.   2. The image forming apparatus using the power monitoring control circuit according to claim 1, wherein the power monitoring control circuit is applied to an image forming apparatus.

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