JP2007316348A - Method of manufacturing thin film transistor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing thin film transistor substrate capable of removing a short ring by cutting without short-circuiting a conductive substrate with a signal line. <P>SOLUTION: The method of manufacturing thin film transistor substrate is constituted as follow: an insulation layer having a thickness of 1 μm is formed on the whole surface of the conductive substrate 11, and a scanning signal line 13 which is integrally connected with the short ring 31 is formed; a belt-like etching region 33 is formed when a contact hole 34a of connecting a reactor 34 is formed; thereafter, the scanning signal line 13 on the etching region 33 is removed by etching and the short ring 31 is cut off from the scanning signal line 13 when patterning a writing signal line 17; and the conductive substrate 11 is cut on the etching region 33 and, then, a cross-section of the scanning signal line 13 is planarly separated from a cut surface of the conductive substrate 11, leaving an insulating layer 12 as it is. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a thin film transistor substrate using a conductive substrate, and more particularly, to a cross-sectional process of a signal line connected to a short ring in a manufacturing process.

  Liquid crystal display devices using a thin film transistor (TFT) substrate have been put into practical use. Some electrophoretic display devices, toner displays, organic EL elements and the like using similar thin film transistor substrates have been put into practical use. In a transmissive liquid crystal display device using a backlight, a transparent insulating substrate in which a transmissive thin film transistor array is formed on a glass substrate is employed. However, in a reflection-type image display device in which incident light from the observation side is folded at the reflection surface, an insulating layer is formed on an opaque conductive substrate such as a metal thin plate, and a thin film transistor, a reflective electrode, etc. are stacked on the insulating layer. Has been proposed.

  In the manufacturing process of a thin film transistor substrate used in a liquid crystal display device, the end of a signal line is connected using a wiring pattern called a short ring provided on the edge of the substrate in order to prevent element destruction due to charging or electrostatic spark. Then, after the thin film transistor element (TFT) and necessary protective resistance are connected to the signal line, the substrate is cut inside the short ring to remove the short ring, and the respective signal lines are separated and independent.

  Patent Document 1 discloses a short ring that goes around a thin film transistor array formed on a glass substrate and short-circuits a scanning signal line and a writing signal line. Here, a special protective resistor is arranged on the signal line connected to the short ring, and the glass substrate is cut outside the protective resistor. Thus, even if the cross section of the signal line exposed on the cut surface comes into contact with another member, the voltage of the signal line is not greatly affected.

JP-A-8-179366

  When an insulating layer is formed on a metal substrate and a signal line is patterned on the insulating layer, the signal line and the conductive substrate are only separated by a very thin insulating layer. Therefore, when the signal line and the metal substrate are integrally cut to remove the short ring, the signal line and the metal substrate may be short-circuited. This is because, when the metal material is cut with a grindstone blade, burrs are generated on the cut surface and get over the insulating layer. Further, when the metal material is cut with a laser processing machine, a metal bridge is formed in the insulating layer due to molten splash or vapor condensation.

  In the thin film transistor substrate disclosed in Patent Document 1, since the signal line exposed on the end face and the signal line on the thin film transistor side are separated by a protective resistor, a fatal short circuit that destroys the thin film transistor can be avoided. However, since the signal lines are in an independent state before the protective resistance is formed, if a voltage is applied to the signal lines, a threshold voltage shift or electrostatic breakdown may occur.

  In addition, since a series of patterning steps for forming a protective resistor is added between the short ring patterned on the substrate and the signal line, the manufacturing cost of the thin film transistor substrate is increased. When the number of processes including cleaning increases, disturbance factors increase and the variation in the quality of thin film transistors increases, which may lead to a reduction in display image quality and a decrease in final yield.

  An object of the present invention is to provide a method of manufacturing a thin film transistor substrate that can cut and remove a short ring without short-circuiting a conductive substrate and a signal line without adding a patterning step as much as possible.

  The method of manufacturing a thin film transistor substrate according to the present invention includes a signal line step of forming a plurality of signal lines connected to a short ring on the insulating layer of a conductive substrate having an insulating layer, and a thin film transistor connected to the signal line. The manufacturing method of the thing provided with the functional element process which forms an array. A cutting preparation step is provided in which the signal line is etched away while leaving the insulating layer on the conductive substrate in a band-like region along the short ring.

  In the method of manufacturing a thin film transistor substrate of the present invention, before cutting the conductive substrate, the signal line at the cut portion (more precisely, the connection portion between the signal line and the short ring) is removed by etching that does not cause burrs or splashes. It is. Then, the cross section of the signal line free from burrs and splashes is located inside the cut surface of the conductive substrate leaving the insulating layer, and the insulating layer left on the conductive substrate is connected to the conductive substrate and the signal line. Prevent short circuit with.

  Therefore, even if burrs or splashes (conductive particles) are generated when the conductive substrate is cut, it cannot reach the cross section of the signal line separated by the planar insulating layer. The stress when cutting the conductive substrate is also blocked by the planar insulating layer region and cannot reach the signal line side.

  Therefore, even if a rough cutting method is performed with priority given to cost, defects due to cutting of the conductive substrate do not occur, and the product yield is improved. And since the patterning process which concerns on formation of a protective resistance is unnecessary, manufacturing cost is not raised.

  Hereinafter, a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention will be described in detail with reference to the drawings. The manufacturing method of the thin film transistor substrate of the present invention is not limited to the limited configuration of the embodiment described below. As long as the signal line is formed on the insulating layer disposed on the conductive substrate, another embodiment in which a part or all of the steps of the embodiment are replaced with the alternative steps can be realized.

  Note that some of the general structure, material, manufacturing method, and the like of the thin film transistor substrate disclosed in Patent Document 1 are not illustrated, and detailed descriptions thereof are also omitted.

<First Embodiment>
FIG. 1 is an equivalent circuit diagram of the thin film transistor substrate according to the first embodiment, and FIG. 2 is an explanatory view of each process for manufacturing the thin film transistor substrate.

  As shown in FIG. 1, in the thin film transistor substrate 100, an insulating layer 12 is formed on a conductive substrate 11, and a short ring 31, a scanning signal line 13, a writing signal line 17, and the like are disposed on the insulating layer 12. The thin film transistor 37 and the drive electrode 29 are arranged corresponding to the intersection of the scanning signal line 13 and the writing signal line 17 that are three-dimensionally crossed. The resistor 34 connects the scanning signal line 13 and the write signal line 17 to protect the thin film transistor 37 from electrostatic charge. The thin film transistor 37 is composed of a general FET element, and has a gate connected to the scanning signal line 13, a source connected to the write signal line 17, and a drain connected to the drive electrode 29.

  The mounting portion 32 is a wide portion formed on the scanning signal line 13 and the writing signal line 17 in order to connect the driver IC. The thin film transistor substrate 100 is cut at an etching region 33 set outside the mounting portion 32 to remove the short ring 31.

As shown in FIG. 2A, the insulating layer 12 is formed on the conductive substrate 11. As the conductive substrate 11, various SUS materials, duralumin, Ti, or the like can be used. As the insulating layer 12 on the conductive substrate 11, an organic insulating layer such as polyimide or an inorganic insulating layer such as SiO ₂ or SiN is formed by sputtering, EB or the like, or applied by spin coating or the like.

  In the first embodiment, the conductive substrate 11 is a SUS430 substrate (100 mm × 100 mm × 0.5 mm) subjected to mirror polishing. The insulating layer 12 was formed by forming a 1.0 μm SiNx film using CVD.

  As shown in FIG. 2B, the scanning signal line 13 is formed. The material layer of the scanning signal line 13 is formed by sputtering, electron beam evaporation (EB), or the like. As a material of the scanning signal line 13, a conductor that can be patterned, is strong against a heating process such as when forming a semiconductor layer, and has low resistance is desirable. The conductor constituting the scanning signal line 13 may be a kind of conductor or a laminate of a plurality of conductors. Wet etching may be used to form the scanning signal line 13, or dry etching may be used. At the time of forming the scanning signal line 13, each feeding signal point other than each scanning signal line 13 and the scanning signal line 13 is electrically short-circuited by the outer conductive short ring 31 made of the scanning signal line 13 forming material.

  In the first embodiment, as a material layer for patterning the scanning signal lines 13, Cr is deposited to a thickness of 100 nm using sputtering. The scanning signal line 13 was formed by etching the Cr film by wet etching. At this time, each scanning signal line 13 is short-circuited by providing the short ring 31 on the outer periphery and connecting the scanning signal line 13.

As shown in FIG. 2C, an insulating layer 14, a semiconductor layer 15, and a doped layer 16 are formed on the patterned scanning signal line 13. As the insulating layer 14, an inorganic insulating layer such as SiO ₂ or SiN can be formed by a vapor deposition method (CVD) or the like. The semiconductor layer 15 can be formed of amorphous silicon, polysilicon, single crystal silicon, or the like by CVD or the like. The doped layer 16 may be formed using a gas mixed with phosphorus or the like during film formation, or may be formed by implanting phosphorus or the like after the semiconductor layer 15 is formed.

  In the first embodiment, the insulating layer 14, the semiconductor layer 15, and the doped layer 16 are continuously formed using vapor deposition (CVD). SiNx is used for the insulating layer 14 and a-Si is used for the semiconductor layer 15. The doped layer 16 is doped with P to form n + a-Si. The formation of n + a-Si is performed by mixing PH3 into the gas at the time of a-Si film formation. The film thickness of each layer (14, 15, 16) was 300 nm, 200 nm, and 50 nm, respectively.

  As shown in FIG. 2D, a contact hole 34 a that connects the material layer (unformed) of the write signal line 17 and the scanning signal line 13 through the insulating layer 14, the semiconductor layer 15, and the doped layer 16. Form. The contact hole 34 a is an opening for connecting and depositing the material layer (unformed) of the resistor 34 to the scanning signal line 13. When the contact hole 34a is formed, the insulating layer 14, the semiconductor layer 15, and the doped layer 16 in the etching region 33 are also removed, and a part of the scanning signal line 13 is exposed. For the formation of the contact hole 34a, wet etching or dry etching may be used.

  In the first embodiment, the contact hole 34a and the etching region 33 are formed by dry etching.

  As shown in FIG. 2E, the write signal line 17 is formed. The material layer of the write signal line 17 is formed by sputtering, EB, or the like. The material of the write signal line 17 is preferably a conductor that can be patterned and has a low specific resistance. The conductor constituting the write signal line 17 may be a kind of conductor or a stack of a plurality of conductors. Wet etching may be used to form the write signal line 17, or dry etching may be used. When the write signal line 17 is formed, separately from the signal line 17, the resistor 34 (FIG. 1) that connects the scan signal lines 13, the write signal lines 17, and the scan signal lines 13 and the write signal lines 17 is connected. Form a pattern. In this step, the scanning signal lines 13, the writing signal lines 17, and the scanning signal lines 13 and the writing signal lines 17 are electrically connected with a certain resistance value.

  In the first embodiment, as the material layer of the write signal line 17, Al is deposited to a thickness of 500 nm using sputtering. The Al film formation layer was etched using wet etching to form the write signal line 17. At this time, the terminal patterns of the resistors 34 connecting the scanning signal lines 13, the writing signal lines 17, and the scanning signal lines 13 and the writing signal lines 17 were also formed. After this step, the scanning signal lines 13, the writing signal lines 17, and the scanning signal lines 13 and the writing signal lines 17 are connected by the resistance value of the semiconductor layer 15. Therefore, even if the short ring 31 is removed, the threshold voltage shift and electrostatic breakdown of the thin film transistor 37 do not occur.

  As shown in FIG. 2F, additional etching is performed while covering the photoresist 18 for forming the write signal line 17. Thereby, a part of the scanning signal line 13 exposed in the etching region 33 is removed by etching without damaging the write signal line 17.

  Here, if the materials constituting the scanning signal line 13 and the writing signal line 17 are the same, or if the etching can be performed with the same kind of etching solution or etching gas, the writing signal line 17 is over-etched to thereby etch the etching solution. Alternatively, the conductive short ring 31 and the scanning signal line 13 can be disconnected without changing the etching gas.

  Further, if the material constituting the scanning signal line 13 and the writing signal line 17 cannot be etched with the same type of etching solution or etching gas, the etching solution or the etching gas is changed after the writing signal line 17 is formed. By performing the above, the conductive short ring 31 and the scanning signal line 13 can be disconnected without adding a photomask and a photolithography process.

  In the first embodiment, the exposed scanning signal line 13 is wet-etched using an etching solution of Cr without removing the photoresist 18 when the write signal line 17 is formed. In this step, the scanning signal line 13 and the short ring 31 inside the mounting portion 32 (FIG. 1) are separated. By doing so, it is possible to prevent a short circuit between the SUS substrate and the scanning signal line 13 (or the writing signal line 17) due to cutting the short ring 31 by laser heating or scribing in the etching region 33.

  As shown in FIG. 2G, patterning of the doped layer 16 and isolation of the semiconductor layer 15 are performed. The dope layer 16 may be patterned using wet etching or dry etching. For patterning the doped layer 16, the write signal line 17 can be used as a metal mask. The patterning of the semiconductor layer 15 may use wet etching or dry etching. By patterning the semiconductor layer 15, an array of a large number of thin film transistors (TFTs) 37 is formed in an inner region (not shown), and each wiring is connected by a resistor 34 having a desired resistance value.

  In the first embodiment, the channel of the thin film transistor 37 is formed by dry etching the doped layer 16 using the write signal line 17 as a metal mask. Further, the semiconductor layer 15 is isolated by dry etching. In this step, the thin film transistor 37 is formed, and at the same time, the resistor 34 is formed to a desired resistance value. The desired value is a value at which the thin film transistor 37 can be driven while the resistor 34 is connected and the threshold voltage shift or electrostatic breakdown of the thin film transistor 37 can be suppressed. In the first embodiment, the value of the resistor 34 is 1 MΩ.

As shown in FIG. 2H, the protective film 19 of the thin film transistor 37 is formed. As the protective film 19, it is desirable to form an inorganic insulating layer such as SiO ₂ or SiN by sputtering, EB or the like, or by spin coating or the like.

  In the first embodiment, SiNx is deposited to a thickness of 1 μm using CVD as a protective film for the thin film transistor 37.

  As shown in FIG. 2I, by cutting the conductive substrate 11 on the etching region 33 or on the conductive short ring 31 side of the etching region 33, the thin film transistor substrate 100 having the thin film transistor array is completed. As shown in FIG. 2E, the conductive substrate 11 is cut when and after the scanning signal line 13 is connected by the semiconductor layer 15, including when and after the thin film transistor 37 is formed. Also good. In the thin film transistor array on the conductive substrate 11 thus manufactured, the electrical contact between the scanning signal line 13 and the conductive substrate 11 does not occur, and a good yield can be obtained.

  In the first embodiment, the thin film transistor substrate 100 is completed by cutting the SUS430 substrate on the cut portion between the scanning signal line 13 and the short ring 31 defined in the etching region 33. In the thin film transistor array on the SUS430 substrate manufactured in this way, electrical contact between the wiring and the conductive substrate 11 does not occur, and a good yield can be obtained.

  As described above in detail, according to the manufacturing method of the first embodiment, when the thin film transistor array is formed on the conductive substrate 11, the conductive short ring 31 is removed by etching after the resistor 34 is formed. To do. This solves the short circuit problem between the conductive substrate 11 and each wiring when the short ring 31 is cut while suppressing the threshold voltage shift and electrostatic breakdown of the thin film transistor 37, and the thin film transistor array on the conductive substrate having a good yield. Can be obtained.

Second Embodiment
FIG. 3 is an explanatory diagram of each step of manufacturing the thin film transistor substrate according to the second embodiment. In the second embodiment, the short ring 31 and the scanning signal line 23 are separated using a process of patterning the drive electrode 29 provided for each pixel. Although the second embodiment will be described with reference to FIG. 1, constituent members unique to the thin film transistor substrate 200 are shown in parentheses in FIG. 1.

First, as shown in FIG. 3A, the insulating layer 22 is formed on the conductive substrate 21. As the conductive substrate 21, various SUS materials, duralumin, Ti, or the like can be used. As the insulating layer 22 on the conductive substrate 21, an organic insulating layer such as polyimide or an inorganic insulating layer such as SiO ₂ or SiN is formed by sputtering, EB or the like, or applied by spin coating or the like.

  Next, as shown in FIG. 3B, the scanning signal line 23 is formed. The material layer of the scanning signal line 23 is formed by sputtering, EB, or the like. As a material of the scanning signal line 23, a conductor that can be patterned, is strong against a heating process such as formation of a semiconductor layer, and has low resistance is desirable. The conductor constituting the scanning signal line 23 may be a kind of conductor or a laminate of a plurality of conductors. For the formation of the scanning signal line 23, wet etching or dry etching may be used. When the scanning signal line 23 is formed, each scanning signal line 23 and various feeding points other than the scanning signal line 23 are electrically short-circuited by a conductive short ring 31 on the outer periphery obtained by patterning the forming material layer of the scanning signal line 23. .

Next, as shown in FIG. 3C, an insulating layer 24, a semiconductor layer 25, and a doped layer 26 are formed. As the insulating layer 24, it is desirable to form an inorganic insulating layer such as SiO ₂ or SiN by CVD or the like. As the semiconductor layer 25, amorphous silicon, polysilicon, single crystal silicon, or the like can be formed by CVD or the like. The doped layer 26 may be formed using a gas in which phosphorus or the like is mixed during film formation, or may be formed by implanting phosphorus or the like after the semiconductor layer 25 is formed.

  Next, as shown in FIG. 3D, contact holes 34 a that connect the signal line layer 27 and the scanning signal line layer 23 are formed in the insulating layer 24, the semiconductor layer 25, and the doped layer 26. When the contact hole 34a is formed, the insulating layer 24, the semiconductor layer 25, and a part of the doped layer 26 on the scanning signal line 23 on the side of the short ring 31 that is more conductive than the mounting portion 32 shown in FIG. Thereby, an etching region 33 is formed, and a part of the scanning signal line 23 is exposed. For the formation of the contact hole 34a, wet etching or dry etching may be used.

  Next, as shown in FIG. 3E, the write signal line 27 is formed. The material of the write signal line 27 is preferably a conductor that can be patterned and has a low specific resistance. The conductor constituting the write signal line 27 may be a kind of conductor or a stack of a plurality of conductors. Wet etching may be used to form the write signal line 27, or dry etching may be used. When patterning the write signal line 27, a terminal pattern of the resistor 34 that connects the scan signal lines 23, the write signal lines 27, and the scan signal lines 23 to the write signal lines 27 is also formed. When the conductor of the write signal line 27 is connected to the semiconductor layer 25 through the contact hole 34a, there is a certain resistance value between the scan signal lines 23, between the write signal lines 27, and between the scan signal line 23 and the write signal line 27. Is electrically connected.

  Next, as shown in FIG. 3F, patterning of the doped layer 26 and isolation of the semiconductor layer 25 are performed. For the patterning of the doped layer 26, wet etching or dry etching may be used. For patterning the doped layer 26, the write signal line 27 can be used as a metal mask. For the patterning of the semiconductor layer 25, wet etching or dry etching may be used. By patterning the semiconductor layer 25, a thin film transistor 37 is formed, and a resistor 34 is formed, and the above-described wirings are connected with a desired resistance value.

Next, as shown in FIG. 3G, a protective film 28 of the thin film transistor element 37 is formed. As the protective film 28, it is desirable to apply an inorganic insulating layer such as SiO ₂ or SiN by sputtering, EB or the like, or by spin coating.

  In the second embodiment, the conductive short ring 31 and the scanning signal line 23 are disconnected when the drive electrode 29 shown in FIG. 3I is formed after the thin film transistor array is formed. The image display device driven using the drive electrode 29 includes an element that can be driven by a thin film transistor array, such as a liquid crystal display element and a particle movement display element.

  After the completion of the thin film transistor array, as shown in FIG. 2H, a contact hole 37a penetrating the protective layer 28 is formed to connect the drive electrode 29 of the element and the drain 37d of the thin film transistor 37. For the formation of the contact hole 37a, wet etching or dry etching may be used. When the contact hole 37a is formed, a part of the protective film 28 in the etching region 33 is also etched to expose a part of the scanning signal line 23.

  Next, as shown in FIG. 3I, a material layer of the drive electrode 29 is formed and patterned into a pixel shape. As a material for the drive electrode 29, a conductive material such as aluminum or silver that can be patterned and has high reflectivity can be used. For the formation of the drive electrode 29, wet etching or dry etching may be used.

  Following the patterning of the drive electrode 29, as shown in FIG. 3J, additional etching is performed with the photoresist 30 for forming the drive electrode 29 covered. In this step, the scanning signal line 23 exposed in the etching region 33 is removed by etching.

  Here, if the scanning signal line 23 and the drive electrode 29 are made of the same material, or can be etched with the same kind of etching solution or etching gas, the etching signal can be obtained by over-etching the scanning signal line 23. Alternatively, the conductive short ring 31 can be cut without changing the etching gas.

  Further, if the material constituting the scanning signal line 23 and the drive electrode 29 cannot be etched with the same kind of etching solution or etching gas, the etching solution or the etching gas is changed after the driving electrode 29 is formed. Therefore, it is possible to cut the conductive short ring 31 without adding a photomask and a photolithography process.

  The cutting of the conductive substrate 21 may be performed any time after wiring coupling by the resistor 34. The conductive substrate 21 is cut on the etching region 33 or on the side of the conductive short ring 31 with respect to the etching region 33. In the thin film transistor array on the conductive substrate 21 manufactured as described above, electrical contact between the wiring and the conductive substrate 21 does not occur, and a good yield can be obtained.

<Comparative Example Thin Film Transistor Substrate>
FIG. 4 is an explanatory view of a conventional method for removing a conductive short ring.

  As shown in FIG. 4A, when the insulating layer 42 is formed on the conductive substrate 41 made of a metal material and the scanning signal line 43 is formed on the insulating layer 42, the conductive substrate 41 and the insulating layer 42 are formed. When the overlap of the scanning signal lines 43 is cut simultaneously, there are the following problems.

  A thin film transistor array (not shown) in which wirings are short-circuited by a conductive short ring 46 is formed on the conductive substrate 41. When the short ring 46 is removed by the laser heating 44 shown in FIG. 4A, the scanning signal line 43 melted by overheating comes into contact with the conductive substrate 41 and short-circuits, resulting in a decrease in yield. Alternatively, when the short ring 46 is removed by the scribe 45 shown in FIG. 4B, the scanning signal line 43 at the cutting point drooped by the scribe 45 comes into contact with the conductive substrate 41 and is short-circuited, resulting in a decrease in yield. Will occur.

  In addition, when a high resistance semiconductor layer (15: see FIG. 2) or a method of joining each wiring on a conductive substrate using a switching element is used, the scanning signal line (13) is formed before the semiconductor layer (15) is formed. : See FIG. 2) or the write signal line (17: see FIG. 2) is in a floating state. This may cause a threshold voltage shift or electrostatic breakdown of the thin film transistor, which also leads to a decrease in yield and a decrease in performance.

  The manufacturing method of the first embodiment has been made in view of such a problem, and enables the thin film transistor array to be manufactured on the conductive substrate 11 with a high yield and at a low cost. The manufacturing method according to the first embodiment includes a step of forming a scanning signal line 13 or a writing signal line 17 in which a plurality of wirings are electrically short-circuited by a conductive short ring 31 on the conductive substrate 11. When the write signal line 17 or the scan signal line 13 is formed, the scan signal line 13 and the write signal line 17 are short-circuited using the resistor 34. There is a step of removing the conductive short-circuit member (scanning signal line 13 in the etching region 33) between the scanning signal line 13 and the writing signal line 17 by dry or wet etching.

  Thus, when the scanning signal line 13 or the writing signal line 17 is formed, the threshold voltage of the thin film transistor 37 is prevented from being shifted or electrostatically broken by the conductive short ring 31. After the separation of the scanning signal line 13, the scanning signal line 13 and the writing signal line 17 are short-circuited using the resistor 34, thereby preventing a threshold voltage shift or electrostatic breakdown of the thin film transistor 37.

  Furthermore, after each wiring is short-circuited by the resistor 34, the conductive short ring 31 is removed by etching. In the step of removing the conductive short ring 31, the removal is performed so that the cut line at the time of cutting out the conductive substrate 11 is within the removal region, so that the conductive substrate 11 and each wiring when the short ring 31 is cut off are removed. Short circuit is prevented.

  In the first and second embodiments, the removal process of the short ring 31 is arranged after the thin film transistor array is completed. However, the removal of the short ring 31 may be performed simultaneously or successively when forming a signal line to be formed later of the write signal line 17 or the scanning signal line 13. The removal of the short ring 31 may be performed simultaneously or continuously with each patterning step after the formation of the write signal line 17 or the scanning signal line 13. The removal of the short ring 31 may be performed simultaneously or continuously when the thin film transistor 31 or the drive electrode 29 is formed. In any case, the removal of the short ring 31 can be performed simultaneously or continuously with the etching of the other electrodes, wirings, and insulating layers, thereby preventing an increase in the number of photomasks and photolithography processes.

<Correspondence with Invention>
The manufacturing method according to the first embodiment includes a signal line process for forming a plurality of scanning signal lines 13 connected to the short ring 31 on the insulating layer 12 disposed on the conductive substrate 11, and a connection to the scanning signal lines 13. Functional element process for forming the thin film transistor array. A cutting preparation step is provided in which the scanning signal line 13 is removed by etching while leaving the insulating layer 12 on the conductive substrate 11 in the strip-shaped etching region 33 along the short ring 31.

  In the manufacturing method according to the first embodiment, before the conductive substrate 11 is cut, burrs and splashes are generated on the scanning signal line 13 at the cut portion (more precisely, the connecting portion between the scanning signal line 13 and the short ring 31). Has been removed by no etching. And since the cross section of the scanning signal line 13 without a burr | flash or a splash is located inside the cut surface of the conductive substrate 11 which left the insulating layer 12 at a distance, the insulating layer left on the conductive substrate 11 12 reliably prevents a short circuit between the conductive substrate 11 and the scanning signal line 13.

  Therefore, even if burrs or splashes (conductive particles) are generated when the conductive substrate 11 is cut, the cross section of the scanning signal line 13 separated by the planar insulating layer 12 cannot be reached. The stress when cutting the conductive substrate 11 is also blocked by the planar insulating layer 12 region and cannot reach the scanning signal line 13 side.

  Therefore, even if a rough cutting method is used with priority given to cost, defects due to cutting of the conductive substrate 11 do not occur, and the product yield is reliably improved.

  In the manufacturing method of the first embodiment, the insulating layer 12 from which the scanning signal lines 13 are removed is left on the thin film transistor array side, and the conductive substrate 11 is cut at the strip-shaped etching region 33 to remove the short ring 31. The process is arranged after the cutting preparation process.

  In the manufacturing method of the first embodiment, the cutting preparation process is arranged after the resistance process for forming the resistor 34 that connects the plurality of scanning signal lines 13 to each other.

  In the manufacturing method of the first embodiment, the cutting preparation step includes a protection step of covering the cross section of the scanning signal line 13 exposed by the etching removal with a protective layer of an insulating material. As a result, the cross section of the scanning signal line 13 is insulated and waterproof, and it is difficult for leakage, signal leakage, short circuit, corrosion, noise input, and the like to occur. Accordingly, options for cleaning and cutting are increased, and manufacturing costs can be reduced, product yields can be further improved, and manufacturing time can be shortened.

  In the manufacturing method of the first embodiment, the protection process also serves as the formation of the protection layer 19 that integrally covers the thin film transistor array.

  In the manufacturing method of the second embodiment, the step of etching away the scanning signal lines 13 in the cutting preparation step also serves as the step of forming the drive electrode 29 of the thin film transistor array.

  In the thin film transistor substrate 100, the scanning scanning signal line 13 is disposed on the insulating layer 12 disposed on the metal material substrate. The cross section of the semiconductor layer 15 overlaid on the scanning scanning signal line 13 is covered with a protective layer 19 made of an insulating material integrally with the cross section of the scanning scanning signal line 13, and the insulating layer 12 is outside the protective layer 19 covering the cross section. The cross section of the metal material substrate is left.

It is an equivalent circuit diagram of the thin film transistor substrate in the first embodiment. It is explanatory drawing of each process which manufactures a thin-film transistor substrate. It is explanatory drawing of each process of manufacturing the thin-film transistor substrate in 2nd Embodiment. It is explanatory drawing of the conventional method for removing a conductive short ring.

Explanation of symbols

11, 21 Conductive substrates 12, 22 Substrate insulating layers 13, 23 Signal lines (scanning signal lines)
14, 24 Insulating layer 15, 25 Semiconductor layer 16, 26 Doped layer 17, 27 Write signal line 18, 30 Photo resist 19, 28 Protective layer 29 Electrode pattern (drive electrode)
31 Short ring 32 Mounting portion 33 Band-shaped region (etching region)
34 Resistance member (resistor)
37 Thin film transistor

Claims (7)

A signal line step of forming a plurality of signal lines connected to the short ring on the insulating layer disposed on the conductive substrate;
In a method of manufacturing a thin film transistor substrate, comprising a functional element step of forming a thin film transistor array connected to the signal line,
A method of manufacturing a thin film transistor substrate, comprising: a cutting preparation step in which the signal line is etched away while leaving the insulating layer on the conductive substrate in a band-shaped region along the short ring.   A cutting step of cutting the conductive substrate in the band-like region to remove the short ring is disposed after the cutting preparation step, leaving the insulating layer from which the signal lines have been removed on the thin film transistor array side. The method for producing a thin film transistor substrate according to claim 1, wherein:   3. The method of manufacturing a thin film transistor substrate according to claim 2, wherein the cutting preparation step is arranged after a resistance step for forming a resistance member for connecting the plurality of signal lines to each other.   4. The method of manufacturing a thin film transistor substrate according to claim 2, wherein the cutting preparation step includes a protection step of covering a cross section of the signal line exposed by the etching removal with a protective layer of an insulating material.   5. The method of manufacturing a thin film transistor substrate according to claim 4, wherein the protection step also serves to form a protective layer that integrally covers the thin film transistor array.   6. The method of manufacturing a thin film transistor substrate according to claim 1, wherein the step of etching away the signal line in the cutting preparation step also serves as a step of forming an electrode pattern of the thin film transistor array. In the thin film transistor substrate in which the scanning signal line is arranged on the insulating layer arranged on the metal material substrate,
The cross section of the semiconductor layer overlaid on the scanning signal line is covered with a protective layer of an insulating material integrally with the cross section of the scanning signal line,
A thin-film transistor substrate, wherein a cross-section of the metal material substrate with the insulating layer remaining outside the protective layer covering the cross-section is located.

Images