JP2007310221A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a flickering phenomenon of a still picture on a display device where an odd-numbered-line video signal and an even-numbered-line video signal of an interlaced signal are superposed and displayed on the same display line alternately. <P>SOLUTION: The time for which an analog switch Asw(n) is on in an odd-numbered-field period is set to a time long enough to write the odd-numbered-line video signal to a holding capacitor Cs, in other words, a time long enough to make a Cs voltage reach a control target voltage. In the next even-numbered-field period, the analog switch Asw(n) is turned off before the even-numbered-line video signal is written to the holding capacitor Cw. In other words, the time for which the analog switch Asw(n) is on is set to a time which is not long enough to make the Cs voltage reach the control target voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device in which an interlace signal is used as a video source, and odd line video signals in odd fields and even line video signals in even fields are displayed alternately on the same display line. .

  In general, interlaced signals such as NTSC are used as a kind of video source for liquid crystal display devices and organic EL display devices in order to improve resolution. As shown in FIG. 5, the interlace signal is an odd line video signal corresponding to 240 odd lines and an even signal corresponding to 240 even lines in the 480 lines of the display screen. It consists of line video signals. In the example of FIG. 5, the interlace signal is a signal corresponding to a still image of the character “X”.

  The frequency of one frame is 30 Hz, and one frame is composed of an odd field and an even field that are alternately switched at a frequency of 60 Hz. An odd line video signal is output in the odd field period, and an even line video signal is output in the even field period. Is output.

  By the way, on the side of a display device that receives an interlace signal and performs display, the number of lines on the display screen is normally composed of 480 lines corresponding to the 480 line interlace signal. For example, in an electronic viewfinder of a digital camera, From the user's required specifications, the number of display lines on the display screen is set to, for example, 240 and half.

  Therefore, in such a display device, as shown in FIGS. 5 and 6, the odd line video signal and the even line video signal of the video source are displayed overwritten on the same line for each field period. . That is, each line is formed by arranging a plurality of pixels, and odd line video signals are written to 240 lines one after another in the odd field period, and even line video signals are 240 lines in the next even field period. One after another is written to the pixel. For example, the odd line video signal A and the even line video signal B are overwritten on the first line, and the odd line video signal C and the even line video signal D are overwritten on the 240th line. In this way, in the example of FIG. 5, the character “X” is displayed on the display device.

A display device using an interlace signal is described in Patent Documents 1 to 4.
JP-A-7-261713 JP-A-7-30836 JP-A-9-265278 JP 2005-107167 A

  In the above display device, the odd line video signal corresponding to the odd field of the video source and the even line video signal corresponding to the even field are alternately displayed on the same line.

  However, in a display device such as an organic EL display device in which the response speed of the display element is as high as several microseconds, when displaying a still image from a video source, between an odd line video signal and an even line video signal. If there is a large difference between the two, there is a problem that it is visually recognized as flickering and it is difficult to see the displayed image. For example, in the example of FIG. 5, the “X” pattern appears to flicker up and down at a frequency of 60 Hz on the display screen.

  The present invention has been made in view of the above-described problems, and includes a plurality of pixels, writes a first video signal output from a video source in a first field period to the plurality of pixels, and a second field period. In the display device in which the second video signal output from the video source is overwritten on a plurality of pixels, the first and second video signals from the video source are connected between the video source and the pixels. A video line to be supplied to the pixel; a switch connected between the video source and the video line; and a switch for determining timing to supply the first and second video signals from the video source to the pixel; And a control circuit that controls the switch to turn on for a first time during the first field period and to turn on for a second time shorter than the first time during the second field period. It is an feature.

  According to the display device of the present invention, in the first field period (for example, odd field period), the first video signal (for example, odd line video signal) is written and displayed as it is on the pixel. In the second field period (eg, even field period), a weighted average of the second video signal (eg, even line video signal) and the immediately preceding first video signal (eg, odd line video signal) was taken. A signal is written to the pixel, and display is performed based on this signal. As a result, the difference between the first video signal and the second video signal written to the pixel is reduced, so that the flicker phenomenon at the time of still image display is suppressed.

  According to the display device of the present invention, in the display device that writes the odd line video signal to the plurality of pixels in the odd field period and writes the even line video signal to the plurality of pixels in the even field period, the display apparatus flickers at the time of still image display. It becomes possible to suppress the phenomenon.

  As an example of a display device to which the present invention is applied, an organic EL display device will be described with reference to the drawings. FIG. 1 is a circuit diagram of an organic EL display device. Although a plurality of pixels are arranged in a matrix, FIG. 1 shows only six pixels corresponding to (m−1) to m rows and (n−1) to (n + 1) columns for convenience. A pixel group in each row corresponds to one display line.

  Although a specific configuration example of the pixel circuit is shown for the pixel (m, n), other pixels also have the same pixel circuit. The pixel circuit of the pixel (m, n) will be described. Q1 is a pixel selecting TFT, the drain is connected to the video line DLn, the gate is connected to the gate line GLm, and the source is the gate of the driving TFT (Q2). It is connected to the. The first terminal of the storage capacitor Cs is connected to the gate of the driving TFT (Q2). A storage capacitor voltage SC is applied to the second terminal of the storage capacitor Cs. The source of the driving TFT (Q2) is connected to the power supply line PVL that supplies the positive power supply potential PVdd, and the drain thereof is connected to the anode of the organic EL element OLED. A negative power supply potential CV is applied to the cathode of the organic EL element OLED.

  The source / drain current flowing through the driving TFT (Q2) changes in accordance with the video signal voltage (hereinafter referred to as Cs voltage) held at the first terminal of the holding capacitor Cs. The organic EL element OLED emits light with a luminance corresponding to the source / drain current, thereby displaying.

  Analog switches Asw (n-1), Asw (n), Asw (n + 1),... Are connected between the video lines DLn-1, DLn, DLn + 1,. . The analog switches Asw (n−1), Asw (n), Asw (n + 1) are controlled to be turned on / off by a control signal from the horizontal drive circuit HD. Also, pixel selection signals are supplied from the vertical drive circuit VD to the gate lines GLm-1, GLm,.

  Focusing on the pixel (m, n), the video signal is updated during the period in which the pixel selection TFT (Q1) is on. That is, during the period when the pixel selection TFT (Q1) is turned on according to the pixel selection signal from the gate line GLm, the analog switch Asw (n) is turned on, and the video signal from the video source is the video line DLn, pixel. It is held in the holding capacitor Cs through the selection TFT (Q1).

  The video source supplies an interlace signal, and the interlace signal is composed of an odd line video signal and an even line video signal. The odd line video signal and the even line video signal are displayed alternately on the same display line in the same manner as in the conventional example. The feature of the present invention is that the odd line video signal and the even line written in the pixel (m, n) are made different in the odd field period and the even field period by making the time during which the analog switch Asw (n) is turned on. This is to reduce the difference between video signals and to suppress the flicker phenomenon when displaying a still image.

  A specific circuit configuration will be described with reference to FIGS. Here, attention is focused on the pixel (m, n) corresponding to the m-th line, but the same applies to other pixels on the same display line. In the odd field period, when the pixel selection TFT (Q1) is turned on for one horizontal period and the analog switch Asw (n) is turned on during that period, an odd line video signal is written to the pixel (m, n).

  At this time, the analog switch Asw (n) is on for a time sufficient to write the odd line video signal to the storage capacitor Cs, in other words, a time sufficient for the Cs voltage to reach the control target voltage. Is set. The control target voltage is a voltage that the video source is a control target. In other words, the video signal from the video source passes through the analog switch Asw (n), the video line DLn, and the pixel selection TFT (Q1), and the storage capacitor Cs. This is the target voltage when transmitting to.

  In the example of FIG. 2, a sufficient discharge time is secured until the Cs voltage of the storage capacitor Cs decreases and stabilizes to the control target voltage. On the other hand, in the next even field period, the pixel selection TFT (Q1) is turned on for one horizontal period, and the analog switch Asw (n) is turned on during that time, but the operation is the same as in the odd field period. Before the even line video signal is written to Cs, the analog switch Asw (n) is turned off. In other words, the time during which the analog switch Asw (n) is on is set to a time that is insufficient for the Cs voltage to reach the control target voltage.

  As a result, the Cs voltage in the odd field period becomes equal to the control target voltage of the odd line video signal, but the Cs voltage in the even field period is equal to the control target voltage of the odd line video signal and the control target voltage of the even line video signal. A weighted average. For convenience, the “control target voltage of the odd line video signal” is simply referred to as “odd line video signal”, and the “control target voltage of the even line video signal” is simply referred to as “even line video signal”.

  FIG. 3 is a functional block diagram of the organic EL display device. In the first line, the odd line video signal A is written in the odd field period and the odd line video signal A and the even line video signal are written in the even field period. The video signal KB obtained by weighting and averaging B is overwritten.

  When the weighted average weights are α and β, KB = (αA + βB) / (α + β). Similarly, in the 240th line, the odd line video signal C is written in the odd field period, and the video signal KD obtained by weighted averaging the odd line video signal C and the even line video signal D is written in the even field period. It is. KD = (αC + βD) / (α + β). The optimum values for the weights α and β are determined for each display device.

  As a result, the difference between the odd line video signal and the even line video signal written to the pixels of the same display line is reduced, so that the flicker phenomenon at the time of still image display is suppressed. On the other hand, as shown in FIG. 4, when the analog switch Asw (n) is set to be on for a sufficient time for the Cs voltage to reach the control target voltage in both the odd field period and the even field period, The difference between the odd line video signal A and the even line video signal B written to the pixels of the same display line is as large as (A−B), and there is no problem in the case of moving image display, but flickers in the case of still image display. A phenomenon occurs.

  In the embodiment of the present invention, even if the handling of the odd field and the even fold is reversed, the flicker suppression effect can be obtained similarly. That is, in the even field period, the time during which the analog switch Asw (n) is on is set to a time sufficient for the Cs voltage to reach the control target voltage. In the next odd field period, the analog switch Asw ( The time during which n) is on is set to a time that is insufficient for the Cs voltage to reach the control target voltage.

  In the embodiment of the present invention, the time during which the analog switch Asw (n) is ON in each field period of the odd field period and the even field period is set for each line scanning period unit or for each pixel scanning period unit. It can also be configured to be switchable.

  Furthermore, when the analog switch Asw (n) is switched for each line scanning period unit or for each pixel scanning period unit, data judging means (for example, a frame memory or the like) is provided so that an odd line video signal and an even line number are provided. A weighted average process is not performed on a predetermined pixel area having a small difference between video signals, and a weighted average process is performed on a predetermined pixel area having a large difference between an odd line video signal and an even line video signal. .

  Further, as shown in FIG. 3, a still image / moving image discriminating circuit 10 for discriminating whether the interlace signal of the video source corresponds to either a moving image or a still image is provided, and a weighted average processing switching signal is provided as the discrimination output. It can also be configured such that it is sent to the organic EL display device and weighted average processing is not performed when moving images are displayed and weighted average processing is performed when still images are displayed. In this case, the horizontal drive circuit HD receives the weighted average processing switching signal, and displays the time during which the analog switch Asw (n) is turned on in both the odd field period and the even field period as shown in FIG. Control is performed so that the signal is turned on for a time sufficient for the signal to be written into the pixel, and the time during which the analog switch Asw (n) is turned on is controlled as described above during still image display.

1 is a circuit diagram of an organic EL display device according to an embodiment of the present invention. FIG. 3 is a first timing chart for explaining the operation of the organic EL display device according to the embodiment of the present invention. 1 is a functional block diagram of an organic EL display device according to an embodiment of the present invention. It is a 2nd timing diagram explaining operation | movement of the organic electroluminescence display which concerns on embodiment of this invention. It is a figure explaining operation | movement of the display apparatus using an interlace signal. It is a functional block diagram of a display device using an interlace signal.

Explanation of symbols

10 Still / Movie discriminating circuit
Asw (n-1), Asw (n), Asw (n + 1) Analog switch Cs Holding capacitor CV Negative power supply potential DLn-1, DLn, DLn + 1 Video line GLm-1, GLm Gate line HD Horizontal drive circuit
OLED Organic EL element PVL Power line Q1 Pixel selection TFT
Q2 Driving TFT
SC storage capacitor potential VD vertical drive circuit

Claims (6)

A plurality of pixels, a first video signal output from the video source in the first field period is written to the plurality of pixels, and a second video signal output from the video source in the second field period is a plurality of pixels. In a display device that writes over a pixel,
A video line connected between the video source and the pixel and supplying first and second video signals from the video source to the pixel;
A switch connected between the video source and the video line and determining a timing of supplying the first and second video signals from the video source to the pixels;
A control circuit for controlling the switch to be turned on for a first time during a first field period and to be turned on for a second time shorter than the first time during a second field period. Display device. The first time is sufficient time for the first video signal to be written to the pixel, and the second time is insufficient time for the second video signal to be written to the pixel. The display device according to claim 1. The control circuit, when the first and second video signals correspond to moving images,
3. The switch according to claim 1, wherein the switch controls the first and second video signals to be turned on for a time sufficient for the first and second video signals to be written to the pixels during the first and second field periods. The display device according to any one of the above. The first and second times when the switch is turned on can be switched for each line scanning period unit or for each pixel scanning period unit. The display device described. The pixel has a holding capacitor for holding the first and second video signals, a transistor for passing a current corresponding to the first and second video signals held in the holding capacitor, and a current flowing through the transistor. The display device according to claim 1, further comprising a light emitting element that emits light. The display device according to claim 5, wherein the light emitting element is an organic EL element.

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