JP2007306569A - Reference voltage generating circuit and system including same, and reference voltage generating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plurality of reference voltage generators generating reference voltages varying with respective termination voltages and a system including them, and a reference voltage generating method so as to supply a stable reference voltage. <P>SOLUTION: A reference voltage generating circuit includes a plurality of termination nodes providing termination voltages for terminating a plurality of data signals through terminating resistances respectively, and the plurality of reference voltage generators which are coupled to the plurality of termination nodes and generate the reference voltages varying with the respective termination voltages so as to decide logic levels of the terminated data signals. The reference voltages varying with the respective termination voltages of the data signals are provided to decrease the error rate when the logic levels of the plurality of data signals are decided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a reference voltage generating circuit, a system including the reference voltage generating method, and a reference voltage generating method, and more particularly, to a reference voltage generating circuit that generates a plurality of reference voltages that change according to respective termination voltages of a plurality of data signals, and the same. And a reference voltage generation method.

  Unlike devices that receive differential signal pairs, devices that receive single-ended data signals require a reference voltage to determine the logic level of the received data signal. The reference voltage preferably maintains an intermediate value between a low voltage corresponding to a logic low level of a received data signal and a high voltage corresponding to a logic high level.

  The device that receives the data signal compares the voltage of the data signal received by the input buffer constituted by the comparator with the reference voltage. When the received data signal voltage is greater than the reference voltage, the input buffer generates a logic high level internal signal and transmits the internal signal to the internal logic, and the received data signal voltage is less than the reference voltage. Generates a logic low level internal signal and transmits it to the internal logic.

Patent Document 1 discloses a semiconductor device that provides the same reference voltage to a plurality of input buffers in order to determine the logic levels of a plurality of data signals.
In the semiconductor device, the data input pins 10a and 10b to which data signals are input are terminated by respective termination voltages through termination resistors connected to the respective termination nodes. In a transmission / reception system, a termination resistor that terminates a data transmission line or a data bus is generally used for impedance matching. Each data signal terminated by each termination voltage is input to an input buffer and compared with a reference voltage.

  A reference voltage generator included in the semiconductor device generates a reference voltage by dividing a voltage between a voltage of an arbitrary common node NC on a power supply voltage line to which a power supply voltage is applied and a ground voltage. When a voltage drop occurs along the power supply voltage line due to the resistance component of the power supply voltage line, the termination node provides different termination voltage values due to the voltage drop. Accordingly, when the reference voltage is generated based on the voltage of one common node NC as described above, the farther the position of the termination node and the position of the common node NC on which the reference voltage is based on the power supply voltage line is, The difference between the reference voltage provided based on the voltage of the node NC and the ideal reference voltage is increased.

  On the other hand, when the voltage levels of a plurality of data signals change due to transmitter noise or the like, the conventional reference voltage generator cannot generate an accurate reference voltage corresponding to each data signal. An incorrect reference voltage increases the error rate related to the determination of the logic level of the data signal, thereby reducing the overall system performance.

  Further, as the data transmission / reception rate increases, the setup time and hold time for latching the data signal compared with the reference voltage are shortened, so that a more precise reference voltage is required.

  In order to solve the above-described problems, a first object of the present invention is to provide a reference voltage generation circuit that generates a plurality of reference voltages that change according to the termination voltages of a plurality of data signals. .

  It is a second object of the present invention to provide a system including a reference voltage generation circuit that generates a plurality of reference voltages that change according to respective termination voltages of a plurality of data signals.

  It is a third object of the present invention to provide a method for generating a plurality of reference voltages that change depending on respective termination voltages of a plurality of data signals.

  The present invention relates to a reference voltage generating circuit for generating a terminal voltage of each of a plurality of data signals, a driving ground voltage of a data driver included in a transmitter that transmits the data signals, and a reference voltage that varies depending on a driving power supply voltage. It is a fourth object of the present invention to provide a system including the above and a reference voltage generation method.

  To achieve the above object, a reference voltage generating circuit according to an embodiment of the present invention includes a plurality of termination nodes that provide termination voltages for terminating a plurality of data signals through termination resistors, and the plurality of termination nodes. And a plurality of reference voltage generators for generating a reference voltage that varies according to each of the termination voltages in order to determine a logic level of the terminated data signal.

  The reference voltage generation circuit may further include a first voltage node that provides a first voltage that varies according to a logic low level of the data signal, and the first voltage is a pull-down of a transmitter that outputs the data signal. It can be provided based on a drive ground voltage coupled to a voltage driver. Accordingly, the plurality of reference voltage generators are connected in parallel between the termination node and the first voltage node.

  Meanwhile, the reference voltage generation circuit includes a first voltage node that provides a first voltage that varies according to a logic low level of the data signal, and a second voltage that provides a second voltage that varies according to a logic high level of the data signal. And the first voltage is provided based on a driving ground voltage coupled to a pull-down data driver of a transmitter that outputs the data signal, and the second voltage is a pull-down voltage of the transmitter. It can be provided based on a driving power supply voltage coupled to the updater driver.

  A system according to an embodiment of the present invention includes a transmitter for transmitting a plurality of data signals using a common driving power supply voltage and a common driving ground voltage, receiving the data signal, and transmitting the received data signal to each of the data signals. In order to determine the logic level of each terminated data signal, the receiver generates a reference voltage that varies according to each termination voltage, and between the transmitter and the receiver. It includes a plurality of linked transmission lines.

  The transmitter may include a plurality of data drivers that generate the data signal according to the common driving ground voltage and the common driving power supply voltage, and a plurality of data output pins that output the data signal. The receiver includes a plurality of data input pins that receive the data signal and are terminated by respective termination voltages, a power supply voltage line in which a plurality of termination nodes that provide the respective termination voltages are arranged, and the data input pins And a plurality of termination resistors respectively coupled between the termination nodes, and each of the termination nodes is coupled to the plurality of termination nodes, and varies according to the respective termination voltages to determine a logic level of each of the received data signals. A plurality of reference voltage generators for generating a reference voltage to be included can be included. The receiver may further include a plurality of input buffers that compare the terminated data signal with a reference voltage that varies according to a respective termination voltage to generate a logic high level or logic low level internal signal.

  The transmitter further includes a first voltage driver that generates a first voltage signal that varies according to the driving ground voltage, and a first voltage output pin that outputs the first voltage signal, and the receiver includes the first voltage signal. The apparatus may further include a first voltage input pin that receives a signal and is coupled to the plurality of reference voltage generators.

  Meanwhile, the transmitter includes a first voltage driver that generates a first voltage signal that changes according to the driving ground voltage, a second voltage driver that generates a second voltage signal that changes according to the driving power supply voltage, and the first voltage signal. And a second voltage output pin for outputting the second voltage signal, wherein the receiver receives the first voltage signal and is coupled to the plurality of reference voltage generators. And a second voltage input pin that receives the second voltage signal and the second voltage signal and is coupled to the plurality of reference voltage generators.

  One of the transmitter and the receiver can be used as a memory controller and the other as a memory device.

  A method for generating a reference voltage according to an embodiment of the present invention includes: receiving a plurality of data signals; terminating the data signal at a termination voltage through a termination resistor; and changing a reference voltage according to the termination voltage. Including the stages that occur.

  The method of generating a reference voltage may further include providing a first voltage that varies according to a driving ground voltage connected to a pull-down data driver of a transmitter that outputs the data signal. Meanwhile, the method for generating a reference voltage includes providing a first voltage that varies according to a driving ground voltage connected to a pull-down data driver of a transmitter that outputs the data signal, and is connected to a pull-up data driver of the transmitter. The method may further include providing a second voltage that varies according to the driving power supply voltage.

  In the embodiments of the present invention disclosed herein, the specific structural or functional description is merely an example for explaining the embodiments of the present invention. It can be implemented in various forms and is not limited to the embodiments described herein.

  The present invention can be variously modified and have various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this should not be construed as limiting the scope of the present invention to the specific embodiments, and that the present invention includes all modifications, equivalents or alternatives that fall within the spirit and scope of the invention. .

  Similar reference numerals have been given to components while describing each drawing.

  The terms such as “first” and “second” can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, the first component can be expressed as the second component, and similarly, the second component can be expressed as the first component without departing from the scope of the present invention.

  When any component is referred to as “coupled” or “connected” to another component, it may be directly coupled or connected to the other component, but in the middle It should be understood that elements may be present. On the other hand, when any component is referred to as being “directly connected” or “directly connected” to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components should be interpreted in the same way, such as “between” and “immediately between” or “adjacent to” and “adjacent to”. .

  The terminology used in this application is used to describe particular embodiments and is not intended to limit the invention. The singular form includes the plural form unless the context clearly dictates otherwise. In this application, it is understood that terms such as “comprising” or “having” do not pre-exclude the presence or additionality of the features, numbers, steps, actions, components, parts or combinations thereof described. Should.

  Unless defined differently, all terms used herein, including technical or scientific terms, are generally understood by those having ordinary skill in the art to which this invention belongs. Have the same meaning. Terms such as those defined in commonly used dictionaries should be construed as having a meaning consistent with the meaning possessed in the context of the related art and, unless explicitly defined in this application, are unusual. Or are not overly interpreted in a formal sense.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same constituent elements in the drawings are given the same reference numerals, and redundant description of the same constituent elements is omitted.

  FIG. 1 is a circuit diagram illustrating a system according to an embodiment of the present invention.

  Referring to FIG. 1, a system 500 includes a transmitter 320, a receiver 220, and a plurality of transmission lines 30a, 30b, 30n, 35.

  The transmitter 320 transmits a plurality of data signals using a common drive power supply voltage VDD ′ and a common drive ground voltage VSS ′. The receiver 220 receives the data signal, terminates the received data signal with the respective termination voltages VDD1, VDD2, VDDn, and sets the logic level (low or high) of each terminated data signal IS1, IS2, ISn. ) Are generated, reference voltages (VREF1, VREF2, VREFn) that change according to respective termination voltages (VDD1, VDD2, VDDn) are generated. The data transmission lines 30a, 30b, and 30n are connected between the transmitter 320 and the receiver 220. The system 500 can further include a voltage transmission line 35.

  The transmitter 320 includes a plurality of data drivers 50a, 50b, and 50n and a plurality of data output pins 40a, 40b, and 40n. The receiver 220 includes a plurality of data input pins 10a, 10b, and 10n, a power supply voltage line 90, and a plurality of data output pins 40a, 40b, and 40n. Terminal resistor RT and a reference voltage generation circuit 120. The receiver 220 may further include a plurality of input buffers 20a, 20b, 20n.

  The plurality of data drivers 50a, 50b, and 50n of the transmitter 320 generate data signals using a common drive ground voltage VSS 'and a common drive power supply voltage VDD'. The generated data signal is output through the plurality of data output pins 40a, 40b, and 40n and transmitted to the receiver 220 through the transmission lines 30a, 30b, and 30n.

  The receiver 220 receives a data signal through the plurality of data input pins 10a, 10b, and 10n. The plurality of data input pins 10a, 10b, and 10n are terminated by respective termination voltages VDD1, VDD2, and VDDn. Each termination voltage VDD1, VDD2, VDDn is provided from a plurality of termination nodes NT1, NT2, NTn arranged on the power supply voltage line 90. The plurality of termination resistors RT are connected between the data input pins 10a, 10b, and 10n and the termination nodes NT1, NT2, and NTn, respectively, and prevent reflected waves that can be generated on the transmission lines 30a, 30b, and 30n. The data signal is received stably.

  The plurality of input buffers 20a, 20b, and 20n compare the terminated data signals IS1, IS2, and ISn with the respective reference voltages VREF1, VREF2, and VREFn, and compare the logic high level or logic low level comparison signals CS1, CS2, Generate CSn.

  The reference voltage generation circuit 120 is connected to termination nodes NT1, NT2, and NTn that provide termination voltages VDD1, VDD2, and VDDn to the data input pins 10a, 10b, and 10n. The reference voltage generation circuit 120 generates reference voltages VREF1, VREF2, and VREFn that change according to the termination voltages VDD1, VDD2, and VDDn, respectively, in order to determine the logic levels of the terminated data signals IS1, IS2, and ISn. .

  Unlike the conventional reference voltage generator, the reference voltage generation circuit 120 according to an exemplary embodiment of the present invention increases or decreases the termination voltages VDD1, VDD2, and VDDn due to noise on the power supply voltage line 90, or the power supply voltage line. When the termination voltages are different due to a voltage drop due to the resistance component of 90, etc., the respective reference voltages VREF1, VREF2, and VREFn that change due to changes in the termination voltages are generated. A specific configuration of the reference voltage generator will be described later.

  The transmitter 320 can further include a first voltage driver 60 and a first voltage output pin 75, and the receiver 220 can further include a first voltage input pin 70. The first voltage driver 60 generates a first voltage signal that varies according to the driving ground voltage VSS ′, and the first voltage signal is transmitted to the receiver 220 through the first voltage output pin 75 and the voltage transmission line 35. The receiver 220 receives the first voltage signal VL through the first voltage input pin 70 connected to the reference voltage generation circuit 120. The first voltage driver 60 maintains a turn-on state when transmitting a data signal.

  In this case, the voltage generation circuit 120 generates the reference voltages VREF1, VREF2, and VREFn corresponding to the data signals IS1, IS2, and ISn terminated based on the termination voltages VDD1, VDD2, and VDDn and the received first voltage signal VL. Is generated. Accordingly, the voltage generation circuit 120 reflects the difference between the noise of the driving ground voltage VSS ′ and the driving power supply voltage VDD ′ of the transmitter 320 and the termination voltage of the receiver 220, respectively, and terminates the respective data signals IS1, IS2. , Reference voltages VREF1, VREF2, and VREFn having voltage levels conforming to ISn are generated.

  Hereinafter, a data signal transmission path and a reference voltage generation path will be described.

  FIG. 2 is a circuit diagram showing a data signal transmission path by an open drain structure data driver.

  Referring to FIG. 2, the pull-down data driver 50 of the transmitter generates a logic low level or logic high level data signal through a switching operation, and the generated data signal is transmitted to the receiver through the transmission line 30. The transmitted data signal is terminated by a termination voltage VTT through a termination resistor RT, and the terminated data signal IS is provided to an internal circuit such as a comparator.

  When the sum of the turn-on resistance of the pull-down data driver 50 and the resistance of the transmission line is modeled as RON (that is, resistance from the driving ground voltage VSS ′ of the transmitter to the data input pin of the receiver), and the termination resistance is modeled as RT. The low voltage VOL of the terminated data signal IS when the pull-down data driver 51 is turned on and the high voltage VOH of the terminated data signal IS when the pull-down data driver 51 is turned off are the same as Equation 1.

VOL = VTT × RON / (RON + RT)
VOL = VTT
... (Formula 1)
Since the reference voltage must be maintained at an intermediate voltage between the low voltage VOL and the high voltage VOH, a reference voltage such as Equation 2 is required.

VREF = (VOL + VOH) / 2 = VTT × (RON + (RT / 2)) / (RON + RT)
... (Formula 2)
FIG. 3 is a circuit diagram illustrating a generation path of a reference voltage by a voltage driver having an open drain structure.

  Referring to FIG. 3, the pull-down voltage driver 60 of the transmitter generates a voltage signal based on the driving ground voltage VSS ′, and the generated voltage signal is transmitted to the receiver through the transmission line 35. The receiver divides the termination voltage VTT and the first voltage VL of the voltage node NL by the pull-up resistor RU and the pull-down resistor RD, and generates the reference voltage VREF through the reference node NR.

  When the sum of the turn-on resistance of the pull-down voltage driver 60 and the resistance of the transmission line 35 is modeled as RON like the transmission path of the data signal in FIG. 3, the reference voltage VREF when the pull-down voltage driver 60 is turned on is The same.

VREF = VTT × (RON + RU) / (RON + RD + RU)
... (Formula 3)
When the pull-down data driver 50 of FIG. 2 and the pull-down voltage driver 60 of FIG. 3 are implemented as transistors having the same size and characteristics, and the resistance characteristics of the data transmission line 30 and the voltage transmission line 35 are the same, RON of Expression 3 and Expression 4 Are the same. Therefore, when RU = RD is satisfied and RU + RD = RT is satisfied, the reference voltages of Equation 2 and Equation 3 are the same.

  FIG. 4 is a circuit diagram illustrating the receiver of FIG. 1 including a reference voltage generation circuit according to an embodiment of the present invention. A description of the same components as those in FIG. 1 is omitted.

  Referring to FIG. 4, the reference voltage generation circuit 120 included in the receiver 220 includes a plurality of reference voltage generators 120a, 120b, and 120n. The plurality of reference voltage generators 120a, 120b, and 120n generate respective reference voltages VREF1, VREF2, and VREFn corresponding to the terminated data signals IS1, IS2, and ISn. Each reference voltage generator 120a, 120b, 120n has a first end connected to each of the termination nodes NT1, NT2, NTn, and a second end connected to a voltage input pin 70 to which the first voltage VL is applied. Is done. Accordingly, the plurality of reference voltage generators 120 a, 120 b and 120 n are connected in parallel between the power supply voltage line 90 and the voltage input pin 70.

  To explain one reference voltage generator as an example, the reference voltage generator 120a divides the termination voltage VDD1 of the termination node NT1 and the first voltage VL to determine the logic level of the terminated data signal IS1. A reference voltage VREF1 is generated. As described with reference to FIGS. 2 and 3, the termination voltage VDD1 is the same as the high voltage of the data signal IS1. The first voltage is provided through the same transmission path as the logic low level data signal IS1, and the total combined resistance of the plurality of reference voltage generators 120a, 120b, 120n connected in parallel is the resistance value of one termination resistor. In the same case, the first voltage is the same as the low voltage of the data signal IS1. That is, the reference voltage generator 120a generates the reference voltage VREF1 based on the termination voltage VDD1 that is the same as the high voltage of the terminated data signal IS1 and the first voltage that is the same as the low voltage. Accordingly, even when the termination voltage VDD1 or the transmitter ground voltage VSS ′ of the transmitter driver changes due to noise or the like, the reference voltage VREF1 also changes due to the change. Therefore, the reference voltage VREF1 is equal to the high voltage of the terminated data signal IS1. An intermediate value of the low voltage can be maintained.

  The plurality of reference voltage generators 120a, 120b, 120n are connected to respective termination voltages. Accordingly, when the values of the termination voltages VDD1, VDD2, and VDDn are different from each other due to the voltage drop of the power supply voltage line 90 or change due to noise, the respective reference voltage generators 120a, 120b, and 120n Respective reference voltages VREF1, VREF2, VREFn adapted to the voltage levels of IS1, IS2, ISn can be provided.

  5 and 6 are circuit diagrams showing the configuration of the reference voltage generating circuit of FIG.

  Referring to FIG. 5, each of the reference voltage generators 121a, 121b, 121n connected in parallel between the plurality of termination nodes NT1, NT2, NTn and the first voltage node NL includes a pull-down resistor RD and a pull-up resistor. Each RU is included. The pull-down resistor RD is connected between the respective reference nodes NR1, NR2, NRn and the first voltage node NL, and the pull-up resistor RU is connected to the respective termination nodes NT1, NT2, NTn and the respective reference nodes NR1, NR2, Connected between NRn.

  For example, when the number of reference voltage generators connected in parallel between the termination nodes NT1, NT2, NTn and the first voltage node NL is n and each termination resistor RT has a resistance value of R, The pull-down resistor RD has a resistance value of n (R / 2), and each pull-up resistor RU has a resistance value of n (R / 2). Accordingly, when the data signal transmission path and the voltage signal transmission path have the same resistance value, the termination voltages VDD1, VDD2, and VDDn are the high voltages (logic high level) of the corresponding data signals IS1, IS2, and ISn, respectively. The voltage VL of the first voltage node NL is the same as the logic low level of the corresponding terminated data signal IS1, IS2, ISn. Therefore, even if the termination voltages VDD1, VDD2, and VDDn are different or the driving ground voltage VSS ′ and the driving power supply voltage VDD ′ of the transmitter are changed, the respective reference voltages VREF1, VREF2, and VREFn are correspondingly terminated data. An intermediate value between the logic low level and the logic high level of the signals IS1, IS2, and ISn can be maintained.

  Referring to FIG. 6, the reference voltage generation circuit 122 further includes a common pull-down resistor RDC connected in common between the first voltage node NL and the reference nodes NR1, NR2, and NRn, and each reference voltage generator 122a, 122b and 122n further include pull-up resistors RU connected between the respective termination nodes NT1, NT2 and NTn and the reference node.

  For example, the number of reference voltage generators 122a, 122b, 122n connected in parallel between the termination nodes NT1, NT2, NTn and the first voltage node NL is n, and each termination resistor RT has a resistance value of R. In some cases, the common pull-down resistor RDC has a resistance value of R / 2, and each pull-up resistor RU has a resistance value of n (R / 2). In this case, the respective reference voltages VREF1, VREF2, and VREFn can maintain the intermediate value between the logic low level and the logic high level of the corresponding terminated data signals IS1, IS2, and ISn as described above. .

  FIG. 7 is a circuit diagram illustrating a system according to another embodiment of the present invention. Unlike the system of FIG. 2 that includes one voltage transmission path, the system of FIG. 8 includes two voltage transmission paths.

  Referring to FIG. 7, the transmitter 340 further includes a first voltage driver 60a, a second voltage driver 60b, a first voltage output pin 75a, and a second voltage output pin 75b for transmitting the transmitter driving voltage. The receiver 240 further includes a first voltage input pin 70a and a second voltage input pin. The first voltage driver 60a generates a first voltage signal that varies according to the driving ground voltage VSS ', and the first voltage signal is transmitted to the receiver 240 through the first voltage output pin 75a and the voltage transmission line 35a. The receiver 240 receives the first voltage signal VL through the first voltage input pin 70 a connected to the reference voltage generation circuit 140. The second voltage driver 60a generates a second voltage signal that varies according to the driving power supply voltage VDD ', and the second voltage signal is transmitted to the receiver 240 through the second voltage output pin 75b and the voltage transmission line 35b. The receiver 240 receives the second voltage signal VH through the second voltage input pin 70 a connected to the reference voltage generation circuit 140. The first voltage driver 60a and the second voltage driver 60b always maintain a turn-on state when transmitting a data signal.

  In this case, the voltage generation circuit 140 includes reference voltages corresponding to the termination voltages VDD1, VDD2, and VDDn, and the data signals IS1, IS2, and ISn terminated based on the received first voltage signal VL and second voltage signal VH. Voltages VREF1, VREF2, and VREFn are generated. Therefore, the voltage generation circuit 140 reflects all the differences in the noise of the driving ground voltage VSS ′ and the driving power supply voltage VDD ′ of the transmitter 340 and the termination voltage of the receiver 240, in the respective data signals IS1, IS2, and ISn. The reference voltages VREF1, VREF2, and VREFn having appropriate voltage levels are generated.

  As described in connection with FIGS. 2 and 3, the first voltage signal VL is transmitted from the driving ground voltage VSS ′ of the transmitter 340 through the same path as the data signal having a logic low level to the first voltage input pin 70a of the receiver 240. Can be transmitted. Similarly, the second voltage signal VH may be transmitted from the driving power supply voltage VDD 'of the transmitter 340 to the second voltage input pin 70b of the receiver 240 through the same path as the logic high level data signal.

  FIG. 8 is a circuit diagram illustrating the receiver of FIG. 7 including a reference voltage generation circuit according to an embodiment of the present invention. A description of the same components as those described above is omitted.

  Referring to FIG. 8, the reference voltage generation circuit 140 included in the receiver 240 includes a plurality of reference voltage generators 140a, 140b, and 140n. The plurality of reference voltage generators 140a, 140b, and 140n generate respective reference voltages VREF1, VREF2, and VREFn corresponding to the terminated data signals IS1, IS2, and ISn.

  Each of the reference voltage generators 140a, 140b, and 140n has a first end connected to the voltage input pin 70a to which the first voltage VL is applied, and a second end to the voltage input pin 70b to which the second voltage VH is applied. Connected. Accordingly, the plurality of reference voltage generators 140a, 140b, and 140n are connected in parallel between the first voltage input pin 70a and the second voltage input pin 70b.

  As an example, one reference voltage generator 140a terminates the first voltage signal VL and the second voltage signal VH to the termination voltage VDD1, and distributes the terminated first voltage and second voltage. A reference voltage VREF1 for determining the logic level of the terminated data signal IS1 is generated. As described above, when the data signal transmission path and the voltage signal transmission path are the same, the terminated first voltage and the terminated second voltage are the same as the low voltage and the high voltage of the data signal IS1, respectively. is there. That is, the reference voltage generator 140a generates the reference voltage VREF1 based on the terminated first voltage and the terminated second voltage that are the same as the low voltage and the high voltage of the terminated data signal IS1. Accordingly, even when the termination voltage VDD1 or the driving ground voltage VSS ′ and the driving power supply voltage VDD ′ of the transmitter driver change due to noise or the like, the reference voltage VREF1 also changes due to the change, so that the reference voltage VREF1 is terminated by the data signal IS1. The intermediate value between the high voltage and the low voltage can be maintained.

  The plurality of reference voltage generators 140a, 140b, and 140n are connected to respective termination voltages. Accordingly, when the values of the termination voltages VDD1, VDD2, and VDDn are different from each other due to the voltage drop of the power supply voltage line 90 or change due to noise, the respective reference voltage generators 120a, 120b, and 120n are connected to the respective terminated data signals IS1. , IS2, ISn can be provided with respective reference voltages VREF1, VREF2, VREFn adapted to the voltage levels.

  FIG. 9 is a circuit diagram showing an example of the configuration of the reference voltage generation circuit of FIG.

  Referring to FIG. 9, each of the reference voltage generators 140a, 140b, and 140n connected in parallel between the plurality of termination nodes NT1, NT2, and NTn and the first voltage node NL and the second voltage node NH includes a first voltage node 140a, 140b, and 140n. It includes a pull-down resistor RD that terminates the voltage signal VL to the termination voltages VDD1, VDD2, and VDDn, and a pull-up resistor RU that terminates the second voltage signal VH to the termination voltages VDD1, VDD2, and VDDn, respectively. The pull-down resistor RD is connected between the respective termination nodes NT1, NT2, NTn and the respective pull-down nodes ND, and the pull-up resistor RU is connected between the respective termination nodes NT1, NT2, NTn and the respective pull-up nodes ND. Connected. A first distribution resistor R1 and a second distribution resistor R2 are connected between the pull-down node ND and the pull-up node NU, and the first voltage terminated at the pull-down node ND through the respective reference nodes NR1, NR2, and NRn. An intermediate voltage of the second voltage terminated at the pull-up node NU can be generated in the respective reference voltages VREF1, VREF2, and VREFn. The first distribution resistor R1 and the second distribution resistor R2 have the same resistance value and can be easily configured with a poly resistor or the like.

  When each termination resistor RT has a resistance value of R, a combined resistance of a pull-down resistor RD connected between the plurality of termination nodes NT1, NT2, NTn and the first voltage node NL has a resistance value of R. The combined resistance of the pull-up resistor RU connected between the plurality of termination nodes NT1, NT2, NTn and the second voltage node NL also has a resistance value of R. Therefore, even if the termination voltages VDD1, VDD2, and VDDn are different or the driving ground voltage VSS ′ and the driving power supply voltage VDD ′ of the transmitter are changed, the respective reference voltages VREF1, VREF2, and VREFn are correspondingly terminated data signals IS1. , IS2 and ISn can be maintained at an intermediate value between the logic low level and the logic high level.

  FIG. 10 is a circuit diagram showing a receiver 240 'including a reference voltage generating circuit according to another embodiment of the present invention, and FIG. 11 is a circuit diagram showing a configuration of the reference voltage generating circuit of FIG. Since the reference voltage generation circuit 160 of FIGS. 10 and 11 has a configuration similar to that of the reference voltage generation circuit 140 of FIGS. 8 and 9, only the difference between the two will be described.

  Unlike the case where each reference voltage generator 140a, 140b, 140n included in the reference voltage generation circuit 140 of FIG. 8 generates one reference voltage based on one termination voltage, the reference voltage generation circuit 160 of FIG. The reference voltage generators 160a and 160b included in each generate the same two reference voltages based on two adjacent termination voltages. Therefore, when generating reference voltages for the same number of data signals, the number of reference voltage generators 160a and 160b in FIG. 10 corresponds to half of the number of reference voltage generators 140a, 140b and 140n in FIG. In this case, the pair of reference voltages is generated based on an average value of two adjacent termination voltages.

  Only the embodiment in which each reference voltage generator generates the same two reference voltages based on two adjacent termination voltages has been described in connection with FIG. A configuration in which the same three reference voltages are generated based on one termination voltage is also possible, and a configuration in which the same reference voltage corresponding to four or more termination voltages is generated is also possible.

  It can be seen that the systems of FIGS. 1 and 7 can be applied to data drivers of an open drain structure and a push-pull structure by setting appropriate resistance values.

  The termination resistor, the pull-up resistor, and the pull-down resistor can be configured to include a MOS transistor or the like. The termination resistor, the pull-up resistor, and the pull-down resistor may be variable resistors, and the resistance values may be adjusted in response to an external control code.

  The reference voltage generating circuit, the system including the reference voltage, and the reference voltage generating method according to the embodiment of the present invention provide a plurality of data signals by providing respective reference voltages that vary depending on respective termination voltages of the data signals. The error rate when determining the logical level can be reduced.

  In addition, a reference voltage generating circuit, a system including the reference voltage generating circuit, and a reference voltage generating method according to embodiments of the present invention include a terminal voltage of each data signal and a driving power source for a data driver included in a transmitter that transmits the data signal. A reference voltage that varies depending on the voltage and the driving ground can be provided to further reduce the error rate when determining the logic levels of the plurality of data signals.

  As described above, the embodiment of the present invention has been described in detail. The present invention can be modified or changed.

1 is a circuit diagram illustrating a system according to an embodiment of the present invention. It is a circuit diagram which shows the transmission path | route of the data signal by the data driver of an open drain structure. FIG. 5 is a circuit diagram showing a generation path of a reference voltage by a voltage driver having an open drain structure. FIG. 2 is a circuit diagram illustrating the receiver of FIG. 1 including a reference voltage generating circuit according to an embodiment of the present invention. FIG. 5 is a circuit diagram illustrating an example of a configuration of a reference voltage generation circuit in FIG. 4. FIG. 5 is a circuit diagram showing another example of the configuration of the reference voltage generation circuit of FIG. 4. FIG. 6 is a circuit diagram illustrating a system according to another embodiment of the present invention. FIG. 8 is a circuit diagram illustrating the receiver of FIG. 7 including a reference voltage generation circuit according to an embodiment of the present invention. FIG. 9 is a circuit diagram illustrating an example of a configuration of a reference voltage generation circuit in FIG. 8. FIG. 5 is a circuit diagram illustrating a receiver including a reference voltage generation circuit according to another embodiment of the present invention. FIG. 11 is a circuit diagram illustrating an example of a configuration of a reference voltage generation circuit in FIG. 10.

Explanation of symbols

10a, 10b, 10n Data input pins 40a, 40b, 40n Data output pins 50, 50a, 50b, 50n Data drivers 60, 60a, 60b Voltage drivers 70, 70a, 70b Voltage input pins 75, 75a, 75b Voltage output pins 90 Power supply Voltage line 100, 120, 121, 122, 140, 160 Reference voltage generation circuit VSS ′ Drive ground voltage VDD ′ Drive power supply voltage VREF Reference voltage VDD1, VDD2, VDDn Termination voltage IS Terminated data signal NT Termination node NR Reference node RT Termination resistor RD Pull-down resistor RU Pull-up resistor

Claims (36)

A plurality of termination nodes that provide termination voltages for terminating a plurality of data signals through termination resistors, respectively;
A plurality of reference voltage generators connected to the plurality of termination nodes and generating a reference voltage that varies according to the termination voltage in order to determine a logic level of the terminated data signal. Generation circuit. The reference voltage generation circuit further includes a first voltage node that provides a first voltage that varies according to a logic low level of the data signal;
The reference voltage generation circuit of claim 1, wherein the first voltage is provided based on a driving ground voltage connected to a pull-down voltage driver of a transmitter that outputs the data signal. The plurality of reference voltage generators are:
3. The reference voltage generation circuit according to claim 2, wherein the reference voltage generation circuit is connected in parallel between the termination node and the first voltage node. Each of the reference voltage generators is
A reference node for generating an intermediate voltage of the respective termination node and the first voltage node in the reference voltage;
A pull-down resistor connected between the reference node and the first voltage node;
3. The reference voltage generating circuit according to claim 2, further comprising a pull-up resistor connected between each of the termination nodes and the reference node.   When the number of reference voltage generators connected in parallel between the termination node and the first voltage node is n (n is a natural number of 2 or more) and each termination resistor has a resistance value of R, 5. The reference voltage generating circuit according to claim 4, wherein each pull-down resistor has a resistance value of n (R / 2), and each of the pull-up resistors has a resistance value of n (R / 2). . Each of the reference voltage generators is
A reference node for generating an intermediate voltage of the respective termination node and the first voltage node in the reference voltage;
A pull-up resistor coupled between the respective termination node and the reference node;
3. The reference voltage generation circuit according to claim 2, wherein the reference voltage generation circuit further includes a common pull-down resistor connected in common between the first voltage node and the reference node.   When the number of reference voltage generators connected in parallel between the termination node and the first voltage node is n (n is a natural number of 2 or more) and each termination resistor has a resistance value of R, 7. The reference voltage generation circuit according to claim 6, wherein the common pull-down resistor has a resistance value of R / 2, and each of the pull-up resistors has a resistance value of n (R / 2). The reference voltage generation circuit includes a first voltage node that provides a first voltage that varies according to a logic low level of the data signal, and a second voltage node that provides a second voltage that varies according to a logic high level of the data signal. In addition,
The first voltage is provided based on a driving ground voltage coupled to a pull-down data driver of a transmitter that outputs the data signal;
The reference voltage generation circuit according to claim 1, wherein the second voltage is provided based on a driving power supply voltage connected to a pull-up data driver of the transmitter. The reference voltage generator is
9. The reference voltage generation circuit according to claim 8, wherein the reference voltage generation circuit is connected in parallel between the first voltage node and the second voltage node. Each of the reference voltage generators is
A pull-down node that terminates the first voltage at the respective termination voltage, a pull-up node that terminates the second voltage at the respective termination voltage, and an intermediate voltage between the pull-down node and the pull-up node as the reference voltage 9. The reference voltage generation circuit according to claim 8, further comprising a reference node that is generated. Each of the reference voltage generators is
A pull-down resistor connected between the respective termination node and the pull-down node to terminate the first voltage signal;
A pull-up resistor connected between the respective termination node and the pull-up node to terminate the second voltage signal;
A first distribution resistor connected between the pull-down node and the reference node;
The reference voltage generation circuit of claim 10, further comprising a second distribution resistor connected between the pull-up node and the reference node.   The number of reference voltage generators connected in parallel between the first voltage node and the second voltage node is n (n is a natural number of 2 or more), and each of the termination resistors has a resistance value of R. The respective pull-down resistors have a resistance value of nR, the respective pull-up resistors have a resistance value of nR, and the first distribution resistor and the second distribution resistor have the same resistance value. The reference voltage generation circuit according to claim 11. Each of the reference voltage generators is
A pull-down node that terminates the first voltage signal with a termination voltage of a first termination node of the two adjacent termination nodes, and a termination of a second termination node of the two adjacent termination nodes with the second voltage signal 9. The reference voltage generation circuit according to claim 8, further comprising: a pull-up node that terminates with a voltage; and a reference node that generates an intermediate voltage between the pull-down node and the pull-up node as the reference voltage. Each of the reference voltage generators is
A pull-down resistor connected between the first termination node and the pull-down node;
A pull-up resistor connected between the second termination node and the pull-up node;
A first distribution resistor connected between the pull-down node and the reference node;
14. The reference voltage generating circuit according to claim 13, further comprising a second distribution resistor connected between the pull-up node and the reference node.   When the number of reference voltage generators connected in parallel between the first voltage node and the second voltage node is n (n is a natural number) and each of the termination resistors has a resistance value of R, The pull-down resistor has a resistance value of nR, each of the pull-up resistors has a resistance value of nR, and the first distribution resistor and the second distribution resistor have the same resistance value. Item 15. The reference voltage generation circuit according to Item 14. A transmitter for transmitting a plurality of data signals using a common drive power supply voltage and a common drive ground voltage;
In order to receive the data signal, terminate the received data signal with a respective termination voltage, and determine a logic level of the terminated data signal, a reference voltage that varies with the termination voltage is determined. A receiver that generates,
And a plurality of transmission lines connected between the transmitter and the receiver. The transmitter is
A plurality of data drivers for generating the data signal according to the common driving ground voltage and the common driving power supply voltage;
A plurality of data output pins for outputting the data signal,
The receiver
A plurality of data input pins that receive the data signal and are terminated by respective termination voltages;
A power supply voltage line in which a plurality of termination nodes providing the respective termination voltages are arranged;
A plurality of termination resistors respectively connected between the data input pin and the termination node;
A plurality of reference voltage generators coupled to each of the plurality of termination nodes and generating a reference voltage that varies according to the respective termination voltage in order to determine a logic level of each received data signal. The system of claim 16. The receiver
18. The method of claim 17, further comprising: a plurality of input buffers that compare the terminated data signal with a reference voltage that varies according to a termination voltage and generate an internal signal of a logic high level or a logic low level. System. The transmitter further includes a first voltage driver that generates a first voltage signal that varies according to the driving ground voltage, and a first voltage output pin that outputs the first voltage signal;
The system of claim 17, wherein the receiver further comprises a first voltage input pin that receives the first voltage signal and is coupled to the plurality of reference voltage generators. The plurality of reference voltage generators are:
20. The system of claim 19, wherein the system is connected in parallel between a termination node of the power supply voltage line and the first voltage input pin. Each of the reference voltage generators is
And including a pull-down resistor and a pull-up resistor for distributing the respective termination voltage and the first voltage of the first voltage input pin, and generating an intermediate voltage between the respective termination voltage and the first voltage in the reference voltage. 21. The system of claim 20, wherein   When each of the termination resistors has a resistance value of R, a total combined resistance of a pull-down resistor and a pull-up resistor connected between the plurality of termination nodes and the first voltage input pin has a resistance value of R. The system of claim 21. The transmitter outputs a first voltage driver that generates a first voltage signal that changes according to the driving ground voltage, a second voltage driver that generates a second voltage signal that changes according to the driving power supply voltage, and the first voltage signal. A first voltage output pin that outputs the second voltage signal, and a second voltage output pin that outputs the second voltage signal.
The receiver receives the first voltage signal and receives a first voltage input pin connected to the plurality of reference voltage generators and the second voltage signal and is connected to the plurality of reference voltage generators. The system of claim 17, further comprising a second voltage input pin. The plurality of reference voltage generators are:
The system of claim 23, wherein the system is connected in parallel between the first voltage input pin and the second voltage input pin. Each of the reference voltage generators is
25. The system of claim 24, comprising a pull-down resistor that terminates the first voltage signal at the respective termination voltage, and a pull-up resistor that terminates the second voltage at the respective termination voltage.   When each of the termination resistors has a resistance value of R, a combined resistance of pull-down resistors connected between the plurality of termination nodes and the first voltage input pin has a resistance value of R, and the plurality of terminations 26. The system of claim 25, wherein a combined resistance of a pull-up resistor connected between a node and the second voltage input pin has a resistance value of R. Each of the reference voltage generators is
A first voltage terminated through the pull-down resistor and a second voltage terminated through the pull-up resistor are distributed to generate an intermediate voltage between the terminated first voltage and the terminated second voltage as the reference voltage. 26. The system of claim 25, further comprising a first distribution resistor and a second distribution resistor.   18. The system of claim 17, wherein one of the transmitter and the receiver is a memory controller and the other is a memory device. Receiving a plurality of data signals; and
Terminating the data signals at respective termination voltages through termination resistors;
Generating a reference voltage that changes according to each of the termination voltages. Terminating the data signals with respective termination voltages comprises:
30. The reference voltage generating method according to claim 29, wherein the data signal is terminated at a termination voltage of each termination node arranged on a common power supply voltage line.   30. The method of claim 29, further comprising providing a first voltage that varies according to a driving ground voltage connected to a pull-down data driver of a transmitter that outputs the data signal. Generating a reference voltage that varies according to the respective termination voltage,
Distributing the respective termination voltage and the first voltage to respective pull-down resistors and respective pull-up resistors;
32. The method of claim 31, further comprising: providing an intermediate voltage between the respective termination voltage and the first voltage to the reference voltage.   When each of the termination resistors has a resistance value of R, a total combined resistance of a pull-down resistor and a pull-up resistor connected between the plurality of termination nodes and the first voltage input pin has a resistance value of R. 33. The reference voltage generating method according to claim 32. Providing a first voltage that varies according to a driving ground voltage coupled to a pull-down data driver of a transmitter that outputs the data signal;
30. The method of claim 29, further comprising: providing a second voltage that varies according to a driving power voltage coupled to a pull-up data driver of the transmitter. Generating a reference voltage that varies according to the respective termination voltage,
Terminating the first voltage and the second voltage through respective pull-down resistors and respective pull-up resistors according to the respective termination voltages;
Distributing a first voltage terminated through the pull-down resistor and a second voltage terminated through the pull-up resistor to a distribution resistor;
35. The method of claim 34, further comprising: providing an intermediate voltage between the first voltage and the second voltage to the reference voltage.   When each of the termination resistors has a resistance value of R, a combined resistance of pull-down resistors connected between the plurality of termination nodes and the first voltage input pin has a resistance value of R, and the plurality of terminations 36. The method of claim 35, wherein the combined resistance of the pull-up resistors connected between the node and the second voltage input pin has an R resistance value.

Images