JP2007306497A

JP2007306497A - Clock synchronization method and circuit in packet transmission

Info

Publication number: JP2007306497A
Application number: JP2006135337A
Authority: JP
Inventors: Tomoyuki Terayama; 知幸寺山
Original assignee: Oki Electric Industry Co Ltd
Current assignee: Oki Electric Industry Co Ltd
Priority date: 2006-05-15
Filing date: 2006-05-15
Publication date: 2007-11-22

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock synchronization method and circuit which can adequately control output jitter on a receiving side. <P>SOLUTION: A synchronization method and circuit are employed between a transmitting side clock signal and a receiving side clock signal, in a packet transmission system which transmits a packet including data processed according to the clock signal through a transmission network. A transmission time stamp is added to a transmission packet supplied to the transmission network, and a reception time stamp is added to the transmission packet every time the transmission packet is taken in from the transmission network as a reception packet. From a series of reception packets obtained by sorting the reception packets in order of time of the transmission time stamp; the reception packet included in a series of reception packets is extracted per predetermined time length, a difference is calculated between a transmission time stamp interval and a reception time stamp interval determined with the previous or the subsequent extracted reception packet, the difference is accumulated per extracted reception packet to calculate a difference accumulated value, and a frequency of the reception clock signal is adjusted according to the difference accumulated value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、クロック信号に従って処理されるべき映像データや音声データの如きデータを含むパケットを伝送網を介して伝送するパケット伝送システムにおける、送信側クロック信号と受信側クロック信号との間の同期をなすクロック同期方法及び回路に関する。 The present invention provides synchronization between a transmission side clock signal and a reception side clock signal in a packet transmission system that transmits a packet including data such as video data and audio data to be processed according to a clock signal via a transmission network. The present invention relates to a clock synchronization method and circuit.

図１は、公知のパケット伝送装置を示している。このパケット伝送装置においては、マスター装置１からスレーブ装置３に向けて例えば映像データの如き主データがパケットに乗せられてＩＰ網２を介して伝送される。ＩＰ網２の如き非同期パケット伝送網を介した通信では、マスター装置１とスレーブ装置３との間で時刻すなわちクロックの同期がなされて、受信パケットに乗せられていた主データに対して適切なパケットデータ処理がなされる必要がある。そこで、基準となるマスタークロック信号を有するマスター装置１は、ＩＰ網２を介してスレーブ装置３へ送信されるべき送信パケットの送信時に、マスタークロック信号に従った送信時刻情報、すなわち、送信タイムスタンプを当該送信パケットに付加する。一方、スレーブ装置３は、マスタークロック信号に従属させるべきスレーブクロック信号を生成する。スレーブ装置３は、マスター装置１からの送信パケットを受信パケットとして受信する度に、スレーブクロック信号に従った受信時刻情報、すなわち、受信タイムスタンプを当該受信パケットに付加する。次いで、スレーブ装置３は、この受信タイムスタンプと当該受信パケットから抽出される送信タイムスタンプとを比較することにより、スレーブクロック信号とマスタークロック信号との間の周波数のズレを検出し、スレーブクロック信号の周波数がマスタークロック信号の周波数と一致するように調整を行う。これにより、マスター装置１とスレーブ装置３との間でクロック同期が実現される。 FIG. 1 shows a known packet transmission apparatus. In this packet transmission apparatus, main data such as video data is transmitted in a packet from the master apparatus 1 to the slave apparatus 3 via the IP network 2. In communication via an asynchronous packet transmission network such as the IP network 2, the master device 1 and the slave device 3 synchronize the time, that is, the clock, and an appropriate packet for the main data carried in the received packet. Data processing needs to be done. Therefore, the master device 1 having a master clock signal serving as a reference, when transmitting a transmission packet to be transmitted to the slave device 3 via the IP network 2, transmits transmission time information according to the master clock signal, that is, a transmission time stamp. Is added to the transmission packet. On the other hand, the slave device 3 generates a slave clock signal to be subordinated to the master clock signal. Each time the slave device 3 receives a transmission packet from the master device 1 as a reception packet, the slave device 3 adds reception time information according to the slave clock signal, that is, a reception time stamp to the reception packet. Next, the slave device 3 detects a frequency shift between the slave clock signal and the master clock signal by comparing the reception time stamp with the transmission time stamp extracted from the received packet. Is adjusted so as to match the frequency of the master clock signal. As a result, clock synchronization is realized between the master device 1 and the slave device 3.

クロック同期の具体的な方法としては、特許文献１及び特許文献２に開示される技術が公知である。前者の技術は、送信及び受信タイムススタンプ値間の差に比例する周波数を、例えばＰＬＬ（Phase Locked Loop）を用いて生成している（段落[００１４]参照）。また、後者の技術は、ネットワーク上の連続した時間間隔の各々における最短のパケット伝達時間を計算し、計算されたこの最短パケット伝達時間という一定値を維持するように第二（受信）クロックの周波数を変え、これによって第一（送信）クロックと第二クロックの位相及び周波数について両者の同期をとっている（段落[０００８]参照）。
特表２００２−５１５７１８号公報特開２００４−２７４７６６号公報 As a specific method of clock synchronization, techniques disclosed in Patent Document 1 and Patent Document 2 are known. The former technique generates a frequency proportional to the difference between the transmission and reception time stamp values using, for example, a PLL (Phase Locked Loop) (see paragraph [0014]). The latter technique also calculates the shortest packet transmission time in each successive time interval on the network, and maintains the constant value of the calculated shortest packet transmission time so that the frequency of the second (receive) clock is maintained. Thus, the phase and frequency of the first (transmission) clock and the second clock are synchronized with each other (see paragraph [0008]).
JP-T-2002-515718 JP 2004-274766 A

しかしながら、ＩＰ網上でのパケット到達遅延時間は一定でも緩慢に変化するものでもなく、時々刻々に変化するジッタが存在する。微視的に見れば、送信タイムスタンプの間隔と受信タイムスタンプの間隔は必ずしも常に同じにはならず、むしろ一致することはほとんどない。さらには、マスタークロック信号とスレーブクロック信号の周波数が完全に一致している場合にさえ、送信タイムスタンプ間隔と受信タイムスタンプ間隔とが一致することなく周波数不一致として検知されてしまう場合がある。パケット到達遅延時間のジッタに精確に追従してスレーブクロック信号の周波数調整を行うと、かえて不適切な調整を行って、結果としてスレーブ装置で再生されるクロック信号の出力ジッタをさらに大きくしてしまうことになる。特に、図２に示される如く、パケットのバースト遅延や到達順序の逆転が発生した場合はその影響が大きい。 However, the packet arrival delay time on the IP network is not constant or slowly changes, and there is jitter that changes from moment to moment. From a microscopic viewpoint, the interval between the transmission time stamp and the interval between the reception time stamps is not always the same. Further, even when the frequencies of the master clock signal and the slave clock signal completely match, there may be a case where the transmission time stamp interval and the reception time stamp interval do not match and a frequency mismatch is detected. If the frequency of the slave clock signal is adjusted accurately following the jitter of the packet arrival delay time, an inappropriate adjustment is performed, resulting in a larger output jitter of the clock signal reproduced by the slave device. Will end up. In particular, as shown in FIG. 2, when the burst delay of packets or the arrival order is reversed, the influence is large.

本発明の目的は、受信側における出力ジッタを適切に抑制し得るクロック同期方法及び回路を提供することである。 An object of the present invention is to provide a clock synchronization method and circuit capable of appropriately suppressing output jitter on the receiving side.

本発明によるクロック同期方法は、クロック信号に従って処理されるべきデータを含むパケットを伝送網を介して伝送するパケット伝送システムにおける、送信側クロック信号と受信側クロック信号との間の同期をなすクロック同期方法であり、該伝送網に供給される送信パケットに、該送信側クロック信号に同期して変化し且つ該伝送網への供給タイミングを示す時刻情報を含む送信タイムスタンプを付加する送信タイムスタンプ付加ステップと、該伝送網から受信パケットとして取り込まれる該送信パケットに、該受信側クロック信号に同期して変化し且つ該伝送網からの取込タイミングを示す時刻情報を含む受信タイムスタンプを付加する受信タイムスタンプ付加ステップと、該受信パケットをその送信タイムスタンプの時刻順に並べて得られる一連の受信パケットから所定時間長の累積期間の１つ毎に、これに含まれる受信パケットを抽出し、抽出して得られる一連の抽出受信パケットの各々について、その前または後の抽出受信パケットとの間で定まる送信タイムスタンプ間隔と受信タイムスタンプ間隔との間の差分値を算出し、これを該抽出受信パケット毎に累積して差分累積値を算出する差分累積値算出ステップと、該差分累積値に応じて該受信クロック信号の周波数を調整する調整動作をなす周波数調整ステップとを含むことを特徴とする。 The clock synchronization method according to the present invention is a clock synchronization that synchronizes a transmission side clock signal and a reception side clock signal in a packet transmission system that transmits a packet including data to be processed according to the clock signal via a transmission network. A method of adding a transmission time stamp to a transmission packet supplied to the transmission network and adding a transmission time stamp that includes time information that changes in synchronization with the transmission side clock signal and indicates a supply timing to the transmission network A reception time stamp that includes time information that changes in synchronization with the reception-side clock signal and that indicates timing of capture from the transmission network, to the transmission packet that is captured as a reception packet from the transmission network A time stamp addition step, and the received packets are arranged in the order of the time of the transmission time stamp. Extracting received packets included in the received packets included in the accumulated time period of a predetermined time length from the obtained received packets and extracting the received packets before or after the extracted extracted received packets. A difference accumulation value calculating step of calculating a difference value between a transmission time stamp interval and a reception time stamp interval determined between the packets, and accumulating the difference value for each extracted reception packet; And a frequency adjustment step for performing an adjustment operation for adjusting the frequency of the received clock signal in accordance with the accumulated difference value.

本発明によるクロック同期回路は、クロック信号に従って処理されるべきデータを含む送信パケットを伝送網を介して受信し、該送信パケットの送信側クロック信号に同期した受信側クロック信号を生成するクロック同期回路であり、該伝送網から取り込んだ受信パケットに、該受信側クロック信号に同期して変化し且つ該伝送網からの取込タイミングを示す時刻情報を含む受信タイムスタンプを付加する受信タイムスタンプ付加手段と、該受信パケットから、該送信側クロック信号に同期して変化し且つ該伝送網に供給された供給タイミングを示す時刻情報を含む送信タイムスタンプを抽出する送信タイムスタンプ抽出手段と、該受信パケットをその送信タイムスタンプの時刻順に並べて得られる一連の受信パケットから所定時間長の累積期間の１つ毎に、これに含まれる受信パケットを抽出し、抽出して得られる一連の抽出受信パケットの各々について、その前または後の抽出受信パケットとの間で定まる送信タイムスタンプ間隔と受信タイムスタンプ間隔との間の差分値を算出し、これを該抽出受信パケット毎に累積して差分累積値を算出する差分累積値算出手段と、該差分累積値に応じて該受信クロック信号の周波数を調整する調整動作をなす周波数調整手段とを含むことを特徴とする。 A clock synchronization circuit according to the present invention receives a transmission packet including data to be processed according to a clock signal via a transmission network, and generates a reception side clock signal synchronized with the transmission side clock signal of the transmission packet. A reception time stamp adding means for adding a reception time stamp that includes time information that changes in synchronization with the reception side clock signal and that indicates a capture timing from the transmission network, to the received packet that is captured from the transmission network A transmission time stamp extracting means for extracting from the received packet a transmission time stamp that includes time information that changes in synchronization with the transmission side clock signal and indicates a supply timing supplied to the transmission network; and the received packet Accumulate a predetermined time length from a series of received packets obtained by arranging them in the order of their transmission time stamps For each of the intervals, the received packet included in this is extracted, and for each of a series of extracted received packets obtained by extraction, the transmission time stamp interval and reception determined between the previous and subsequent extracted received packets are received. A difference accumulated value calculating means for calculating a difference value between the time stamp intervals and accumulating the difference value for each extracted received packet to calculate a difference accumulated value; and a frequency of the received clock signal according to the difference accumulated value And frequency adjusting means for adjusting the frequency.

本発明によるクロック同期方法及び回路によれば、送信側クロック信号と受信側クロック信号との周波数がずれている場合のみならず一致してい場合にも適切な調整がなされて、受信側における出力ジッタが適切に抑制される。 According to the clock synchronization method and circuit of the present invention, an appropriate adjustment is made not only when the frequency of the transmission side clock signal is different from the frequency of the reception side clock signal but also when they coincide with each other. Is appropriately suppressed.

本発明の実施例について添付の図面を参照しつつ詳細に説明する。 Embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図３は、本発明の実施例を示し、伝送システムの全体の構成を示している。伝送システムは、マスター装置１００と、ＩＰ網２００と、スレーブ装置３００から構成される。マスター装置１００からスレーブ装置３００に向けて例えば映像データの如き主データがパケットに乗せられてＩＰ網２００を介して伝送される。マスター装置１００における送信クロック信号すなわちマスタークロック信号とスレーブ装置３００における受信側クロック信号すなわちスレーブクロック信号との同期がなされて、伝送されるパケットに格納される主データが適切にデータ処理される必要がある。 FIG. 3 shows an embodiment of the present invention and shows the overall configuration of the transmission system. The transmission system includes a master device 100, an IP network 200, and a slave device 300. For example, main data such as video data is transmitted in packets from the master device 100 to the slave device 300 via the IP network 200. The transmission clock signal in the master device 100, that is, the master clock signal, and the reception side clock signal in the slave device 300, that is, the slave clock signal, are synchronized, and main data stored in the transmitted packet needs to be appropriately processed. is there.

スレーブ装置３００は、ＩＰ網２００から供給されるパケットに基づいてクロック同期をなすクロック同期回路１０と、ＩＰ網２００から供給されるパケットを受信して、クロック同期回路１０から供給されるクロック信号に従って、該パケットのペイロードとしての主データに対して任意のデータ処理をなす主データ処理部２０とからなる。主データ処理部２０の行うデータ処理としては、例えば、主データとしての映像信号に対する復号伸張処理等のデータ処理が有り得る。 The slave device 300 receives a clock synchronization circuit 10 that performs clock synchronization based on a packet supplied from the IP network 200, and a packet supplied from the IP network 200, and follows a clock signal supplied from the clock synchronization circuit 10. The main data processing unit 20 performs arbitrary data processing on the main data as the payload of the packet. Data processing performed by the main data processing unit 20 may be data processing such as decoding / decompression processing for a video signal as main data, for example.

ＩＰ網２００から到来する受信パケットには、目的となる主データが格納されていると共に、送信側のマスタ装置１００により、パケット生成順に振られるシーケンス番号と、送信時に振られる送信タイムスタンプが設定すなわち打刻されている。送信タイムスタンプの作成方法は、通常、マスター装置１００おいてマスタークロック信号を基に一定の規則で生成する連続した数列であれば良く、通常、マスタークロック信号により駆動される数十ビットのカウンタ出力が用いられる。 In the received packet arriving from the IP network 200, target main data is stored, and a sequence number assigned in the order of packet generation and a transmission time stamp assigned at the time of transmission are set by the master device 100 on the transmission side. It is stamped. The generation method of the transmission time stamp is usually a continuous sequence generated by the master device 100 according to a certain rule based on the master clock signal. Usually, the counter output of several tens of bits driven by the master clock signal is used. Is used.

クロック同期回路１０は、スレーブクロック１１と、受信タイムスタップ生成部１２と、受信タイムスタップ打刻部１３と、送信タイムスタップ抽出部１４と、送受信タイムスタンプ差分算出部１５と、差分蓄積部１６と、調整動作判定部１７と、差分繰越部１８と、利得調整部１９とからなる。 The clock synchronization circuit 10 includes a slave clock 11, a reception time stamp generation unit 12, a reception time stamp stamping unit 13, a transmission time stamp extraction unit 14, a transmission / reception time stamp difference calculation unit 15, and a difference accumulation unit 16. The adjustment operation determination unit 17, the difference carryover unit 18, and the gain adjustment unit 19 are included.

スレーブクロック１１は、利得調整部１９からの制御信号に応じて発振周波数の値が変化するクロック信号を生成し、これを主データ処理部２０に供給する共に、受信タイムスタップ生成部１２に供給する。受信タイムスタップ生成部１２は、スレーブクロック１１から供給されるクロック信号のクロックをカウンタによりカウントすることにより受信タイムスタンプを生成して、これを受信タイムスタップ打刻部１３に供給する。受信タイムスタンプの生成方法は、マスタ装置の送信タイムスタンプの生成方法と同一の方法で生成されるのが好ましいが、マスタ装置と異なる方法で生成しても良い。例えば、スレーブクロック信号の周波数がマスタークロック信号の周波数の逓倍若しくは分周した関係にあっても良い。この場合、受信タイムスタンプの生成において両者の違いを吸収する適切な換算処理が必要となる。 The slave clock 11 generates a clock signal whose oscillation frequency value changes in accordance with a control signal from the gain adjustment unit 19, supplies this to the main data processing unit 20, and supplies it to the reception time strip generation unit 12. . The reception time stamp generation unit 12 generates a reception time stamp by counting the clock of the clock signal supplied from the slave clock 11 by a counter, and supplies this to the reception time stamp stamping unit 13. The generation method of the reception time stamp is preferably generated by the same method as the transmission time stamp generation method of the master device, but may be generated by a method different from that of the master device. For example, the slave clock signal may have a frequency obtained by multiplying or dividing the frequency of the master clock signal. In this case, an appropriate conversion process that absorbs the difference between the two in generating the reception time stamp is required.

受信タイムスタップ打刻部１３は、受信パケットの各々に、受信タイムスタップ生成部１２から供給される受信タイムスタンプを打刻し、打刻された受信パケットを送信タイムスタップ抽出部１４に供給する。送信タイムスタップ抽出部１４は、受信タイムスタップ打刻部１３から供給される受信パケットからシーケンス番号と送信タイムスタンプを抽出し、シーケンス番号に基づいて受信パケットの正しい順序と、受信タイムスタンプ及び送信タイムスタンプとを認識する。パケット間隔算出部１５は、該パケットの順序と受信タイムスタンプ及び送信タイムスタンプとに基づいて、受信タイムスタンプ間隔及び送信タイムスタンプ間隔を受信パケット毎に算出する。すなわち、受信パケットをその送信タイムスタンプの時刻順に並べて得られる一連の受信パケットから所定時間長の累積期間の１つ毎に、これに含まれる受信パケットが抽出され、得られる一連の抽出受信パケットの各々について、その前または後の抽出受信パケットとの間で定まる一対の送信タイムスタンプ間隔と受信タイムスタンプ間隔とが算出される。 The reception time stamp stamping unit 13 stamps each reception packet with the reception time stamp supplied from the reception time stamp generation unit 12 and supplies the stamped reception packet to the transmission time stamp extraction unit 14. The transmission time stamp extraction unit 14 extracts a sequence number and a transmission time stamp from the reception packet supplied from the reception time stamp stamping unit 13, and based on the sequence number, the correct order of the reception packet, the reception time stamp, and the transmission time Recognize stamps. The packet interval calculation unit 15 calculates the reception time stamp interval and the transmission time stamp interval for each received packet based on the order of the packets, the reception time stamp, and the transmission time stamp. That is, for each one of the cumulative periods of a predetermined time length from a series of received packets obtained by arranging the received packets in the order of their transmission time stamps, the received packets included therein are extracted, and a series of extracted received packets obtained For each, a pair of transmission time stamp intervals and reception time stamp intervals determined between before and after the extracted reception packet are calculated.

差分累積部１６は、一対の受信タイムスタンプ間隔と送信タイムスタンプ間隔との差分を受信パケット毎に算出し、これを該累積期間の全体にわたって累積して差分累積値を得る。例えば、送信側におけるマスタークロック信号の周波数を１０ＭＨｚとし、パケットの送信間隔を１０ｍｓｅｃとする。この場合、送信タイムスタンプがマスタークロック信号の単純なカウント数により生成されるとすると、送信タイムスタンプは０、１００００、２００００と振られることになる。そして、受信タイムスタンプは、ジッタのない理想的に条件下では、やはり１００００ずつ増加するはずである。この場合、累積期間を１０ｓｅｃすなわち１００００個のパケットがサンプリングされ得る累積期間とすると、該累積期間にわたって１００００個の差分が求められ、これが累積されて差分累積値が得られる。 The difference accumulating unit 16 calculates the difference between the pair of reception time stamp intervals and the transmission time stamp interval for each received packet, and accumulates the difference over the entire accumulation period to obtain a difference accumulation value. For example, the frequency of the master clock signal on the transmission side is 10 MHz, and the packet transmission interval is 10 msec. In this case, if the transmission time stamp is generated by a simple count number of the master clock signal, the transmission time stamp is set to 0, 10000, and 20000. The reception time stamp should also increase by 10,000 under ideal conditions without jitter. In this case, assuming that the accumulation period is 10 seconds, that is, an accumulation period in which 10,000 packets can be sampled, 10,000 differences are obtained over the accumulation period, and these are accumulated to obtain a difference accumulated value.

調整動作判定部１７は、該累積期間の完了毎に、該累積期間全体にわたって累積された差分累積値と、後述する差分繰越部１８から得られる繰越値を基にして、スレーブクロック信号の調整動作をなすか否かを差分繰越テーブル３０に規定された条件で判定し、調整動作をなすと判定した場合にどの程度の調整をなすかの調整量を算定し、これを利得調整部１９に供給する。差分繰越部１８は、調整動作判定部１７が調整量の算定に加えなかった分の差分累積値を、次回すなわち次の累積期間の調整量の算定に繰り越すために保持する。利得調整部１９は、調整動作判定部１７から得られる調整量に応じて、スレーブクロック１１の周波数を適切に変換せしめるための利得調整を施してスレーブクロック１１の周波数を調整する。調整量は、連続した値のみならず、例えば、調整しない場合を“０”とし、周波数をプラスに調整する場合を“＋１”とし、周波数をマイナスに調整する場合を“−１”とする離散的な数値であっても良い。 The adjustment operation determination unit 17 adjusts the slave clock signal every time the accumulation period is completed, based on the accumulated difference value accumulated over the entire accumulation period and the carry-over value obtained from the difference carry-over unit 18 described later. Is determined under the conditions defined in the differential carry-over table 30, and when it is determined that the adjustment operation is to be performed, an adjustment amount of how much adjustment is performed is calculated and supplied to the gain adjustment unit 19 To do. The difference carry-over unit 18 holds the difference accumulated value that is not added to the adjustment amount calculation by the adjustment operation determination unit 17 in order to carry over to the calculation of the adjustment amount for the next accumulation period. The gain adjustment unit 19 adjusts the frequency of the slave clock 11 by performing gain adjustment for appropriately converting the frequency of the slave clock 11 according to the adjustment amount obtained from the adjustment operation determination unit 17. The adjustment amount is not only a continuous value, but is, for example, discrete when “0” is set when no adjustment is performed, “+1” is set when the frequency is adjusted to plus, and “−1” is set when the frequency is adjusted to minus. It may be a numerical value.

図４は、図３に示された差分繰越テーブル３０の設定例を示している。ここでは、「差分累積値＋繰越値」と、「利得調整分への出力」と、「繰越値」との対応関係が設定されている。「差分累積値＋繰越値」が“｜差分累積値＋繰越値｜＜調整閾値”の場合には、「利得調整分への出力」を“０(調整を行なわない)”とし、「繰越値」を“ 差分累積値＋繰越値”とする。「差分累積値＋繰越値」が“（差分累積値＋繰越値）≧調整閾値”の場合には、「利得調整分への出力」を“１(＋方向に調整)”とし、「繰越値」を“差分累積値＋繰越値−調整閾値”とする。「差分累積値＋繰越値」が“−（差分累積値＋繰越値）≧調整閾値”の場合には、「利得調整分への出力」を“−１(−方向に調整)”とし、「繰越値」を“差分累積値＋繰越値＋調整閾値”とする。本図における差分繰越テーブル３０は、１つの設定例であり、複数の閾値を組み合わせた多様な条件を設定することも可能である。 FIG. 4 shows a setting example of the difference carry-over table 30 shown in FIG. Here, the correspondence relationship between “difference accumulated value + carry-over value”, “output to gain adjustment”, and “carry-over value” is set. When “difference accumulated value + carry-over value” is “| difference accumulated value + carry-over value | <adjustment threshold”, “output to gain adjustment” is set to “0 (no adjustment)” and “carry-over value” "Is" difference accumulated value + carry forward value ". When “difference accumulated value + carry over value” is “(difference accumulated value + carry over value) ≧ adjustment threshold”, “output to gain adjustment” is set to “1 (adjusted in + direction)” and “carry over value” Is “difference accumulated value + carried over value−adjustment threshold”. When “difference accumulated value + carrying value” is “− (difference accumulated value + carrying value) ≧ adjustment threshold”, “output to gain adjustment” is set to “−1 (adjusted in the − direction)”, and “ “Carry forward value” is defined as “difference accumulated value + carry forward value + adjustment threshold”. The difference carry-over table 30 in this figure is one setting example, and various conditions combining a plurality of threshold values can be set.

図５は、本発明によるクロック同期方法及び回路の動作を説明している。前提として、マスタークロック信号の周波数を１０ＭＨｚ、パケット送信間隔を１ｍｓ、累積期間を１００００パケットをサンプリングし得る期間である１０ｓとしている。また、送信タイムスタンプのパケット毎の増分量が１００００であることから、調整閾値を１０μｓのジッタに相当する“１００”としている。 FIG. 5 illustrates the operation of the clock synchronization method and circuit according to the present invention. As a premise, the frequency of the master clock signal is 10 MHz, the packet transmission interval is 1 ms, and the cumulative period is 10 s, which is a period during which 10000 packets can be sampled. Further, since the increment amount of each transmission time stamp for each packet is 10,000, the adjustment threshold is set to “100” corresponding to a jitter of 10 μs.

ここで、シーケンス番号が０〜１００００のパケットにおける送受信タイムスタンプの差分累積値は“−４０”であり且つ差分の繰越値が“０”であることから、差分累積値と繰越値との合計値が“−４０”であり合計値の絶対値が調整閾値未満である。この場合、調整は行われず、差分の繰越値に“−４０”が設定される。シーケンス番号が１００００〜２００００のパケットについては、差分累積値と繰越値の合計値が“−８０”である。この場合も、調整は行われず、差分の繰越値に“−８０”が設定される。次に、シーケンス番号が２００００〜３００００のパケットについては、送受信タイムスタンプの差分累積値が“−４０”であり且つ繰越値が“−８０”であることから合計値が“−１２０”となって、合計値の絶対値が調整閾値以上となっている。この場合は調整が行われ、さらに、調整閾値分の“−１００”が既に周波数調整に有効に働いているものと認められることから残りの端数である“−２０”が繰越値として次回へ繰り越される。 Here, since the accumulated difference value of the transmission / reception time stamps in the packets having the sequence numbers 0 to 10000 is “−40” and the carryover value of the difference is “0”, the total value of the accumulated difference value and the carryover value. Is “−40” and the absolute value of the total value is less than the adjustment threshold. In this case, no adjustment is made, and “−40” is set as the carry over value of the difference. For a packet with a sequence number of 10,000 to 20000, the sum of the difference accumulation value and the carry-over value is “−80”. Also in this case, no adjustment is made, and “−80” is set as the carry over value of the difference. Next, for packets with a sequence number of 20000 to 30000, the accumulated difference value of the transmission / reception time stamp is “−40” and the carry-over value is “−80”, so the total value is “−120”. The absolute value of the total value is equal to or greater than the adjustment threshold value. In this case, adjustment is performed, and further, it is recognized that “−100” corresponding to the adjustment threshold value has already worked effectively for frequency adjustment, so that “−20” which is the remaining fraction is carried over to the next time as a carry-over value. It is.

尚、以上の例では調整閾値を“１００”としたが、かかる条件では１０μｓ程度を超えるジッタの影響を抑制することができないため、１０ｍｓ程度の大きなジッタに対しては、調整閾値を１０００倍にする対応がなされる必要がある。 In the above example, the adjustment threshold is set to “100”. However, under such conditions, the influence of jitter exceeding about 10 μs cannot be suppressed. Therefore, the adjustment threshold is increased 1000 times for large jitter of about 10 ms. There is a need to take action.

以上の実施例において、本発明によるクロック同期方法及び回路を用いることにより、送受信タイムスタンプ差分の平均値で調整を行うことなく、差分累積値を用い且つこれを次の累積期間に繰り越す繰越方法を用いて調整が行われる。平均値を算出して受信側クロック周波数を調整する構成においては、クロック同期回路を実現するレジスタ等のハードウェア上の制約から、平均値の切り上げ、切り下げあるいは丸め誤差に起因して出力ジッタがむしろ拡大する虞がある。本発明による構成においては、累積値をそのまま用いて周波数を調整することから、かかる不都合が回避されている。 In the above embodiment, by using the clock synchronization method and circuit according to the present invention, there is provided a carry-over method that uses a difference accumulated value and carries it over to the next accumulation period without adjusting the average value of the transmission / reception time stamp difference. Adjustments are made. In a configuration that calculates the average value and adjusts the clock frequency on the receiving side, the output jitter is rather increased due to round-off error due to rounding up / down of the average value due to hardware restrictions such as registers that implement the clock synchronization circuit. There is a risk of doing. In the configuration according to the present invention, since the frequency is adjusted using the accumulated value as it is, such inconvenience is avoided.

尚、以上の実施例において、タイムスタンプ及びシーケンス番号を利用してＩＰ網を介したクロック同期方法及び回路が説明されたが、マスター装置からのパケット送信間隔を一定とすることで、送信タイムスタンプ間隔に代えて、該パケット送信間隔と受信タイムスタンプ間隔との差分値を算出することによりクロック同期を実現することも可能である。 In the above embodiment, the clock synchronization method and circuit via the IP network using the time stamp and the sequence number have been described. However, the transmission time stamp can be set by keeping the packet transmission interval from the master device constant. Instead of the interval, clock synchronization can be realized by calculating a difference value between the packet transmission interval and the reception timestamp interval.

従来のマスタ装置及びスレーブ装置の構成を示すブロック図である。It is a block diagram which shows the structure of the conventional master apparatus and a slave apparatus. ＩＰ網上でのパケット到達遅延時間のバラツキを説明する説明図である。It is explanatory drawing explaining the dispersion | variation in the packet arrival delay time on an IP network. 本発明の実施例を示し、伝送システムの全体の構成を示すブロック図である。1 is a block diagram illustrating an overall configuration of a transmission system according to an embodiment of the present invention. 差分繰越テーブルの設定例を示す図である。It is a figure which shows the example of a setting of a difference carry over table. 送受信タイムスタンプ差分累積値の繰越方法を説明する説明図である。It is explanatory drawing explaining the carry-over method of the transmission / reception time stamp difference accumulation value.

Explanation of symbols

１０クロック同期回路
１１スレーブクロック
１２受信タイムスタンプ生成部
１３受信タイムスタンプ打刻部
１４送信タイムスタンプ抽出部
１５スタンプ間隔算出部
１６差分累積部
１７調整動作判定部
１８差分繰越部
１９利得調整部
２０主データ処理部
３０差分繰越テーブル
１００マスター装置
２００ＩＰ網
３００スレーブ装置 DESCRIPTION OF SYMBOLS 10 Clock synchronization circuit 11 Slave clock 12 Reception time stamp production | generation part 13 Reception time stamp stamping part 14 Transmission time stamp extraction part 15 Stamp interval calculation part 16 Difference accumulation part 17 Adjustment operation | movement determination part 18 Difference carryover part 19 Gain adjustment part 20 Main Data processing unit 30 Differential carry-over table 100 Master device 200 IP network 300 Slave device

Claims

A clock synchronization method for synchronizing between a transmission side clock signal and a reception side clock signal in a packet transmission system for transmitting a packet including data to be processed according to a clock signal via a transmission network,
A transmission time stamp adding step for adding to the transmission packet supplied to the transmission network a transmission time stamp that includes time information that changes in synchronization with the transmission side clock signal and indicates the supply timing to the transmission network;
A reception time stamp addition for adding a reception time stamp that includes time information that changes in synchronization with the reception side clock signal and indicates a capture timing from the transmission network to the transmission packet that is captured as a reception packet from the transmission network Steps,
A series of extracted receptions obtained by extracting and extracting the received packets included in each of the accumulated periods of a predetermined time length from the series of received packets obtained by arranging the received packets in the order of the time of the transmission timestamps. For each packet, a difference value between a transmission time stamp interval and a reception time stamp interval determined between the previous and subsequent extracted reception packets is calculated, and this is accumulated for each extracted reception packet. A difference accumulated value calculating step for calculating a value;
A frequency adjustment step of performing an adjustment operation of adjusting the frequency of the reception clock signal according to the difference accumulated value;
Including a clock synchronization method.

The frequency adjustment step is a step of comparing the difference accumulated value with a predetermined adjustment threshold value and performing the adjustment operation only when the difference accumulated value is larger than the adjustment threshold value. The clock synchronization method according to claim 1.

The frequency adjustment step includes a step of adding a value obtained by subtracting the adjustment threshold value from the difference accumulation value to a difference accumulation value in a next accumulation period when the difference accumulation value is larger than the adjustment threshold value. The clock synchronization method according to claim 2.

The frequency adjustment step includes a step of adding the difference accumulation value to a difference accumulation value in a next accumulation period when the difference accumulation value is not larger than the adjustment threshold. Clock synchronization method.

The difference accumulated value calculating step is a step of calculating a difference value between the transmission interval and the reception timestamp time interval instead of the transmission timestamp when the transmission interval of the transmission packet is constant. The clock synchronization method according to claim 1.

A clock synchronization circuit that receives a transmission packet including data to be processed according to a clock signal via a transmission network and generates a reception side clock signal synchronized with a transmission side clock signal of the transmission packet;
A reception time stamp adding means for adding a reception time stamp that includes time information that changes in synchronization with the reception side clock signal and that indicates a capture timing from the transmission network, to the reception packet captured from the transmission network;
A transmission time stamp extraction means for extracting from the received packet a transmission time stamp that includes time information that changes in synchronization with the transmission side clock signal and indicates a supply timing supplied to the transmission network;
A series of extracted receptions obtained by extracting and extracting the received packets included in each of the accumulated periods of a predetermined time length from the series of received packets obtained by arranging the received packets in the order of the time of the transmission timestamps. For each packet, a difference value between a transmission time stamp interval and a reception time stamp interval determined between the previous and subsequent extracted reception packets is calculated, and this is accumulated for each extracted reception packet. Difference accumulated value calculating means for calculating a value;
Frequency adjusting means for performing an adjusting operation of adjusting the frequency of the reception clock signal in accordance with the accumulated difference value;
A clock synchronization circuit comprising: