JP2007305746A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Manufacturing method of semiconductor device and semiconductor device Download PDF

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JP2007305746A
JP2007305746A JP2006131706A JP2006131706A JP2007305746A JP 2007305746 A JP2007305746 A JP 2007305746A JP 2006131706 A JP2006131706 A JP 2006131706A JP 2006131706 A JP2006131706 A JP 2006131706A JP 2007305746 A JP2007305746 A JP 2007305746A
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peripheral circuit
resist layer
layer
lens
circuit portion
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Takeo Yoshida
丈夫 吉田
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Fujifilm Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of protecting a metal wiring unit of a peripheral circuit against damage, when an intralayer lens is formed in a pixel unit. <P>SOLUTION: When the semiconductor device with a semiconductor substrate 10, and a pixel unit 21 with an intralayer lens and a peripheral circuit 11 with a metal wiring unit 13 that are both formed on the semiconductor substrate 10 is manufactured, insulating film 14 are formed at the pixel unit 21 and the peripheral circuit 11 to cover the metal wiring unit 13, a lens material layer 15 for forming the intralayer lens is laminated on the insulating film 14, a resist layer 16 is formed for use in etching the lens material layer 15, and after the resist layer 16 is hardened, and a region in which the resist layer 16 is thicker than the other resist layer 16 in the pixel unit 21 side region is formed on the peripheral circuit 11 of the resist layer 16. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子の製造方法に関し、具体的には画素部に層内レンズを備える半導体素子の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor element, and more specifically to a method for manufacturing a semiconductor element having an inner lens in a pixel portion.

半導体素子としては、例えば、下記特許文献１又は２に記載のようなＣＣＤなどの固体撮像素子が知られている。固体撮像素子は、半導体基板の画素部にフォトダイオードなどの光電変換部と、光電変換部で生じた電荷を転送する電荷転送部とを備え、画素部の表面にはマイクロレンズが形成されている。また、固体撮像素子は、マイクロレンズに集光した光を光電変換部へ確実に受光させて光感度を向上させるために、画素部の層内の所定の膜（例えば、パッシベーション膜）を、光電変換部上の領域がレンズ形状となるように形成された層内レンズとする構成のものがある。   As the semiconductor element, for example, a solid-state imaging element such as a CCD as described in Patent Document 1 or 2 below is known. The solid-state imaging device includes a photoelectric conversion unit such as a photodiode in a pixel portion of a semiconductor substrate, and a charge transfer unit that transfers charges generated in the photoelectric conversion unit, and a microlens is formed on the surface of the pixel unit. . In addition, the solid-state imaging device uses a predetermined film (for example, a passivation film) in the layer of the pixel unit as a photoelectrical film in order to make the photoelectric conversion unit reliably receive the light condensed on the microlens and improve the photosensitivity. There is a configuration in which an intralayer lens is formed so that a region on the conversion unit has a lens shape.

特開２００２−２４６５７８号公報JP 2002-246578 A 特開２００３−７９８８号公報JP 2003-7988 A

ところで、ＣＣＤ等の固体撮像素子の光学層に下凸層内レンズを設ける場合には、下凸層内レンズ層の表面の平坦度を向上させ、若しくは、最上部のマイクロレンズまでの距離を調整するために、エッチバック法を用いて下凸層内レンズの厚さを制御している。このとき、下記のよう不具合が生じることが懸念されている。   By the way, when a lower convex inner lens is provided in the optical layer of a solid-state imaging device such as a CCD, the surface flatness of the lower convex inner lens layer is improved, or the distance to the uppermost microlens is adjusted. In order to achieve this, the thickness of the lower convex in-layer lens is controlled using an etch back method. At this time, there are concerns that the following problems may occur.

図４は、固体撮像素子の製造プロセスの一部を説明するための断面模式図である。図４において、半導体基板１には、金属配線部３が形成された周辺回路部１ａと、図示しない光電変換部と電荷転送電極２が形成された画素部１ｂとが設けられ、画素部１ｂには層内レンズ層５が形成されている。層内レンズ層５は、周辺回路部１ａと画素部１ｂとを含む半導体基板の表面全体に塗布した後、エッチバック法によって所定の厚さとなるように表面処理される。このとき、層内レンズ層５がエッチバック法によって全体的に薄くなる結果、周辺回路部１ａの層内レンズ層５に被服された金属配線部３の上部が露呈してしまい、該金属配線部３に損傷を与えてしまう懸念があった。   FIG. 4 is a schematic cross-sectional view for explaining a part of the manufacturing process of the solid-state imaging device. In FIG. 4, the semiconductor substrate 1 is provided with a peripheral circuit portion 1a in which a metal wiring portion 3 is formed, and a pixel portion 1b in which a photoelectric conversion portion and a charge transfer electrode 2 (not shown) are formed. The inner lens layer 5 is formed. The in-layer lens layer 5 is applied to the entire surface of the semiconductor substrate including the peripheral circuit portion 1a and the pixel portion 1b, and then subjected to surface treatment so as to have a predetermined thickness by an etch back method. At this time, as a result of the inner lens layer 5 being thinned entirely by the etch back method, the upper part of the metal wiring portion 3 covered with the inner lens layer 5 of the peripheral circuit portion 1a is exposed, and the metal wiring portion is exposed. There was a concern that 3 would be damaged.

本発明は、上記事情に鑑みてなされたもので、その目的は、画素部に層内レンズを形成する際に、周辺回路部の金属配線部を損傷することを防止できる半導体素子の製造方法及び半導体素子を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor element capable of preventing damage to a metal wiring portion of a peripheral circuit portion when an intralayer lens is formed in a pixel portion. It is to provide a semiconductor device.

本発明の上記目的は、下記構成によって達成される。
（１）半導体基板と、前記半導体基板上に、層内レンズを有する画素部と金属配線部を有する周辺回路部とを備えた半導体素子の製造方法であって、前記画素部と前記周辺回路部に絶縁膜を形成して前記金属配線部を覆い、前記絶縁膜上に、前記層内レンズを形成するためのレンズ材料層を積層し、前記レンズ材料層をエッチングするためのレジスト層を形成し、前記レジスト層を硬化させた後、前記レジスト層の前記周辺回路部上に、該レジスト層の厚さが前記画素部側の領域より厚い領域を形成することを特徴とする半導体素子の製造方法。
（２）前記レジスト層を硬化させた後で、該レジスト層の前記周辺回路部上の領域に、前記補助レジスト層を積層することを特徴とする上記（１）に記載の半導体素子の製造方法。
（３）前記レジスト層を硬化させた後で、該レジスト層の前記画素部上の領域を現像して前記周辺回路部側の前記レジスト層の厚さより薄くすることを特徴とする上記（１）に記載の半導体素子の製造方法。
（４）半導体基板と、前記半導体基板上に、層内レンズを有する画素部と金属配線部を有する周辺回路部とを備えた半導体素子であって、前記金属配線部を覆うとともに前記画素部と前記周辺回路部に形成された絶縁膜と、前記絶縁膜上に設けられ、前記層内レンズを形成するためのレンズ材料層と、を有し、前記レンズ材料層の、前記周辺回路部上の厚さが前記画素部側の厚さより厚いことを特徴とする半導体素子。 The above object of the present invention is achieved by the following configurations.
(1) A method for manufacturing a semiconductor device, comprising: a semiconductor substrate; a pixel portion having an intra-layer lens; and a peripheral circuit portion having a metal wiring portion on the semiconductor substrate, wherein the pixel portion and the peripheral circuit portion An insulating film is formed to cover the metal wiring portion, a lens material layer for forming the inner lens is laminated on the insulating film, and a resist layer for etching the lens material layer is formed. A method of manufacturing a semiconductor device, comprising: curing a resist layer; and forming a region of the resist layer thicker than a region on the pixel portion side on the peripheral circuit portion of the resist layer. .
(2) The method for manufacturing a semiconductor element according to (1), wherein after the resist layer is cured, the auxiliary resist layer is laminated in a region on the peripheral circuit portion of the resist layer. .
(3) The method according to (1), wherein after the resist layer is cured, a region on the pixel portion of the resist layer is developed to be thinner than the thickness of the resist layer on the peripheral circuit portion side. The manufacturing method of the semiconductor element of description.
(4) A semiconductor element comprising a semiconductor substrate, and a pixel portion having an intra-layer lens and a peripheral circuit portion having a metal wiring portion on the semiconductor substrate, the semiconductor element covering the metal wiring portion and the pixel portion; An insulating film formed on the peripheral circuit portion; and a lens material layer provided on the insulating film for forming the intra-layer lens; and the lens material layer on the peripheral circuit portion A semiconductor element characterized in that the thickness is larger than the thickness on the pixel portion side.

本発明によれば、レンズ材料層を覆うレジスト層が、周辺回路部上の領域を画素部側よりも厚くなるように形成されている。そして、層内レンズを形成する際に、レンズ材料層をエッチバックすると、画素部及び周辺回路部上のレンズ材料層が薄くなるが、周辺回路部上のレジスト層が画素部よりも厚いため、エッチバック後に周辺回路部上に残るレンズ材料層の厚さが、画素部側の厚さよりも厚く残る。このため、周辺回路部においてレンズ材料層の下に形成された金属配線部が露呈してしまうことを防止でき、該金属配線部が損傷することを防止できる。   According to the present invention, the resist layer covering the lens material layer is formed so that the region on the peripheral circuit portion is thicker than the pixel portion side. And when forming the lens in the layer, if the lens material layer is etched back, the lens material layer on the pixel portion and the peripheral circuit portion becomes thin, but the resist layer on the peripheral circuit portion is thicker than the pixel portion, The thickness of the lens material layer remaining on the peripheral circuit portion after the etch back remains thicker than the thickness on the pixel portion side. For this reason, it can prevent that the metal wiring part formed under the lens material layer in the peripheral circuit part is exposed, and can prevent the metal wiring part from being damaged.

本発明によれば、画素部に層内レンズを形成する際に、周辺回路部の金属配線部を損傷することを防止できる半導体素子の製造方法及び半導体素子を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, when forming an intralayer lens in a pixel part, the manufacturing method and semiconductor element of a semiconductor element which can prevent damaging the metal wiring part of a peripheral circuit part can be provided.

以下、本発明の実施形態を図面に基づいて詳しく説明する。
図１，２は、本発明にかかる半導体素子の製造方法の第１実施形態の手順を説明する断面図である。以下の実施形態では、半導体素子として固体撮像素子を例に説明するが、半導体素子は固体撮像素子に限定されず、例えば、ＣＭＯＳ型イメージセンサなどにも適用することができる。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
1 and 2 are cross-sectional views illustrating the procedure of the first embodiment of the method for manufacturing a semiconductor device according to the present invention. In the following embodiments, a solid-state image sensor is described as an example of a semiconductor element. However, the semiconductor element is not limited to a solid-state image sensor, and can be applied to, for example, a CMOS image sensor.

本実施形態の固体撮像素子は、イオンドーピングにより不純物領域が形成されたシリコンなどからなる半導体基板１０を有し、半導体基板１０に、図示しないフォトダイオードなどの光電変換部と、光電変換部で生じた電荷を転送するための電荷転送領域が形成されている。   The solid-state imaging device of this embodiment includes a semiconductor substrate 10 made of silicon or the like in which an impurity region is formed by ion doping, and is generated in the semiconductor substrate 10 by a photoelectric conversion unit such as a photodiode (not shown) and a photoelectric conversion unit. A charge transfer region for transferring the charged charges is formed.

半導体基板には、金属配線部が形成される領域である周辺回路部１１と、画素ごとに光電変換部が形成された画素部２１とを有している。   The semiconductor substrate has a peripheral circuit portion 11 which is a region where a metal wiring portion is formed, and a pixel portion 21 in which a photoelectric conversion portion is formed for each pixel.

半導体基板の表面には、図示しないが、ゲート絶縁膜が形成されている。例えば、ゲート絶縁膜は、酸化膜と窒化膜と酸化膜とを順次に成膜した３層構造とすることができる。   Although not shown, a gate insulating film is formed on the surface of the semiconductor substrate. For example, the gate insulating film can have a three-layer structure in which an oxide film, a nitride film, and an oxide film are sequentially formed.

図１（ａ）に示すように、半導体基板１０の、周辺回路部１１及び画素部２１にポリシリコンなどからなる電荷転送電極１２が形成される。また、周辺回路部１１には、電荷転送電極１２上に図示しない絶縁膜を介してアルミニウムなどからなる金属配線部１３が形成される。   As shown in FIG. 1A, charge transfer electrodes 12 made of polysilicon or the like are formed on the peripheral circuit portion 11 and the pixel portion 21 of the semiconductor substrate 10. In the peripheral circuit portion 11, a metal wiring portion 13 made of aluminum or the like is formed on the charge transfer electrode 12 through an insulating film (not shown).

図１（ｂ）に示すように、周辺回路部１１及び画素部２１上に、ＢＰＳＧ膜など透明な絶縁膜１４を形成、熱処理（リフロー処理）を行うことで、絶縁膜１４の表面をなだらかにする。   As shown in FIG. 1B, a transparent insulating film 14 such as a BPSG film is formed on the peripheral circuit portion 11 and the pixel portion 21, and heat treatment (reflow treatment) is performed, so that the surface of the insulating film 14 is gently formed. To do.

図１（ｃ）に示すように、絶縁膜１４にリフロー処理を行った後、この絶縁膜１４上に層内レンズを形成するためのレンズ材料層１５を積層する。本実施形態では、画素部２１の光電変換部上に層内レンズの下凸形状を有するレンズ部が位置するように構成される。   As shown in FIG. 1C, after a reflow process is performed on the insulating film 14, a lens material layer 15 for forming an intralayer lens is laminated on the insulating film 14. In the present embodiment, the lens unit having a downward convex shape of the in-layer lens is positioned on the photoelectric conversion unit of the pixel unit 21.

図１（ｄ）に示すように、レンズ材料層１５を積層した後、該レンズ材料層１５上にエッチバック用のポジ型のレジスト層１６を塗布する。そして、レジスト層１６にプリベーク処理を行う。   As shown in FIG. 1D, after the lens material layer 15 is laminated, a positive resist layer 16 for etching back is applied on the lens material layer 15. Then, a pre-bake process is performed on the resist layer 16.

プリベーク処理は、レジスト層１６を硬化させる工程であり、具体的には、従来では９０℃〜１１０℃程度であるのに対し、１８０℃〜２３０℃の高温のプリベーク処理を行うことで、レジスト層１６を硬化させる。また、レジスト層１６を硬化させる手段としては、プリベーク処理に限定されず、紫外線照射装置を使用して紫外線エネルギーによりレジスト層１６に含まれる熱効果成分を硬化させてもよい。   The pre-baking process is a step of curing the resist layer 16, and specifically, the resist layer 16 is obtained by performing a high-temperature pre-baking process at 180 ° C. to 230 ° C. compared to the conventional process at about 90 ° C. to 110 ° C. 16 is cured. The means for curing the resist layer 16 is not limited to the pre-bake treatment, and the thermal effect component contained in the resist layer 16 may be cured by ultraviolet energy using an ultraviolet irradiation device.

次に、図２（ａ）及び２（ｂ）に示すように、本実施形態では、硬化したレジスト層１６の、周辺回路部１１上の領域に補助レジスト層１８を積層する。補助レジスト層１８を形成する際には、画素部２１の領域に補助レジスト層１８を形成しないように、フォトリソグラフィ工程においてパターニングされたマスクによって露光し、現像する。このとき、露光装置は、補助レジスト層１８の感光機構に合っていれば、特に限定されない。   Next, as shown in FIGS. 2A and 2B, in this embodiment, an auxiliary resist layer 18 is laminated in a region on the peripheral circuit portion 11 of the cured resist layer 16. When the auxiliary resist layer 18 is formed, exposure and development are performed using a mask patterned in a photolithography process so that the auxiliary resist layer 18 is not formed in the region of the pixel portion 21. At this time, the exposure apparatus is not particularly limited as long as it matches the photosensitive mechanism of the auxiliary resist layer 18.

図２（ｃ）に示すように、レジスト層１６及び補助レジスト層１８を形成した状態で、エッチバック処理を行う。すると、エッチバックによって、周辺回路部１１及び画素部２１を覆うレンズ材料層１５が均一に薄くなるものの、周辺回路部１１ではレジスト層１６の上に更に補助レジスト層１８を形成しているため、周辺回路部１１において、レンズ材料層１５を、画素部２１上のレンズ材料層２１より厚く残すことができ、このとき、金属配線部１３がレンズ材料層１５から露呈してしまうことを防止できる。   As shown in FIG. 2C, an etch back process is performed with the resist layer 16 and the auxiliary resist layer 18 formed. Then, the lens material layer 15 covering the peripheral circuit portion 11 and the pixel portion 21 is uniformly thinned by etch back, but the auxiliary circuit layer 18 is further formed on the resist layer 16 in the peripheral circuit portion 11. In the peripheral circuit portion 11, the lens material layer 15 can be left thicker than the lens material layer 21 on the pixel portion 21. At this time, the metal wiring portion 13 can be prevented from being exposed from the lens material layer 15.

また、本実施形態の製造方法によって得られる固体撮像素子は、レンズ材料層１５の、周辺回路部１１上の厚さが画素部２１側の厚さよりも厚くなるように形成することができる。   Further, the solid-state imaging device obtained by the manufacturing method of the present embodiment can be formed such that the thickness of the lens material layer 15 on the peripheral circuit portion 11 is larger than the thickness on the pixel portion 21 side.

本実施形態の製造方法によれば、レンズ材料層１５を覆うレジスト層１６が、周辺回路部１１上の領域を画素部２１側よりも厚くなるように形成されている。そして、層内レンズを形成する際に、レンズ材料層１５をエッチバックすると、画素部２１及び周辺回路部１１上のレンズ材料層１５が薄くなるが、周辺回路部１１上のレジスト層１６が補充レジスト層１８の分だけ画素部２１よりも厚いため、エッチバック後に周辺回路部１１上に残るレンズ材料層１５の厚さが、画素部２１側の厚さよりも厚く残る。このため、周辺回路部１１においてレンズ材料層１５の下に形成された金属配線部１３が露呈してしまうことを防止でき、該金属配線部１３が損傷することを防止できる。   According to the manufacturing method of the present embodiment, the resist layer 16 covering the lens material layer 15 is formed so that the region on the peripheral circuit unit 11 is thicker than the pixel unit 21 side. When the lens material layer 15 is etched back when forming the inner lens, the lens material layer 15 on the pixel portion 21 and the peripheral circuit portion 11 is thinned, but the resist layer 16 on the peripheral circuit portion 11 is supplemented. Since the resist layer 18 is thicker than the pixel portion 21, the thickness of the lens material layer 15 remaining on the peripheral circuit portion 11 after the etch back remains thicker than the thickness on the pixel portion 21 side. For this reason, it can prevent that the metal wiring part 13 formed under the lens material layer 15 in the peripheral circuit part 11 is exposed, and can prevent this metal wiring part 13 from being damaged.

本実施形態では、レジスト層１６の、周辺回路部１１上の領域に更に補助レジスト層１８を積層する工程を行ったが、実質的に、レジスト層の周辺回路部１１上に、該レジスト層の厚さを画素部２１より厚くすることができれば、以下の実施形態に説明するように他の手段を用いてもよい。   In the present embodiment, the step of further laminating the auxiliary resist layer 18 in the region of the resist layer 16 on the peripheral circuit portion 11 is performed, but the resist layer 16 is substantially formed on the peripheral circuit portion 11 of the resist layer. As long as the thickness can be made larger than that of the pixel portion 21, other means may be used as described in the following embodiments.

次に、本発明にかかる第２実施形態を説明する。なお、以下に説明する実施形態において、すでに説明した部材などと同等な構成・作用を有する部材等については、図中に同一符号又は相当符号を付すことにより、説明を簡略化或いは省略する。   Next, a second embodiment according to the present invention will be described. In the embodiments described below, members having the same configuration / action as those already described are denoted by the same or corresponding reference numerals in the drawings, and description thereof is simplified or omitted.

図３は、本発明にかかる半導体素子の製造方法の第２実施形態の手順を説明する断面図である。本実施形態において、半導体基板１０の、周辺回路部１１及び画素部２１の上に絶縁膜１４と、レンズ材料層１５とを形成する手順は、上記実施形態と同じであるため、説明を省略する。   FIG. 3 is a cross-sectional view for explaining the procedure of the second embodiment of the semiconductor device manufacturing method according to the present invention. In this embodiment, the procedure for forming the insulating film 14 and the lens material layer 15 on the peripheral circuit portion 11 and the pixel portion 21 of the semiconductor substrate 10 is the same as that in the above embodiment, and thus the description thereof is omitted. .

図３（ａ）に示すように、レンズ材料層１５の上に、８００ｎｍ〜２４００ｎｍの厚さで、レンズ材料層１５をエッチバックするためのポジ型のレジスト層２７を形成する。なお、従来の塗布されるレジスト層の厚さは、４００〜１２００ｎｍである。ここで、フォトレジストはｉ線露光又はｇ線露光に対応する材料とする。   As shown in FIG. 3A, a positive resist layer 27 for etching back the lens material layer 15 is formed on the lens material layer 15 with a thickness of 800 nm to 2400 nm. In addition, the thickness of the conventionally applied resist layer is 400 to 1200 nm. Here, the photoresist is a material corresponding to i-line exposure or g-line exposure.

次に、レジスト層２７にプリベーク処理を行い、硬化させる。プリベーク処理は、上記実施形態と同様に行うことができ、具体的には、従来では９０℃〜１１０℃程度であるのに対し、１８０℃〜２３０℃の高温のプリベーク処理を行うことで、レジスト層２７を硬化させる。   Next, the resist layer 27 is pre-baked and cured. The pre-baking process can be performed in the same manner as in the above-described embodiment. Specifically, the pre-baking process is performed at a high temperature of 180 ° C. to 230 ° C., whereas the conventional resist baking process is performed at about 90 ° C. to 110 ° C. Layer 27 is cured.

本実施形態では、図３（ｂ）に示すように、レジスト層２７の、画素部２１上における領域２７ｂを露光領域とするフォトマスクを用いて、この画素部２１上の領域２７ｂのみを露光し、ＰＥＢ（露光後のベーク処理）、現像処理を行う。露光光源は、ｉ線又はｇ線であり、露光エネルギーは、Eth（現像液に溶解するフォトレジスト残膜がちょうど０となる露光エネルギー）未満に設定する。このように、露光エネルギーをEth未満とすることで、現像後にレジスト層２７の残膜の厚さを調整することができる。一般に、Eth以下の現像速度、とりわけ現像開始直後の現像速度は速く、制御することが困難であるが、プリベーク温度は通常より高い温度に制御し、また、ＰＥＢ温度は通常より低い温度に制御することで、現像液溶解速度を著しく低下させ、制御性を向上させることができる。なお、露光する領域のパターンは、厳密である必要がなく、ラフなものでもよいため、障害とはならない。また、現像液は、任意の濃度のＴＭＡＨ水溶液を使用し、現像時間を３０〜９０秒とする。   In the present embodiment, as shown in FIG. 3B, only the region 27b on the pixel portion 21 is exposed using a photomask having the region 27b on the pixel portion 21 of the resist layer 27 as an exposure region. , PEB (baking after exposure) and development. The exposure light source is i-line or g-line, and the exposure energy is set to less than Eth (exposure energy at which the photoresist remaining film dissolved in the developer is exactly 0). Thus, by setting the exposure energy to less than Eth, the thickness of the remaining film of the resist layer 27 can be adjusted after development. In general, the development speed below Eth, especially the development speed immediately after the start of development is fast and difficult to control, but the pre-baking temperature is controlled to a higher temperature than usual, and the PEB temperature is controlled to a lower temperature than usual. As a result, the dissolution rate of the developer can be remarkably reduced and the controllability can be improved. Note that the pattern of the area to be exposed does not need to be strict and may be rough so that it does not become an obstacle. Further, as the developer, an aqueous TMAH solution having an arbitrary concentration is used, and the development time is set to 30 to 90 seconds.

このように、現像処理されたレジスト層２７は、周辺回路部１１上の領域２７ａが、画素部２１上の領域２７ｂより厚く残されるため、エッチバックからの保護に十分な厚さを保ちつつ、画素部２１はエッチバック材として必要な所望のレジスト厚みとすることができる。このため、図３（ｃ）に示すように、周辺回路部１１の金属配線部１３がレンズ材料層１５から露呈することを防止することができる。   As described above, the developed resist layer 27 has a region 27a on the peripheral circuit portion 11 that is thicker than the region 27b on the pixel portion 21, so that the resist layer 27 has a sufficient thickness for protection from etch back. The pixel portion 21 can have a desired resist thickness necessary as an etchback material. For this reason, as shown in FIG. 3C, it is possible to prevent the metal wiring portion 13 of the peripheral circuit portion 11 from being exposed from the lens material layer 15.

本発明の半導体素子の製造方法によれば、画素部と周辺回路部との設計上の理由による工程の相違にかかわらず、周辺回路部に影響を及ぼすことなく画素部にエッチバックを行うことができる。   According to the method for manufacturing a semiconductor device of the present invention, it is possible to etch back a pixel portion without affecting the peripheral circuit portion, regardless of the difference in process due to design reasons between the pixel portion and the peripheral circuit portion. it can.

なお、本発明は、前述した実施形態に限定されるものではなく、適宜な変形、改良などが可能である。
例えば、上記実施形態のような下凸型の層内レンズの形成プロセスに限定されず、エッチバックのプロセスを用いてて周辺回路部の保護を必要とする構成の半導体素子に応用することができる。 In addition, this invention is not limited to embodiment mentioned above, A suitable deformation | transformation, improvement, etc. are possible.
For example, the present invention is not limited to the process of forming a downward convex in-layer lens as in the above embodiment, and can be applied to a semiconductor element having a configuration that requires protection of the peripheral circuit portion using an etch back process. .

本発明にかかる半導体素子の製造方法の第１実施形態の手順を説明する断面図である。It is sectional drawing explaining the procedure of 1st Embodiment of the manufacturing method of the semiconductor element concerning this invention. 半導体素子の製造方法の第１実施形態の手順を説明するための断面図である。It is sectional drawing for demonstrating the procedure of 1st Embodiment of the manufacturing method of a semiconductor element. 半導体素子の製造方法の第２実施形態の手順を説明する断面図である。It is sectional drawing explaining the procedure of 2nd Embodiment of the manufacturing method of a semiconductor element. 固体撮像素子の製造プロセスの一部を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating a part of manufacturing process of a solid-state image sensor.

符号の説明Explanation of symbols

１０ 半導体基板
１１ 周辺回路部
１３ 金属配線部
１５ レンズ材料層
１６，２７ （エッチバック用の）レジスト層
２１ 画素部 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Peripheral circuit part 13 Metal wiring part 15 Lens material layer 16, 27 Resist layer 21 (for etch back) Pixel part

Claims (4)

半導体基板と、前記半導体基板上に、層内レンズを有する画素部と金属配線部を有する周辺回路部とを備えた半導体素子の製造方法であって、
前記画素部と前記周辺回路部に絶縁膜を形成して前記金属配線部を覆い、前記絶縁膜上に、前記層内レンズを形成するためのレンズ材料層を積層し、前記レンズ材料層をエッチングするためのレジスト層を形成し、前記レジスト層を硬化させた後、前記レジスト層の前記周辺回路部上に、該レジスト層の厚さが前記画素部側の領域より厚い領域を形成することを特徴とする半導体素子の製造方法。 A method of manufacturing a semiconductor device comprising a semiconductor substrate, and a pixel portion having an inner lens and a peripheral circuit portion having a metal wiring portion on the semiconductor substrate,
An insulating film is formed on the pixel portion and the peripheral circuit portion to cover the metal wiring portion, a lens material layer for forming the intra-layer lens is laminated on the insulating film, and the lens material layer is etched. Forming a resist layer for curing, and curing the resist layer, and then forming a region where the thickness of the resist layer is thicker than the region on the pixel portion side on the peripheral circuit portion of the resist layer. A method for manufacturing a semiconductor device. 前記レジスト層を硬化させた後で、該レジスト層の前記周辺回路部上の領域に、前記補助レジスト層を積層することを特徴とする請求項１に記載の半導体素子の製造方法。   2. The method of manufacturing a semiconductor element according to claim 1, wherein after the resist layer is cured, the auxiliary resist layer is laminated in a region on the peripheral circuit portion of the resist layer. 前記レジスト層を硬化させた後で、該レジスト層の前記画素部上の領域を現像して前記周辺回路部側の前記レジスト層の厚さより薄くすることを特徴とする請求項１に記載の半導体素子の製造方法。   2. The semiconductor according to claim 1, wherein after the resist layer is cured, a region on the pixel portion of the resist layer is developed so as to be thinner than the thickness of the resist layer on the peripheral circuit portion side. Device manufacturing method. 半導体基板と、前記半導体基板上に、層内レンズを有する画素部と金属配線部を有する周辺回路部とを備えた半導体素子であって、
前記金属配線部を覆うとともに前記画素部と前記周辺回路部に形成された絶縁膜と、
前記絶縁膜上に設けられ、前記層内レンズを形成するためのレンズ材料層と、を有し、
前記レンズ材料層の、前記周辺回路部上の厚さが前記画素部側の厚さより厚いことを特徴とする半導体素子。 A semiconductor element comprising a semiconductor substrate, and a pixel portion having an inner lens and a peripheral circuit portion having a metal wiring portion on the semiconductor substrate,
An insulating film covering the metal wiring portion and formed in the pixel portion and the peripheral circuit portion;
A lens material layer provided on the insulating film for forming the in-layer lens;
A semiconductor element, wherein a thickness of the lens material layer on the peripheral circuit portion is larger than a thickness on the pixel portion side.
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