JP2007303859A - Test selection circuit, and semiconductor device equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably monitor a desired signal. <P>SOLUTION: This test selection circuit 10 is integrated in a semiconductor integrated circuit, and selects one out of a plurality of digital signals appearing in its inside, to be output to an outside via a test output terminal 114, when testing the semiconductor integrated circuit. A selection register 12 includes a plurality of flip-flop circuits FF1-FF7 capable of invalidating a reset function. A control circuit 16 outputs a control data Dcnt in response to a control signal Scnt from the outside, to each of data terminals in the flip-flop circuits FF1-FF7. A selector circuit 14 selects one digital signal correlated with a logic level of a selection signal Ssel, out of the digital signals SIG1-SIGn. The reset function for the flip-flop circuits FF1-FF7 is invalidated at least in a usual test. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a test circuit integrated in a semiconductor integrated circuit, and more particularly to a test select circuit that selects one of a plurality of digital signals inside a circuit and outputs the selected signal outside the circuit during a test.

  Various electronic devices such as cellular phones, PDAs (Personal Digital Assistants), and notebook personal computers in recent years include power supply circuits, CPUs (Central Processing Units) that perform digital signal processing, DSPs (Digital Signal Processors), and other analogs. Many electronic circuits such as digital circuits are installed. In such an electronic circuit, in order to inspect whether the circuit operates normally, some signals are monitored from the outside in the inspection process. When a pad is provided for each signal to be monitored in order to monitor a signal, there is a problem that the circuit area increases as the number of signals increases.

Here, as a method for reducing the number of pads for inspection, a technique for selecting one of a plurality of signals and outputting a circuit from one pad (hereinafter referred to as a test select circuit) in an integrated circuit is examined. To do. When the test select circuit is provided, it is necessary to provide a control signal from the outside in order to select which of a plurality of signals is to be monitored. This control signal is generally written in a register provided in the integrated circuit.
JP 2004-022947 A

  As a result of studying such a test select circuit, the present inventor has recognized the following problems. Generally, a register is configured using a flip-flop. Here, if a flip-flop is reset while a certain signal is being monitored, there is a problem that the signal selected by the test select circuit is switched.

  The present invention has been made in view of such a problem, and an object thereof is to provide a test select circuit capable of stably monitoring a desired signal.

  One embodiment of the present invention is a test integrated with a semiconductor integrated circuit and selecting one of a plurality of digital signals appearing inside the semiconductor integrated circuit and outputting the selected signal to the outside of the semiconductor integrated circuit when testing the semiconductor integrated circuit. The present invention relates to a select circuit. The test select circuit includes a selection register including a plurality of flip-flop circuits, a control circuit that outputs control data corresponding to an external control signal to each of data terminals of the plurality of flip-flop circuits, a plurality of digital signals, and A selector circuit that receives selection signals output from a plurality of flip-flop circuits, and selects and outputs one digital signal associated with the logic level of the selection signal from the plurality of digital signals. The reset function of the plurality of flip-flop circuits included in the selection register is configured to be invalidated.

  According to this aspect, the flip-flop circuit is prevented from being reset while a certain digital signal is being output to the outside by disabling the reset function of the flip-flop circuit during a test such as an inspection process. Thus, unnecessary switching of the selection signal can be prevented and a desired signal can be monitored stably.

In one aspect, each of the plurality of flip-flop circuits includes a reset terminal, and the selection register fixes the logic level of the reset terminal of the plurality of flip-flops in a normal test mode for testing the function of the semiconductor integrated circuit. In a scan test mode for testing whether a logic gate group including a plurality of flip-flop circuits functions normally, a reset selector circuit that outputs a high-level or low-level logic signal to a reset terminal of the plurality of flip-flops May further be included.
According to this aspect, since the level of the reset terminal is fixed in the normal test mode, unnecessary switching of the selection signal can be prevented, and in the scan test mode, the flip-flop is flipped by the high level and low level logic signals. The circuit can be tested.

  In one embodiment, the reset selector circuit has a signal with a fixed logic level input to the first input terminal, and a high-level or low-level scan reset signal input to the second input terminal. A signal at the first input terminal or the second input terminal may be output to the reset terminals of the plurality of flip-flops according to the mode select signal for switching the scan test mode.

  In one embodiment, a plurality of flip-flop circuits may be configured without a reset terminal. In this case, since the number of gates included in the flip-flop circuit can be reduced, the circuit area can be reduced.

  In one embodiment, the plurality of digital signals are output signals of a low-voltage malfunction prevention circuit built in the semiconductor integrated circuit, and the low voltage indicating a low voltage state in which the power supply voltage supplied to the semiconductor integrated circuit is lower than a predetermined value A signal related to the detection signal may be included.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  The test select circuit according to the present invention can monitor a desired signal stably.

  Hereinafter, a test select circuit according to an embodiment of the present invention will be described with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate.

  FIG. 1 is a circuit diagram showing a configuration of a test select circuit 10 according to the embodiment. FIG. 2 is a block diagram of a power supply circuit 100 in which the test select circuit 10 of FIG. 1 is preferably used, and an entire electronic device 1000 including the power supply circuit 100. First, the overall configuration of the electronic device 1000 will be described with reference to FIG. The electronic device 1000 is a battery-driven information terminal device such as a mobile phone terminal, PDA, or notebook PC. The electronic device 1000 includes a power supply circuit 100, a battery 200, and a CPU 300.

  The CPU 300 is a processor that controls the entire electronic device 1000 and executes various arithmetic processes, and is driven by power supply voltages Vdd1 to Vdd3 supplied by the power supply circuit 100. Hereinafter, the power supply voltages Vdd1 to Vdd3 are also simply referred to as power supply voltage Vdd. The CPU 300 is configured to operate with different power supply voltages for each circuit block for high-efficiency operation, and is configured to be able to individually turn on and off the power supply. For example, the power supply voltages Vdd1 to Vdd3 are supplied to the core block, the memory block, and the input / output (I / O) block, respectively. Further, the CPU 300 receives a reset signal RST from the power supply circuit 100. The reset signal RST is a signal for notifying that the supply of the power supply voltage Vdd is completed from the power supply circuit 100 to the CPU 300 or a low voltage state.

  Actually, the load driven by the power supply circuit 100 is not limited to the CPU 300, but other DSPs or light emitting diodes may be driven instead of or in addition to this.

  The battery 200 is a secondary battery such as a Li ion battery, and outputs a battery voltage Vbat of about 2V to 4.2V. The battery voltage Vbat decreases with power consumption and increases with charging.

  The power supply circuit 100 includes a battery terminal 102, a reset terminal 104, power supply terminals 106, 108, and 110, and an AC terminal 112 as input / output terminals. A battery 200 is connected to the battery terminal 102. The reset terminal 104 and the power supply terminals 106, 108 and 110 are all connected to the CPU 300. The AC terminal 112 is connected to an external power supply circuit. The external power supply circuit is, for example, a so-called AC adapter that converts a commercial AC voltage into a DC voltage.

  The power supply voltage Vdd supplied to the CPU 300 needs to be stabilized at a predetermined voltage of 2 V or less. On the other hand, the battery voltage Vbat of the battery 200 is about 2V to 4.2V. Therefore, the power supply circuit 100 steps down the battery voltage Vbat supplied from the battery 200, stabilizes it to a constant value independent of the value of the battery voltage Vbat, and supplies it to the CPU 300.

  The power supply circuit 100 includes a test select circuit 10 in addition to the first regulator circuit 30, the second regulator circuit 32, the third regulator circuit 34, the charging circuit 40, and the UVLO circuit 50. The DC voltage Vdc is supplied to the charging circuit 40 when an AC adapter is connected to the AC terminal 112. At this time, the charging circuit 40 supplies a charging current to the battery 200 to charge the battery 200 to about 4.2V.

  The battery voltage Vbat is supplied to the first regulator circuit 30, the second regulator circuit 32, and the third regulator circuit 34 via the battery terminal 102. The first regulator circuit 30, the second regulator circuit 32, and the third regulator circuit 34 are linear regulators, respectively, step down the battery voltage Vbat and output stabilized power supply voltages Vdd1 to Vdd3, and power supply terminals It outputs to CPU300 via 106,108,110.

  The UVLO circuit 50 receives a battery voltage Vbat as an input voltage, and also receives a power-on signal (hereinafter also referred to as a start signal) PWR_ON whose level varies depending on the on / off state of the power key of the electronic device 1000. Has been. Since the power-on signal PWR_ON is a signal for instructing activation of the electronic device 1000, it is also referred to as an activation signal hereinafter.

  The UVLO circuit 50 monitors the battery voltage Vbat and determines whether or not the monitored battery voltage Vbat satisfies a predetermined condition. Specifically, the battery voltage Vbat is compared with a predetermined threshold voltage Vth, Vbat <Vth is determined as a low voltage state, and Vbat> Vth is determined as a non-low voltage state. The UVLO circuit 50 executes a predetermined sequence when the activation signal PWR_ON becomes a high level in the non-low voltage state. In the present embodiment, the UVLO circuit 50 sequentially turns the first regulator circuit 30, the second regulator circuit 32, and the third regulator circuit 34 when the battery voltage Vbat is higher than a predetermined threshold voltage Vth. When the activation is completed, a reset signal RST is output to the CPU 300.

  The UVLO circuit 50 outputs the first sequence signal SEQ1, the second sequence signal SEQ2, and the third sequence signal SEQ3 to the first regulator circuit 30, the second regulator circuit 32, and the third regulator circuit 34, respectively. When the UVLO circuit 50 is ready to start, the first sequence signal SEQ1 to the third sequence signal SEQ3 are sequentially switched to a high level. When the high-level sequence signals SEQ1 to SEQ3 are input, the first regulator circuit 30 to the third regulator circuit 34 start a stabilizing operation and output power supply voltages Vdd1 to Vdd3.

  The test select circuit 10 selects one of a plurality of digital signals appearing inside the power supply circuit 100 and outputs it outside the semiconductor integrated circuit when testing the power supply circuit 100 that is a semiconductor integrated circuit. In the present embodiment, sequence signals SEQ1 to SEQ3, a reset signal RST, and other digital signals (not shown) output from the test select circuit 10 are input to the test select circuit 10. The test select circuit 10 selects an externally designated signal from the input signals and outputs a test signal Test from the test output terminal 114. By providing the test select circuit 10, a plurality of signals in the power supply circuit 100 can be monitored without providing a pad for each signal. Note that the test select circuit 10 is in a non-operating state during a normal operation in which the power supply circuit 100 supplies the power supply voltage to the CPU 300.

Hereinafter, returning to FIG. 1, the configuration and operation of the test select circuit 10 according to the embodiment will be described in detail.
As described above, the test select circuit 10 selects any one of the plurality of digital signals SIG1 to SIGn and outputs the selected signal from the test output terminal 114. The test select circuit 10 includes a selection register 12, a selector circuit 14, and a control circuit 16. The selection register 12 includes a plurality of flip-flop circuits FF1 to FF7, and functions as a memory that holds a selection signal Ssel that indicates which digital signal to select and output during testing. Although seven flip-flop circuits are illustrated in the embodiment, the number of flip-flop circuits may be determined according to the number of digital signals SIG input to the test select circuit 10. For example, when seven flip-flop circuits are provided, one signal can be selected and output from 7 bits = 128 digital signals SIG1 to SIG128.

A control signal Scnt is input to the control circuit 16 from the outside during the test. The control circuit 16 is connected to an external tester or CPU via an I ² C bus or the like, and decodes the input control signal Scnt. The control circuit 16 outputs control data Dcnt1 to Dcnt7 corresponding to the control signal Scnt to the data terminals of the flip-flop circuits FF1 to FF7 included in the selection register 12, respectively. In the present embodiment, the control data Dcnt is a 7-bit digital signal.

  A plurality of digital signals SIG1, SIG2, SIG3,..., SIGn are input to the selector circuit. The plurality of digital signals SIG are, for example, output signals of the UVLO circuit 50 incorporated in the semiconductor integrated circuit, and a low voltage detection signal indicating a low voltage state in which the power supply voltage Vdd supplied to the semiconductor integrated circuit is lower than a predetermined value. Contains signals related to. “Related signal” refers to an output signal of a comparator that compares the battery voltage Vbat and the threshold voltage Vth, a delayed signal, or a signal obtained by logical operation of these signals and other digital signals. Say. For example, signals related to the low voltage detection signal are the sequence signals SEQ1 to SEQ3 and the reset signal RST output from the test select circuit 10 of FIG.

  Further, the selector circuit 14 is supplied with the selection signal Ssel output from the plurality of flip-flop circuits FF1 to FF7, and one of the plurality of digital signals SIG1 to SIGn is associated with the logic level of the selection signal Ssel. Select and output the digital signal.

  In the present embodiment, the plurality of flip-flop circuits FF1 to FF7 included in the selection register 12 are configured to be able to invalidate the reset function. FIG. 3 is a circuit diagram showing a configuration of the selection register 12. The selection register 12 includes a reset selector circuit 22 and a plurality of flip-flop circuits FF1 to FF7. The flip-flop circuits FF1 to FF7 each have a reset terminal. The reset selector circuit 22 fixes the logic levels of the reset terminals of the plurality of flip-flop circuits FF1 to FF7 in the normal test mode for testing the function of the power supply circuit 100 that is a semiconductor integrated circuit. In addition, the selection register 12 is connected to reset terminals of the plurality of flip-flop circuits FF1 to FF7 in the scan test mode for testing whether the logic gate group 20 including the plurality of flip-flop circuits FF1 to FF7 functions normally. A scan reset signal SRST, which is a high level or low level logic signal, is output.

  In the reset selector circuit 22, a signal whose logic level is fixed to a high level is input to the first input terminal IN1, and a scan reset signal SRST that takes either a high level or a low level is input to the second input terminal IN2. Is entered. Further, the mode selector signal MODE for switching between the normal test mode and the scan test mode is input to the reset selector circuit 22. The reset selector circuit 22 outputs a signal input to the first input terminal IN1 or the second input terminal IN2 to the reset terminals of the plurality of flip-flop circuits FF1 to FF7 in accordance with the mode select signal MODE.

The operation of the test select circuit 10 configured as described above will be described.
When a control signal Scnt is input to the control circuit 16 from the outside during a normal test, the control data Dcnt1 to Dcnt7 are held in the flip-flop circuits FF1 to FF7, respectively. One of the digital signals SIG1 to SIGn input to the selector circuit 14 is selected by the selection signal Ssel which is the output of the flip-flop circuits FF1 to FF7, and is output from the test output terminal 114.

  For example, it is assumed that the digital signal SIG1 is the sequence signal SEQ1 output from the UVLO circuit 50 and the digital signal SIG1 is selected by the control signal Scnt. At this time, if the voltage input to the battery terminal 102 is changed, after exceeding the threshold voltage Vth, the sequence signal SEQ1 becomes high level, and the test signal Test output from the test output terminal 114 also becomes high level. When another signal, for example, the second sequence signal SEQ2 is monitored, the digital signal SIG2 may be selected by the control signal Scnt.

  In the present embodiment, during a normal test, the level of the signal input to the reset terminals of the flip-flop circuits FF1 to FF2 is fixed and the reset function is invalidated, so a certain digital signal SIG is monitored. During the process, the selection signal Ssel can be prevented from changing. As a result, the signal output from the test output terminal 114 can be prevented from being switched to another signal, and the desired digital signal SIG can be monitored stably.

  If the signal at the reset terminal of the flip-flop circuits FF1 to FF7 is not fixed during the normal test, and the voltage at the reset terminal fluctuates for some reason, the signal output from the test output terminal 114 is changed to another signal. Switching causes a problem that the test becomes impossible, but this problem can be solved by using the test select circuit 10 according to the present embodiment.

  Further, when a reset signal can be input to the reset terminals of the flip-flop circuits FF1 to FF7 from the outside of the power supply circuit 100 that is a semiconductor integrated circuit, it is necessary to separately provide a pad for inputting the reset signal. However, in this embodiment, it is not necessary to provide such a pad separately, so that the circuit area can be reduced.

  Next, the operation in the scan test mode will be described. The scan test is one of the tests executed in a general digital circuit, and a scan chain is constituted by flip-flop circuits inside the circuit and tests whether each flip-flop circuit functions normally. . In such a scan test, the flip-flop circuit included in the logic gate group 20 to be tested must be resettable from the outside.

  In the test select circuit 10 according to the present embodiment, the level of the signal at the reset terminal of the flip-flop circuits FF1 to FF7 can be switched in the scan test mode. As a result, a scan test including the flip-flop circuits FF1 to FF7 of the selection register 12 can be executed.

  Although the present invention has been described above based on the embodiments, it should be understood that the embodiments merely illustrate the principles and applications of the present invention, and the embodiments are within the scope of the claims. Needless to say, many modifications and arrangements can be made without departing from the concept of the present invention.

  In the embodiment, the case where the reset terminal is provided in the flip-flop circuits FF1 to FF7 of the selection register 12 has been described, but the present invention is not limited to this. For example, the plurality of flip-flop circuits FF1 to FF7 may be configured without a reset terminal. In this case, since the number of gates included in the plurality of flip-flop circuits FF1 to FF7 can be reduced, the circuit area can be reduced.

  Although the case where the test select circuit 10 is built in the power supply circuit 100 has been described in the embodiment, the present invention is not limited to this and can be used for many semiconductor devices including digital circuits.

  In the present embodiment, the setting of the logical values of the high level and the low level is an example, and can be freely changed by appropriately inverting it with an inverter or the like.

It is a circuit diagram which shows the structure of the test select circuit based on Embodiment. It is a block diagram of the whole power supply circuit and electronic device in which the test selection circuit of FIG. 1 is used suitably. It is a circuit diagram which shows the structure of a selection register.

Explanation of symbols

  10 test select circuit, 12 selection register, 14 selector circuit, 16 control circuit, 20 logic gate group, 22 reset selector circuit, FF flip-flop circuit.

Claims (6)

A test select circuit that is integrated in a semiconductor integrated circuit and selects one of a plurality of digital signals appearing inside the semiconductor integrated circuit and outputs the selected signal to the outside of the semiconductor integrated circuit when testing the semiconductor integrated circuit. And
A selection register including a plurality of flip-flop circuits;
A control circuit that outputs control data in accordance with an external control signal to each of the data terminals of the plurality of flip-flop circuits;
The plurality of digital signals and the selection signals output from the plurality of flip-flop circuits are input, and one digital signal associated with the logic level of the selection signal is selected from the plurality of digital signals. A selector circuit to output,
With
A test select circuit characterized in that a reset function of the plurality of flip-flop circuits can be invalidated. Each of the plurality of flip-flop circuits includes a reset terminal,
The selection register is
In a normal test mode for testing the function of the semiconductor integrated circuit, the logic levels of the reset terminals of the plurality of flip-flops are fixed, and the logic gate group including the plurality of flip-flop circuits is tested to function normally. 2. The test select circuit according to claim 1, further comprising a reset selector circuit that outputs a high level or low level logic signal to a reset terminal of the plurality of flip-flops in a scan test mode. The reset selector circuit includes:
A mode in which a signal having a fixed logic level is input to the first input terminal, and a high-level or low-level scan reset signal is input to the second input terminal, and the normal test mode and the scan test mode are switched. 3. The test select circuit according to claim 2, wherein a signal of the first input terminal or the second input terminal is output to a reset terminal of the plurality of flip-flops according to a select signal.   2. The test select circuit according to claim 1, wherein the plurality of flip-flop circuits are configured not to have a reset terminal. The plurality of digital signals appearing inside the semiconductor integrated circuit are:
An output signal of a low-voltage malfunction prevention circuit built in the semiconductor integrated circuit, the signal including a signal related to a low-voltage detection signal indicating a low-voltage state in which a power supply voltage supplied to the semiconductor integrated circuit is lower than a predetermined value The test select circuit according to claim 1, wherein:   A semiconductor device comprising the test select circuit according to claim 1.

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