JP2007299044A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve low power consumption in a semiconductor integrated circuit device, by suppressing unnecessary startup of a memory. <P>SOLUTION: For instance, a memory startup control block CTRL1 is provided between a memory block MEM1 invariant in access latency represented by an SRAM or the like and an arithmetic block IP1. The memory startup control block CTRL1 interprets an address signal ADDR11 and an instruction signal CMD11 input from the arithmetic block IP1, and when a readout instruction is issued successively two times or more for a same memory address, stops a memory starting signal CLK12 to the memory block MEM1. The arithmetic block IP1, for the readout instruction issued at the second time or later, receives readout data of the first time held in the memory block MEM1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and is particularly useful when applied to a semiconductor integrated circuit device such as a system LSI for portable equipment.

As a technology to improve the data transfer speed between the arithmetic circuit and the memory, for example, for memory with variable access latency, the activation of the memory is controlled in cooperation with the arithmetic circuit side, and read commands to the same address continue In addition, a technique for shortening the access latency after the second time is known (see, for example, Patent Document 1 and Patent Document 2).
Japanese Unexamined Patent Publication No. 57-10853 Japanese Patent Laid-Open No. 11-184751

  In recent years, SoCs (System-on-a-Chip) including system LSIs for mobile phones have become increasingly functional because integration of IP (Intelligent Property) has become easier. For this reason, a CPU core and a memory are mainly mounted as IP on the conventional SoC. However, many accelerators are now mounted in addition to the CPU and the memory. Each accelerator is equipped with a large-capacity memory for advanced processing of large-scale data.

  A typical process performed by such an accelerator is video and audio compression and expansion processing. A feature of this process is that the same data (memory data at the same address) is referred to a plurality of times. For example, in the video expansion process, the frame data between the previous and next frame data is complemented, or the next frame data is predicted from the current frame data. For this reason, the number of accesses to the memory has increased, and the memory power has come to occupy most of the SoC power. Therefore, reduction of memory power is an important issue in SoC design.

  As described above, in the general SoC, the ratio of the memory power, in particular, the memory power mounted on the accelerator is increasing. Therefore, there is a strong demand to reduce this memory power. This requirement becomes even more important in SoCs for mobile phones driven by batteries.

  Under such circumstances, for example, the technique of Patent Document 1 or Patent Document 2 is known. Utilizing these technologies, it is possible to reduce memory power by suppressing unnecessary activation of the memory in cooperation with the arithmetic circuit side. However, all of these techniques are directed to memories with variable access latency, such as DRAM. In other words, when a read instruction to the same address continues for a memory with variable access latency, the read latency is concealed by outputting the already read value to the arithmetic circuit as it is for the second and subsequent times. It was the purpose. At this time, the access latency of the memory changes depending on the issued instruction. Therefore, in these technologies, a sequencer or the like that simulates the operation of the memory and notifies the arithmetic circuit side that the output data preparation is complete is essential. It was. The signal line 20 in FIG. 1 of Patent Document 1, the output signal of the bank busy counter 6 in FIG. 1 and the output signal of the busy selector 8 in Patent Document 2 correspond to this sequencer.

  However, the subject of the present invention is a memory mounted on SoC or the like, that is, an access latency invariant memory. Even if the conventional technology is applied to a memory whose access latency is constant, memory access cannot be accelerated. Therefore, there has been no motivation to apply the prior art to a memory whose access latency is unchanged.

  Therefore, the inventors of the present application have studied a method for reducing power consumption by suppressing unnecessary activation of a memory having an invariable access latency mounted on the SoC. In this method, there is no need to provide a sequencer on the memory side to notify the completion of data preparation, which was essential in the prior art, and the function to fetch data at different timings corresponding to different access latencies is provided on the arithmetic circuit side. Since there is no need to provide it, the area overhead can be minimized and the power reduction effect can be increased.

  However, in order to control the activation of the memory in this way, it is necessary to process the memory activation signal, so that the access time to the memory is deteriorated. A typical SRAM as an access latency invariant memory is characterized by high-speed operation, and it has been difficult to perform memory activation control leading to deterioration in access time. Therefore, the inventors of the present application pay attention to an IP that operates at a low frequency among the IPs that constitute the SoC, for example, an accelerator, and suppress memory power by controlling unnecessary activation of an access latency invariant memory connected to the accelerator. To reduce power consumption of semiconductor integrated circuit devices.

  When considering this reduction in power consumption, among the many IPs that make up the SoC, the IP that requires high-speed operation is limited to a part such as CPU and cache, and the accelerator group does not necessarily require high-speed operation. It was. That is, a large number of memories mounted on the accelerator group can operate at a lower speed than a memory used as a cache. Therefore, the accelerator has a sufficient time for access from the arithmetic circuit to the memory, and it is possible to process the memory activation signal and suppress unnecessary activation.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the semiconductor integrated circuit device of the present invention has a memory block and an operation block whose access latency is not changed, and when the operation block continuously issues a read command directed to the same memory address to the memory block, 2 A memory activation control block for stopping a memory block read operation associated with a read command after the first time is provided. As a result, unnecessary activation of the memory can be suppressed, and memory power consumption can be reduced.

  Specifically, when an address signal and a command signal output from the operation block to the memory block are interpreted and a read command to the same address is issued twice or more in succession, for example, the memory block The actual operation of the memory block is stopped by not supplying the clock signal. Further, for example, the actual operation of the memory block can be stopped by supplying a no-operation instruction to the memory block. Since the memory block holds the data read by the first read command, the operation block may receive the held data in the second and subsequent read commands.

  Briefly explaining the effects obtained by typical ones of the inventions disclosed in the present application, it is possible to suppress unnecessary start-up of the memory and reduce the power consumption of the memory, thereby reducing the power consumption of the semiconductor integrated circuit device. can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 1 includes an operation block IP1, a memory block MEM1, and a memory activation control block CTRL1. The memory activation control block CTRL1 includes buffer circuits BUF11 and BUF12, a read instruction determination circuit READ1, an address comparison circuit CMP1, a negative logical product circuit NAND1, a negative phase latch circuit ILAT1, and a logical product circuit AND1.

  The address signal ADDR11, command signal CMD11, and data 11 signal DAT11, which are output terminals of the arithmetic block IP1, are connected to the input terminal of the memory block MEM1, respectively, and the address signal ADDR11 and command signal CMD11 are input terminals of the memory activation control block CTRL1. Connected to each. The data 12 signal DAT12 that is the output terminal of the memory block MEM1 is connected to the input terminal of the arithmetic block IP1. A memory activation signal CLK12 that is an output terminal of the memory activation control block CTRL1 is connected to an input terminal of the memory block MEM1. The clock signal CLK11 is input to the arithmetic block IP1 and the memory activation control block CTRL1. The address signal ADDR11, the command signal CMD11, the data 11 signal DAT11, and the data 12 signal DAT12 mentioned so far may be a single bit or a plurality of bits. Similarly, the buffer circuits BUF11 and BUF12 may be a single bit or a plurality of bits.

  Connections in the memory activation control block CTRL1 are as follows. The command signal CMD11 is connected to the data input of the buffer circuit BUF11 and one input of the read command determination circuit READ1, and the data output CMD12 of the buffer circuit BUF11 is connected to the other input of the read command determination circuit READ1. The address signal ADDR11 is connected to the data input of the buffer circuit BUF12 and one input of the address comparison circuit CMP1, and the data output ADDR12 of the buffer circuit BUF12 is connected to the other input of the address comparison circuit CMP1.

  Further, the output READ_OUT1 of the read command determination circuit READ1 is connected to one input of the NAND circuit NAND1, and the output CMP_OUT1 of the address comparison circuit CMP1 is connected to the other input of the NAND circuit NAND1. The continuous read determination signal JGE_OUT1 that is the output of the NAND circuit NAND1 is connected to the data input of the anti-phase latch circuit ILAT1, and the data output ILAT_OUT1 of the anti-phase latch circuit ILAT1 is connected to one input of the AND circuit AND1. The The clock signal CLK11 is connected to the buffer circuits BUF11 and BUF12, the clock input of the anti-phase latch ILAT1, and the other input of the AND circuit AND1. Then, the output of the AND circuit AND1 becomes the memory activation signal CLK12.

  The calculation block IP1 is a circuit block that performs calculations while exchanging data with the memory. In synchronization with the clock signal CLK11, an address signal ADDR11, a command signal CMD11, and a data 11 signal DAT11 are output. The contents of the command signal CMD11 include a write command, a read command, a standby command, and the like. In the memory activation control block CTRL1, the instruction signal CMD11 is taken into the buffer circuit BUF11, and the address signal ADDR11 is taken into the buffer circuit BUF12 in synchronization with the clock signal CLK11. The read command determination circuit READ1 outputs a high level VDD to READ_OUT1 when both the command signal CMD11 and the output signal CMD12 of the buffer circuit BUF11 are read commands, and otherwise outputs a low level VSS to READ_OUT1.

  The address comparison circuit CMP1 outputs the high level VDD to CMP_OUT1 when the address of the address signal ADDR11 and the output signal ADDR12 of the buffer circuit BUF12 match, and outputs the low level VSS to CMP_OUT1 when they do not match. The NAND circuit NAND1 outputs the low level VSS to JGE_OUT1 when both the output READ_OUT1 of the read instruction determination circuit READ1 and the output CMP_OUT1 of the address comparison circuit are high level VDD, and otherwise, the high level VDD is set to JGE_OUT1. Output.

  The anti-phase latch circuit ILAT1 outputs JGE_OUT1 as it is as ILAT_OUT1 when the clock signal CLK11 is at the low level VSS, and when the clock signal CLK11 is at the high level VDD, the logical value of JGE_OUT1 when the clock signal CLK11 is at the low level VSS. Is continuously output to ILAT_OUT1. The AND circuit AND1 outputs the high level VDD when both the clock signal CLK11 and the output ILAT_OUT1 of the anti-phase latch circuit ILAT1 are at the high level VDD, and outputs the low level VSS in the other cases as the memory activation signal CLK12.

  The memory block MEM1 is activated in synchronization with the memory activation signal CLK12. When the command signal CMD11 is a read command accompanying this activation, the memory block MEM1 outputs the value held in the memory cell at the address specified by the address signal ADDR11 to the data 12 signal DAT12. On the other hand, when the command signal CMD11 is a write command along with activation, the memory block MEM1 writes the value of the data 11 signal DAT11 to the memory cell at the address specified by the address signal ADDR11. When the command signal CMD11 is on standby, nothing is performed even if the command signal CMD11 is activated by the memory activation signal CLK12.

  In such a configuration, the feature of the semiconductor integrated circuit device according to the present embodiment is that unnecessary activation of the memory block MEM1 is suppressed by using two signals of the address signal ADDR11 and the command signal CMD11. This operation is realized by the memory activation control block CTRL1 judging a continuous read command to the same address and blocking the propagation of the clock signal CLK1 to the memory block MEM1 when it is not necessary. At this time, the memory activation control block CTRL1 generates a read command determination signal READ_OUT1 that determines whether it is a continuous read command from the current command signal CMD11 and the command signal CMD12 one cycle before. Further, an address comparison signal CMP_OUT1 that determines whether or not the address is the same from the current address signal ADDR11 and the address signal ADDR12 one cycle before is generated. Then, a continuous read determination signal JGE_OUT1 is generated using the read command determination signal READ_OUT1 and the address comparison signal CMP_OUT1, and this signal becomes low level VSS when a read command is issued continuously to the same address, otherwise Becomes the high level VDD. The continuous read command determination signal JGE_OUT1 is used as a clock cutoff signal ILAT_OUT1 after being synchronized by the anti-phase latch ILAT1.

  FIG. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. In FIG. 2, the clock signal CLK11 outputs a high level VDD and a low level VSS with a period from time T1 to T6. The address signal ADDR11 changes to an address value A before time T18 and changes to another address value B at time T18. The instruction signal CMD11 is a read command read before time T2 and a write command write at times T2 to T9. Assume that the read command read is again after time T9. In other words, four clock signals CLK11 are input during time T1-T22, and instructions associated with the respective clock signals are, in order, a read command for address A, a write command for address A, and a read command for address A. Read command for address A.

  At time T1-T22, the output signal ADDR12 of the buffer BUF12 changes to the same logical value as that of the address signal ADDR11 in synchronization with the rising edge of the clock signal CLK11, and therefore remains at the address value A. Similarly, the output signal CMD12 of the buffer BUF11 changes to the same logical value as the command signal CMD11 in synchronization with the rising edge of the clock signal CLK11, and therefore changes from the read command read to the write command write at time T8. At T12, the write command write is changed to the read command read again.

  Next, since the read command determination signal READ_OUT1 becomes the high level VDD when both the command signal CMD11 and the command signal CMD12 are the read command READ, the read command determination signal READ_OUT1 becomes the low level VSS in the period T3-T14, and the high level VDD in the other periods. It becomes. Further, the address comparison signal CMP_OUT1 becomes the high level VDD when the address signal ADDR11 and the address signal ADDR12 coincide with each other, and therefore changes from the high level VDD to the low level VSS at time T19. The continuous read determination signal JGE_OUT1 is at the low level VSS when both the read command determination signal READ_OUT1 and the address comparison signal CMP_OUT1 are at the high level VDD. High level VDD.

  The continuous read determination signal JGE_OUT1 passes through the anti-phase latch ILAT1, and ILAT1 can change the logical value only during the period when the clock signal CLK11 is at the low level VSS. Therefore, the clock cutoff signal ILAT_OUT1 that is the output of ILAT1 immediately reflects JGE_OUT1 at times T4 and T15, transitions to high level VDD at time T5, and transitions to low level VSS at time T16, but immediately reflects at time T20. Instead, after the clock signal CLK11 becomes the low level VSS at the time T21, the signal transits to the high level VDD at the time T22. The clock signal CLK11 is processed into an untoothed state by being ANDed with the clock cutoff signal ILAT_OUT1, and as a result, a period during which a continuous read command is issued to the same address (for example, at the time of the fourth clock command) Clock signal CLK11 is not propagated to memory activation signal CLK12. The memory activation signal CLK12 transitions from low level VSS → high level VDD → low level VSS only twice at times T7 and T11, and memory power is consumed only during this period.

  Further, along with the memory activation signal CLK12 at time T7, the data value data1 is output to the data 11 signal DAT11, and thus the data value data1 is written to the address A of the memory block MEM1. Subsequently, the memory activation signal CLK12 at time T11 is received, and at time T13, the data value data1 is read from the memory block MEM1 to the data 12 signal DAT12.

  This read data is updated only when a read command read is issued together with the memory activation signal CLK12 to the memory block MEM1, and in other cases, the read data is held in a buffer provided in the output stage. Therefore, in the clock signal CLK11 at time T17, a continuous read command to the same address is generated from the arithmetic circuit IP1 toward the memory block MEM1, but in this case, the memory block MEM1 is not activated and the arithmetic circuit IP1 The data value data1 held in the MEM1 buffer is received. Here, the timing from when the arithmetic circuit IP1 issues a read command to the memory block MEM1 until the IP1 receives read data from the MEM1 is whether the read command is a continuous read command directed to the same address. It is constant regardless of whether or not.

  As described above, by performing the operation as shown in FIG. 2 using the semiconductor integrated circuit device as shown in FIG. 1, it is possible to reduce the power consumption of the memory when the continuous read command to the same address is generated. Further, since the timing at which the operation block IP1 receives data from the memory block MEM1 is constant regardless of whether or not a continuous read command is generated, a sequencer or the like related to timing control as in the above-described Patent Documents 1 and 2 is not necessary. In other words, memory power consumption can be reduced with a small circuit.

  In FIG. 1, an operation block IP1 is, for example, an accelerator that performs image processing, and a memory block MEM1 is, for example, a synchronous SRAM whose access latency is unchanged. Since such an accelerator operates at, for example, 33 MHz or 66 MHz, the delay caused by the memory activation control block CTRL1 does not cause a problem. When the memory activation control block CTRL1 is mounted on such an accelerator and SRAM configuration, the memory power consumption can be reduced by about 50 to 60% as an example, although it depends on the processing contents of the accelerator. .

  Also, the access latency invariant means that the timing (or the number of clock cycles) from when the memory block receives the read command to when the data is actually output is unchanged. For example, in FIG. 2, the memory block receives the third instruction and accesses it in one clock cycle. Since the fourth instruction is not accessed, the access latency is unchanged in one clock cycle. . On the other hand, when the operation example as shown in FIG. 2 is applied to the techniques of Patent Document 1 and Patent Document 2, the memory block receives the third instruction and accesses it in, for example, three clock cycles. For example, access is performed in one clock cycle by using a read data register or the like in the memory block. That is, the access latency is variable. Note that even if the memory block MEM1 of FIG. 1 is provided with a read data register as in Patent Document 1 and Patent Document 2, access is performed in one clock cycle for the fourth instruction, so that the access latency remains unchanged. It becomes.

  FIG. 3 is a block diagram showing a modification of the semiconductor integrated circuit device of FIG. Here, there is shown an example in which the configuration example of FIG. 1 is modified and the memory activation control block CTRL3 is mounted in the arithmetic block IP3. The semiconductor integrated circuit device shown in FIG. 3 includes an operation block IP3 and a memory block MEM3. The configuration of the memory activation control block CTRL3 is the same as that of the memory activation control block CTRL1, and includes buffer circuits BUF31 and BUF32, a read instruction determination circuit READ3, an address comparison circuit CMP3, a negative AND circuit NAND3, a negative-phase latch circuit ILAT3, a logical product It consists of a circuit AND3.

  The address signal ADDR31, the command signal CMD31, and the data 31 signal DAT31, which are output terminals of the arithmetic block IP3, are connected to the input terminals of the memory block MEM3, respectively, and the address signal ADDR31 and the command signal CMD31 are activated in the memory inside the arithmetic block IP3. It is also connected to the control block CTRL3. The data 32 signal DAT32 that is the output terminal of the memory block MEM3 is connected to the data input terminal of the operation block IP3. Further, the clock signal CLK31 is input to the arithmetic block IP3, and the memory activation signal CLK32 generated by the arithmetic block IP3 is input as the activation signal of the memory block MEM3. The address signal ADDR31, the command signal CMD31, the data 31 signal DAT31, and the data 32 signal DAT32 mentioned so far may be a single bit or a plurality of bits. Similarly, the buffer circuits BUF31 and BUF32 may be a single bit or a plurality of bits.

  The connection of the memory activation control block CTRL3 in the calculation block IP3 is as follows, similarly to the memory activation control block CTRL1. The command signal CMD31 is connected to the data input of the buffer circuit BUF31 and one input of the read command determination circuit READ3, and the data output CMD32 of the buffer circuit BUF31 is connected to the other input of the read command determination circuit READ3. The address signal ADDR31 is connected to the data input of the buffer circuit BUF32 and one input of the address comparison circuit CMP3, and the data output ADDR32 of the buffer circuit BUF32 is connected to the other input of the address comparison circuit CMP3. The output READ_OUT3 of the read command determination circuit READ3 is connected to one input of the NAND circuit NAND3, and the output CMP_OUT3 of the address comparison circuit CMP3 is connected to the other input of the NAND circuit NAND3.

  The continuous read determination signal JGE_OUT3 that is the output of the NAND circuit NAND3 is connected to the data input of the anti-phase latch circuit ILAT3, and the data output ILAT_OUT3 of the anti-phase latch circuit ILAT3 is connected to one input of the AND circuit AND3. The The clock signal CLK31 is connected to the buffer circuits BUF31 and BUF32, the clock input of the anti-phase latch ILAT3, and the other input of the AND circuit AND3. Then, the output of the AND circuit AND3 becomes the memory activation signal CLK32.

  The calculation block IP3 is a circuit block that performs calculations while exchanging data with the memory. The arithmetic block IP3 outputs an address signal ADDR31, a command signal CMD31, and a data 31 signal DAT31 in synchronization with the clock signal CLK31. The contents of the command signal CMD3 include a write command write, a read command read, a standby command wait, and the like. In the memory activation control block CTRL3, the instruction signal CMD31 is taken into the buffer circuit BUF31 and the address signal ADDR31 is taken into the buffer circuit BUF32 in synchronization with the clock signal CLK31.

  The read command determination circuit READ3 outputs the high level VDD to READ_OUT3 when both the command signal CMD31 and the output signal CMD32 of the buffer circuit BUF31 are read commands, and otherwise outputs the low level VSS to READ_OUT3. The address comparison circuit CMOP3 outputs the high level VDD to CMP_OUT3 when the address of the address signal ADDR31 and the output signal ADDR32 of the buffer circuit BUF32 match, and outputs the low level VSS to CMP_OUT3 when they do not match. The NAND circuit NAND3 outputs the low level VSS to JGE_OUT3 when both the output READ_OUT3 of the read command determination circuit READ3 and the output CMP_OUT3 of the address comparison circuit CMP3 are at the high level VDD, and otherwise outputs the high level VDD to JGE_OUT3. Output to.

  The anti-phase latch ILAT3 outputs JGE_OUT3 as ILAT_OUT3 as it is when the clock signal CLK31 is at the low level VSS, and outputs the logical value of JGE_OUT3 when the clock signal CLK31 is at the low level VSS when the clock signal CLK31 is at the high level VDD. Continue to output to ILAT_OUT3. The AND circuit AND3 outputs the high level VDD when the clock signal CLK31 and the output ILAT_OUT3 of the anti-phase latch ILAT3 are both at the high level VDD, and outputs the low level VSS in the other cases as the memory activation signal CLK32.

  The memory block MEM3 is activated in synchronization with the memory activation signal CLK32. When the command signal CMD31 accompanying the memory activation signal CLK32 is a read command, the memory block MEM3 outputs the value held in the memory cell at the address specified by the address signal ADDR31 to the data 32 signal DAT32. On the other hand, when the command signal CMD31 accompanying the memory activation signal CLK32 is a write command, the memory block MEM3 writes the value of the data 31 signal DAT31 to the memory cell at the address specified by the address signal ADDR31. When the command signal CMD31 is on standby, nothing is performed even when the command signal CMD31 is activated by the memory activation signal CLK32.

  As described above, if the memory activation control block CTRL3 is mounted in the arithmetic block IP3 in advance as in the semiconductor integrated circuit device of FIG. 3, the timing, the memory block, and the memory activation control block are not laid out separately. Optimization is possible in terms of layout area. Therefore, by using the configuration example of FIG. 3, in addition to the effects described with reference to FIG. 1, the area can be further reduced, and communication between the arithmetic block and the memory block can be performed as compared with the configuration example of FIG. The speed can be increased.

  FIG. 4 is a block diagram showing another modification of the semiconductor integrated circuit device of FIG. Here, an example in which the memory activation control block CTRL4 is mounted inside the memory block MEM4 by modifying the configuration example of FIG. 1 is shown. The semiconductor integrated circuit device shown in FIG. 4 includes an operation block IP4 and a memory block MEM4. The configuration of the memory activation control block CTRL4 is the same as that of the memory activation control block CTRL1, and includes buffer circuits BUF41 and BUF42, a read instruction determination circuit READ4, an address comparison circuit CMP4, a negative AND circuit NAND4, a negative-phase latch circuit ILAT4, and a logical product. It consists of a circuit AND4.

  The address signal ADDR41, command signal CMD41, and data 41 signal DAT41, which are output terminals of the arithmetic block IP4, are respectively connected to the input terminals of the memory block MEM4, and the address signal ADDR41 and command signal CMD41 are activated in the memory block MEM4. It is also connected to the control block CTRL4. The data 42 signal DAT42 which is the output terminal of the memory block MEM4 is connected to the input terminal of the operation block IP4. The clock signal CLK41 is input to the arithmetic block IP4 and the memory block MEM4. Note that the address signal ADDR41, the command signal CMD41, the data 41 signal DAT41, and the data 42 signal DAT42 mentioned so far may be a single bit or a plurality of bits. Similarly, the buffer circuits BUF41 and BUF42 may be a single bit or a plurality of bits.

  The connection of the memory activation control block CTRL4 in the memory block MEM4 is as follows similarly to the memory activation control block CTRL1. The command signal CMD41 is connected to the data input of the buffer circuit BUF41 and one input of the read command determination circuit READ4, and the data output CMD42 of the buffer circuit BUF41 is connected to the other input of the read command determination circuit READ4. The address signal ADDR41 is connected to the data input of the buffer circuit BUF42 and one input of the address comparison circuit CMP4, and the data output ADDR42 of the buffer circuit BUF42 is connected to the other input of the address comparison circuit CMP4. The output READ_OUT4 of the read command determination circuit READ4 is connected to one input of the NAND circuit NAND4, and the output CMP_OUT4 of the address comparison circuit CMP4 is connected to the other input of the NAND circuit NAND4.

  The continuous read determination signal JGE_OUT4 that is the output of the NAND circuit NAND4 is connected to the data input of the anti-phase latch circuit ILAT4, and the data output ILAT_OUT4 of the anti-phase latch circuit ILAT4 is connected to one input of the AND circuit AND4. The The clock signal CLK41 is connected to the buffer circuits BUF41 and BUF42, the clock input of the anti-phase latch ILAT4, and the other input of the AND circuit AND4. The output of the AND circuit AND4 becomes the memory activation signal CLK42 that activates the inside of the memory block MEM4.

  The arithmetic block IP4 is a circuit block that performs arithmetic while exchanging data with the memory, and outputs an address signal ADDR41, a command signal CMD41, and a data 41 signal DAT41 in synchronization with the clock signal CLK41. The contents of the command signal CMD4 include a write command WRITE, a read command READ, a standby command WAIT, and the like. In the memory activation control block CTRL4 in the memory block MEM4, the instruction signal CMD41 is taken into the buffer circuit BUF41 and the address signal ADDR41 is taken into the buffer circuit BUF42 in synchronization with the clock signal CLK41.

  The read command determination circuit READ4 outputs a high level VDD to READ_OUT4 when both the command signal CMD41 and the output signal CMD42 of the buffer circuit BUF41 are read commands, and otherwise outputs a low level VSS to READ_OUT4. The address comparison circuit CMP4 outputs the high level VDD to CMP_OUT4 when the address signal ADDR41 and the output signal ADDR42 of the buffer circuit BUF42 match, and outputs the low level VSS to CMP_OUT4 when they do not match. The NAND circuit NAND4 outputs the low level VSS to JGE_OUT4 when both the output READ_OUT4 of the read instruction determination circuit READ4 and the output CMP_OUT4 of the address comparison circuit CMP4 are at the high level VDD, and otherwise outputs the high level VDD to JGE_OUT4. Output to.

  The anti-phase latch ILAT4 outputs JGE_OUT4 as ILAT_OUT4 as it is when the clock signal CLK41 is at the low level VSS, and outputs the logical value of JGE_OUT4 when the clock signal CLK41 is at the low level VSS when the clock signal CLK41 is at the high level VDD. Continue to output to ILAT_OUT4. The AND circuit AND4 outputs the high level VDD when the clock signal CLK41 and the output ILAT_OUT4 of the anti-phase latch ILAT4 are both at the high level VDD, and outputs the low level VSS in the other cases as the memory activation signal CLK42.

  The inside of the memory block MEM4 is activated by the memory activation signal CLK42. When the command signal CMD41 accompanying the memory activation signal CLK42 is a read command, the memory block MEM4 outputs the value held in the memory cell at the address specified by the address signal ADDR41 to the data 42 signal DAT42. On the other hand, when the command signal CMD41 accompanying the memory activation signal CLK42 is a write command, the memory block MEM4 writes the value of the data 41 signal DAT41 to the memory cell at the address specified by the address signal ADDR41. When the command signal CMD41 is on standby, nothing is performed even if the command signal CMD41 is activated by the memory activation signal CLK42.

  As described above, if the memory activation control block CTRL4 is mounted in advance in the memory block MEM4 as in the semiconductor integrated circuit device of FIG. 4, the timing, Optimization is possible in terms of layout area. Therefore, by using the configuration example of FIG. 4, in addition to the effects described with reference to FIG. 1, the area can be further reduced, and communication between the arithmetic block and the memory block can be performed as compared with the configuration example of FIG. The speed can be increased.

  FIG. 5 is a block diagram showing another example of the configuration of the semiconductor integrated circuit device according to one embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 5 includes an operation block IP5, a memory block MEM5, and a memory activation control block CTRL5. The memory activation control block CTRL5 includes buffer circuits BUF51 and BUF52, a read instruction determination circuit READ5, an address comparison circuit CMP5, a negative AND circuit NAND5, and an instruction conversion circuit CONV5.

  The address signal ADDR51 and the data 51 signal DAT51, which are output terminals of the arithmetic block IP5, are connected to the input terminal of the memory block MEM5, respectively, and the address signal ADDR51 and the command signal CMD51 are connected to the input terminals of the memory activation control block CTRL5, respectively. The The data 52 signal DAT52, which is the output terminal of the memory block MEM5, is connected to the input terminal of the arithmetic block IP5. The command signal CMD53 that is the output terminal of the memory activation control block CTRL5 is connected to the input terminal of the memory block MEM5. In addition, the clock signal CLK51 is input to the arithmetic block IP5, the memory activation control block CTRL5, and the memory block MEM5. Note that the address signal ADDR51, the command signal CMD51, the data 51 signal DAT51, and the data 52 signal DAT52 mentioned so far may be a single bit or a plurality of bits. Similarly, the buffer circuits BUF51 and BUF52 may be a single bit or a plurality of bits.

  Connections in the memory activation control block CTRL5 are as follows. The command signal CMD51 is connected to the data input of the buffer circuit BUF51 and one input of the read command determination circuit READ5, and the data output CMD52 of the buffer circuit BUF51 is connected to the other input of the read command determination circuit READ5. The address signal ADDR51 is connected to the data input of the buffer circuit BUF52 and one input of the address comparison circuit CMP5, and the data output ADDR52 of the buffer circuit BUF52 is connected to the other input of the address comparison circuit CMP5. The output READ_OUT5 of the read command determination circuit READ5 is connected to one input of the NAND circuit NAND5, and the output CMP_OUT5 of the address comparison circuit CMP5 is connected to the other input of the NAND circuit NAND5. The continuous read determination signal JGE_OUT5 and the command signal CMD51 that are output from the NAND circuit NAND5 are input to the command conversion circuit CONV5, and the output of the command conversion circuit CONV5 is the command signal CMD53.

  The arithmetic block IP5 is a circuit block that performs arithmetic while exchanging data with the memory, and outputs an address signal ADDR51, a command signal CMD51, and a data 51 signal DAT51 in synchronization with the clock signal CLK51. The contents of the command signal CMD51 include a write command, a read command, a standby command, and the like. In the memory activation control block CTRL5, the instruction signal CMD51 is taken into the buffer circuit BUF51, and the address signal ADDR51 is taken into the buffer circuit BUF52 in synchronization with the clock signal CLK51.

  The read command determination circuit READ5 outputs a high level VDD to READ_OUT5 when both the command signal CMD51 and the output signal CMD52 of the buffer circuit BUF51 are read commands, and otherwise outputs a low level VSS to READ_OUT5. The address comparison circuit CMP5 outputs the high level VDD to CMP_OUT5 when the address signal ADDR51 and the address of the output signal ADDR52 of the buffer circuit BUF52 match, and outputs the low level VSS to CMP_OUT5 when they do not match. The NAND circuit NAND5 outputs the low level VSS to the continuous read determination signal JGE_OUT5 when both the output READ_OUT5 of the read instruction determination circuit READ5 and the output CMP_OUT5 of the address comparison circuit CMP5 are at the high level VDD, otherwise it is high. The level VDD is output to the continuous read determination signal JGE_OUT5.

  The command conversion circuit CONV5 outputs the command signal CMD51 as the command signal CMD53 as it is when the continuous read determination signal JGE_OUT5 is at the high level VDD, and the standby command as the command signal CMD53 when the continuous read determination signal JGE_OUT5 is at the low level VSS. Output. The memory block MEM5 is activated in synchronization with the memory activation signal CLK51. When the instruction signal CMD53 output from the memory activation control block CTRL5 according to the memory activation signal CLK51 is a read instruction, the memory block MEM5 stores the value held in the memory cell at the address specified by the address signal ADDR51 as the data 52. Output to signal DAT52. If the command signal CMD53 output in the same manner is a write command, the memory block MEM5 writes the value of the data 51 signal DAT51 into the memory cell at the address specified by the address signal ADDR51. Further, when the command signal CMD53 output in the same manner is a standby command, the memory block MEM5 does nothing even when activated by the memory activation signal CLK51.

  As described above, by using the semiconductor integrated circuit device as shown in FIG. 5, it is possible to reduce the memory power consumption when the continuous read command to the same address is generated. That is, as a matter of course when the instruction signal CMD51 from the operation block IP5 is a standby instruction, a standby instruction can be issued to the memory block MEM5 even when a continuous read instruction to the same address is issued from IP5. In the case of a standby instruction, even when the memory block MEM5 is activated by the memory activation signal CLK51, the MEM5 substantially consumes little power. Similarly to the description in FIG. 1 and FIG. 2, the timing at which the operation block IP5 receives data from the memory block MEM5 is constant regardless of whether or not the continuous read command is generated. Thus, a sequencer or the like related to timing control is not necessary, and memory power consumption can be reduced with a small circuit. Here, when a continuous read command is generated, it is converted into a standby command. Of course, if the memory block MEM5 does not perform an actual operation (no operation command), it can be appropriately replaced.

  Further, in the configuration example of FIG. 5, the memory power consumption is reduced by processing the command signal CMD51 without processing the memory activation signal as in the configuration example of FIG. As a result, even when there is no sufficient timing margin in the memory activation signal, it is possible to reduce the memory power consumption if there is a timing margin in the command signal CMD53. For example, in an actual design, a clock signal such as a memory activation signal may not be easily processed due to generally severe timing restrictions. However, it can be applied even in such a case. Note that the configuration example of FIG. 5 can of course be modified in the same way as in FIGS. 3 and 4, and thereby the circuit area and timing can be optimized.

  FIG. 6 is a block diagram showing a configuration example of a semiconductor integrated circuit device to which the configuration example of FIG. The semiconductor integrated circuit device shown in FIG. 6 is, for example, a SoC in which a plurality of IPs are formed on a single semiconductor chip. It is an example to which a configuration example is applied. The semiconductor integrated circuit device (semiconductor chip) LSI 6 of FIG. 6 includes, for example, arithmetic blocks IP61 and IP62, memory blocks MEM61 and MEM62, a memory activation control block CTRL61, and the like. Of these five blocks, the arithmetic block IP61 is an accelerator operating at a low frequency, for example, and the arithmetic block IP62 is a CPU operating at a high frequency, for example.

  Therefore, in FIG. 6, the memory activation control block CTRL61 as shown in FIG. 1 or the like is applied to the arithmetic block IP61 and the memory block MEM61 that operate at a low frequency. Of course, the configuration of this application location is not limited to that shown in FIG. 1, but may be as shown in FIG. 5. The memory control block CTRL 61 is connected to the arithmetic block IP 61 or the like as shown in FIG. It may be included in the memory block MEM61.

  As described above, as shown in FIG. 6, even within the same semiconductor chip, by selectively applying the memory activation control block to the low frequency block, the operation speed of the SoC or the like is not affected, and the entire SoC is not affected. There is an effect that power can be reduced. Further, since the memory activation control block can be realized with a small area as described above, it hardly affects the chip area.

  FIG. 7 is a block diagram showing a configuration example of a semiconductor integrated circuit device including a semiconductor chip and a memory chip to which the configuration example of FIG. The semiconductor integrated circuit device shown in FIG. 7 has, for example, a so-called SIP (System In Package) configuration in which a semiconductor chip and a memory chip are mounted in one package. The semiconductor integrated circuit device of FIG. 7 includes, for example, a semiconductor chip LSI7 including an operation block IP7 and a memory activation control block CTRL7, a memory chip corresponding to the memory block MEM7, and the like. The connection and operation contents of these three blocks may be the same as in FIG. 1 or FIG. 5, and the memory control block CTRL7 is included in the arithmetic block IP7 or the memory block MEM7 as shown in FIG. 3 or FIG. Also good.

  As described above, by using the configuration example as shown in FIG. 7, even in a semiconductor integrated circuit device having an off-chip memory, the power consumption of the semiconductor integrated circuit device can be reduced. In addition, power consumption can be reduced without substantially increasing the size of the semiconductor integrated circuit device.

  FIG. 8 is a design flow chart showing an example of the design method in the semiconductor integrated circuit device according to the embodiment of the present invention. The design flow shown in FIG. 8 is a design flow in the case where the memory control block CTRL as described above is applied to, for example, a newly designed operation block IP and memory block MEM.

  As shown in FIG. 8, in the new design, first, RTL description of the operation block IP and the memory block MEM is performed (S801). Next, the memory control block CTRL described above is incorporated with the address signal ADDR and the instruction signal CMD of the operation block IP as inputs (S802). Then, after verifying the operation using the RTL description designed in this way (S803), logic synthesis is performed to generate a gate level netlist from the RTL description (S804). Subsequently, after performing operation verification using the gate level description (S805), the gate level cell is laid out (S806), and a clock tree is generated (S807). Finally, timing verification is performed to complete the layout design (S808).

  As described above, even when the RTL design of the arithmetic block IP and the memory block MEM is independently performed, the memory control block CTRL can be easily incorporated into the arithmetic block IP and the memory block MEM after the RTL design. By incorporating the memory control block CTRL, there is no need to change the design flow. Therefore, for example, a design flow for individually designing each block as seen in SoC or the like can be used as it is, and as a result, low power can be realized with extremely small area overhead.

  FIG. 9 is a design flowchart showing another example of the design method in the semiconductor integrated circuit device according to one embodiment of the present invention. The design flow shown in FIG. 9 is a design flow when the memory control block CTRL as described above is applied to, for example, an existing chip. That is, even for a chip that has already been designed, memory power can be reduced by slightly modifying the design data after layout. For example, as shown in FIG. 9, a memory activation control block CTRL is arranged and wired between the memory block MEM and the operation block IP using layout data of an existing chip as shown in FIG. 9 (S901). It is only necessary to perform timing verification for some of the paths affected by (S902).

  For example, when the memory activation control block CTRL1 as shown in FIG. 1 is applied, after the signal line connected to the activation signal pin of the memory block MEM1 is deleted and CTRL1 is added, the memory activation which is the output of CTRL1 Reconnect signal CLK12 to the clock pin of MEM1. At this time, the timing verification may be performed only on a path to which the clock signal CLK11, the memory activation signal CLK12, the address signal ADDR11, and the command signal CMD11 are connected.

  Further, when the memory activation control block CTRL5 as shown in FIG. 5 is applied, the signal line connected to the command signal pin of the memory block MEM5 is deleted, and after adding CTRL5, the command signal which is the output of CTRL5 Reconnect CMD53 to the command signal pin of MEM5. At this time, the timing verification may be performed only on a path to which the clock signal CLK51, the address signal ADDR51, the command signal CMD51, and the command signal CMD53 are connected.

  In either case of FIG. 1 or FIG. 5, when viewed from the operation block, the memory block is connected via the memory activation control block, but the data returned from the memory block is before the memory activation control block is inserted. And invariant. That is, since no change occurs in the function of the circuit, no new operation verification is necessary. Further, when the memory activation control block CTRL is actually arranged, the CTRL is applied to the memory block MEM and the operation block IP whose communication speed is relatively small and the communication speed between them is relatively low. It is easy to embed layout data that has already been completed.

  As mentioned above, when the typical effect by using each embodiment described so far is given, it is possible to suppress unnecessary activation of the memory provided in the semiconductor integrated circuit device and reduce its power. Become. In addition, since unnecessary memory activation can be suppressed and memory power can be reduced, the power consumption of the semiconductor integrated circuit device can be reduced. Furthermore, low power consumption of the semiconductor integrated circuit device can be realized with a small area overhead. In addition, it can be easily applied to newly designed semiconductor products and existing semiconductor products, and low power consumption of the semiconductor products can be realized at low cost.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the above-described memory activation control block is particularly useful when applied to an arithmetic block and a memory block that operate at a relatively low frequency such as an accelerator, but of course a delay due to the memory activation control block is allowed. As long as it is applied to arithmetic blocks and memory blocks that operate at a relatively high frequency, such as a CPU, it is also beneficial. Further, for example, FIG. 2 shows an example in which the memory operates with an access latency of one cycle, but the present invention can be similarly applied even when the memory operates with an access latency of a constant multiple cycles.

  The semiconductor device integrated circuit device according to the present invention is particularly useful when applied to a system LSI for mobile phones that require low power consumption, and is not limited to this. It can be widely applied as a low power consumption technology.

1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. FIG. 10 is a block diagram illustrating a modification of the semiconductor integrated circuit device of FIG. 1. FIG. 10 is a block diagram showing another modification of the semiconductor integrated circuit device of FIG. 1. FIG. 10 is a block diagram showing another example of the configuration of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a semiconductor integrated circuit device to which the configuration example of FIG. 1 and the like is partially applied. FIG. 2 is a block diagram illustrating a configuration example of a semiconductor integrated circuit device including a semiconductor chip and a memory chip to which a configuration example such as FIG. 1 is partially applied. FIG. 10 is a design flow chart showing an example of a design method in the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 10 is a design flow chart showing another example of the design method in the semiconductor integrated circuit device according to one embodiment of the present invention.

Explanation of symbols

ADDR address signal CMD instruction signal DAT data signal CLK clock signal or memory activation signal IP arithmetic block MEM memory block CTRL memory activation control block BUF buffer AND logical product circuit NAND negative logical product circuit ILAT reverse phase latch circuit READ read command determination circuit CMP address Comparison circuit CONV instruction conversion circuit

Claims (14)

A memory block with indefinite access latency,
An operation block that issues an instruction to the memory block and performs desired processing using data stored in the memory block;
A memory activation control block that stops a read operation of the memory block in response to a second or subsequent read command when the arithmetic block continuously issues a read command directed to the same memory address to the memory block; A semiconductor integrated circuit device comprising: The semiconductor integrated circuit device according to claim 1.
The memory activation control block stops reading operation of the memory block by stopping supply of a clock signal to the memory block. The semiconductor integrated circuit device according to claim 1.
The memory activation control block stops the read operation of the memory block by converting the second and subsequent read instructions into an instruction not performing an operation and transmitting the converted instruction to the memory block. apparatus. The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device, wherein the memory activation control block is arranged in the arithmetic block. The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device, wherein the memory activation control block is arranged in the memory block. The semiconductor integrated circuit device according to claim 2.
The memory activation control block includes
A first buffer circuit that receives an external clock signal and holds an input command signal in synchronization with a transition from the first level to the second level of the external clock signal;
A second buffer circuit for holding an input address signal in synchronization with a transition from the first level to the second level of the external clock signal;
Read that compares the input command signal with the output signal of the first buffer circuit, and outputs a third level signal when both signals are read commands, and outputs a fourth level signal otherwise An instruction determination circuit;
An address that compares the input address signal and the output signal of the second buffer circuit, outputs a fifth level signal when both signals have the same address, and outputs a sixth level signal otherwise. A comparison circuit;
When the output signal of the read command determination circuit is the third level signal and the output signal of the address comparison circuit is the fifth level signal, a seventh level signal is output, and otherwise Is a NAND circuit that outputs an 8th level signal;
The output signal of the NAND circuit and the external clock signal are input. When the external clock signal is at the first level, the output signal of the NAND circuit is output as it is, and the external clock signal is the second clock signal. In the case of a level, a negative phase latch circuit that holds the output signal of the NAND circuit when it was the immediately preceding first level;
When the output signal of the anti-phase latch circuit and the external clock signal are input, and the output signal of the anti-phase latch circuit is the seventh level signal, the external clock signal is transmitted to the memory block, and the anti-phase latch circuit And a logical product circuit that does not transmit the external clock signal to the memory block when the output signal of the latch circuit is the signal of the eighth level. The semiconductor integrated circuit device according to claim 3.
The memory activation control block includes
A first buffer circuit that receives an external clock signal and holds an input command signal in synchronization with a transition from the first level to the second level of the external clock signal;
A second buffer circuit for holding an input address signal in synchronization with a transition from the first level to the second level of the external clock signal;
A read that compares the input command signal with the output signal of the first buffer circuit and outputs a third level signal when both signals are read commands, and outputs a fourth level signal otherwise. An instruction determination circuit;
An address that compares the input address signal and the output signal of the second buffer circuit, and outputs a fifth level signal when both signals have the same address, and outputs a sixth level signal otherwise. A comparison circuit;
When the output signal of the read command determination circuit is the third level signal and the output signal of the address comparison circuit is the fifth level signal, a seventh level signal is output, otherwise A NAND circuit for outputting an eighth level signal;
When the output signal of the negative logic product circuit and the input command signal are input, and the output signal of the negative logical product circuit is the seventh level signal, the input command signal is converted into a command for performing no operation. And an instruction conversion circuit that outputs to the memory block and outputs the input instruction signal to the memory block as it is when the output signal of the NAND circuit is the signal of the eighth level. A semiconductor integrated circuit device. A first memory block and a second memory block;
A first operation block that issues an instruction to the first memory block and performs desired processing using data stored in the first memory block;
A second operation block that issues an instruction to the second memory block and performs desired processing using data stored in the second memory block;
The communication speed between the first memory block and the first calculation block is slower than the communication speed between the second memory block and the second calculation block,
The access latency of the first memory block is unchanged,
The signal line between the first memory block and the first arithmetic block is when the first arithmetic block continuously issues a read command for the same memory address to the first memory block. A semiconductor integrated circuit device, comprising: a memory activation control block for stopping a read operation of the first memory block in response to a second and subsequent read commands. The semiconductor integrated circuit device according to claim 8.
The semiconductor integrated circuit device according to claim 1, wherein the first calculation block is an accelerator that performs audio or image signal processing. The semiconductor integrated circuit device according to claim 8.
The semiconductor integrated circuit device, wherein the first memory block is an SRAM. The semiconductor integrated circuit device according to claim 8.
The semiconductor integrated circuit device is formed on one semiconductor chip. A memory block;
An operation block that issues an instruction to the memory block and performs desired processing using data stored in the memory block;
A memory activation control block that stops a read operation of the memory block in response to a second or subsequent read command when the arithmetic block continuously issues a read command directed to the same memory address to the memory block; Have
The memory block continues the first data output operation associated with the first read instruction until a new read operation is performed,
In the arithmetic block, the timing from when the first read command is issued to the memory block until the first data is received, and the second and subsequent read commands are issued to the memory block. The semiconductor integrated circuit device is characterized in that the timing from when the first data is received to when the first data is received is the same. The semiconductor integrated circuit device according to claim 12, wherein
The memory activation control block stops reading operation of the memory block by stopping supply of a clock signal to the memory block. The semiconductor integrated circuit device according to claim 12, wherein
The memory activation control block stops the read operation of the memory block by converting the second and subsequent read instructions into an instruction not performing an operation and transmitting the converted instruction to the memory block. apparatus.

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