JP2007295411A - Power clipping circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress generation of a modulation error in clipping to a minimum. <P>SOLUTION: The selection as to whether to pass a quadrature baseband signal to a clipping processing circuit is decided, by comparing RI<SP>2</SP>+RQ<SP>2</SP>squaring and adding quadrature baseband signals RI, RQ with a clipping level RL<SP>2</SP>. Thus, only a signal requiring power limitation is inputted to a clipping means 101, and regarding a signal that does not require power limitation, a selector 106 is controlled via an AND gate 107, and a timing-controlled signal passed via a timing controller 105 is outputted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power clipping circuit, and more particularly to a clipping circuit that limits the amplitude of a baseband signal supplied to a power amplifier in a wireless transmission system.

  In a wireless communication system such as a digital cellular phone, a power amplifier used in a wireless digital modulation circuit is required to have good linearity and high efficiency characteristics for all amplitude values of a signal to be transmitted. However, it is difficult to use a power amplifier having good line formation for all amplitude values due to an increase in price, circuit scale and power consumption. Therefore, a general power amplifier having linearity up to a certain amplitude but having a nonlinear characteristic above a certain level is often used.

  In a multi-carrier scheme such as a CDMA (Code Division Multiple Access) scheme, since transmission signals superimposed on a plurality of carriers are added on the time axis, the peak power of the multiplexed signal increases. When such a signal having a large peak power is amplified using a general power amplifier as described above, non-linear distortion occurs, causing deterioration of error rate characteristics and out-of-band radiation. For this reason, various methods have been proposed in order to avoid the generation of nonlinear output signals in the power amplifier.

  One of them is clipping processing of the in-phase signal (I) and the quadrature signal (Q) in the transmission data baseband signal processing unit. Typical examples of clipping processing include rectangular clipping and circular clipping. Since the rectangular clipping circuit performs the clipping process independently for each of the baseband signal I and Q signals, it can be realized with a relatively small circuit scale. However, if only one of the signals exceeds the clip level, Only the above signal is subjected to clipping processing, and the other signal is not subjected to clipping processing, so that there is a drawback that a phase error occurs in the processed data and the EVM (Error Vector Magnitude) of the modulated wave deteriorates.

  On the other hand, in the circular clipping process, both the I signal and the Q signal are clipped along the phase, so that a phase error that causes a problem in the rectangular clipping process does not occur. Since processing such as reading increases, the circuit scale increases and power consumption increases.

  In order to solve such a problem, Patent Document 1 adopts a polygon clipping unit in which a series configuration of a rectangular clip unit and a phase rotation unit is connected in a plurality of stages, thereby performing arithmetic processing, data reading, and the like. A technique for reducing the amount of processing and obtaining a clipping characteristic close to a circular clipping process has been proposed. In Patent Document 2, a clipping technique using a CORDIC (coordinate rotation digital computer) calculation technique is proposed.

  In Patent Document 3, in a clipping circuit that employs polygon clipping means, a signal that does not pass through the clipping circuit is output as it is for a signal that does not require power limitation, and only for a signal that requires clipping processing. By selectively outputting a signal that has been subjected to clipping processing, the amount of processing such as computation processing and data reading is suppressed, and clipping characteristics close to circular clipping processing are obtained, and the occurrence of modulation errors associated with clipping processing is minimized. Technologies that limit it to the limit have been proposed.

  FIG. 10 is a functional block diagram showing a power clipping circuit adopting the polygon clipping means proposed in Patent Document 3. RI and RQ, which are orthogonal components after performing baseband signal processing, are timing adjustments. The signal is input to the unit 205 and the hexagonal clipping means 201, and either one of the signals is selected according to the amplitude value of the baseband signal and output as an I / Q signal.

  The quadrature components RI and RQ after the baseband signal processing are also input to the absolute value conversion circuit 202, and the I component and the Q component are each processed into an absolute value in the absolute value conversion circuit 202, and are supplied to the adder 203. It is input and added. Then, an addition value (| RI) of a signal level (clip level = RL) that needs to be clipped in advance as a radio communication system and an amplitude value of an absolute value baseband signal that is an output of the adder 203 | + | RQ |) is compared by the comparator 204.

  As a result of this comparison, when the added value (| RI | + | RQ |) is equal to or higher than the clip level RL, the selector 206 is controlled via the AND gate 207 and the signal after the clip processing via the hexagonal clipping means 201 is performed. Is output. On the other hand, when the added value is smaller than the clip level RL, the selector 206 is controlled via the AND gate 207, and a signal after timing adjustment via the timing adjuster 205 is output.

  This is because if the hexagonal clipping process is performed on all signals, the clipping means 201 is passed through even a small level signal that does not need to be power limited, and a modulation error is caused accordingly. In order to avoid this, the clipping process is selectively performed only on a signal that may need the clipping process.

  Note that the timing adjuster 205 adjusts the output timings of the signal after the clipping process that has passed through the hexagonal clip means 201 and the signal that has not passed through the hexagonal clip means 201. The timing adjuster 205 is constituted by buffers having the number of stages corresponding to the time required for the clipping process of the hexagonal clip means 201. The AND gate 207 is for controlling ON / OFF of the clipping process by an external command.

JP 2004-072626 A JP-T-2004-516716 WO 2005/046154 A1

FIG. 11 shows the relationship between the clipping level RL on the IQ coordinate of the clipping circuit shown in FIG. 10 and the clipping process. The square (121) drawn inside has a distance from the coordinate center to each vertex. Is equal to the clip level RL,
| RI | + | RQ | = RL
It is a square represented by The hexagon 122 on the outside of each square 121 inscribed at each vertex indicates the clip level boundary of the hexagonal clip means 201 in FIG.

  Therefore, in the clipping circuit shown in FIG. 10, at the signal level of the inner portion (123) of the square 121, the signal from the timing adjuster 205 (the signal not passing through the hexagonal clipping means 201) is selected and output. At the signal level of the outer portion of the square 121, the signal from the hexagonal clipping means 201 is selected and output.

  However, in the clipping circuit shown in FIG. 10, the signal level that is actually subjected to the amplitude limitation by the hexagonal clipping means 201 is the signal level in the region indicated by 125 outside the hexagonal 122, and the signal level is the square 121. In the region (124) between the hex and the hexagon 122, the signal path through the hex clipping means 201 is selected, but the amplitude is not limited by the hex clipping means 201.

  As described above, in the clipping circuit shown in FIG. 10, a part of the signal point (signal in the region 124) that has an amplitude below the clipping level and does not need to be clipped originally and should not be affected by clipping. Since the signal passes through the clipping processing circuit and is not subjected to the amplitude limitation, the calculation processing by the hexagonal clipping unit 201 is received. Therefore, a gap caused by the calculation processing is generated between the signal input to the hexagonal clipping unit 201 and the output signal. Occurs, resulting in a modulation error.

  In view of the above problems, an object of the present invention is to provide a clipping circuit having means for selecting whether to pass or bypass a clipping processing circuit according to the signal level. Therefore, it is possible to provide a means capable of suppressing the generation of a modulation error while suppressing the circuit scale by reducing the output region as much as possible.

  According to the present invention, in a power clipping circuit that performs clipping processing on an orthogonal signal and performs power limitation, the sum of the squares of the I component and Q component of the orthogonal signal is greater than a square value of a predetermined clip level. When the orthogonal signal processed by the clipping processing means is selected and output, and the sum of the squares of the I component and Q component of the orthogonal signal is less than or equal to the square value of the clip level, Output signal selection means for selecting and outputting the orthogonal signal that does not pass through the clipping means is provided.

  The clipping processing means can be configured as a polygon clipping means in which a series configuration of a rectangular clip means and a phase rotation means is connected in a plurality of stages.

  The signal path that does not pass through the clipping means may be provided with a timing adjustment means that adjusts and outputs the orthogonal signal for a time corresponding to the processing time of the clipping means.

  More specifically, the power clipping circuit of the present invention includes a clipping processing means for inputting a quadrature signal and outputting a signal subjected to clipping processing, and a time corresponding to a processing time of the clipping processing means for inputting the orthogonal signal. Timing adjusting means for outputting the quadrature signal delayed by a square, squaring means for inputting the quadrature signal and calculating the square values of the I component and Q component of the quadrature signal, and the squared The adding means for adding the I component and Q component of the orthogonal signal, and the sum of the squares of the added I component and Q component of the orthogonal signal and the square value of the predetermined clip level are compared. When the sum of the squares of the I component and Q component of the orthogonal signal is greater than the square value of the clip level, the first control signal is output, A comparison means for outputting a second control signal when the sum of the squares of the component and the Q component is less than or equal to the square value of the clip level, and when the first control signal is received from the comparison means And selecting and outputting the quadrature signal output from the clipping processing means, and selecting the quadrature signal output from the timing adjustment means when receiving the second control signal from the comparison means. Output signal selection means.

  Alternatively, a clipping processing unit that inputs an orthogonal signal and outputs a signal subjected to clipping processing, and a timing adjustment unit that inputs the orthogonal signal and outputs the orthogonal signal delayed by a time corresponding to a processing time of the clipping processing unit A squaring means for inputting the quadrature signal and calculating a square value of each of the I component and the Q component of the quadrature signal, and an addition for adding the squared I component and Q component of the quadrature signal Means for comparing the sum of the squares of the I component and the Q component of the added quadrature signal with a square value of a predetermined clip level, and comparing the I component and the Q component of the quadrature signal. When the sum of the squares is larger than the square value of the clip level, the first control signal is output, and the sum of the squares of the I component and Q component of the orthogonal signal Comparing means for outputting a second control signal when the clip level is less than or equal to the square value of the clip level, and inputting the orthogonal signal to the clipping processing means when receiving the first control signal from the comparing means And a signal selecting means for inputting the orthogonal signal to the timing adjusting means when receiving the second control signal from the comparing means.

In the present invention, RI ² + RQ ^{2 obtained} by squaring and adding RI and RQ, which are quadrature components after processing the baseband signal, are added to the clipping processing circuit. Since it is determined by comparison with the power RL ² , the range in which a signal that does not necessarily need to be power limited is input to the clipping processing circuit is minimized, and the signal that needs to be power limited is efficiently clipped processing circuit Will be entered.

  According to the present invention, since it is possible to output a signal having an amplitude level that does not need to be input to the clipping unit without passing through the clipping unit as much as possible, the occurrence of a modulation error in the clipping circuit system is minimized. To the limit.

  FIG. 1 is a functional block diagram of a clipping circuit showing an embodiment of the present invention, and FIG. 2 is a diagram showing a relationship between a clipping level RL and clipping processing on the IQ coordinates of the clipping circuit of the present embodiment.

  In FIG. 1, RI and RQ, which are orthogonal components after baseband signal processing, are input to the timing adjuster 105, the hexagonal clipping unit 101, and the squaring circuit 102, respectively. In the squaring circuit 102, the I component and the Q component are respectively squared, input to the I / Q adder 103, and added.

Then, a square (RL ² ) of a signal level (clip level = RL) that needs to be determined in advance as a radio communication system, and an I component of a baseband signal that is an output of the I / Q adder 103 The value (RI ² + RQ ² ) obtained by adding the square values of the Q component and Q component is compared by the comparator 104.

As a result of this comparison, when the added value (RI ² + RQ ² ) is larger than the square value (RL ² ) of the clip level RL, the selector 106 is controlled via the AND gate 107 and the hexagonal clipping means 101 is passed. The signal after clip processing is output. On the other hand, when the added value (RI ² + RQ ² ) is less than or equal to the square value (RL ² ) of the clip level RL, the selector 106 is controlled via the AND gate 107 and the timing after the timing adjustment via the timing adjuster 105 is adjusted. A signal is output.

  The timing adjuster 105 adjusts the output timings of the signal after clipping processing that has passed through the hexagonal clipping means 101 and the signal that has not passed through the hexagonal clipping means 101. The timing adjuster 105 is composed of buffers having the number of stages corresponding to the time required for the clipping process of the hexagonal clip means 101. The AND gate 107 is for controlling ON / OFF of the clipping process by an external command.

  FIG. 3 is a functional block diagram showing an example of the hexagonal clip means 101 in the present embodiment. In order from the input stage, a square clip circuit 301, a + π / 4 phase rotation unit 302, a square clip circuit 303, and −π / 8. The phase rotation unit 304, the square clip circuit 305, the −π / 4 phase rotation unit 306, the square clip circuit 307, the + π / 8 phase rotation unit 308, and the amplitude adjustment unit (amplitude scaling unit) 309 are included. The hexagonal clip means 101 has the same configuration as the conventional hexagonal clip means 201 shown in FIG.

  The rectangular clip circuits 301, 303, 305, and 307 all have the same circuit configuration, and a known configuration (see, for example, Patent Document 1) is used. By inputting the clip level, the input signals I and Q components (Ich, Qch) are independent of each other, that is, the I signal is clipped in the I-axis direction and the Q signal is clipped individually in the Q-axis direction. The phase rotation unit 302 rotates the phase of the input signal by + π / 4, the phase rotation unit 304 rotates the phase of the input signal by −π / 8, and the phase rotation unit 306 rotates the phase of the input signal by −π / 4. The phase rotation unit 308 rotates the phase of the input signal by + π / 8. Further, the amplitude adjustment unit (amplitude scaling unit) 309 returns the amplitude value of the signal that has become smaller than the actual value due to square clipping or phase rotation to the amplitude value (level) of the original input signal (compensation adjustment). To do).

  4 to 7 are specific examples of the phase rotation units 302, 304, 306, and 308 of the hexagonal clip unit 101, and FIG. 8 illustrates the amplitude adjustment unit (amplitude scaling unit) 309 of the hexagonal clip unit 101. It is a specific example. FIG. 9 is a diagram illustrating a state in which the signal level changes with the phase rotation in each phase rotation unit. These configurations can also be realized by the same configuration as the conventional hexagonal clip means 201 shown in FIG.

The clipping circuit of the present embodiment is provided with a squaring circuit that squares the I and Q signals in place of the absolute value converting circuit 202 in the conventional clipping circuit shown in FIG. The value obtained by squaring RI and RQ and adding them (RI ² + RQ ² ) and the square value of the clipping level RL Judgment is made by comparison with (RL ² ). As a result, it is possible to reduce as much as possible the signal area in which signals that do not need to be power limited are output through the clipping processing circuit.

  Next, the operation of the present embodiment will be described in detail with reference to FIGS.

  When an I signal and a Q signal, which are orthogonal components of the baseband signal, are input from the baseband signal processing unit (not shown) to the clipping circuit unit, the I and Q signals are supplied to the 16-side clipping means 101 and 16 The rectangular clipping process is performed and output to the selector 106. The I and Q signals are also input to the timing adjuster 105, and the timing adjustment corresponding to the time required for the hexagonal clipping process is performed and output to the selector 106.

The above I and Q signals are also input to the squaring circuit 102 and squared. The squared I and Q signals RI ² and RQ ² are input to the I / Q adder 103 to become RI ² + RQ ² , and this addition output is input to the comparator 104. The comparator 104 compares the level of the signal input from the I / Q adder 103 with the square value RL ^{2 of the} clip level, determines the magnitude thereof, and uses it as a selection signal for the selector 106. When the sum of the square amplitudes of the input signals (RI ² + RQ ² ) is larger than the square value (RL ² ) of the clip level, the selector 106 outputs a signal that has passed through the hexagonal clip means 101 and vice versa. When the value is less than or equal to the square value (RL ² ), a signal that has passed through the timing adjuster 105 is output.

  In this selection by the selector 106, if a hexagonal clipping process is performed on all signals, a modulation error due to the clipping process occurs even for a signal that does not need to be power limited. In order to avoid this, the clipping process is performed. This is for selectively performing clipping processing only on a signal that requires. Note that the AND gate 107 can easily perform clipping control mask control by an external command.

The I and Q signals input to the hexagonal clipping means 101 are first subjected to rectangular clipping in the rectangular clipping circuit 301. At this time, the clip level RL0 is
RL0 = RL
And set externally. The signal clipped by the square clipping circuit 301 is rotated in phase by + π / 4 in the phase rotation unit 302.

  As shown in FIG. 4, the phase rotation unit 302 has a known configuration including adders 401 and 402 and a sign inverter 403, and the I signal and the Q signal are added by the adder 402 to form a Q signal. And an inverted signal of the Q signal are added by an adder 401 to become an I signal. By this + π / 4 phase rotation, the signal amplitude changes by √2.

The output of the phase inverting unit 302 is input to the rectangular clip circuit 303. At this time, the clip level RL1 is
RL1 = RL0 × √2 = RL√2
And set externally. This is because the signal phase is rotated by + π / 4 by the phase rotation unit 302 and the amplitude has changed by a factor of √2, so the clip level must be increased accordingly. Note that FIG. 9A shows a state in which the level changes by √2 when the phase is rotated by π / 4, and can be obtained by the three-square theorem.

  Next, the signal phase is rotated by −π / 8 by the phase rotation unit 304. As shown in FIG. 5, the phase rotation unit 304 has a known configuration including adders 501 and 502, multipliers 503 and 504, and a sign inverter 505. The I signal and the coefficient (n bits) are multiplied by the multiplier 503, the lower n bits of the multiplication output are discarded, the sign is inverted by the sign inverter 505, and the Q signal is added by the adder 502. It becomes. Further, the Q signal and the coefficient are multiplied by the multiplier 504, the lower n bits of the multiplication output are discarded, and the adder 501 adds the signal to the I signal to become an I signal. By this -π / 8 phase rotation, the signal amplitude changes by {square root} {2 × (2−√2)} times.

The output of the phase rotator 304 is input to the rectangular clip circuit 305, and the clip level RL2 at this time is determined in consideration of the amplitude change of the phase rotator 304.
RL2 = RL1 × √ {2 × (2−√2)}
= RL0 × √2 × √ {2 × (2-√2)}
= RL × 2 × √ (2-√2)
And is set externally. FIG. 9 (2) shows a state in which the level changes by √2 × √ (2-√2), that is, √ {2 × (2-√2)}, when the phase is rotated by π / 8. .

  Next, the signal phase is rotated by −π / 4 by the phase rotation unit 306. As shown in FIG. 6, the phase rotation unit 306 has a known configuration including adders 601 and 602 and a sign inverter 603. The I signal and the Q signal are added by an adder 601 to be an I signal, and the sign inversion signal of the I signal and the Q signal are added by an adder 602 to be a Q signal. The signal amplitude is changed by a factor of √2 by this −π / 4 phase rotation, as in the previous phase rotation unit 302.

The output of the phase rotation unit 306 is input to the rectangular clip circuit 307, and the clip level RL3 at this time takes into account the amplitude change of the phase rotation unit 306,
RL3 = RL2 × √2
= RL × 2√2 × √ (2-√2)
And is set externally. The output of the rectangular clip circuit 307 is input to the phase rotation unit 308 and rotated in phase by + π / 8. As shown in FIG. 7, the phase rotation unit 308 has a known configuration including adders 701 and 702, multipliers 703 and 704, and a sign inverter 705.

  The I signal is multiplied by a coefficient (n bits) by a multiplier 703, the lower n bits of the multiplication output are discarded, and added to the Q signal by an adder 702 to become a Q signal. The Q signal is multiplied by a coefficient by a multiplier 704, the lower n bits of the multiplication output are discarded, the sign is inverted by a sign inverter 705, and the I signal is added to an I signal by an adder 701.

  By this + π / 8 phase rotation, the amplitude changes by {square root} {2 × (2−√2)} times. It should be noted that the phase rotation amount can be controlled by controlling the value of the coefficient n in FIG. 7 and the previous FIG. 5, but in this example, since it is ± π / 8, a fixed relationship corresponding thereto is obtained. A numerical value is entered.

  Finally, the amplitude adjustment unit 309 returns the amplitude value that is larger than the actual amplitude value to the original input signal level by square clipping or phase rotation. FIG. 8 shows an example of the configuration of the amplitude adjustment unit 309 and includes multipliers 801 and 802. The I signal is multiplied by a coefficient (n bits) by a multiplier 801 to be an I signal, and the Q signal is multiplied by a coefficient (n bits) by a multiplier 802 to be a Q signal. The amplitude adjustment at this time is (2 + √2) / 8 times. The above is the hexagonal clipping processing in this embodiment.

On the other hand, as described above, the I and Q signals are input to the squaring circuit 102 and squared, and the squared RI ² and RQ ² are input to the I / Q adder 103 to become RI ² + RQ ² , The added output and the clip level square value RL ² are compared by the comparator 104. If RI ² + RQ ² is larger than the clip level square value RL ² , it passes through the hexagonal clip means 101. In contrast, when the clip level is less than the square value RL ² of the clip level, the signal that has passed through the timing adjuster 105 is selected and output. The relationship between the level RL and the clip processing is as shown in FIG.

In FIG. 2, a circle 111 inscribed in the regular hexagon 112 indicating the clip level boundary of the hexagonal clip means 101 has a radius equal to the clip level RL.
RI ² + RQ ² = RL ²
It is a circle represented by Therefore, in the case of the signal level in the region of the circle 111, a signal that does not pass through the hexagonal clipping means 101, that is, a signal that has passed through the timing adjuster 105 in FIG.

  The hexagon 112 circumscribing the circle 111 indicates the clip level boundary of the hexagonal clip means 101 of FIG. 1, so in the case of a signal at a level located in the area (115) outside the hexagon 112, In the case of a signal that is subjected to amplitude limitation by the hexagonal clipping means 101 but is at a level located in the region (114) between the circle 111 and the hexagonal shape 112, the signal passes through the hexagonal clipping means 101 but is not limited in amplitude. .

The relationship between the clip level RL and the clip processing in the clipping circuit of this embodiment shown in FIG. 2 is the same as the relationship between the clip level RL and the clip processing in the conventional clipping circuit shown in FIG.
| RI | + | RQ | = RL
As is clear from the case of determining whether to use the output from the clip processing means based on the above, in this embodiment, the region (114) that passes through the clip processing means even though it does not need to be subjected to amplitude processing. Is much smaller than the area (124 in FIG. 11) that passes through the clip processing means although it is not necessary to perform amplitude processing in the conventional clipping circuit.

  Therefore, according to the present embodiment, the hexagonal clipping means can obtain a clipping characteristic close to that of the circular clipping process while suppressing the amount of processing such as arithmetic processing and data reading, and also does not require the clipping process. Since most of the levels can be output without passing through the clipping processing means, it is possible to configure a clipping circuit that can suppress the circuit scale and minimize the occurrence of modulation errors.

  In the clipping circuit of the above embodiment, the hexagonal clipping means is adopted as the clipping processing means. However, the number of stages of the rectangular clip circuit and the number of stages of the phase rotation unit in FIG. By changing the adjustment value of the (amplitude scaling unit) accordingly, a clipping circuit using polygon clipping means other than a hexagon can be realized.

  In the embodiment shown in FIG. 1, the selector 106 is provided on the output side of the circuit, and the output of the timing adjuster 105 or the output of the hexagonal clip means 101 is selected according to the output of the comparator 104. However, the selector 106 is provided in the input stage, and whether the quadrature signal after baseband signal processing is input to the timing adjuster 105 or the hexagonal clipping unit 101 depending on the output of the comparator 104 It is good also as a structure which selects. With such a configuration, signals that do not need to be processed are not input to the timing adjuster 105 and the hexagonal clipping unit 101, so that useless processing can be omitted.

It is a functional block diagram of a clipping circuit showing an embodiment of the present invention. It is a figure which shows the relationship between the clipping level RL on the IQ coordinate of the clipping circuit of this embodiment, and a clipping process. It is a functional block diagram which shows the example of the 16-sided clip means used by this embodiment. FIG. 4 is a circuit diagram of a phase rotation unit 402 in the hex clip means 101 of FIG. 3. FIG. 4 is a circuit diagram of a phase rotation unit 404 in the hex clip means 101 of FIG. 3. FIG. 4 is a circuit diagram of a phase rotation unit 406 in the hex clip means 101 of FIG. 3. FIG. 4 is a circuit diagram of a phase rotation unit 408 in the hex clip means 101 of FIG. 3. FIG. 4 is a circuit diagram of an amplitude adjustment unit 409 in the hex clip means 101 of FIG. 3. It is a figure explaining the change of the clip level (RL) at the time of phase rotation. It is a functional block diagram of a conventional clipping circuit. It is a figure which shows the relationship between the clipping level RL on the IQ coordinate of the conventional clipping circuit shown in FIG. 10, and a clipping process.

Explanation of symbols

101 hexagonal clip means 102 square circuit 103 I / Q adder 104 comparator 105 timing adjustment period 106 selector 107 AND gate

Claims (10)

In a power clipping circuit that outputs a power-limited orthogonal signal by clipping the orthogonal signal,
When the sum of the squares of the I component and the Q component of the orthogonal signal is larger than a predetermined square value of the clip level, the orthogonal signal processed by the clipping processing means is selected and output, Output signal selection means for selecting and outputting the orthogonal signal that does not pass through the clipping means when the sum of the squares of the I component and Q component of the orthogonal signal is equal to or less than the square value of the clip level. A power clipping circuit characterized by comprising:   2. The power clipping circuit according to claim 1, wherein the clipping processing unit is configured as a polygon clipping unit in which a series configuration of a square clipping unit and a phase rotation unit is cascade-connected in a plurality of stages.   3. The signal path that does not pass through the clipping means is provided with timing adjustment means that adjusts and outputs the orthogonal signal for a time corresponding to the processing time of the clipping means. The power clipping circuit described. Clipping processing means for inputting an orthogonal signal and outputting a signal subjected to clipping processing;
Timing adjusting means for inputting the orthogonal signal and outputting the orthogonal signal delayed by a time corresponding to the processing time of the clipping processing means;
Squaring means for inputting the orthogonal signal and calculating square values of the I component and the Q component of the orthogonal signal;
Adding means for adding the I and Q components of the orthogonal signal squared by the squaring means;
The sum of the squares of the I component and Q component of the orthogonal signal added by the adding means is compared with the square value of a predetermined clip level, and the I component and Q component of the orthogonal signal are compared. When the sum of the squares of each is larger than the square value of the clip level, the first control signal is output, and the sum of the squares of the I component and Q component of the orthogonal signal is 2 of the clip level. Comparing means for outputting a second control signal when the value is less than or equal to a multiplier value;
When the first control signal is received from the comparison means, the orthogonal signal output from the clipping processing means is selected and output, and when the second control signal is received from the comparison means, Signal selection means for selecting and outputting the orthogonal signal output from the timing adjustment means;
A power clipping circuit comprising: Clipping processing means for inputting an orthogonal signal and outputting a signal subjected to clipping processing;
Timing adjusting means for inputting the orthogonal signal and outputting the orthogonal signal delayed by a time corresponding to the processing time of the clipping processing means;
Squaring means for inputting the orthogonal signal and calculating square values of the I component and the Q component of the orthogonal signal;
Adding means for adding the I and Q components of the orthogonal signal squared by the squaring means;
The sum of the squares of the I component and Q component of the orthogonal signal added by the adding means is compared with the square value of a predetermined clip level, and the I component and Q component of the orthogonal signal are compared. When the sum of the squares of each is larger than the square value of the clip level, the first control signal is output, and the sum of the squares of the I component and Q component of the orthogonal signal is 2 of the clip level. Comparing means for outputting a second control signal when the value is less than or equal to a multiplier value;
When the first control signal is received from the comparison means, the orthogonal signal is input to the clipping processing means, and when the second control signal is received from the comparison means, the orthogonal signal is input to the timing. Signal selection means for input to the adjustment means;
A power clipping circuit comprising:   6. The power clipping circuit according to claim 4, wherein the clipping processing unit is configured as a polygon clipping unit in which a series configuration of a square clipping unit and a phase rotation unit is cascade-connected in a plurality of stages.   A wireless transmission device comprising the power clipping circuit according to claim 1. In a power clipping method for clipping a quadrature signal to output a power limited quadrature signal,
When the sum of the squares of the I component and Q component of the orthogonal signal is greater than a square value of a predetermined clip level, the orthogonal signal that has passed through the clipping processing path is selected and output, When the sum of the squares of the I component and Q component of the orthogonal signal is equal to or less than the square value of the clip level, the orthogonal signal that does not pass through the clipping processing path is selected and output. Power clipping method.   9. The power clipping method according to claim 8, wherein the clipping process is a process of executing polygon clipping by repeating square clipping and phase rotation a plurality of times. 10. The power clipping method according to claim 8, wherein when the clip level is equal to or less than a square value of the clip level, the orthogonal signal that has been delay-adjusted by a time corresponding to the time of the clipping process is output.

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