JP2007293816A - Processor device and processing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute instructions fast by predicting local slack with simpler constitution than conventional techniques. <P>SOLUTION: A processor predicts predicted slack which is a predicted value of local slack of an instruction to be executed and executes the instruction using the predicted slack. A slack table is referred to upon execution of an instruction to obtain predicted slack of the instruction and execution latency is increased by an amount equivalent to the obtained predicted slack. Then, it is estimated, based on behavior exhibited upon execution of the instruction, whether or not the predicted slack has reached target slack which is an appropriate value of current local slack of the instruction. The predicted slack is gradually increased each time the instruction is executed, until it is estimated that the predicted slack has reached the target slack. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a processor device that predicts local slack of an instruction executed by a processor and executes the instruction, and a processing method of the processor device.

  In recent years, many studies on speeding up of microprocessors and reduction of power consumption using information on critical paths have been conducted (for example, see Non-Patent Documents 2, 3, 8, 11, and 13). A critical path is a path composed of a dynamic instruction sequence that determines the execution time of the entire program. If the execution latency of instructions on the critical path is increased even by one cycle, the number of execution cycles of the entire program increases. However, there are only two types of critical path information, whether the instruction is on the critical path or not, and the instruction can only be classified into two types. In addition, the number of instructions on the critical path is significantly smaller than the number of instructions on the non-critical path, and when the instruction processing is divided for each category, the load balance is poor. Therefore, the application range of critical path information becomes narrow.

  On the other hand, a technique using instruction slack instead of the critical path has been proposed (see, for example, Non-Patent Documents 4 and 5). The slack of an instruction is the number of cycles that can increase the execution latency of the instruction without increasing the number of execution cycles of the entire program. Knowing the instruction slack, not only whether each instruction is on the critical path, but also how much the execution latency of instructions not on the critical path can be increased without affecting program execution. I understand. Therefore, if slack is used, the instructions can be divided into three or more categories, and further, the imbalance in the number of instructions belonging to each category can be alleviated.

  The slack of each dynamic instruction is a value having a certain range. The minimum value of slack is always 0. On the other hand, the maximum value of slack (global slack (see, for example, Non-Patent Document 5)) is dynamically determined. In order to make the best use of slack, it is necessary to seek global slack. However, in order to obtain the global slack of an instruction, the influence of the increase in execution latency on the number of execution cycles of the entire program must be examined during the execution of the program. Therefore, it is very difficult to seek global slack.

  Therefore, a method for predicting local slack (for example, see Non-Patent Document 5) instead of global slack has been proposed (for example, see Non-Patent Documents 6 and 10). The local slack of an instruction is the maximum slack value that does not affect the execution of subsequent instructions as well as the number of execution cycles of the entire program. The local slack of a certain instruction can be easily obtained simply by paying attention to the succeeding instruction having a dependency relationship. In the conventional method, the local slack of the instruction is obtained from the difference between the time when the instruction defines the register data or memory data and the time when the data is first referenced. Predict local slack.

  However, in the conventional method, it is necessary to prepare a table for holding the time at which the data is defined and an arithmetic unit for obtaining the time difference. In parallel with the execution of the program, it is necessary to refer to / update the table holding the defined time and subtract the time. The cause of these costs is the direct calculation of local slack using data definition / reference times.

  Next, slack will be described below.

  FIG. 1A is a diagram showing an example of a program including a plurality of instructions used for explaining slack according to the prior art, and FIG. 1B is a process of executing each instruction of the program on a processor device. It is a timing chart which shows. In FIG. 1A and FIG. 1B, a node indicates an instruction, and an edge indicates a data dependency between instructions. The vertical axis indicates the cycle in which the instruction is executed. The length of the node indicates an instruction execution latency (referred to as an execution delay time). The execution latency is two cycles for the instruction i1 and the instruction i4, and one cycle for the other instructions.

  Here, the slack of the instruction i0 is considered. When the execution latency of the instruction i0 is increased by 3 cycles, execution of the instructions i3 and i5 that depend directly or indirectly on the instruction i0 is delayed. As a result, the instruction i5 is executed at the same time as the instruction i6 executed last in the program. Therefore, if the execution latency of the instruction i0 is further increased, the number of execution cycles of the entire program increases. That is, the global slack of the instruction i0 is 3. As described above, in order to obtain the global slack of a certain instruction, it is necessary to examine the influence of the increase in the execution latency of the instruction on the execution of the entire program. Therefore, it is very difficult to determine global slack.

  On the other hand, when the execution of the instruction i0 is increased by two cycles, the execution of the subsequent instruction is not affected. However, if the execution latency is further increased, execution of the instructions i3 and i5 that are directly or indirectly dependent on each other is delayed. That is, the local slack of the instruction i0 is 2. Thus, in order to obtain the local slack of a certain instruction, attention should be paid to the influence on the instruction depending on the instruction. Therefore, local slack can be determined relatively easily.

  Next, a slack prediction method according to the prior art will be described below. For example, by subtracting 1 from the difference between time 0 when the instruction i0 in FIG. 1B defined data and time 3 when the data was first referred to by the instruction i3, the local slack of the instruction i0 is 2 Calculate that Based on this, the local slack in the next execution of the instruction i0 is predicted to be 2.

  FIG. 2 is a block diagram illustrating a configuration of a processor device including a local slack prediction mechanism according to the related art. In FIG. 2, the processor 10 includes a fetch unit 11 that fetches an instruction from the main storage device 9, a decode unit 12, an instruction window (I-win) 13, a register file (RF) 14, and a plurality of An execution unit (EU) 15 and a reorder buffer (ROB) 16 are provided. On the right side of the processor 10, a local slack prediction mechanism according to the prior art is shown. The local slack prediction mechanism includes a register definition table 2 for holding a time at which register data is defined, a memory definition table 3 for holding a time at which memory data is defined, and these two definition tables 2, 3 includes a multiplexer 4 that selectively switches the output from 3 and outputs a defined time, and a subtractor 5 that is an arithmetic unit for obtaining a difference between the defined time and the current time. Further, the local slack prediction mechanism includes a slack table 6 for holding local slack for each instruction. Here, the register definition table 2, the memory definition table 3, and the slack table 6 are configured by a storage device for storing each table.

  The operation of the conventional mechanism will be briefly described using local slack of the instruction i0 in FIG. 1B as an example. When the instruction i0 defines data, it records the current time 0 in the definition table together with the instruction i0 itself. i3} obtains the instruction i0 defining the data and the time (definition time) 0 defining the data from the definition tables 2 and 3 when using the data. Then, the local slack 2 of the instruction i0 is obtained by further subtracting 1 from the difference between the current time 3 and the definition time 0. The obtained slack is recorded in the entry corresponding to the instruction i0 in the slack table 6. When the instruction i0 is next fetched by the fetch unit 11, the slack table 6 is referred to, and the local slack of the instruction i0 is predicted to be 2 from the obtained slack.

  As described above, in the conventional method, it is necessary to prepare the definition tables 2 and 3 and the subtracter 6, which increases the hardware cost. In addition, since the definition tables 2 and 3 must be referred to and updated and the time is subtracted in parallel with the execution of the program, a high-speed operation is required, which may greatly affect power consumption. The cause of such a problem is that the local slack is directly calculated by paying attention to the definition of data and the reference time.

JP 2000-353099 A. Japanese Patent Application Laid-Open No. 2004-286381. D. Burger et al., "The Simplescalar Tool Set Version 2.0", Technical Report 1342, Department of Computer Sciences, University of Wisconsin-Madison, June 1997. Nobuhiro Chiyo et al., “Proposal of Critical Path Predictor for Low Power Consumption Processor Architecture”, Research Report of Information Processing Society of Japan, 2002-ARC-149, published by Information Processing Society of Japan, August 2002. B. Fields et al., “Focusing Processor Policies via Critical-Path Prediction”, In Proceedings of ISCA-28, June 2001. B. Fields et al., "Using Interaction Costs for Microarchitectural Bottleneck Analysis", In proceedings of MICRO-36, December 2003. B. Fields et al., “Slack: Maximizing Performance under Technological Constraints”, In Proceedings of ISCA-29, May 2002. Fukuyama Tomohisa et al., “Instruction Scheduling for Power Saving Architecture Using Slack Prediction”, Advanced Computational Infrastructure System Symposium, ACSIS 2005, May 2005. J. L. Hennessy et al., "Computer Architecture: A Quantitative Approach", 2nd Edition, Morgan Kaufmann Publishing Incorporated, San Francisco, California, U.S.A., 1996. Ryotaro Kobayashi et al., "Instruction Issuing Mechanism in Clustered Superscalar Processor Focusing on Longest Path of Dataflow Graph", 2001 Parallel Processing Symposium JSPP 2001, June 2001. M. Levy, "Samsung Twists ARM Past 1GHz", Microprocessor Report 2002-10-16, October 2002. Liu Koji et al., “Slack Prediction for Criticality Prediction”, Advanced Computational Infrastructure System Symposium SACSIS 2004, May 2004. J. S. Seng et al., “Reducing Power with Dynamic Critical Path Information”, In Proceedings of MICRO-34, December 2001. P. Shivakumar et al., “CACTI 3.0: An Integrated Cache Timing and Power, and Area Model”, Compaq WRL Report 2001/2, August 2001. E. Tune et al., “Dynamic Prediction of Critical Path Instructions”, In Proceedings of HPCA-7, January 2001.

  According to the above-described prediction method according to the prior art, it is possible to accurately predict local slack to some extent. However, in addition to the slack table, two definition tables and a computing unit are necessary, and the prediction mechanism is hard. Wear costs are extremely high. In parallel with program execution, definition table reference / update and time subtraction must be performed at a high speed, and an increase in power consumption due to the operation of the prediction mechanism may be difficult to ignore.

  Also, actual local slack (actual slack) changes dynamically. Therefore, a method corresponding to this change has been proposed (see, for example, Non-Patent Document 6). However, there is a problem in that the actual slack change cannot be sufficiently followed and there is a possibility that the performance may be degraded.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to perform prediction of local slack and execution of program instructions at high speed with a simple configuration compared to the prior art, and processing of the processor apparatus It is to provide a method.

According to a first aspect of the present invention, there is provided a processor device that predicts predicted slack, which is a predicted value of local slack of an instruction executed by the processor device, and executes the instruction using the predicted slack.
Storage means for storing a slack table including the predicted slack;
Setting means for acquiring predicted slack of the instruction with reference to the slack table upon execution of the instruction and increasing execution latency by the amount of the acquired predicted slack;
An estimation means for estimating whether or not the predicted slack has reached the target slack, which is an appropriate value of the current local slack of the instruction, based on the execution behavior of the instruction;
Update means for gradually increasing the predicted slack every time the instruction is executed until the estimated means estimates that the predicted slack has reached the target slack.

  In the processor device, the updating means may change a parameter used for updating the slack according to the predicted slack value so as to suppress a decrease in performance of the processor device while maintaining the number of slack instructions. Features.

  Further, in the processor device, the updating means changes a parameter used for updating the slack according to whether or not the predicted slack is equal to or greater than a predetermined threshold value.

Furthermore, in the processor device, the estimation means includes
(A) A branch prediction error occurred during execution of the instruction,
(B) A cache miss occurred during execution of the instruction;
(C) Operand forwarding for the subsequent instruction has occurred,
(D) that store data forwarding has occurred for the subsequent instruction;
(E) the instruction is the oldest instruction in the instruction window;
(F) the instruction is the oldest instruction in the reorder buffer;
(G) The instruction is an instruction that passes the execution result to the oldest instruction in the instruction window.
(H) The instruction is an instruction that passes the execution result to the most subsequent instructions among the instructions executed in the same cycle;
(I) By passing the execution result of the instruction, at least one of the fact that the number of subsequent instructions that can be executed becomes equal to or greater than a predetermined determination value is used as a condition for establishing the above estimation The arrival of the predicted slack to the target slack is estimated.

Furthermore, in the processor device, when a condition for establishing that the predicted slack has reached the target slack is satisfied, the counter value is increased or decreased, and the condition for establishing the estimation is not satisfied. Further comprising a reliability counter whose counter value is decreased or increased when
The updating means increases the prediction slack on the condition that the counter value of the reliability counter becomes an increase determination value, and the prediction on the condition that the counter value of the reliability counter becomes a decrease determination value. It is characterized by reducing slack.

  In the processor device, the increment or decrement of the counter value when the condition for establishment of the estimation is satisfied in the reliability counter is the decrease or increase of the counter value when the condition for establishment of the estimation is not established. It is characterized by being set larger than the amount.

  Further, in the processor device, the increment and decrement of the counter value are set to be different depending on the type of each instruction.

  Still further, in the processor device, the amount of update of the predicted slack of each instruction by the update unit is set to be different depending on the type of each instruction.

  In the processor device, an upper limit value is set for the predicted slack of each instruction updated by the updating means, and the upper limit value is set differently depending on the type of instruction.

Further, the processor device further includes a branch history register for recording a branch history of the program,
In the slack table, predicted slack of the instruction is individually recorded in addition to a branch pattern obtained by referring to the branch history register.

According to a second aspect of the present invention, there is provided a processing method of a processor device for predicting predicted slack, which is a predicted value of local slack of an instruction executed by the processor device, and executing the instruction using the predicted slack. In the processing method,
The instruction executed by the processor unit is executed with the execution latency increased by the value of the predicted slack, and the target slack which is the appropriate value of the current local slack based on the behavior at the time of execution of the instruction. Including a control step of estimating whether or not the predicted slack has been reached and updating the predicted slack so as to gradually increase each time the instruction is executed until it is estimated that the predicted slack has been reached. And

  In the processing method of the processor device, the control step changes the parameter used for updating the slack so as to suppress the performance degradation of the processor device while maintaining the number of slack instructions according to the predicted slack value. It is characterized by doing.

  In the processing method of the processor device, the control step changes a parameter used for updating the slack according to whether or not the predicted slack is a predetermined threshold value or more.

Further, in the processing method of the processor device, as a condition for establishing the estimation that the predicted slack has reached the target slack,
(A) A branch prediction error occurred during execution of the instruction,
(B) A cache miss occurred during execution of the instruction;
(C) Operand forwarding for the subsequent instruction has occurred,
(D) that store data forwarding has occurred for the subsequent instruction;
(E) the instruction is the oldest instruction in the instruction window;
(F) the instruction is the oldest instruction in the reorder buffer;
(G) The instruction is an instruction that passes the execution result to the oldest instruction in the instruction window.
(H) The instruction is an instruction that passes the execution result to the most subsequent instructions among the instructions executed in the same cycle;
(I) It is characterized in that at least one of the number of succeeding instructions that become executable by passing the execution result of the instruction is at least a predetermined determination value is included.

  Furthermore, in the processing method of the processor device, when it is estimated that the predicted slack has reached the target slack, the predicted slack is decreased.

  Further, in the processing method of the processor device, the increase in the predicted slack is performed on the condition that the number of times that the estimated condition that the predicted slack has reached the target slack has not been satisfied is a specified number. The decrease in the predicted slack is performed under the condition that the number of times the satisfaction condition is satisfied reaches a specified number.

  Further, in the processing method of the processor device, the number of times that the satisfaction condition is not satisfied to increase the predicted slack is set to be greater than the number of times that the satisfaction condition is required to decrease the predicted slack. It is characterized by.

  Still further, in the processing method of the processor device, the increase in the predicted slack is performed on the condition that the number of times that the estimated condition that the predicted slack has reached the target slack has not been satisfied becomes a specified number. The decrease in the predicted slack is performed on the condition that the satisfaction condition is satisfied.

  In the processing method of the processor device, the prescribed number of times is set to be different depending on the type of the instruction.

  Furthermore, in the processing method of the processor device, the amount of update of predicted slack per time is set differently depending on the type of the instruction.

  Still further, in the processing method of the processor device, the upper limit value of the predicted slack is set to be different depending on the type of the instruction.

  According to the processor device and the processing method thereof according to the present invention, when executing an instruction, the predicted slack of the instruction is acquired with reference to the slack table, the execution latency is increased by the acquired predicted slack, Based on the behavior at the time of execution of the instruction, it is estimated whether the predicted slack has reached target slack, which is the appropriate value of the current local slack of the instruction, and the predicted slack has reached the target slack. The estimated slack is gradually increased for each execution of the instruction until it is estimated. Therefore, instead of directly calculating the predicted value of local slack of the instruction (predicted slack), the predicted slack is gradually increased until the appropriate value is reached while observing the behavior at the time of execution of the instruction. Therefore, a complicated mechanism required for direct calculation of predicted slack is not required, and local slack can be predicted with a simpler configuration.

  Further, since the parameters used for slack update are changed according to the value of local slack, it is possible to suppress performance degradation while maintaining the number of slack instructions. Therefore, it is possible to perform local slack prediction and execute program instructions at a higher speed with a simpler configuration as compared with the prior art.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. Also, chapter and section numbers are assigned independently for each embodiment.

First embodiment.
In the first embodiment according to the present invention, a mechanism for predicting local slack based on a heuristic technique is proposed. In this mechanism, local slack is predicted by trial and error while observing the behavior during instruction execution. This eliminates the need to calculate local slack directly. Furthermore, in the present embodiment, as an application example, a method for reducing the power consumption of functional units using local slack is taken up and the effect of the proposed mechanism is evaluated.

1. A method for heuristic prediction of local slack.
In contrast to the conventional method, this embodiment proposes a method for heuristically predicting local slack. In this method, while observing the behavior during instruction execution, the predicted local slack (hereinafter referred to as predicted slack) is increased or decreased to bring the predicted slack closer to actual local slack (hereinafter referred to as target slack). Go. Since prediction is performed by trial and error, it is not necessary to directly calculate local slack as in the conventional method.

  In the following, in order to simplify the description, first, the basic operation of the proposed method will be described. Then, modifications are made to accommodate the dynamic change in target slack. Finally, the configuration of the proposed method will be described.

1.1. basic action.
First, the basic operation of the proposed method according to this embodiment is shown. Local slack is predicted at the time of instruction fetch, and instruction execution latency is increased based on the predicted slack. For any instruction, the first time it is fetched, local slack is expected to be zero. That is, the initial value of predicted slack is 0. After that, while observing the behavior at the time of instruction execution, the predicted slack is gradually increased until the target slack is reached.

  That is, in this prediction method, specifically, at the time of fetching an instruction, first, predicted slack of the instruction is acquired, and the execution latency of the instruction is increased by the acquired predicted slack. For example, for an instruction whose execution latency is originally “1 cycle”, when the predicted slack is “2”, the execution latency of the instruction is increased to “3 cycles”. For any instruction, when the instruction is fetched for the first time after the start of the program, the local slack is predicted to be “0”. That is, the initial value of the predicted slack is set to “0” for all instructions. Thereafter, the behavior of the instruction at the time of execution is observed, and the predicted slack is gradually increased until it is estimated that the predicted slack has reached the target slack.

  Next, a method of determining whether or not predicted slack has reached target slack based on the behavior at the time of instruction execution in the basic operation will be described. Here, let us consider a situation where the predicted slack of an instruction is increased and the value reaches the target slack. At this time, if the execution latency is increased even by one cycle, the instruction is in a state in which the execution of the instruction depending on the instruction is delayed. Further, as the dependency relationship between instructions, control dependency, dependency via a cache line, register data dependency, and memory data dependency can be given. Therefore, an instruction in which predicted slack reaches target slack is considered to exhibit one of the following behaviors.

(A) branch misprediction,
(B) cash miss,
(C) Operand forwarding for subsequent instructions, and (d) Store data forwarding for subsequent instructions.

  First, the branch prediction error (a) will be described. Since a processor that performs pipeline processing simultaneously executes a large number of instructions in a work flow, if the instruction sequence that is subsequently executed by a branch instruction is changed, all subsequent instructions that have already started processing must be discarded. In other words, the processing efficiency decreases. In order to prevent this, it is predicted whether or not the instruction will branch based on the state of occurrence of the branch when the branch instruction was previously executed, and the branch prediction destination instruction is speculatively executed according to the prediction result. Consider the situation where predicted slack exceeds target slack. In such a situation, the execution latency of the preceding instruction is excessively increased, causing a delay in the execution of the succeeding instruction that depends on it. In such a case, proper branch prediction cannot be performed, and branch prediction results are likely to be erroneous. For this reason, when a branch prediction error occurs, it can be considered that there is a high possibility that the predicted slack exceeds the target slack.

  Next, the cache miss (b) will be described. In many processors, frequently used data and the like are stored in a high-speed cache memory, thereby reducing access to a low-speed storage device and increasing the processing speed of the processor. If the predicted slack of the preceding instruction exceeds the target slack, such a cache operation cannot be performed properly, and a cache miss is likely to occur. Therefore, it can be considered that there is a high possibility that the predicted slack exceeds the target slack even when a cache miss occurs.

  Next, operand forwarding and store data forwarding for the subsequent instructions (c) and (d) will be described. If the execution interval between the preceding instruction and the subsequent instruction that refers to the data defined by the preceding instruction is short, a data hazard may occur when the subsequent instruction tries to read the data before the data writing is completed. Therefore, in many processors with multistage pipelines, a bypass circuit is provided to avoid such data hazards by performing operand forwarding or store data forwarding that directly gives the data before writing to subsequent instructions. Yes. Such forwarding occurs when a subsequent instruction that refers to data defined by the preceding instruction is executed immediately after the preceding instruction. Therefore, when operand forwarding or store data forwarding occurs, it can be determined that the predicted slack matches the target slack.

  In this prediction method, when the behavior at the time of instruction execution corresponds to one of the above (a) to (d), it is estimated that the predicted slack has reached the target slack, and otherwise it is determined that it has not been reached. Like to do. The condition for establishing that such predicted slack has reached target slack is defined as the logical sum condition (a) to (d) above, and is referred to as “target slack arrival condition”. Note that a mechanism for detecting the behavior at the time of instruction execution as described in the above (a) to (d) is usually provided from the beginning as long as it is a processor that performs branch prediction, cache, and forwarding. Therefore, it is possible to confirm whether or not the arrival condition is satisfied without newly adding such a detection mechanism for local slack prediction.

  FIG. 3 (a) is a basic operation of the processor device using the method for heuristically predicting local slack according to the first embodiment of the present invention, and is a timing chart showing the first execution operation. FIG. 3B is a timing chart showing the basic operation of the processor device and the second execution operation, and FIG. 3C is the basic operation of the processor device, and shows the third operation. It is a timing chart which shows execution operation. That is, the process of repeatedly executing the program of FIG. 1A based on the basic operation of the proposed method is shown in FIGS. 3A, 3B, and 3C. In FIG. 3A, FIG. 3B, and FIG. 3C, the hatched portion of each node indicates the execution latency increased according to the predicted slack. 3 (a), 3 (b), and 3 (c), for the sake of simplicity, only local slack of the instruction i0 is targeted for prediction, and predicted slack is increased by 1 at a time. To do.

  In the first execution of FIG. 3A, the predicted slack of the instruction i0 is zero. In this case, since the behavior at the time of executing the instruction i0 does not correspond to any of the target slack arrival conditions, the predicted slack has not yet reached the target slack. Therefore, the predicted slack of the instruction i0 is increased by 1. As a result, the predicted slack of the instruction i0 is 1 in the second execution of FIG. Again, the predicted slack has not reached the target slack. Therefore, the predicted slack of the instruction i0 is further increased by 1. Thereby, in the third execution of FIG. 3C, the predicted slack of the instruction i0 is 2. As a result, the instruction i0 performs operand forwarding on the subsequent instruction. This satisfies the target slack arrival condition. The predicted slack has reached the target slack and will not be increased any further. The local slack of the instruction i0 is predicted as described above.

1.2. Response to dynamic changes in target slack.
The basic operation cannot sufficiently cope with the dynamic change of the target slack. Even if the target slack changes dynamically, if it is larger than the predicted slack, there is no problem because the predicted slack only increases toward the new target slack. However, if the target slack becomes smaller than the predicted slack, the predicted slack remains unchanged and maintains the same value. Therefore, the execution of the subsequent instruction is delayed by the amount exceeding the target slack (slack predicted mispenalty). End up. This can adversely affect performance.

  To solve this problem, a solution is proposed in which the predicted slack is reduced when the target slack becomes smaller than the predicted slack. However, when the target slack repeatedly increases and decreases, even if this method is introduced, the predicted slack cannot follow the target slack. As a result, a situation occurs frequently in which the target slack is smaller than the predicted slack. Therefore, we propose a solution method that introduces reliability, increases predicted slack carefully, and reduces predicted slack quickly.

  Hereinafter, the above two solutions will be described in detail.

1.2.1. Reduced predicted slack.
As a method for realizing the reduction of the predicted slack, a method of using the execution time of the subsequent instruction when the slack prediction is not performed (the time when the subsequent instruction should be executed) can be considered. If the time at which the subsequent instruction should be executed is known, it can be checked whether the execution time of the subsequent instruction is delayed due to a slack prediction error. Alternatively, target slack can be calculated directly and compared to predicted slack. However, in any case, it is necessary to calculate the time when the subsequent instruction should be executed in consideration of various factors (resource constraints, data dependency, control dependency, etc.) that can determine the execution time of the instruction. Can't be realized easily.

  Therefore, the present inventor pays attention to the above-mentioned “target slack arrival condition”. Using this condition, it is easy to see that the predicted slack is below the target slack and that it has arrived at the target slack. Using this feature, when predicted slack arrives at the target slack, the predicted slack is decreased until it falls below the target slack. This makes it possible to cope with a dynamic reduction in target slack with very simple modifications. The predicted slack below the target slack is wasted, but is considered well tolerated.

  With reference to FIGS. 4A and 4B, the problem of the basic operation and the solution thereof will be described. FIG. 4A is a graph showing the cycle-to-slack characteristics for explaining the problem of the basic operation of FIG. 3, and FIG. 4B is the cycle-to-slack characteristic for explaining a solution to the problem. It is a graph which shows. That is, FIGS. 4A and 4B are examples showing how predicted slack changes when target slack dynamically decreases. 4A and 4B, the vertical axis indicates slack, and the horizontal axis indicates time. In the line graph, the dotted line is the target slack, and the solid line is the predicted slack. The hatched portion indicates a portion where the predicted slack exceeds the target slack. 4A shows the case of the basic operation, and FIG. 4B shows the case where the solution proposed in this section is introduced.

  In FIG. 4A, the predicted slack increases until reaching the target slack. Thereafter, the target slack decreases and becomes smaller than the predicted slack. However, the predicted slack maintains the value as it is, and continuously delays the execution of subsequent instructions.

  On the other hand, as shown in FIG. 4B, in the operation after correction, first, the predicted slack increases until reaching the target slack. After arrival, the predicted slack decreases but falls below the target slack, so it immediately starts increasing and reaches the target slack again. This change is repeated for a while. Thereafter, when the target slack decreases, the predicted slack decreases until it falls below the target slack, and increases and decreases again. Thus, the predicted slack can be reduced in accordance with the reduction of the target slack.

1.2.2. Introduction of reliability.
Further modifications to basic behavior to accommodate rapid changes in target slack. First, a reliability counter is introduced for each predicted slack. The counter value is decreased if the instruction satisfies the target slack arrival condition, and is increased otherwise. Then, the predicted slack is decreased when the counter value becomes 0, and the predicted slack is increased when the counter value exceeds a certain threshold value.

  In order to carefully increase the predicted slack, the counter value is reset to 0 when increasing the predicted slack. In order to reduce predicted slack quickly, if the instruction satisfies the “target slack arrival condition”, the counter value is reset to zero.

  FIG. 5A is a graph showing cycle-to-slack characteristics for explaining the problem of the solution method of FIG. 4, and FIG. 5B is a cycle-to-slack characteristic for explaining the solution method of the problem. It is a graph which shows. With reference to FIGS. 5A and 5B, the problem of the solution method described in the previous section and a method for solving the problem will be described. FIGS. 5A and 5B are examples showing how the predicted slack changes when the target slack rapidly increases and decreases, and FIG. 5A shows the basic operation. FIG. 5 (b) shows the case where the slack reduction is introduced, and FIG. 5 (b) shows the case where the reliability is further introduced.

  In FIG. 5A, it can be seen that predicted slack tries to change toward the target slack, but cannot follow the rapid change and frequently exceeds the target slack. On the other hand, as shown in Fig. 5 (b), when reliability is introduced, the predicted slack gradually increases toward the target slack and decreases immediately when the target slack is reached (or exceeded). Repeat the change. As a result, the frequency at which the predicted slack exceeds the target slack can be reduced.

1.3. Hardware configuration.
FIG. 6 is a block diagram illustrating a configuration of the processor 10 including the slack table 20 according to the first embodiment of the present invention. In FIG. 6, the right portion of the processor 10 is a local slack prediction mechanism proposed by the present inventor, and the proposed mechanism is composed of a slack table 20 for holding predicted slack. The slack table 20 includes a storage device, and uses an instruction program counter value (PC: a memory address of the main storage device 9 that stores the instruction) as an index, and each entry includes predicted slack of the corresponding instruction. And maintain the reliability of the target slack arrival conditions.

  In FIG. 6, a processor 10 includes a fetch unit 11, a decode unit 12, an instruction window (I-win) 13, a register file (RF) 14, an execution unit (EU) 15, and a reorder buffer. (ROB) 16. The function of each unit constituting the processor 10 is as follows. The fetch unit 11 reads an instruction from the main storage device 9. The decode unit 12 analyzes (decodes) the content of the read instruction and stores it in the instruction window 13 and the reorder buffer 16, respectively. The instruction window 13 is a buffer (memory) that temporarily stores instructions before execution. The control circuit of the processor 10 takes out instructions from the buffer of the instruction window 13 and sequentially inputs them to the execution unit 15. On the other hand, the reorder buffer 16 is a first-in first-out (FIFO) type stack memory for storing instructions. When the execution of the instruction having the earliest storage order is completed, Is retrieved (committed). Here, commit refers to updating the processor state according to the execution result. Further, the FIFO 17 is obtained by the fetch unit 11 from the slack table 20, and then the predicted slug and reliability output from the decode unit 12 are input as a set at each timing, stored, and output to the slack table 20. Note that the register file 14 is an entity of various registers for storing data necessary for execution of instructions, execution results of instructions, addresses and indexes of instructions that are being executed and scheduled to be executed, and the like.

  The instruction refers to the slack table with the program counter value (PC) as an index when fetching, and obtains predicted slack from the corresponding entry. Then, when committing, the slack table is updated based on the behavior when the instruction is executed. The parameters and contents related to the slack table update are shown below. However, the predicted slack minimum value Vmin = 0 and the reliability minimum value Cmin = 0.

(1) Vmax: Maximum value of predicted slack,
(2) Vmin: Minimum value of predicted slack (= 0),
(3) Vinc: Increase amount of predicted slack per time,
(4) Vdec: decrease amount of predicted slack per time,
(5) Cmax: maximum reliability,
(6) Cmin: minimum value of reliability (= 0),
(7) Cth: threshold of reliability,
(8) Cinc: the amount of increase in reliability per time, and (9) Cdec: the amount of decrease in reliability per time.

  The flow of updating the slack table 20 is shown below. If the above-described target slack arrival condition is satisfied, the reliability is reset to 0. Otherwise, the reliability is increased by the increase amount Cinc. When the reliability exceeds the threshold Cth, the predicted slack is increased by the increase amount Vinc, and the reliability is reset to zero. On the other hand, when the reliability becomes 0, the predicted slack is decreased by the decrease amount Vdec. In addition, 1.2. In the clause, since the reliability is reset to 0 when the target slack arrival condition is satisfied, Cdec = Cth. Further, since the reliability is reset to 0 when the predicted slack is increased, Cmax = Cth.

5). Evaluation of slack prediction mechanism.
In this chapter, we first describe the evaluation model and the evaluation environment. Next, evaluation results will be described.

5.1. Evaluation model.
The following models were evaluated.

(1) NO-DELAY model: A model that does not increase execution latency based on predicted slack.
(2) B model: A model that performs only the basic operation of the proposed method.
(3) BCn model: This model introduces reliability into the basic operation of the proposed method. A numerical value n added to the model represents a reliability threshold value Cth.
(4) BD model: This model introduces a reduction in predicted slack into the basic operation of the proposed method.
(5) BDCn model: This model introduces the prediction slack reduction and reliability into the basic operation of the proposed method. A numerical value n added to the model represents a reliability threshold value Cth.

  Since the B model, the BCn model, the BD model, and the BDCn model are models based on the proposed method, they are referred to as a proposed model.

2.2. Evaluation environment.
As a simulator, a simulator for a super scalar processor of a well-known Simple Scalar Tool Set (see, for example, Non-Patent Document 1) was used, and the proposed method was incorporated and evaluated. For the instruction set, a known SimpleScalar / PISA that is an extension of the known MIPSR10000 was used. As the benchmark program, eight known SPECint2000 bzip2, gcc, gzip, mcf, parser, perlbmk, vortex, and vpr were used. After skipping the 1G instruction in gcc and the 2G instruction in others, a 100M instruction was executed. Table 1 shows the measurement conditions. For comparison with the conventional method, the number of entries in the slack table is the same as that in the conventional method (for example, see Non-Patent Document 10).

  Among the parameters relating to the update of the slack table, the maximum value Vmax, the increase amount Vinc, the decrease amount Vdec, the threshold value Cth, and the increase amount Cinc can be changed. Since these combinations are enormous numbers, some parameters are fixed to certain values. First, since the ratio between the increase amount Cinc and the threshold value Cth represents the frequency of increasing slack, the increase amount Cinc = 1 is fixed and only the threshold value Cth is changed. Next, in order to make the predicted slack as close as possible to the target slack, the increase amount Vinc = 1 is fixed. Finally, in order to reduce the predicted slack as soon as possible, the reduction amount is fixed at Vdec = Vmax. As described above, in this chapter, only the maximum value Vmax and the threshold value Cth are changed, and the proposed method is evaluated. However, in order to facilitate the comparison, the threshold value Cth is limited to two ways of 5 and 15, and the maximum value Vmax is restricted to three ways of 1, 5, and 15.

2.3. Slack prediction accuracy.
Here, first, actual slack (hereinafter referred to as actual slack) is measured for each dynamic execution instruction. Specifically, in the NO-DELAY model, the local slack of the instruction is obtained from the difference between the time when an instruction defines register data or memory data and the time when the data is first referred to. Therefore, the slack of an instruction (branch instruction) that does not define data is infinite.

  FIG. 7 is a graph showing the simulation result of the embodiment of the proposed mechanism of FIG. 6 and the ratio of each program to the number of executed instructions with respect to actual slack. That is, FIG. 7 shows the cumulative distribution of actual slack. The vertical axis in FIG. 7 indicates the ratio of the total number of executed instructions, and the horizontal axis indicates actual slack. In the line graph, the solid line indicates the benchmark average, and the dotted line indicates each benchmark. This is the case of vpr, bzip, gzip, parser, average, perlbmk, gcc, vortex, mcf in order from the top at the point where the actual slack is 32 cycles.

  As shown in FIG. 7, there is an average of 52.7% of actual slack 0 instructions. As the actual slack increases, the ratio to the number of executed instructions gradually saturates. In addition, it can be seen that there are 28.9% of instructions that have actual slack of 30 cycles or more. However, when the instruction execution latency is increased by several tens of cycles or more in a normal processor, these instructions occupy buffers (reorder buffer (ROB) 16, instruction window (I-win) 13, etc.) in the processor. Therefore, the performance is greatly reduced (see, for example, Non-Patent Document 10). How to use such large slack has not been studied enough.

  8, 9, and 10 are simulation results of the embodiment of the proposed mechanism of FIG. 6, and the ratio of the predicted slack maximum value Vmax = 1, 5, 15 to the number of executed instructions for each model (slack It is a graph which shows prediction accuracy. That is, in FIG. 8 thru | or FIG. 10, the result of having measured the slack prediction precision of each proposal model is shown by a benchmark average. The vertical axis in FIGS. 8 to 10 represents the ratio of the total number of executed instructions, and the horizontal axis represents the model. The bar graph is composed of six parts. The upper four predict the slack as n (n is 1 or more) and the lower two predict the slack as 0. When slack is predicted as n, in order from the top, when predicted slack n exceeds actual slack m (m is 1 or more) (n> m), exceeds actual slack 0 (n> 0), actual slack Is less than (n <m), and is coincident with actual slack (n = m). On the other hand, when slack is predicted to be 0, in order from the top, it is below actual slack (0 <m), and when it is coincident with real slack (0 = m). However, when the maximum value of predicted slack Vmax = 1, predicted slack n does not exceed actual slack m, so the bar graph is composed of five parts. Hereinafter, when the predicted slack and the actual slack coincide with each other, the prediction hits.

  From FIG. 8 to FIG. 10, it can be seen that the ratio of prediction hits is the lowest in the B model. On the other hand, it can be seen that both the model in which the decrease in predicted slack (BD model) and the model in which reliability is introduced (BCn model) are effective in improving the hit rate. Further, a model in which both are introduced (BDCn model) can obtain a higher effect. In the case of a model in which reliability is introduced, the higher the reliability threshold (number added to the model), the higher the hit rate. Note that the prediction hits in most cases when the actual slack is 0, except for the B model with the predicted slack maximum value Vmax = 1. In this case, slack is not available.

  If predicted slack exceeds actual slack, slack exceeding actual slack is used. Therefore, a penalty due to a misprediction occurs. From FIG. 8 to FIG. 10, the occurrence rate of the prediction miss penalty can be lowered as the hit rate is higher. On the other hand, if the predicted slack is lower than the actual slack, the predicted miss penalty does not occur. In this case, if the predicted slack is 1 or more, slack can be used. From FIG. 8 to FIG. 10, the rate at which slack can be used without generating a prediction mispenalty decreases as the hit rate increases, but the change is relatively gradual. Therefore, the proposed mechanism does not simply reduce the rate at which the predicted slack is 1 or more, but rather changes the predicted slack so that the incidence of the predicted mispenalty is reduced. I understand.

  Next, the influence of the maximum value Vmax of predicted slack will be considered. From FIG. 8 to FIG. 10, when the maximum value Vmax of predicted slack is changed, the ratio that the predicted slack is 0 and the ratio that is 1 or more do not change much. From this, it can be seen that the number of instructions predicted to have one or more slack (or no slack) does not depend much on the maximum value Vmax of predicted slack. The breakdown of instructions with predicted slack of 1 or more changes when the maximum predicted slack value Vmax is increased from 1 to 5, but is not so much when the maximum predicted slack value Vmax is increased from 5 to 15. It turns out that it does not change. From these, it can be seen that when the maximum value Vmax of predicted slack increases to some extent, the magnitude relationship between predicted slack and actual slack does not change much.

2.4. Difference between actual slack and predicted slack.
From the evaluation in the previous section, we were able to know the magnitude relationship between actual slack and predicted slack. However, this alone does not reveal how much the difference between the two is actually. Therefore, a cumulative distribution of values obtained by subtracting predicted slack from actual slack is measured. In the measurement, first, all the actual slack of each dynamic execution instruction is collected in the NO-DELAY model. In each proposed model, a value obtained by subtracting predicted slack corresponding to the collected actual slack is obtained.

  FIGS. 11, 12 and 13 are simulation results of the embodiment of the proposed mechanism of FIG. 6, and show the difference between actual slack and predicted slack in each model at the maximum predicted slack value Vmax = 1, 5, and 15. It is a graph which shows the ratio which occupies for the number of execution instructions. The vertical axis in FIGS. 11 to 13 indicates the ratio of the total number of executed instructions to the benchmark average, and the horizontal axis indicates a value obtained by subtracting predicted slack from actual slack. If this value is negative, it indicates that the predicted slack exceeds the actual slack. 0 indicates that slack prediction is hit. A positive value indicates that predicted slack is below actual slack. The minimum value on the horizontal axis is a value obtained by subtracting the maximum value Vmax of predicted slack from the minimum value 0 of actual slack. In FIG. 11, the line graph is the case where the top graph is the B model, the nearly overlapping graphs are the BC15 model and the BD model, and the bottom graph is the BDC15 model. On the other hand, in FIG.12 and FIG.13, a line graph is a case of B model, BC15 model, BD model, and BDC15 model in an order from the top. In order to facilitate the comparison of the models, the results when the threshold value Cth = 5 are omitted.

  As is apparent from FIGS. 11 to 13, it can be seen that if the prediction slack is reduced or the reliability is introduced, not only the occurrence rate of the prediction miss penalty but also the size of the prediction miss penalty can be suppressed. Further, the difference between the models is larger in the negative region than in the positive region. This indicates that the difference in the effect of reducing the prediction miss penalty is larger than the difference in the effect of increasing the prediction slack. From this, it can be seen that the introduction of the decrease in predicted slack and the introduction of reliability can reduce the slack prediction miss penalty as intended. Furthermore, in any model, it can be seen that as the maximum value Vmax of predicted slack increases, the predicted miss penalty increases. This is due to the fact that there are a large number of instructions whose actual slack is greatly reduced. For example, when the maximum value of predicted slack Vmax = 15, in the B model in which only predicted slack is increased / decreased, the instruction with a difference of −15 cycles is 31.1%. This indicates that there are 31.1% of instructions whose actual slack has decreased by 15 cycles or more.

2.5. Effect on performance.
FIG. 14 is a graph showing simulation results of the embodiment of the proposed mechanism of FIG. 6 and showing normalized IPC (Instructions Per Clock cycle: average number of instructions that can be processed per clock) in each model. The vertical axis in FIG. 14 shows the IPC normalized in the case of the NO-DELAY model as a benchmark average. The horizontal axis of FIG. 14 shows the model. The three bar graphs are the cases where the maximum value Vmax of predicted slack is 1, 5, and 15 in order from the left. FIG. 14 shows that when models having the same predicted slack maximum value Vmax are compared, the IPC has the lowest B model. In addition, it can be seen that a model (BDCn model) combining them achieves higher performance than a model in which reduction of predicted slack and reliability are independently introduced. In the case of a model incorporating reliability, the higher the reliability threshold (the number added to the model), the higher the performance.

  The cause of the performance degradation of each model is the occurrence of slack prediction miss penalty. Therefore, comparing the above results with FIGS. 8 to 10 showing the slack prediction accuracy, if the maximum value Vmax of predicted slack is the same, the ratio of predicted slack exceeding actual slack (occurrence of predicted mispenalty) It can be seen that the lower the model, the higher the performance.

  FIG. 14 shows that in each model, the IPC decreases as the maximum value Vmax of predicted slack increases. However, it can be seen that the higher the IPC, the more the IPC can be reduced. The reason for this is that, as can be seen from FIG. 11 to FIG. 13, when the prediction slack is reduced or the reliability is introduced, not only the occurrence rate of the prediction mispenalty but also the size of the prediction mispenalty can be suppressed.

  FIG. 15 is a graph showing the simulation result of the embodiment of the proposed mechanism of FIG. 6 and showing the ratio of the number of slack instructions in each model. FIG. 16 is a graph showing simulation results of the embodiment of the proposed mechanism of FIG. 6 and showing average predicted slack in each model. That is, FIG. 15 and FIG. 16 show the results of evaluating the predicted slack of each model. FIG. 15 shows the number of “slack instructions”. Here, the “slack instruction” is an instruction that increases the execution latency by one cycle or more based on the predicted slack. The vertical axis in FIG. 15 indicates the ratio of the number of slack instructions to the total number of executed instructions as a benchmark average, and the horizontal axis indicates the model. On the other hand, FIG. 16 shows “average predicted slack”. Here, “average predicted slack” is a value obtained by dividing the total predicted slack by the number of slack instructions. The vertical axis in FIG. 16 indicates the average value of predicted slack as a benchmark average, and the horizontal axis indicates a model. From these FIG. 15 and FIG. 16, it is possible to know the ratio of the instructions that could increase the execution latency and the average of the execution latencies that could be increased for those instructions.

  From FIG. 15, the number of slack instructions depends on the model type and the reliability threshold, and the number of slack instructions decreases as the IPC increases, but hardly depends on the maximum value Vmax of predicted slack. On the other hand, as shown in FIG. 16, the average predicted slack increases as the maximum value Vmax of predicted slack increases, but does not change much depending on the type of model and the reliability threshold value. Accordingly, when models having the same predicted slack maximum value Vmax are compared, the increased total execution latency is reduced by introducing a reduction in predicted slack and reliability, and is the smallest in the BDCn model. In the case of a model incorporating reliability, the higher the reliability threshold, the smaller the total execution latency increased.

  However, the BDCn model can most suppress the decrease in IPC due to the increase in the maximum value Vmax of predicted slack. Therefore, there is a case where the predicted slack can be increased more than other models without significantly reducing the performance. For example, in a situation where IPC reduction is allowed to about 80%, the BC15 model, BD model, and BDC15 model can increase the maximum value Vmax of predicted slack to 5, 5, and 15, respectively. At this time, in the BDC15 model, the total execution latency that can be increased is 15.6% higher than that of the BC15 model and 32.6% higher than that of the BD model.

  In Non-Patent Document 10, local slack is predicted by a conventional method, and the performance and the number of slack instructions when the instruction execution latency is increased by one cycle based on the prediction are measured. According to this, in the conventional method, when the performance degradation is 2.8 cycles, the ratio of the number of slack instructions is 26.7%.

  On the other hand, although the benchmark program and the processor configuration are different from the above research, the closest evaluation in the present embodiment is performed when the maximum value of predicted slack Vmax = 1 in the BDC15 model. In this case, when the performance degradation is 2.5 cycles, the ratio of the number of slack instructions is 31.6%. From this, it can be seen that the proposed method shows the same result as the conventional method.

  FIG. 17 is a graph showing a simulation result of another embodiment of the proposed mechanism of FIG. 6 and showing the relationship between the number of slack instructions and the IPC for each value of the maximum value Vmax of predicted slack. FIG. 18 is a graph showing simulation results of another example of the proposed mechanism of FIG. 6 and showing the total integrated value of predicted slack with respect to IPC.

  That is, FIG. 17 shows the number of slack instructions and the measurement result of IPC in the evaluation. The vertical axis in FIG. 17 represents the ratio of the number of slack instructions to the total number of executed instructions in each combination of the maximum value Vmax and the threshold value Cth, and the ratio of the measured IPC to the IPC when no slack prediction is performed. Is shown. In addition, the four vertical bars in each of the maximum values Vmax (“1”, “5”, “10”, “15”) have thresholds Cth of “1”, “ The measurement results in the cases of “5”, “10”, and “15” are respectively shown.

  As shown in FIG. 17, when the threshold value Cth is increased, the number of slack instructions decreases. This is because the increase condition of the predicted slack becomes stricter due to the increase of the threshold value Cth, and the increase frequency of the predicted slack becomes lower. However, if the threshold value Cth is increased, the frequency at which predicted slack exceeds target slack decreases, and IPC is improved. From this result, it was confirmed that the introduction of the reliability can suppress a decrease in instruction processing performance due to the slack prediction miss penalty. On the other hand, if the maximum value Vmax of predicted slack is increased, the predicted slack can take a larger value, so that the penalty for slack prediction mistakes increases and the processing performance (IPC) decreases.

  FIG. 18 shows the relationship between predicted slack and IPC in the above measurement results. The vertical axis in FIG. 18 indicates the ratio of the benchmark average value of the total integrated value of predicted slack with the parameter (Vmax, Cth) = (1, 1) as the reference (100), and the horizontal axis is The ratios of IPC benchmark average values based on the standard (100) when no slack prediction is performed are shown. Note that the numbers given to the points in FIG. 18 indicate the value of the threshold value Cth.

  As shown in FIG. 18, when the maximum value Vmax of predicted slack is increased, the processing performance is reduced, but the predicted slack is greatly increased. In addition, by increasing the threshold value Cth together with the maximum value Vmax, some combinations of parameters that increase predicted slack without substantially decreasing IPC were confirmed. For example, in the case of the parameter (Vmax, Cth) = (1, 1), when the parameter (Vmax, Cth) = (5, 15), the decrease in IPC is only 0.3%, The predicted slack is about 2.2 times.

  As is clear from the above results, the processing performance is in a trade-off relationship with the number of slack instructions and predicted slack, and the optimum value of each parameter varies depending on the request of the application target.

3. Evaluation of hardware for slack prediction mechanism.
The hardware amount, access time, and power consumption of the slack prediction mechanism proposed in this embodiment are compared with those of the conventional mechanism.

3.1. Hardware configuration.
The processor configuration is the same as the evaluation environment in the previous chapter. That is, the conventional mechanism of FIG. 2 is used, and the BDC model of FIG. 6 evaluated in the previous chapter is used as the proposed mechanism. First, hardware necessary for the conventional mechanism of FIG. 2 is shown below.

(1) The table includes a slack table 20, a memory definition table 3, and a register definition table 2 (see FIG. 2).
(2) The computing unit includes the subtracter 5 (calculation of slack value), the comparator (address comparison), and the comparator (physical register number comparison) shown in FIG. Note that the two comparators are hardware necessary when the table is pipelined, as will be described in detail later, and are not shown in FIG.

  In the conventional mechanism of FIG. 2, the slack table 20 holds the slack value of an instruction, and refers to the program counter value (PC) as an index at the time of fetch and updates at the time of execution. The memory definition table 3 stores the program counter value (PC) of the instruction that stores the data at the corresponding memory address and the definition time of the data, with the memory address as an index. The memory definition table 3 is updated with the store address and referenced with the load address. The register definition table 2 uses a physical register number as an index, and holds a program counter value (PC) of an instruction that writes data to a corresponding physical register and a definition time of the data. The register definition table 2 is referred to by the physical register number corresponding to the source register of the instruction and updated with the physical register number corresponding to the destination register immediately before execution of the instruction. The subtracter 5 calculates the slack of the executed instruction by taking the difference between the definition time obtained from the definition table and the current time. The comparator (address comparison) and the comparator (physical register number comparison) are respectively required when the memory definition table 3 and the register definition table 2 are pipelined for high-speed operation. When the tables of the memory definition table 3 and the register definition table 2 are pipelined, if the definition time is referenced before the update of the definition time is completed, the correct definition time cannot be obtained from the table. To solve this problem, it is necessary to forward the defined time. Specifically, first, an address used for update and an address used for reference are compared, and a physical register number of a destination register used for update and a source register used for reference is compared. When the address or the physical register number matches, the memory definition time and the register definition time are forwarded, respectively.

  Next, the hardware required for the proposed mechanism is shown below.

(1) As shown in FIG. 6, the table includes a slack table 20 and a FIFO 17 that records reliability and predicted slack.
(2) As shown in FIGS. 19 and 46, the computing unit corresponds to the reliability adder 40 and the reliability comparator (corresponding to the AND gate 31 in FIG. 19 and the comparator 94 in FIG. A comparator 94), a predicted slack adder 50, and a predicted slack comparator (corresponding to the AND gate 35 in FIG. 19 and the predicted slack comparator 112 in FIG. 46, hereinafter referred to as a predicted slack comparator 112). Prepare.

  In the proposed mechanism, the slack table 20 holds the slack value and reliability of a certain program counter value (PC), and is referred to when fetched and updated when committed. The FIFO 17 is a FIFO that holds the reliability and predicted slack obtained from the slack table 20 in the order of instruction fetch, and writes at the time of dispatch and reads at the time of commit. These values are used to calculate the update data of the slack table 20. The FIFO 17 has the same entry as the ROB 16 and writes the instruction to the ROB 16. At the same time, the reliability of the instruction and the predicted slack are written to the FIFO 17 using the same index, and at the same time the instruction is committed from the ROB 16. Using the index, the reliability and predicted slack of the instruction are read from the FIFO 17 and output to the slack table 20.

  The computing unit is used for predictive slack and reliability update. The reliability adder 40 is used to increase the reliability by the increase amount Cinc. The reliability comparator 94 is used to check whether or not the increased reliability is equal to or higher than the threshold value Cth. The predicted slack adder 50 is used to increase the predicted slack by the increase amount Vinc. The predicted slack comparator 112 is used to check whether the increased predicted slack exceeds Vmax. If the predicted slack exceeds its maximum value Vmax, the predicted slack is set to its maximum value Vmax. Note that when the reliability is reduced, the resetting is simply reset to 0, so that there is no need for an arithmetic unit for subtracting the reliability and a comparator for checking whether the reliability is equal to or lower than the minimum value Cmin. Further, in this evaluation, Vdec = Vmax is set, and when the predicted slack is decreased, it is only reset to 0. Therefore, an arithmetic unit for subtracting the predicted slack and whether the predicted slack is equal to or lower than Vmin are checked. There is no need for a comparator.

  Since the increase amount Cinc and the increase amount Vinc are both 1, the adders 40 and 50 of the proposed mechanism perform only a very simple operation of inputting only 1 to the reliability or predicted slack and adding 1 to the input. Good. Specifically, if the 0th bit to the (n-1) th bit of the input are all 1, the inverted nth bit of the input is the nth bit of the output, otherwise the nth bit of the input Is the nth bit of the output. Therefore, unlike the subtracter 5 of the conventional mechanism, it can be realized very easily.

  By utilizing that the increments Cinc and Vinc are both 1, the comparators 94 and 112 of the proposed mechanism can be simplified. The proposed mechanism adder 40 (or 50) only adds 1 to the reliability (or predicted slack). Therefore, if the input data of the adder 40 (or 50) matches Cth−1 (or Vmax), the comparators 94 and 112 output the adder 40 (or 50) with the threshold value Cth or more. (Or exceeding the maximum value Vmax).

  In order to accurately compare the conventional mechanism with the proposed mechanism, the table structure (number of entries, association degree, line size) in which the slack prediction accuracy hardly changes in each mechanism and the access time and power consumption are minimized. Need to know the number of ports). However, in the conventional mechanism, the influence of the configuration of the tables (slack table 20, memory definition table 3, and register definition table 2) on the slack prediction accuracy has not been sufficiently investigated yet.

  Therefore, in this chapter, a table configuration is used in which the accuracy of the conventional mechanism and the proposed mechanism is comparable. Specifically, for the slack table 20, the configuration (number of entries 8K, association degree 2) used in the evaluation in the previous chapter is used. Both the threshold value Cth and the maximum value Vmax are assumed to be 15 which is the value at which the hardware amount of the proposed mechanism is the largest among the values used in the evaluation in the previous chapter. Regarding the memory definition table 3 and the register definition table 2, the configuration assumed in Non-Patent Document 10 cited for comparison of accuracy in the previous chapter is used. Specifically, the memory definition table 3 has an entry number of 8K and an association degree of 4, and the register definition table 2 has an entry number of 64 and an association degree of 64.

  According to Non-Patent Document 10, the definition tables 3 and 2 hold a part of the program counter value (PC). In addition, as can be seen from the evaluation results in the previous chapter, there are about 70% of dynamic execution instructions with actual slack of 30% or less, so the number of bits required to represent the definition time can be reduced. There is sex. However, in Non-Patent Document 10, there is no specific discussion regarding these numerical values. In this chapter, therefore, slack prediction accuracy is emphasized, and it is assumed that definition tables 3 and 2 hold all program counter values (PC). Further, it is assumed that the number of bits necessary for representing the definition time is not reduced. Therefore, the data fields in the definition tables 3 and 2 are set assuming the worst case.

  Since the above-described table configuration emphasizes slack prediction accuracy, the access time and power consumption may be excessive. However, there is an advantage that the access time and the power consumption can be compared using a table configuration that has been found to have substantially the same accuracy.

3.2. Comparison of hardware amount.
The hardware amount is compared based on the number of memory cells held in the necessary table and the number and number of input bits of the arithmetic unit. In the table, a tag array and a data array occupy most of the hardware amount. Therefore, the hardware amount of the table is estimated by the number of memory cells held by the tag array and the data array. Table 2 shows the required number of memory cells and ports in the table. Table 2 (a) shows the case of the conventional mechanism, and Table 2 (b) shows the case of the proposed mechanism.

Table 2 shows the number of entries in each table, and then shows the number of memory cells per entry divided into a tag field and a data field. The product of the number of entries and the number of memory cells per entry is the total number of memory cells in the table. The table also shows the number of ports in each table. The number of ports will be used later to evaluate access time and power consumption. In Table 2, the slack table 20, a memory definition table 3, expressed register definition table 2 number of entries each _{E slack,} E _mdef, and _{E RDEF,} respectively _{associativity,} A _slack, A _mdef, represented as _{A RDEF.} In order to make a comparison under the same conditions, the number of entries in the slack table and the degree of association are the same in the proposed mechanism and the conventional mechanism. N _fetch , N _issue , N _dcport , and N _commit represent the fetch width, issue width, number of data cache ports, and commit width, respectively. N _fetch , N _issue , and N _commit are assumed to be the same. Erob represents the number of ROB entries. From the evaluation environment of the previous chapter, N _fetch = 8 and E _ROB = 256.

The time T _cs is a value representing the context switch interval in units of cycles. In the conventional mechanism, slack is calculated using time. When the time when the process selected by the scheduler starts execution is set to 0, the time is counted until the process is saved from the processor by the context switch. Therefore, log ₂ (T _cs ) bits are required to correctly represent the time. In Linux OS, since the interval between context switches is on the order of msec, it is assumed that the time T _cs is about 1 msec. Further, it is assumed that the operating frequency of the processor is 1.2 GHz from the operating frequency of the ARM core at the time of the 0.13 μm process shown in Non-Patent Document 9. Therefore, approximately 20 bits are required to express the time. Therefore, hereinafter, log ₂ (T _cs ) = 20.

Comparing the slack table 20 between the conventional mechanism and the proposed mechanism, the conventional mechanism increases the number of memory cells in the data field by log ₂ (Cth + 1) bits. However, since there are tables other than the slack table 20, the size of the hardware amount of all the tables cannot be determined only by the slack table 20.

  Therefore, the hardware amount of all tables is calculated by substituting values for each variable of the table. The number of memory cells of the proposed mechanism is 229376 for the slack table, 2048 for the FIFO, and a total of 231424. On the other hand, the number of memory cells of the conventional mechanism is 196608 for the slack table 20, 598016 for the memory definition table 3, and 3840 for the register definition table 2, and the total is 798464. Therefore, the number of memory cells is smaller in the proposed mechanism.

  In the above evaluation, the definition table of the conventional mechanism is set assuming that the size of each data field is the worst case, but even if this size is halved, the memory / The conclusion that there are fewer cells remains the same. However, as explained in the previous section, in order to perform an accurate comparison, it is necessary to know a table configuration that can provide sufficient slack prediction accuracy, which is a future problem.

  Next, the hardware amount of the computing unit is compared. Table 3 shows the number of input bits and the number of arithmetic units. Table 3 (a) shows the case of the conventional mechanism, and Table 3 (b) shows the case of the proposed mechanism.

  The number of input bits is the total number of bits of each input of the arithmetic unit. Note that the number of comparators 94 and 112 is a value when the number of pipeline stages that perform forwarding at the defined time is one. If the number of stages increases, the number of comparators 94 and 112 increases in proportion to the number of stages. However, if it is not necessary to perform forwarding, a comparator is not necessary.

  Compare the calculator of the conventional mechanism and the proposed mechanism. Here, in order to show that the proposed mechanism surely reduces the amount of hardware, consider the case where the conventional mechanism does not need to forward the defined time.

Since N _issue = N _commit = 8, it can be seen that the proposed mechanism has 24 more arithmetic units than the conventional mechanism. However, since the arithmetic unit of the proposed mechanism can be realized very easily as described above, it is not possible to compare hardware amounts by simply focusing on the number of arithmetic units. Therefore, the configuration of each arithmetic unit will be examined in detail. First, since the subtracter of the conventional mechanism has log ₂ (T _cs ) = 20, the input is 20 bits. The basic circuit configuration is almost the same as an adder with an input of 20 bits. A hardware amount of the conventional mechanism is obtained by multiplying the adder by 8 times.

  Next, the configuration of the calculator of the proposed mechanism will be examined in detail. First, if the threshold value Cth and the maximum value Vmax are both assumed to be 15 as before, each arithmetic unit of the proposed mechanism has an input of 4 bits.

  FIG. 19 is a block diagram showing the configuration of the update unit 30 according to the first embodiment of the present invention. Here, FIG. 19 shows a circuit configuration of an arithmetic unit (a circuit constituted by these is referred to as an update unit 30) required for one instruction to be committed. A hardware amount of the proposed mechanism is eight times the circuit of the update unit 30. The arrival condition flag Rflag in FIG. 19 is 1 when the target slack arrival condition is satisfied, and 0 when it is not. The central AND gates 31 and 35 in FIG. 19 constitute a reliability comparator 94 and a prediction slack comparator 112, respectively, and the portions surrounded by dotted lines constitute adders 40 and 50, and other elements (OR gate 33). 37 and multiplexers 34, 38, 39) are control circuits. Here, when the number of input bits is 4 bits, the reliability comparator 94 and the prediction slack comparator 112 each have a 4-input AND gate that inputs each bit of the input value as it is or an inverted version. 31 and the AND gate 35. Each adder 40, 50 of the proposed mechanism has two AND gates (41-42; 51-52), four inverters (43-46; 53-56), and three multiplexers (47-49; 57-59). Therefore, it can be said that it can be realized with a hardware amount sufficiently smaller than that of the 20-bit subtractor required in the conventional mechanism.

3.3. Comparison of access time and power consumption.
In this section, in order to obtain the access time of the table and the energy consumption per access, a known CATTI that is a cache simulator (for example, see Non-Patent Document 12) is used. In the evaluation by CACTI, it is assumed that the process is 0.13 μm and the power supply voltage is 1.1 V based on the ARM core data of Non-Patent Document 9. In CACTI, it is necessary to input the line size of the table in bytes. However, in the slack table of the conventional mechanism, since the data field is 4 bits, the line size is less than 1 byte. Therefore, the data field is assumed to be 8 bits only when the evaluation is performed by the CACTI. However, this assumption only doubles the size of the slack table of the conventional mechanism, so a fair comparison cannot be made as it is. Therefore, when the proposed mechanism is evaluated by CACTI, the data fields of the slack table 20 and the FIFO 17 which are tables holding slack values are increased from 8 bits to 16 bits. Since the memory definition table 3 and the register definition table 2 do not hold slack values, the data field is not changed.

  Based on the above assumption, the slack table 20 of the proposed mechanism increases the access time by 4.1% and the energy consumption by 23%. From this, it can be considered that a similar error has occurred in the evaluation result of the slack table 20 of the conventional mechanism. In addition, the FIFO 17 of the proposed mechanism reduces the access time by 4.2% and increases the energy consumption by 116%. Therefore, the effect of this error is taken into account when making the comparison. The reason why the access time of the FIFO 27O is reduced is that CACTI changes the data array dividing method depending on the table configuration.

  First, the access time of the proposed mechanism and the conventional mechanism are compared. As already indicated, the scale of the arithmetic unit used in the slack prediction mechanism is smaller than ALU (Arithmetic Logical Unit). On the other hand, there is a table of the same size (or more) as the data cache used in the processor. Therefore, it can be considered that the access time of the proposed mechanism and the conventional mechanism is determined by the access time of the table. Therefore, the table access times are compared.

  Table 4 shows the access time of the table measured by CACTI. When Table 4 (a) is a conventional mechanism, Table 4 (b) is a case of a proposed mechanism.

  From Table 4, it can be seen that the slack table 20 has a much longer access time than the memory definition table 3, although the amount of hardware is small. This is because the table access time is determined not by the amount of hardware but by the table configuration (number of entries, associativeness, line size, number of ports, etc.).

  Since the operating frequency is assumed to be 1.2 GHz (cycle time 0.83 nsec), in order to access the slack table 20, the memory definition table 3, and the register definition table 2 at high speed, It can be seen that it is necessary to pipeline into 6 stages, 3 stages and 2 stages. Even if the measurement error of the access time in the slack table 20 is taken into consideration, the number of stages does not decrease. However, even if these tables 3 and 2 are pipelined into six stages, the number of cycles required to obtain the predicted slack of the fetched instruction is very long, and it is difficult to use it. In addition, when the memory definition table 3 and the register definition table 2 are pipelined, there is a problem that power consumption increases because of forwarding of the definition time. However, in this section, discussions are made assuming that these tables 3 and 2 are pipelined as described above, and these problems will be discussed in the next section.

  Furthermore, it can be seen from Table 4 that the access time of the slack table 20 is the longest in either mechanism. Therefore, it can be seen that the access time is longer in the proposed mechanism. Although there is a measurement error in the access time of the slack table 20, the access time is considered to increase to the same extent in either mechanism, so this conclusion is not affected.

  Next, power consumption is compared. However, from the evaluation results in the previous chapter, the execution time of the conventional mechanism and the proposed mechanism is almost the same, so energy consumption should be compared. The total energy consumption of the circuit is represented by the product of the energy consumption required per operation and the number of operations.

  The number of operations of each circuit is measured using the evaluation environment in the previous chapter. Since the conventional mechanism is not incorporated in the simulator used in the previous chapter, the number of operations of each circuit of the conventional mechanism is estimated from the operation of the processor 10. Specifically, in the case of the slack table 20, since it is referred to when fetched and updated when an instruction is executed, the sum of the number of fetched instructions and the number of instructions executed by the functional unit is set as the number of operations. In the case of the memory definition table 3, since it is referenced when a load instruction is executed and updated when a store instruction is executed, the number of executions of the load / store instruction is set as the number of operations. In the case of the register definition table 2, since the physical register number corresponding to the source register of the instruction to be executed is referred to and updated with the physical register number corresponding to the destination register, the source register of the instruction executed by the functional unit 15 The number of operations is the sum of the number and the number of destination registers. In the case of the subtracter 5, the number of operations is the sum of the number of instructions that may calculate slack from the time, that is, the instruction having the destination register and the store instruction executed by the functional unit 15. As for the comparator of the conventional mechanism, it is assumed that the pipelined memory definition table 3 and the register definition table 2 exist, and which instruction references and updates which table in each cycle is simulated. . Then, between instructions that reference / update the same table, the memory address comparison or physical register number comparison required for forwarding at the defined time is performed, and the number of comparisons is assigned to each address. The number of operations of the comparator for register and the comparator for register number. Since the cycle time is assumed to be 0.83 nsec, it is assumed from Table 4 that the memory definition table 3 and the register definition table 2 are pipelined in three stages and two stages, respectively.

  In the case of a table, the energy consumption per operation is measured using CACTI. On the other hand, in the case of computing units, we will consider which energy consumption will be larger based on the hardware amount shown in the previous section.

  Table 5 shows the benchmark average of the number of operations of each circuit and the energy consumption per operation of the table. Table 5 (a) shows the case of the conventional mechanism, and Table 5 (b) shows the case of the proposed mechanism.

  First, the energy consumption of computing units is compared. Here, the energy consumption per operation of the arithmetic unit is represented by the product of the average of the load capacity charged and discharged in one operation and the square of the power supply voltage. The power supply voltage is constant. On the other hand, the load capacity to be charged / discharged is represented by the total capacity of the node switched during operation. In order to obtain this value accurately, it is necessary to design an arithmetic unit and check which node is switched with respect to a given input, which cannot be easily evaluated. Therefore, in this section, to simplify the comparison, it is assumed that the load capacity for charging / discharging increases as the amount of hardware increases. Then, the energy consumption per operation of the computing unit is compared based on the hardware amount shown in the previous section.

  From the previous section, the hardware amount of the calculator (update unit 30) of the proposed mechanism is sufficiently smaller than the subtractor of the conventional mechanism. Therefore, it can be determined that less energy is required to operate the computing unit of the proposed mechanism once. Also, from Table 5, the number of operations of the computing unit is smaller in the proposed mechanism. From these, it is considered that the total energy consumption of the calculator of the proposed mechanism is smaller than that of the subtractor of the conventional mechanism.

  Further, in the conventional mechanism, it is necessary to perform forwarding at a defined time. Specifically, the comparison value (address or register number) and the definition time are broadcast using wiring, the address comparison or register number comparison is performed using the comparator, and if the comparison results match, the multiplexer 4 Then, an operation of supplying the corresponding definition time to the subtracter 5 is performed. Therefore, the energy consumption per operation is considered to be a level that cannot be ignored. From Table 5, the number of address comparisons and the number of register number comparisons are 27M and 488M, respectively.

  From these, it can be considered that the total energy consumption of the calculator of the proposed mechanism is considerably smaller than the total energy consumption of the calculators of the conventional mechanism (subtractor, comparator, and broadcast wiring).

  Next, the energy consumption of the tables is compared. In the slack table 20 whose roles are almost the same, the energy consumption per operation is smaller in the conventional mechanism and the number of operations is smaller in the proposed mechanism, but the total energy consumption in the slack table 20 is the same as that of the conventional mechanism. Will be less. However, the total energy consumption of the entire table is 1.76 J in the case of the conventional mechanism and 1.62 J in the case of the proposed mechanism, which indicates that the number of the proposed mechanism is smaller.

  Here, the influence of the measurement error of CACTI is considered. Although there is a measurement error in the energy consumption of the slack table 20, it can be said that the energy consumption of both mechanisms increases to the same extent, so that the comparison result of the slack table 20 is not affected. Further, although the consumed energy of the FIFO is estimated to be larger due to the measurement error, no measurement error occurs in the consumed energy of the memory definition table 3 and the register definition table 2. Therefore, considering the influence on the energy consumption of the entire table, the generated measurement error is more disadvantageous for the proposed mechanism. Therefore, it can be said that the conclusion that the energy consumption of the proposed mechanism is smaller does not change.

  From the above, it is considered that the energy consumption of the conventional mechanism is larger in both the calculator and the table.

  The slack table 20 of the conventional mechanism consumes less energy than the proposed mechanism. Therefore, if the energy consumption of the memory definition table 3 and the register definition table 2 can be reduced without reducing the slack prediction accuracy, the energy consumption of all the tables may be made smaller than that of the proposed mechanism. As an approach to achieve this object, a method of reducing the size of the transistor used in the circuit and reducing the load capacity for charging and discharging can be considered. In this method, since it is not necessary to change the table configuration, energy consumption can be reduced without reducing slack prediction accuracy.

  However, in this approach, the transistor size is reduced, so that the access time of the memory definition table 3 and the register definition table 2 becomes long. As a result, the number of pipeline stages in these tables increases, and the energy consumption required for forwarding at the defined time increases. Thus, it can be seen that the forwarding at the defined time required for high-speed access not only increases the energy consumption of the computing unit, but also prevents the energy consumption from being reduced by the above approach.

3.4. Optimization of table structure using locality of reference.
The table configuration used in the previous section causes a problem of making it difficult to use the predicted slack because the access time becomes very long, and a problem of increasing the energy consumption related to the forwarding at the defined time. In order to solve these problems, it is necessary to change the table configuration (number of entries, association degree, line size, number of ports). However, 3.1. As described in the section, the influence of the table configuration on the slack prediction accuracy is not clarified in the conventional mechanism. Therefore, it does not make much sense to simply change the table configuration and measure the access time and power consumption.

  Therefore, in this section, only the changes that are considered to have little effect on slack prediction accuracy are made to the table configuration used in the previous section, and how the access time and power consumption are improved is evaluated. The FIFO 17 of the proposed mechanism does not change the configuration because the access time is sufficiently shorter than other tables.

  For this purpose, the inventors pay attention to the access pattern of each table. First, the slack table 20 is considered separately for data reference patterns and update patterns. In referring to the slack table 20, the program counter value (PC) of the instruction to be fetched is used as an index. Therefore, like the instruction cache, the program counter value (PC) used as an index is continuous until the branch predicted as “taken” (taken: “branch”) is reached, and the locality of reference is very high.

  On the other hand, in updating the slack table 20, in the case of the conventional mechanism, the program counter value (PC) of the instruction executed by the functional unit 15 is used as an index. Therefore, although the program counter value (PC) used as an index becomes discontinuous due to out-of-order execution, the range in which the order is changed is limited to the instructions in the processor 10, so that the locality of reference is still high. I can say that. In the case of the proposed mechanism, the program counter value (PC) of the instruction committed from the ROB 16 is used as an index. Therefore, the program counter value (PC) used as an index is continuous until reaching the taken branch, and the locality of the update is very high.

  From the above, in the slack table 20, it is considered that the line size can be increased with little influence on the slack prediction accuracy. However, as with the cache, if the line size is increased too much, the line utilization efficiency decreases and the table miss rate increases. Therefore, it is necessary to determine the line size in consideration of this fact.

  Furthermore, it is considered that the read port and the write port can be reduced by using the fact that the program counter value (PC) used as an index is continuous and performing the reference / update in line units.

Here, if the line size of the slack table 20 is increased and the slack value for two instructions is held on one line, how much the read port and the write port can be reduced by referring / updating in line units. think of. In the processor 10 assumed in this section, since N _fetch = 8, the number of ports can be reduced to 10 (5 read ports, 5 write ports) if reference / update is performed in line units. Even if there are more ports, they cannot be used. In addition, since the slack values to be referenced / updated are not necessarily arranged in order from the beginning of the line, if the number of ports is further reduced to 8, the reference / update may fail. . From these, it can be seen that if the line size is determined, the number of ports that can be reduced is uniquely determined.

  Similarly, when the line size is further increased, it is understood that the number of ports becomes 6 and 4 respectively when the slack values for 4 instructions and 8 instructions are held on one line. . However, even if the line size is increased beyond this, the slack value to be referenced / updated may exist in two lines, so the number of ports cannot be made smaller than four. In the case of the conventional mechanism, since the PCs used as indexes at the time of updating are not continuous, the number of write ports cannot be reduced even if updating is performed in line units. However, it can be considered that update data can be aligned relatively easily if a change is made such that update data is stored in a buffer and then updated in the order of fetching. Therefore, in this section, it is assumed that the number of write ports can be reduced even in the conventional mechanism.

FIG. 20 is a graph showing the result of simulation of the conventional mechanism according to the prior art and showing the access time of the slack length with respect to the line size. FIG. 21 is a graph showing simulation results of the proposed mechanism including the update unit 30 of FIG. 19 and showing the access time of the slack length with respect to the line size. That is, FIG. 20 and FIG. 21 show the results of evaluating the access time by increasing the line size of the slack table 20 by 2 ⁿ times (1 ≦ n ≦ 7) in the conventional mechanism and the proposed mechanism, respectively. CACTI is used for evaluation. As described in the previous section, since the data field of the slack table 20 of the conventional mechanism is 4 bits, it cannot be evaluated by CACTI unless the line size is increased. However, if the line size is increased as described above, the line size increases in units of bytes, so that the evaluation can be performed using CACTI. Therefore, in this section, unlike the previous section, evaluation is performed without changing the number of bits in the data field. As a result, the conventional mechanism and the proposed mechanism can be compared more accurately than in the previous section.

  20 and 21, the vertical axis represents access time, and the horizontal axis represents line size. In the line graph, the upper side does not reduce the number of ports, and the lower side shows a case where the number of ports is reduced. As can be seen from FIGS. 20 and 21, it can be seen that the access time is shortened when the number of ports is reduced. On the other hand, it can be seen that the access time decreases at the beginning as the line size increases, but tends to increase after a while. Therefore, it can be seen that if the access time is reduced, the number of ports should be reduced and a slack value for 8 instructions or 16 instructions may be held on one line. However, even if slack values of 16 instructions or more are held on one line, they are not all required at the same time, and the line utilization efficiency is lowered. Therefore, in this section, the line size in the slack table 20 is changed to a size that can hold the slack value for 8 instructions, and the number of ports is reduced. Specifically, it is 4B in the case of the conventional mechanism (B is a byte, the same applies hereinafter), and is 8B in the case of the proposed mechanism. At this time, in any mechanism, the number of ports can be reduced to four.

  Next, consider the memory definition table 3. The memory definition table 3 is updated by referring to the load address and the store address as indexes. Therefore, like the data cache, it can be said that the locality of reference is high. Therefore, it is considered that the line size can be increased with little influence on the slack prediction accuracy. However, as before, it is necessary not to increase the line size too much.

  FIG. 22 is a graph showing a simulation result of the proposed mechanism including the update unit 30 of FIG. 19 and showing the access time of the memory definition table with respect to the line size. That is, FIG. 22 shows the result of evaluating the access time by changing the line size of the memory definition table 3. The vertical axis in FIG. 22 indicates access time, and the horizontal axis in FIG. 22 indicates line size. As can be seen from FIG. 22, the access time decreases as the line size increases, but does not decrease at 28B, and increases at 112B or higher. Therefore, it can be seen that if the access time is reduced, the line size should be increased so as not to exceed 56B.

  However, if the line size is increased too much, the line utilization efficiency decreases, and the table error rate may increase. According to Non-Patent Document 7, when the line size is increased from 16B to 256B in a data cache having a capacity of 1K to 256KB, the cache miss rate decreases at any capacity up to 32B. It is shown to go. In this case, since the minimum block is 4B, when the line size is 32B, it means that data for 8 blocks is held on one line. Although the evaluation environment such as the benchmark is different, this section assumes the line size range that does not increase the table miss rate, referring to this result. Specifically, in the memory definition table 3, since the smallest block is 7B (PC + definition time), it is assumed that the table miss rate does not increase if the line size is 56B or less. As described above, in this section, the line size of the memory definition table 3 is changed to 56B.

  Finally, consider register definition table 2. The register definition table 2 is updated by referring to the physical register number assigned to the instruction as an index immediately before execution of the instruction. Therefore, there is no locality of reference like the slack table 20 and the memory definition table 3. Therefore, in this section, the configuration of the register definition table 2 is not changed.

  Table 6 shows the access time and energy consumption per operation when the table configuration is optimized focusing on the locality of reference. In this section, it is not necessary to change the number of bits of the data field as in the previous section when evaluating with CACTI. Therefore, the access time and energy consumption per operation are also shown for the FIFO 17 when such a change is not made.

  From Table 6, it can be seen that both the slack tables of the conventional mechanism and the proposed mechanism have a significantly reduced access time, which is very close to the assumed cycle time of 0.83 nsec. As a result, the number of pipeline stages is reduced to one in the case of the conventional mechanism and to two in the case of the proposed mechanism, so that the slack value of the fetched instruction can be used sufficiently. Also, the access time of the memory definition table is reduced, and the number of pipeline stages is changed from three to two. As a result, the number of address comparators is reduced by the number of stages, and the number of times this comparator is operated is reduced from 27M to 13M. However, forwarding at the defined time is still necessary, and the total energy consumption of the arithmetic unit is larger in the conventional mechanism. Table 6 also shows that the energy consumption per operation is reduced in both the slack table 20 and the memory definition table 3.

  Next, consider the access time and energy consumption of the overall slack prediction mechanism. From Tables 4 and 6, it can be seen that the access time of the conventional mechanism is longer than that of the proposed mechanism because the access time of the slack table 20 is reduced.

  Using Tables 5 and 6, the energy consumption after the table configuration is optimized is calculated. Note that the slack table 20 has been changed so that the number of ports is reduced to 1/4 by referring / updating on a line basis, so the number of operations of the slack table is equal to the value shown in Table 5. The calculation is performed assuming that it is 1/4. As a result of calculation, the energy consumption of the entire table is 0.37 J in the case of the conventional mechanism and 0.06 J in the case of the proposed mechanism, and it can be seen that both are greatly reduced. As in the previous section, the energy consumption of the slack table 20 is smaller in the conventional mechanism, and the energy consumption of the entire table is smaller in the proposed mechanism.

  From the above, it can be seen that the problem related to the access time of the slack table 20 can be solved by optimizing the table configuration using the locality of reference. Moreover, it turns out that the energy consumption of a slack prediction mechanism can be reduced significantly.

4). Reduction of power consumption of functional units.
As an application example of local slack prediction, an instruction having one or more predicted slacks is executed by a functional unit that is slower and consumes less power, thereby reducing the power consumption of the functional unit without greatly degrading the performance. Research has been carried out (for example, see Non-Patent Document 6). Therefore, also in this embodiment, the reduction in power consumption is taken as an application example, and the effect of the proposed method is evaluated.

4.1. Evaluation environment.
The differences from the evaluation environment described in Chapter 2 are described. FIG. 23 is a block diagram showing a configuration of a processor 10A having a slack table 20 according to a first modification of the first embodiment of the present invention.

  Two types of function units (iALU) for integer operations are prepared, high speed and low speed. In FIG. 23, 15a is a functional unit that operates at a high speed, and 15b is a functional unit that operates at a low speed. Non-Patent Document 9 shows that the ARM core in the 0.13 μm process has a power supply voltage of 1.1 V and 0.7 V, respectively, when the operating frequency is 1.2 GHz and 600 MHz. Based on this, the operating frequency of the processor is 1.2 GHz (cycle time 0.83 nsec), and the high-speed iALU and the low-speed iALU have an execution latency of 1 cycle and 2 cycles, respectively, and the power supply voltage is 1.1 V and 0, respectively. .7V. In the evaluation, a model having n high-speed iALUs is referred to as an (nf, (6-n) s) model.

  Predict local slack using the proposed method. In order to perform the evaluation under conditions close to those of the conventional method, the maximum value of predicted slack Vmax = 1 and the threshold value Cth = 15, and all parameters of the slack table 20 are fixed. After the instruction scheduler selects an instruction to be executed by the iALU from the instructions having the operands, the instruction having a predicted slack of 1 is selected as a low-speed iALU and the instruction having a predicted slack of 0 is selected as a high-speed iALU. Assign to. However, an instruction is assigned to a high-speed iALU if there is no free space in the low-speed iALU, and to a low-speed iALU if there is no free space in the high-speed iALU. Predictive slack is used only when an instruction is assigned to an iALU, and is not used in other processes. For example, the instruction scheduler does not use predicted slack when selecting an instruction to be executed by an iALU. Also, the order in which instructions are assigned to iALUs is in accordance with the order in which instructions are selected by the instruction scheduler, and predicted slack is not used.

  In the above method, the energy consumption of the iALU is reduced by executing the instruction with the low-speed iALU. However, if the predicted slack exceeds the actual slack, the processor performance is adversely affected. In the processor 10, performance is a very important factor. Therefore, the product of energy consumption and processor execution time (EDP: Energy Delay Product) is measured as an index that can simultaneously consider the effect of reducing energy consumption and adverse effects on processor performance.

  The execution time of the processor 10 can be represented by the product of the number of execution cycles and the cycle time (reciprocal of the operating frequency). On the other hand, the energy consumption of the functional units 15a and 15b can be represented by the product of the number of times an instruction is executed by iALU and the energy consumption per execution. The energy consumption per execution can be expressed by the product of the average of the load capacity charged and discharged in one execution and the square of the power supply voltage. Therefore, EDP is expressed by the following equation (1).

[Equation 1]
^{_{EDP = (C f · V f}} 2 · N f + C s · V s 2 · N s) · N c / f (1)

Here, C _f and C _s are load capacities that are charged and discharged per execution in the high-speed iALU and the low-speed iALU, respectively. V _f and V _s are the power supply voltages of the fast iALU and the slow iALU, respectively. N _f and N _s are the number of times instructions are executed in the high-speed iALU and low-speed iALU, respectively, and Nc is the number of execution cycles. f is the operating frequency.

As the parameters Vf, Vs, f, values assumed previously are used. The parameters N _f , N _s , and N _c are obtained by simulation. The high-speed iALU and the low-speed iALU have different operating frequencies and power supply voltages, but the types of instructions that can be executed are the same. Therefore, in this section, it is assumed that, regardless of which iALU a dynamic instruction is executed, the load capacity (the total capacity of nodes that are switched during operation) to be charged and discharged until the execution of the instruction is completed is the same. _Let C _f = C _s .

  Strictly speaking, since the node to be switched in the circuit depends on the type of operation (addition, shift, etc.) and the input value, if these are different, the load capacity to be charged / discharged in one execution changes. In order to accurately obtain this value, it is necessary to design an arithmetic unit and check which node has switched for a given input, which is not easy. For this reason, the evaluation in this section does not consider changes in load capacity that occur due to differences in the types of calculations and input values.

4.2. Evaluation Results FIG. 24 is a graph showing simulation results of the embodiment of the processor 10A of FIG. 23 and showing normalized IPC for each program. FIG. 25 is a graph showing simulation results of the embodiment of the processor 10A of FIG. 23 and showing normalized EDP (Energy Delay Product: product of consumed energy and execution time of the processor 10A) for each program. That is, FIG. 24 and FIG. 25 show IPC and EDP of each benchmark, respectively. The bar graphs made up of six lines are (5f / 1s), (4f / 2s), (3f / 3s), (2f / 4s), (1f / 5s), (0f / 6s) in order from the left. This is the case with a model. The vertical axis of FIG. 24 shows the IPC normalized by the IPC of the (6f / 0s) model (a model in which all iALUs are high-speed), and the vertical axis of FIG. 25 is normalized by the EDP of the (6f / 0s) model. EDP is shown.

  From FIG. 24 and FIG. 25, it is understood that almost the same tendency is shown in any benchmark. When the number of fast iALUs is reduced, in most cases the EDP decreases monotonically. However, since the proposed method schedules instructions based on the predicted slack, it can suppress the decrease in IPC. In the (0f / 6s) model (a model in which all iALUs are low speed), the IPC reduction is 20.2% and the EDP reduction rate is 41.6% on average. On the other hand, the (1f / 5s) model can improve the IPC reduction to 10.5% despite the EDP reduction rate of 34.5%. In addition, the (3f / 3s) model has an EDP reduction rate of 20.3% even though the IPC reduction is only 3.8%.

  In Non-Patent Document 6, although a benchmark program and a processor configuration are different from the present embodiment, a (3f / 3s) model is evaluated using a conventional method as a slack prediction mechanism. As a result, it is shown that EDP can be reduced by 19% with a decrease in IPC of 4.5%. From this, it can be seen that the proposed method shows the same result as the conventional method.

  The above evaluation focuses only on the power consumption of the functional unit. Considering the power consumption of the slack table, there is a possibility that the power consumption of the entire processor will not decrease, which is a future issue. However, even in the present situation, it is considered that the effect of reducing hot spots on the chip can be obtained by suppressing the power consumption of the functional unit.

4.3. Application example when the maximum value Vmax of predicted slack is 2 or more.
In the application example evaluated in the previous section, the advantage of slack that the degree of urgency when executing each instruction can be divided into three or more types is not utilized. Therefore, an application example in the case where the maximum value Vmax of predicted slack is 2 or more in the proposed slack prediction mechanism will be described.

  As an application example, it is conceivable to suppress a decrease in performance of a processor that has reduced power consumption of a functional unit. For example, in the (3f / 3s) model with the maximum predicted slack value Vmax = 2, the instruction selected by the instruction scheduler is assigned to the iALU as follows. First, an instruction whose predicted slack is 0 is assigned to a high-speed iALU. If there is no space in the high-speed iALU, it is assigned to the low-speed iALU. Next, an instruction with a predicted slack of 2 is assigned to a slow iALU. If the low-speed iALU has no free space, it is assigned to the high-speed iALU. Finally, an instruction with a predicted slack of 1 is assigned to a slow iALU. If the low-speed iALU has no free space, it is assigned to the high-speed iALU. As a result, when the total number of instructions with predicted slack of 1 or 2 exceeds the number of low-speed iALUs, instructions with higher urgency (predicted slack of 1) are preferentially fast iALU. Can be assigned to.

  In addition to the above, an application example in which instruction scheduling is performed based on predicted slack to improve performance can be considered. For example, in the (3f / 3s) model with Vmax = 2, the following modification is added to the instruction scheduler. In other words, instructions are selected in ascending order of predicted slack from the instructions with the same operand, and if the predicted slack of the instruction not selected is 1 or 2, it is reduced by 1. The reason why the predicted slack of the instruction that has not been selected is reduced by 1 is because the execution start of the instruction is delayed by one cycle because it is not selected. With this modification, an instruction with predicted slack of n + 1 or more is not selected instead of an instruction with predicted slack of n. As a result, instructions can be executed in the order according to the degree of urgency, which may reduce performance degradation due to low power consumption.

5). Summary.
The present inventor has proposed a mechanism for predicting slack by a heuristic technique. Since slack is indirectly estimated from the behavior of instructions, it can be realized with simpler hardware than conventional methods. As a result of the evaluation, it was found that when the reliability threshold value of the slack table is 15, the execution latency can be increased by one cycle for 31.6% of the instructions with a decrease of IPC of only 2.5%. Further, it was found that when the power consumption of the functional unit is reduced, the EDP can be reduced by 20.3% with an IPC reduction of only 3.8%.

6). Simulation Results of Another Example Further, simulation results of another example will be described below.

  FIG. 26 is a graph showing simulation results of another embodiment of the processor 10A of FIG. 23 and showing normalized IPC for each program. FIG. 27 is a graph showing simulation results of another example of the processor 10A of FIG. 23 and showing normalized EDP (Energy Delay Product: product of consumed energy and processor execution time) for each program. That is, FIG. 26 and FIG. 27 show the measurement results of normalized IPC and normalized EDP in each benchmark in each model. The vertical axis in FIG. 26 represents the ratio of IPCs based on the IPC in the (6f, 0s) model (all iALU is a high-speed model) as the reference (100), and the vertical axis in FIG. The ratio of EDP with EDP as a reference (100) in (all iALU is a high-speed model) is shown. 26 and 27, the six vertical bars in each benchmark program are (5f, 1s), (4f, 2s), (3f, 3s), (2f, 4s), ( 1f, 5s) and (0f, 6s), the measurement results for the respective models are shown.

  As shown in FIGS. 26 and 27, the same tendency can be seen in any of the benchmark programs. That is, when the number of high-speed iALUs is decreased, in most cases, EDP decreases monotonously. However, since the instructions are distributed based on the prediction result of local slack, the decrease in IPC accompanying the decrease in the number of high-speed iALUs is suitably suppressed. For example, in the (0f, 6s) model, that is, a model in which all iALUs are low speed, the benchmark average IPC decrease is 20.2%, and the EDP reduction rate is 41.6%. On the other hand, in the (1f, 6s) model, although the EDP reduction rate is 34.5%, the decrease in IPC is only 10.5%. Furthermore, in the (3f, 3s) model, the reduction rate of EDP is 20.3% while the decrease in IPC is only 3.8%.

  In the above evaluation, only the power consumption of the functional unit 15 is focused, and the power consumption required for the operation of the slack table 20 is not considered at all. Therefore, the effect of reducing the power consumption of the entire processor is based on the above result. Becomes lower. However, as long as the power consumption required for the operation of the slack table 20 can be kept sufficiently low, a sufficient effect can be expected for reducing the power consumption of the entire processor. However, the functional unit 15 is one of the typical hot spots on the chip. Even if the power consumption of the entire processor is not suitable, if the power consumption of the functional unit can be suppressed, the distribution of hot spots on the chip is possible. The effect that it can be made can be acquired.

  In the local slack prediction mechanism of this embodiment, the fetch unit 11 also functions as the execution latency setting unit. In addition, the slack table 20 (strictly, the operation circuit related to the update of the entry) also has the functions as the estimation means and the predicted slack update means.

According to the local slack prediction method and local slack prediction mechanism of the present embodiment described above, the following effects can be obtained.
(1) Predicted slack is not calculated directly by calculation, but is calculated by gradually increasing the predicted slack until the target slack is reached while observing the behavior during execution of the instruction. The complicated mechanism required for the direct calculation is not required, and local slack can be predicted with a simpler configuration.
(2) Since the behavior at the time of instruction execution of the above conditions (A) to (D) that can be detected by the detection mechanism provided by the processor is the local slack arrival condition, a special detection mechanism is provided for local slack prediction. Even without additional installation, the arrival of the predicted slack to the target slack can be confirmed.
(3) Since the predicted slack is reduced when the target slack arrival condition is satisfied, it is possible to suitably suppress the execution delay of the subsequent instruction due to the excessive evaluation of the predicted slack.
(4) Since a reliability counter is installed and the predicted slack is carefully increased and decreased rapidly, the subsequent instruction due to overestimation of the predicted slack even when the target slack repeatedly increases and decreases The frequency of occurrence of execution delay can be kept low.

7). Extension of Slack Table Indexing Method Next, the local slack prediction method and the extension of further functions of the prediction mechanism will be described. In many cases, the behavior of a branch instruction in a program depends on what function or instruction has been executed (hereinafter referred to as a control flow) before the branch is executed. A technique for predicting the result of a branch instruction with higher accuracy using this property has been proposed. Conventionally, such a branch prediction method has been used to improve the accuracy of speculative execution of instructions. However, in the prediction of local slack, further improvement of the prediction accuracy can be expected by introducing the same principle. Hereinafter, a method for performing slack prediction with higher accuracy in consideration of the control flow will be described.

  Since the program uses a branch instruction to determine what function or instruction is executed, the control flow can be simplified by paying attention to the branch condition in the program. Specifically, “1” is recorded if the branch condition is satisfied, and “0” is stored if the branch condition is not satisfied. For example, the branch history when the branch condition is established (1) → established (1) → not established (0) → established (1) in the fetch order is expressed as “1101” when the newer one is recorded in the lower order. The In order to use the branch history for slack prediction, an index to the slack table is generated from the branch history and the PC of the instruction. In this way, slack can be predicted in consideration of both the program counter value (PC) and the control flow. For example, even if the program counter value (PC) is the same, if the control flow is different, different entries in the slack table are used, so that prediction according to the control flow can be performed.

  FIG. 28 is a block diagram showing a configuration of the processor 10 including the slack table 20 and the two index generation circuits 22A and 22B according to the second modification of the first embodiment of the present invention. That is, FIG. 28 shows an example of a hardware configuration of a local slack prediction mechanism that performs slack prediction in consideration of the control flow. In this configuration, in addition to the example shown in FIG. 6, a branch history register 21A, a branch history register 21B, and two index generation circuits 22A and 22B are newly added. The branch history register 21A and the branch history register 21B are registers for recording a branch history.

  The index generation circuits 22A and 22B have the same circuit configuration except for the difference in input. At the time of fetching an instruction, the branch history register value from the branch history register 21A and the program counter value (PC) of the instruction are input, and the index generation circuit 22A generates an index to the slack table 20, and the slack table 20 Reference. On the other hand, when the instruction is committed, the branch history register value from the branch history register 21B and the program counter value (PC) of the instruction are input, and the index generation circuit 22B generates an index to the slack table 20, and the slack The entries in Table 20 are updated. Hereinafter, the branch history registers 21A and 21B and the index generation circuits 22A and 22B will be described in more detail.

  First, the branch history update operation of the branch history registers 21A and 21B will be described. The branch history register 21A records a branch history based on the branch prediction result of the processor. Specifically, when a branch instruction is fetched, the value held in the branch history register 21A is shifted to the left by one bit, and if the branch condition of the branch instruction is predicted to be satisfied in the fetch unit 11 If “1” is predicted to be not established, “0” is written in the least significant bit of the branch history register 21A.

  On the other hand, the branch history register 21B records the branch history based on the branch execution result of the processor. Specifically, when the branch instruction is committed, the value held in the branch history register 21B is shifted to the left by 1 bit. If the branch condition of the branch instruction is satisfied, “1” is set. This is performed by a procedure of writing “0” to the least significant bit of the branch history register 21B.

  As described above, there are two ways of taking the branch history. The reason for using the branch history of both branch history registers 21A and 21B is that the slack reference is performed at the fetch time and the slack table is updated at the commit time. There is a difference. At the time of fetching, the branch instruction has not been executed yet, and the processor predicts whether or not the branch condition is satisfied and reads the instruction from the memory. Therefore, the branch history register 21A used at the time of fetching can only record the branch history based on the branch prediction. On the other hand, at the time of commit, the branch instruction has already been executed, and the branch history can be recorded based on the execution result.

  Next, the details of the index generation mode by the index generation circuits 22A and 22B will be described with reference to FIGS.

  FIG. 29 is a diagram illustrating an operation example when performing slack prediction without considering the control flow in the slack prediction mechanism according to the first embodiment. That is, FIG. 29 shows the index generation method in the above embodiment, that is, the index generation method using only the instruction PC. In this case, some bits of the program counter value (PC) are cut out and used as an index to the slack table 20.

  FIG. 30 is a diagram illustrating a first operation example when performing slack prediction in consideration of the control flow in the slack prediction mechanism of FIG. FIG. 31 is a diagram showing a second operation example when performing slack prediction in consideration of the control flow in the slack prediction mechanism of FIG. 30 shows an example of index generation using the branch history and the program counter value (PC), and FIG. 31 shows another example of index generation using the branch history and the program counter value (PC). Each example is shown below. In mounting on the actual processor 10, it is necessary to adopt a common index generation method for both index generation circuits 22A and 22B. The reason is that if different index generation methods are employed in both index generation circuits 22A and 22B, different indexes are generated when the slack table 20 is updated and when the slack table 20 is referenced, and slack cannot be correctly predicted.

  In the case of FIG. 30, the index is generated by concatenating i bits of the branch history and j bits cut out from the program counter value (PC). On the other hand, in the case of FIG. 31, the exclusive OR (EXOR) of i bits of the branch history and the same number (i) of bits extracted from the PC is taken for each bit by the exclusive OR gate 120. The bit string and j bits further extracted from the program counter value (PC) are concatenated to generate an index.

  As shown in FIG. 31, even when the branch history is monotonous (all established or all not established), the upper bits of the index do not become monotonous by taking the exclusive OR with the bits cut out from the PC. Thus, the entries in the slack table 20 can be used effectively.

  For example, as shown in FIG. 30 and FIG. 31, when the branch history is 4 bits and the lower bit cut out from the program counter value (PC) is 2 bits, the lower 2 cut out from the program counter value (PC) Consider a case in which the slack of two instructions (instruction 1 and instruction 2) having the same bit only is updated. In the following description, among the PCs of instruction 1 and instruction 2, bits not related to index generation are omitted, and the upper 4 bits and lower 2 bits of the bits not omitted are separated by a space. indicate. Here, it is assumed that the PC of instruction 1 is “... 101101..., And the PC of instruction 2 is“. If all branch histories of instruction 1 and instruction 2 are established (1111), the method of FIG. 30 causes the index to the slack table 20 to be the same value (111101) for both instructions. On the other hand, in the method of FIG. 31, the index to the slack table 20 is “110001” for the instruction 1 and “001101” for the instruction 2, and in this case also, the index is different.

  As described above, the method of FIG. 31 is more advantageous for effective use of the entry. However, since an extra calculation is required, a request to the slack table, that is, whether higher accuracy of slack prediction is desired. The method to be adopted is selected depending on whether the simplicity of the mechanism is desired. In any case, the accuracy of slack prediction can be further improved by separately recording predicted slack for each branch pattern in consideration of the control flow.

8). Expansion of target slack arrival conditions In addition to the above-mentioned arrival conditions (A) to (D), for example, the following (E) to (I) are listed as behaviors during instruction execution that can be used as target slack arrival conditions. ) Is considered. By adding some or all of these to the target slack arrival condition, there is a possibility that slack can be predicted more accurately.
(E) The instruction becomes the oldest instruction in the instruction window 13 (see FIGS. 6 and 28) (the instruction remains in the instruction window 13 for the longest time).
(F) The oldest instruction in the reorder buffer 16 (see FIGS. 6 and 28) (the instruction remains in the ROB for the longest time).
(G) The instruction is an instruction that passes the execution result to the oldest instruction among the instructions existing in the instruction window.
(H) The instruction is an instruction that passes the execution result to the largest number of subsequent instructions among the instructions executed in the same cycle. For example, if two instructions are executed in the same cycle and one of them passes the execution result to two subsequent instructions and the other passes the execution result to five subsequent instructions, the latter instruction reaches the target slack. It is determined that the condition is satisfied.
(I) The number of subsequent instructions that can be executed by passing the execution result of the instruction is equal to or greater than a predetermined determination value. The executable state here means a state where input data is ready and execution can be started at any time.

For these arrival conditions (E) to (I), the following instructions i1 to i6, that is,
Instruction i1: A = 5 + 3;
Instruction i2: B = 8-3;
Instruction i3: C = 3 + A;
Instruction i4: D = A + C;
Instruction i5: E = 9 + B; and Instruction i6: F = 7−B;
An example of executing is described.

  First, if the instruction i1 and the instruction i2 are simultaneously executed in the first cycle, the instruction i1 passes the execution result to the instruction i3 and the instruction i4, and the instruction i2 passes the execution result to the instruction i5 and the instruction i6. Therefore, the number of subsequent instructions that pass the execution result is two, but since the input data of the instruction i4 has not been prepared yet, the number of instructions that can be executed by the execution result of the instruction i1 is one, the instruction i2 The number of instructions that can be executed by the execution result of is two. If the determination value under the condition (I) is “1”, the instruction (i) and the instruction i2 satisfy the condition (I). If the determination value is “2”, only the instruction i2 is satisfied.

  These conditions (E) to (I) have been proposed to be used as conditions for detecting a critical path in the past, but can be sufficiently used as local slack arrival conditions. is there.

9. Expansion of parameters related to slack table update In the above-described embodiment, among the parameters related to slack table update, the amount of decrease Vdec and Cdec per time of predicted slack and reliability counter is set to the maximum value Vmax and the threshold value of predicted slack, respectively. It was fixed to the same value as the value Cth. Further, the increments Vinc and Cinc of the predicted slack and reliability counter per time are both fixed to “1”. However, the optimum value of the parameter varies depending on the situation, for example, when it is important to suppress performance degradation or when it is desired to increase the amount of slack that can be predicted as much as possible. Therefore, it is not always necessary to fix the parameters as described above, and it is desirable to appropriately determine the parameters according to the field to which slack prediction is applied.

  In the above embodiment, each parameter related to the update of the slack table is a uniform value regardless of the type of instruction. For example, the same value is used for the reliability threshold Cth regardless of whether it is a load instruction or a branch instruction. However, in practice, depending on the type of instruction, there is a difference in local slack behavior such as the dynamic change degree and the frequency of the change. A typical example is a branch instruction. Branch instructions have a much more variable amount of local slack than other instructions. When branch prediction is successful, the impact on subsequent instructions is very small and local slack tends to be large, but when branch prediction is unsuccessful, all instructions that were executed in error are discarded and very Because it incurs a large penalty, the local slack is “0”. This means that the local slack changes rapidly when the success and failure of branch prediction are switched. Therefore, in the case of a branch instruction, it is desirable to make the threshold value Cth of the reliability counter and the amount of decrease Cdec per time larger than other instructions.

  In addition, if an instruction belonging to a type other than the branch instruction has a characteristic in the operation in the processor, it is considered that an appropriate value of a parameter suitable for the characteristic exists for each type. Therefore, there is a possibility that the prediction accuracy is further improved by dividing the instructions into several categories and individually setting the parameters related to the slack table update for each category. For example, focusing on the difference in operation within the processor, the instructions can be classified into the following four categories: a load instruction category, a store instruction category, a branch instruction category, and other instruction categories.

  Parameters are individually set for each category of instructions thus classified. When updating, it is first determined to which category the instruction belongs. This determination can be easily made by looking at the operation code of the instruction. Then, the slack table is updated using the parameters specific to the category to which the instruction belongs. In addition, as a classification mode of the instruction category, a mode in which the load instruction and the store instruction are set to the same category, and addition and subtraction are divided into different categories is also conceivable. How instructions are classified depends on the range to which slack prediction is applied. If individual parameters are used for each type of instruction in this way, the configuration of the local slack prediction mechanism becomes complicated. To suppress this, it is necessary to reduce the number of categories to the minimum necessary. is there.

10. Summary of the first embodiment.
Hereinafter, in this embodiment, the means for solving the problem will be summarized as follows.

  In the local slack prediction method according to the present embodiment, the instruction executed by the processor is executed with the execution latency increased by the predicted slack value that is the predicted value of the local slack of the instruction, and Based on the behavior at the time of execution of the instruction, it is estimated whether or not the predicted slack has reached the target slack which is an appropriate value of the current local slack, and the predicted slack is estimated until it is estimated that the target slack has been reached. Each time the instruction is executed, it is gradually increased.

  In the prediction method, the predicted value of local slack (predicted slack) of an instruction is gradually increased every time the instruction is executed. If the predicted slack is increased in this way, the value eventually reaches the appropriate value (target slack) of the current local slack. On the other hand, the arrival of predicted slack to the target slack is estimated from the behavior of the processor at the time of execution of the instruction, and the increase in predicted slack is stopped at the time when it is estimated that the arrival has been reached. As a result, local slack can be predicted without directly calculating predicted slack.

In addition, the estimation of the arrival of predicted slack to the target slack as described above is a condition for establishing the estimation,
(A) A branch prediction error occurred during execution of the instruction,
(B) A cache miss occurred during execution of the instruction;
(C) Operand forwarding for the subsequent instruction has occurred,
(D) that store data forwarding has occurred for the subsequent instruction;
(E) the instruction is the oldest instruction in the instruction window;
(F) the instruction is the oldest instruction in the reorder buffer;
(G) The instruction is an instruction that passes an execution result to the oldest instruction among the instructions existing in the instruction window;
(H) The instruction is an instruction that passes the execution result to the most subsequent instructions among the instructions executed in the same cycle;
(I) The number of subsequent instructions that can be executed by passing the execution result of the instruction is equal to or greater than a predetermined determination value.
One of them is included.

  Here, the behaviors of (A) and (B) are observed in a state where the predicted slack exceeds the target slack and the execution of the subsequent instruction is delayed. The behaviors (C) and (D) are observed when the predicted slack matches the target slack. Therefore, when these behaviors are observed, it can be estimated that the predicted slack has reached the target slack.

  On the other hand, the above behaviors (E) to (I) are conventionally used as a determination condition as to whether or not an instruction is on the critical path. When the predicted slack reaches the target slack, if the instruction execution latency is further increased by one cycle, the execution of subsequent instructions will be delayed, resulting in a situation similar to the instruction on the critical path. It can also be used as an estimation condition.

  If the target slack decreases dynamically when the predicted slack matches the target slack until then, the predicted slack exceeds the target slack, and the execution of subsequent instructions is delayed. A misprediction penalty occurs. In this regard, if it is estimated that predicted slack has reached target slack, it is possible to cope with such a dynamic decrease in target slack by reducing the predicted slack.

  If the predicted slack is increased or decreased immediately after the above estimation is established or not established, there is a risk that the frequency of occurrence of a misprediction penalty increases when the target slack frequently increases and decreases. Even in such a case, the predicted slack is increased on the condition that the number of times that the estimated condition that the predicted slack has reached the target slack is not satisfied is the specified number of times. If the predicted slack is decreased on the condition that the target slack is increased, it is possible to suppress an increase in the frequency of the predicted mispenalty when the target slack frequently increases or decreases.

  In this case, if the number of times that the satisfaction condition necessary to increase the predicted slack is set to be greater than the number of times the satisfaction condition required to decrease the predicted slack is set, the increase in predicted slack The reduction will be done quickly. Therefore, it is possible to effectively suppress an increase in the frequency of the prediction mispenalty when the target slack is frequently increased and decreased. These effects increase the predicted slack on the condition that the number of times that the estimated condition that the predicted slack has reached the target slack has not been satisfied is the specified number of times, while the decrease in the predicted slack indicates that the satisfied condition is satisfied Even if it is performed under the condition, it can be obtained similarly.

  Depending on the type of instruction, there is a difference in local slack behavior such as the dynamic change degree and the frequency of the change. Therefore, in order to predict local slack with higher accuracy, it is desirable that the upper limit value of predicted slack and the update amount (increase amount or decrease amount) per time differ for each instruction type. In addition, when updating the predicted slack on condition that the number of times the established condition is satisfied or the number of times it is not satisfied is a specified number of times, it is more Predictions can be made with high accuracy. Incidentally, the types of such instructions may be classified into four categories, for example, load instructions, store instructions, branch instructions, and other instructions.

  By the way, the local slack of an instruction may change greatly depending on the branch path of the program leading to the execution of the instruction. In that respect, if the predicted slack is set separately for each branch pattern of the program leading to the execution of the instruction, local slack is predicted for each branch path of the program leading to the execution of the instruction. Thus, local slack can be predicted with higher accuracy.

  On the other hand, in order to solve the above-described problem, the local slack prediction mechanism according to the present embodiment uses predicted slack that is a predicted value of local slack of each instruction as a mechanism for predicting local slack of instructions executed by the processor. A slack table in which is recorded and held, an execution latency setting means for acquiring the predicted slack of the instruction with reference to the slack table upon execution of the instruction, and increasing the execution latency by the acquired predicted slack, and Based on the behavior at the time of execution of the instruction, estimation means for estimating whether the predicted slack has reached target slack, which is an appropriate value of the current local slack of the instruction, and the predicted slack by the estimation means Until the estimated slack reaches the target slack. The so that and an predicted slack update means gradually increasing for each execution of the instruction.

  In the above configuration, the predicted slack of the instruction is gradually increased by the predicted slack updating means every time the instruction is executed, and the execution latency of the instruction is also gradually increased by the execution latency setting means every time the instruction is executed. When the predicted slack reaches the target slack in this way, the behavior of the processor at the time of execution of the instruction indicates that, and the estimation means estimates that. As a result, the predicted slack update means increases the predicted slack. You can stop. As described above, predicted slack is obtained without performing direct calculation.

  Note that the estimation of the arrival of predicted slack to the target slack by the estimating means is, for example, the estimation of any one of the above (A) to (I) or a plurality thereof (that is, at least one). This can be done by establishing the conditions for establishment.

  Also, the counter value is increased / decreased when the condition for establishing the estimation that the predicted slack has reached the target slack is satisfied, and the counter value is decreased / decreased when the condition for establishing the estimation is not satisfied. A reliability counter to be increased is provided, and the predicted slack is increased on the condition that the counter value of the reliability counter becomes an increase determination value, and the counter value of the reliability counter becomes a subtraction determination value. If the predicted slack updating means reduces the predicted slack on the condition of the above, it is possible to suitably suppress an increase in the occurrence frequency of the predicted mispenalty when the target slack is repeatedly increased and decreased. In order to more effectively suppress an increase in the frequency of occurrence of prediction mispenalties in such a state, the increment / decrement amount of the counter value when the condition for establishment of the estimation in the reliability counter is satisfied can be established. It is desirable to set a larger value than the decrease / increase amount of the counter value when the condition is not satisfied.

  Furthermore, in order to more accurately predict local slack in response to differences in the dynamic change of local slack depending on the type of instruction, the amount of update of predicted slack for each instruction by the updating means ( It is desirable to vary the amount of increase or decrease) depending on the type of instruction. When an upper limit value is set for the predicted slack of each instruction updated by the updating means, it is also effective to make the upper limit value different depending on the type of instruction. Furthermore, when a reliability counter is provided, it is effective to vary the increment and decrement of the counter value depending on the type of instruction. Incidentally, the types of instructions can be classified into four categories: load instructions, store instructions, branch instructions, and other instructions.

  In addition to providing a branch history register that records the branch history of a program, it is also possible to record the predicted slack of instructions separately in the slack table for each branch pattern obtained by referring to the branch history register. It is effective to improve

  According to the local slack prediction method and prediction mechanism according to the present embodiment, instead of directly calculating the predicted value of local slack (predicted slack) of an instruction, the behavior at the time of execution of the instruction is observed. However, it is obtained by gradually increasing the predicted slack until it reaches an appropriate value. Therefore, a complicated mechanism required for direct calculation of predicted slack is unnecessary, and local slack can be predicted with a simpler configuration.

Second embodiment.
The second embodiment proposes a method for removing memory ambiguity using slack prediction. Slack is the number of cycles that can increase the execution latency of an instruction without affecting other instructions. In the proposed mechanism, a store instruction whose slack exceeds a predetermined threshold is predicted not to depend on a subsequent load instruction, and the load instruction is speculatively executed. Thus, even if the slack of the store instruction is used, the subsequent load execution is not delayed.

1. Problems of the first embodiment and the prior art.
As described above, since there is a memory ambiguity between load / store instructions, the use of store instruction slack based on prediction delays the execution of subsequent loads, which adversely affects the performance of the processor. There is a problem. Here, memory ambiguity means that the dependency between load / store instructions is not known until the memory address to be accessed is known.

  Therefore, this embodiment proposes a mechanism that speculatively removes memory ambiguity by predicting the data dependency between store instructions and load instructions using slack. In this mechanism, a store instruction in which slack exceeds a predetermined threshold is predicted not to depend on a subsequent load instruction, and the load instruction is speculatively executed. Thus, even if the slack of the store instruction is used, the subsequent load execution is not delayed.

2. slack.
Regarding slack, as described in the prior art and the first embodiment, unlike global slack, local slack is not only obtained but also easy to use. Therefore, in the present embodiment, the discussion will proceed with “local slack” as a target. Further, “local slack” is simply expressed as “slack”.

3. The effect of memory ambiguity on slack usage.
This chapter explains the problems that occur due to memory ambiguity when using slack for store instructions.

  FIG. 32A is a diagram for explaining a problem that occurs due to the ambiguity of the memory when the slack of the store instruction is used in the prior art, and shows a program before decoding. FIG. 32B is a diagram for explaining a problem that occurs due to the ambiguity of the memory when the slack of the store instruction is used in the prior art, and shows a program after decoding.

  In FIG. 32A, r1, r2,... Indicate the first register, the second register,. The store instruction i1 stores the value of the register r4 at a memory address obtained by adding 3 to the value of the register r1. The load instruction i5 writes the value loaded from the memory address obtained by adding the value of the register r2 and 8 to the register r7. The load instruction i6 writes the value loaded from the memory address obtained by adding the value of the register r3 and 8 to the register r8. The instruction i7 writes a value obtained by adding 5 to the value of the register r7 into the register r9. The instruction i8 writes a value obtained by adding the value of the register r9 and 8 to the register r10.

  It is assumed that the instruction i5 does not depend on the instruction i1, and the instruction i6 depends on the instruction i1. However, it should be noted that in the processor 10B (see FIG. 35), due to the ambiguity of the memory, their dependency relationship is not known until the address calculation is completed. Further, the instruction i7 requires the value obtained by the instruction i5, and the instruction i8 requires the value obtained by the instruction i7.

  Assume that a separate load / store scheme is used as a scheme for efficiently scheduling load / store instructions. In this method, a memory instruction is divided into two parts, an address calculation part and a memory access part, and these are scheduled separately. For scheduling, a dedicated buffer memory called a load and store queue (hereinafter referred to as LSQ) 62 is used. Since address calculation has only register dependence, scheduling is performed using the reservation station 14A. On the other hand, the memory access is scheduled to satisfy the memory dependence.

  FIG. 32B shows a program after decoding the program of FIG. 32A in the processor using the separate load / store system. In FIGS. 32A and 32B, the memory instruction is separated into an address calculation instruction (an instruction with a added to the name) and a memory access instruction (an instruction with m added to the name).

  FIG. 33A is a diagram used for explaining the influence of the ambiguity of the memory on the use of slack in the processing of the processor, and is a timing chart showing the process of executing the program when slack is not used. FIG. 33B is a diagram used for explaining the influence of the ambiguity of the memory on the use of slack in the processing of the processor, and is a timing showing the process of executing the program when using the slack It is a chart.

  The process of executing the program shown in FIGS. 32 (a) and (b) is shown in FIGS. 33 (a) and 33 (b). In FIGS. 33A and 33B, the vertical axis indicates the number of cycles, and a rectangular portion surrounded by a solid line indicates an instruction executed in the cycle and the content of the execution.

  FIG. 33A shows an example in which slack is not used. In this example, it is assumed that the execution results of the instructions i1a, i5a, i7, i8, i6a are obtained in the 0th, 2, 5th, and 6th cycles, respectively.

  Since the address of the instruction i1 is found in the 0th cycle, the memory access of the instruction i1 can be performed in the 1st cycle. Next, in the second cycle, the address of the instruction i5 is determined. At this point, it becomes clear that the instruction i5 does not depend on the instruction i1, which is the preceding store. Therefore, the instruction i5 performs memory access in the third cycle. In the fourth cycle, addition is performed using the value loaded by the instruction i5. In the fifth cycle, addition is performed using the value obtained by the instruction i7. In the sixth cycle, it is found that the instruction i6 depends on the instruction i1, which is the preceding store. At this point, since the instruction i1 has finished executing, the instruction i6 depending on it can also start executing. In the ninth cycle, the store data is forwarded from the instruction i1 to the instruction i6 depending on the instruction i1.

  On the other hand, FIG. 33B shows a case where slack of the instruction i1 is used. In this case, it is assumed that slack is predicted to be 5 and the execution latency of the instruction i1a is increased by 5 cycles. By using the slack of the instruction i1, in FIG. 33B, the cycle in which the execution result of the instruction i1a is obtained is delayed by 5 cycles compared to the case of FIG.

  In the second cycle, the address of the instruction i5 is determined. However, at this time, the address of the instruction i1, which is the preceding store, is unknown. Even though its own address is known, it is not known whether it depends on the preceding store, so the memory cannot be accessed and execution is delayed. When the address of the instruction i1 is found in the fifth cycle, it is finally found that the instruction i5 does not depend on the instruction i1. Therefore, the instruction i5 performs memory access in the sixth cycle. This is a wasteful execution delay and adversely affects performance.

4). Speculative removal of memory ambiguity using slack prediction.
In order to mitigate the adverse effect of the use of the slack of the store instruction on the execution of the load instruction that does not depend on the slack of the store instruction, attention is paid to how to determine the slack of the store instruction in the conventional method. In the conventional method, the slack of a store instruction is obtained by paying attention only to a load having a dependency relationship with the store. Therefore, when the slack of the store instruction is n (n> 0), it can be seen that a load instruction depending on the n instruction is executed after n cycles when the store is executed.

  From this, it can be considered that when a memory instruction is separated into address calculation and memory access, a store / load instruction having a dependency relationship is likely to be executed in the following order. First, the address of the store instruction is calculated. Thereafter, the memory access of the store instruction is performed. After n-1 cycles, the address calculation of the load instruction depending on it is performed, and the memory access is performed in the next cycle.

  When the memory instructions are executed in the above order, the load instruction depending on the store instruction does not perform address calculation for at least n cycles after the store instruction performs address calculation. Therefore, it can be seen that the load instruction whose address is found during that time does not depend on the store instruction without comparing the addresses.

  As described above, even if the address calculation of the store instruction is delayed by n cycles as a result of increasing the execution latency of the store instruction whose slack is n (> 0), the load instruction whose address is found in the meantime is It can be considered that there is a high possibility of not depending on

  Therefore, the present inventor predicts that the load instruction whose address has been found does not depend on the preceding store instruction whose slack is n (> 0), and speculatively removes the memory ambiguity related to the store instruction. Propose. As a result, the adverse effect of the use of the slack of the store instruction on the execution of the load instruction that does not depend on the slack can be reduced.

  FIG. 34 is a timing chart showing speculative removal of memory ambiguity according to the second embodiment of the present invention. Here, the target operation of the proposed method will be described with reference to FIG. That is, FIG. 34 shows a process when the program shown in FIG. 32 is executed using the proposed method. Similar to FIG. 33B, the slack of the instruction i1a is predicted to be 5, and the execution latency of the instruction i1a is increased by 5 cycles. However, unlike FIG. 33B, the ambiguity of the memory related to the instruction i1 is speculatively removed using slack.

  In the second cycle, the address of the instruction i5 is determined. At this time, the address of the instruction i1, which is the preceding store, is unknown. However, since the instruction i1 has a slack larger than 0 (has slack), it is predicted that the instruction i5 does not depend on the instruction i1. In the third cycle, the instruction i5 speculatively accesses the memory. As described above, execution of a load instruction that does not depend on a store instruction using slack is prevented from being delayed.

  However, since slack is obtained by prediction, there is a possibility that prediction of memory dependency may fail. The penalty for failure is large, so you need to make your predictions as carefully as possible. Therefore, only when the slack of the store instruction exceeds a certain threshold value Vth, it is predicted that the subsequent load instruction does not depend on the store instruction.

5). Proposed mechanism.
This chapter describes the mechanism that implements the proposed method shown in Chapter 4.

5.1. Overview of the proposed mechanism.
FIG. 35 is a block diagram showing a configuration of a processor 10B including the memory ambiguity speculative removal mechanism (hereinafter referred to as a proposed mechanism) in FIG. In FIG. 35, an instruction cache 11A and a data cache 63 are shown above and below the processor 10B, respectively. The right side of the processor 20 shows a slack prediction mechanism 60 that predicts the slack of fetched instructions. The inside of the processor 10B is large, and is divided into a front end 7, an execution core 1A, and a back end 8.

  The instruction cache 11A temporarily stores the instruction from the main storage device 9 and then outputs it to the decoding unit 12. The decode unit 12 includes an instruction decode unit 12a and a tag assignment unit 12b. The decode unit 12 decodes an input instruction and assigns a tag, and then outputs the instruction to the reservation station 14A of the execution core 1A.

  The execution core 1A schedules the address calculation using the reservation station 14A, calculates the address by the functional unit 61 (corresponding to the execution unit 15), and outputs it to the LSQ 62 and the ROB 16 of the back end 8. In addition, the execution core 1A schedules a load instruction and / or a store instruction using the LSQ 62 and sends the load request and / or the store request to the data cache 63. At the time of reordering, the address output from the ROB 16 is input to the reservation station 14A via the register file 14.

  The proposed mechanism shown in FIG. 35 is implemented in the LSQ 62, and can be mainly divided into a memory-dependent prediction mechanism and a recovery mechanism from a prediction error. The memory dependence prediction mechanism predicts memory dependence based on slack and speculatively executes a load instruction. On the other hand, the recovery mechanism confirms the success or failure of the memory dependence prediction, and recovers the processor state from a state in which the memory dependence prediction is missed.

  In the following, the memory dependence prediction mechanism will be described first, and then the recovery mechanism will be described.

5.2. Memory dependent prediction mechanism.
The proposed mechanism according to the present embodiment realizes a memory-dependent prediction mechanism by adding simple modifications to the LSQ 62. First, the configuration of the modified LSQ 62 will be described.

  FIG. 36 is a diagram showing a format of the modified instruction data entered in the load and store queue (LSQ) 62 of FIG. 36, in addition to the operation code 71, the memory address 73, the tag 75, and the store data 76, three flags 72, 74, and 77 are added. Here, Ra and Rd are flags indicating that an address and store data are available. Sflag is a flag for predicting the predicted slack of a store instruction newly added to introduce the proposed mechanism, and indicates whether the predicted slack of the store instruction is equal to or greater than a threshold value Vth. In the case of a load instruction, the flag Sflag has no meaning. The flag Sflag is set to 1 if the predicted slack of the store instruction is equal to or greater than the threshold value Vth, and is reset to 0 otherwise. Setting / resetting of the flag Sflag is performed by the functional unit 61 when a store instruction is assigned to the LSQ 62.

  Next, the operation of the LSQ 62 after correction will be described. In the normal LSQ 62, when the load instruction finds its own address and the addresses of all preceding store instructions, it compares the addresses. Then, if it is found that it does not depend on the preceding store, memory access is performed. Otherwise, data is obtained from the dependent store by forwarding.

On the other hand, in the modified LSQ 62, the load instruction finds its own address, and if the preceding store instruction does not leak and satisfies any of the following conditions, it compares the addresses.
(1) The address is known.
(2) Although the address is not known, the flag Sflag is 1.

  However, address comparison is performed only for store instructions whose addresses are known. It is predicted that there is no dependency for a store instruction whose address is not known and the flag Sflag is 1. As a result of the address comparison, if it is found that there is no dependent store instruction, a memory access is performed. Otherwise, data is obtained from the dependent store by forwarding. If the memory dependency is predicted, the load instruction is speculatively executed.

5.3. Recovery mechanism.
Since the proposed mechanism according to the present embodiment examines whether or not the prediction of the memory dependency relationship is correct, the address of the store instruction that may have been subject to the prediction, that is, the store instruction with the flag Sflag being 1 is found. Later, the success or failure of the prediction is confirmed. Specifically, the address of the store instruction is compared with the address of the subsequent load instruction that has been executed.

  If the addresses do not match, the memory dependence prediction is successful. By using the slack of the store instruction, it is possible to prevent the execution of the load instruction that does not depend on the store instruction from being delayed. On the other hand, if the addresses match, the memory dependence prediction fails. The load instruction with the matching address and subsequent instructions are flushed from the processor, and the execution is restarted. The cycle required to redo execution is the prediction miss penalty.

6). Processing flow of LSQ62.
FIG. 37 is a flowchart showing the processing of the LSQ 62 of FIG. 35 for a load instruction. In FIG. 37, (*) is added after the step number for the additional step as compared with the conventional mechanism, and in FIG. 37, the process of step S7 is added. In FIG. 37, in order to make the explanation easy to understand, the part from step S2 to step S8 is set as a loop treatment, but this part is usually processed in parallel. In FIG. 37 and FIG. 38, the address means a memory address of the main storage device 9 in which each instruction is stored.

  In FIG. 37, first, in step S1, a load instruction is written to the LSQ 62 and the ROB 16. Next, in step S1A, it is determined whether or not the address of the load instruction written in the LSQ 62 has been determined. If YES, the process proceeds to step S2, while if NO, the process proceeds to step S10. In step S2, the next preceding store instruction is acquired. In step S3, it is determined whether or not the address of the preceding store instruction has been found. If YES, the process proceeds to step S4. If NO, the process proceeds to step S7. In step S4, the addresses of the load instruction and the preceding store instruction are compared. In step S5, it is determined whether or not these addresses match. If YES, the process proceeds to step S6. If NO, the process proceeds to step S8. move on. In step S6, after “store data forwarding” is executed, the processing of the LSQ 62 is terminated.

  In step S7, it is determined whether or not the flag Sflag of the preceding store instruction is 1, that is, whether the predicted slack is equal to or greater than the threshold value Vth. If YES, the process proceeds to step S8. If NO, step S10 is performed. Return to. In step S10, after waiting for one cycle, the process returns to step S1A. In step S8, it is determined whether or not the address comparison between the load instruction and all preceding store instructions has been completed. If NO, the process returns to step S2, while if YES, the memory access is performed, and then The process of LSQ 62 is terminated.

  Note that “store data forwarding” in step S6 refers to the following processing. When the data requested by the load instruction is data of a store instruction preceding a store queue or a buffer sheet such as the LSQ 62, normally, the store instruction is retired and written to the data cache 63, and the memory dependence is resolved. I need to wait. If the necessary store data can be obtained from the buffer, this useless waiting time is eliminated. Supplying store data from the buffer before it is written to the data cache 63 is called “store data forwarding”. This can be realized by modifying the buffer so as to output the corresponding store data when a matching entry is found as a result of the associative search of the buffer by the execution address.

  FIG. 38 is a flowchart showing the processing of the LSQ 62 of FIG. 35 for a store instruction. In FIG. 38, (*) is added after the step number for the additional steps as compared with the conventional mechanism. In FIG. 38, the processes of steps S14 and S20-S22 are added.

  38, first, in step S11, after the store instruction is written to the LSQ 62 and ROB 16, it is determined in step S12 whether or not the address of the store instruction has been found. If NO, the process returns to step S13, while YES. In this case, the process proceeds to step S14. In step S13, after waiting for one cycle, the process returns to step S12. In step S14, it is determined whether or not the flag Sflag of the store instruction is 0, that is, whether or not the predicted slack of the store instruction is greater than or equal to the threshold value Vth. If YES, the process proceeds to step S15. If NO, the process proceeds to step S20. In step S20, the store instruction is compared with the addresses of all subsequent load instructions, and it is determined whether or not there is a load instruction with the same address. If YES, the process proceeds to step S22. Proceed to In step S22, the load instruction and subsequent instructions are flushed from the processor 10 (instruction data is cleared), the execution of these instructions is performed again, and the process proceeds to step S15.

  In step S15, it is determined whether or not store instruction data has been obtained. If YES, the process proceeds to step S17. If NO, the process proceeds to step S16. In step S16, after waiting for one cycle, the process returns to step S15. In step S17, it is determined whether or not the store instruction is retired from the ROB 16. If YES, the process proceeds to step S19. If NO, the process proceeds to step S18. In step S18, after waiting for one cycle, the process returns to step S17. In step S19, after performing memory access, the processing of the LSQ 62 is terminated.

  Note that “retirement” means that processing in the back end 8 ends and instructions are no longer sent from the processor 10B.

7). Effects of the second embodiment.
As described above, according to the processor and the processing method thereof according to the second embodiment of the present invention, a store instruction having predicted slack equal to or greater than a predetermined threshold value is loaded with the load instruction and data following the store instruction. Therefore, even if the memory address of the store instruction is not known, the subsequent load instruction is speculatively executed. Therefore, if the prediction is correct, the use of the slack of the store instruction does not delay the execution of the load instruction having no data dependency with the store instruction, and the adverse effect on the performance of the processor device can be suppressed. In addition, in order to use the output result of the slack prediction mechanism, it is not necessary to prepare new hardware for predicting the dependency between the store instruction and the load instruction. Therefore, local slack can be predicted and program instructions can be executed at a high speed with a simpler configuration compared to the prior art.

Third embodiment.
In the present embodiment, a method for sharing local slack based on the dependency relationship is proposed. Local slack is the number of cycles that can increase the execution latency of an instruction without affecting other instructions. In the proposed mechanism according to the present embodiment, local slack possessed by a certain instruction is shared among instructions having a dependency relationship. As a result, instructions that do not have local slack can use slack.

1. Problems of the prior art and the first embodiment.
As described above, with the technique according to the conventional technique and the first embodiment, the number of instructions that can be predicted to have one or more local slacks (the number of slack instructions) is small, and a sufficient opportunity to use slack cannot be secured.

  Therefore, this embodiment proposes a method of sharing local slack possessed by a certain instruction among a plurality of dependent instructions. In this proposed mechanism, an instruction having local slack is used as a starting point, and information that there is sharable slack is propagated from an dependence destination to a dependence source between instructions having no local slack. Based on this information, the amount of slack used by each instruction is determined using a heuristic technique. As a result, instructions that do not have local slack can use slack.

2. slack.
FIG. 39 is a timing chart showing a program used to explain slack according to the prior art. In FIG. 39, nodes indicate instructions, and edges indicate data dependency between instructions. The vertical axis in FIG. 39 indicates the cycle in which the instruction is executed. The length of the node indicates an instruction execution latency (referred to as an execution delay time). The execution latency is two cycles for the instructions i1, i4, i5, i6, and i9, and one cycle for the other instructions.

  First, consider global slack of instruction i3. When the execution latency of the instruction i3 is increased by 7 cycles, the execution of the instruction i8 and the instruction i10 that depend on it directly and indirectly is delayed. As a result, the instruction i10 is executed at the same time as the instruction i11 executed last in the program. Therefore, if the execution latency of the instruction i3 is further increased, the number of execution cycles of the entire program increases. That is, the global slack of the instruction i3 is 7. As described above, in order to obtain the global slack of a certain instruction, it is necessary to examine the influence of the increase in the execution latency of the instruction on the execution of the entire program. Therefore, it is very difficult to determine global slack.

  Here, in addition to the instruction i3, attention is focused on the global slack of the instruction i0 that is indirectly dependent on the instruction i3. In the same manner as described above, it can be seen that the global slack of the instruction i0 is also 7. Therefore, when these instructions use global slack to increase the execution latency by 7 cycles, the instruction i10 is executed after 7 cycles rather than the last execution in the program. Thus, when one instruction uses global slack, another instruction may not use global slack. Therefore, it can be said that global slack is difficult to use.

  Next, consider local slack of instruction i3.

  When the execution of the instruction i3 is increased by 6 cycles, the execution of the subsequent instruction is not affected. However, if the execution latency is further increased, the execution of the instruction i8 that directly depends on the instruction i3 is delayed. That is, the local slack of the instruction i3 is 6. Thus, in order to obtain the local slack of a certain instruction, attention should be paid to the influence on the instruction depending on the instruction. Therefore, local slack can be determined relatively easily.

  Here, attention is focused on the local slack of the instruction i10 that is indirectly dependent on the instruction i3. Similarly to the above, it can be seen that the local slack of the instruction i10 is 1. Even if 3 uses local slack, it does not affect instructions that depend directly on it, so instruction i10 can use local slack. Unlike global slack, if one instruction uses local slack, other instructions can use local slack regardless.

  As described above, unlike global slack, local slack is not only easy to find but also easy to use. Therefore, in the present embodiment, the discussion will proceed with respect to local slack thereafter.

3. Conventional slack prediction mechanism.
The outline of the conventional mechanism will be described. Details have been described in the related art and the first embodiment. In a time-based mechanism, local slack is calculated from the difference between the time when an instruction defines data and the time when the data is referenced by another instruction, and the local slack at the next execution is obtained by calculation. Expect to be the same as local slack. On the other hand, the mechanism based on the heuristic method increases or decreases the predicted local slack (predicted slack) while observing the behavior at the time of instruction execution such as branch misprediction and forwarding, and the predicted slack is changed to the actual local slack ( Move closer to the actual slack).

  Both methods can achieve the same level of prediction accuracy, but have a problem that the number of slack instructions is small. For example, in the heuristic method, in a processor that issues four instructions, the number of slack instructions that can be predicted is about 30 to 50% of the total execution instructions while suppressing the performance degradation to less than 10%. If the number of slack instructions is small, the opportunity to use slack is also limited. Therefore, it is important to consider measures to increase the number of slack instructions.

4). A technique to increase the number of slack instructions.
In this chapter, we propose a method of using (sharing) local slack of an instruction not only for the instruction but also for other instructions. If the slack sharing can make slack available to instructions that do not have local slack, the number of slack instructions can be increased.

  First, let us consider what kind of relationship holds between instructions that share slack.

  If an instruction without local slack increases the execution latency, it affects the execution of the instruction that depends on it. As a result, if the local slack possessed by a certain instruction is reduced, it can be considered that these instructions share slack. Therefore, the present inventor has considered that an instruction that can share slack is an instruction that can affect the execution of an instruction having local slack, that is, an instruction that directly or indirectly supplies an operand.

  For example, in FIG. 39, the instruction i3 is an instruction having local slack. The instructions i0 and i2 are instructions that share operands directly and indirectly with the instruction i3. Increasing the execution latency of these instructions decreases the available local slack for instruction i3. Therefore, the local slack of the instruction i3 can be shared between the instructions i0, i2, and i3.

  FIG. 40A is a timing chart showing a program for explaining the use of slack according to the conventional technique, and FIG. 40B is a technique for increasing the number of slack instructions according to the second embodiment of the present invention. It is a timing chart which shows the program explaining utilization of the slack concerning.

  The conventional method and the sharing method according to the present embodiment will be described with reference to FIGS. FIGS. 40A and 40B show the operation when local slack of the instruction i3 is used in the program of FIG. In the conventional method of FIG. 40A, only the instruction i3 uses the local slack of the instruction i3. On the other hand, in the proposed method of FIG. 40B, it can be seen that the local slack of the instruction i3 is shared between the instructions i0, i2, and i3. This increases the number of slack instructions. Note that slack per instruction is reduced by sharing. Therefore, it should be noted that sharing is not suitable for applications that require a lot of slack per instruction.

  Next, consider a method for obtaining an instruction to share slack.

  As a technique for realizing sharing, a method of using a data flow graph (DFG: Data Flow Graph) indicating dependency relation between instructions can be considered. If the data flow graph is known, it is possible to obtain an instruction for supplying operands directly or indirectly, that is, an instruction for sharing, to local slack of a certain instruction. Thereafter, the slack distribution method may be determined according to the situation, such as evenly dividing slack between these instructions. However, since the dependency relationship between instructions is complicated and the relationship dynamically changes by branching, it is not easy to create a data flow graph.

  Therefore, the present inventor propagates information (shared information) that there is sharable slack, starting from an instruction having local slack, and tracing the dependency relationship from the dependency destination to the dependency source in reverse. Let's go. For example, in FIG. 39, the sharing information is propagated from the instruction i3 having local slack to the instruction i2, and then from the instruction i2 to the instruction i0. Since each instruction only needs to propagate shared information to an instruction that directly depends on itself and does not have slack, it is much easier to implement than a method of creating a data flow graph.

  Furthermore, since the local slack changes dynamically, the propagation speed of the shared information can be changed. Specifically, the instruction propagates the shared information when its predicted slack exceeds a certain threshold (propagation threshold). Hereinafter, the propagation threshold is referred to as a propagation threshold Pth.

  Finally, consider the slack prediction method. There are two types of prediction. The prediction of local slack and the prediction of slack used by the instruction that receives the sharing information.

  Local slack changes dynamically. When sharing is performed, the slack per instruction is reduced, and the dynamic change of local slack is further complicated. In order to cope with this change, heuristic local slack prediction (see the first embodiment) capable of controlling the rate of increase / decrease in predicted slack is used as a local slack prediction method.

  The slack that can be shared changes dynamically. Also, the instruction that receives the sharing information only knows that slack can be shared. This is very similar to the situation in heuristic local slack prediction where the predicted slack changes dynamically and each instruction only knows whether the predicted slack has reached actual slack. Therefore, slack is predicted heuristically even for an instruction that receives shared information.

  Specifically, it is as follows. First, a reliability counter is introduced for each predicted slack. When sharing information is received at the time of execution, it is determined that predicted slack has not yet reached available slack, and the reliability counter is incremented. If not, the predicted slack determines that available slack has been reached and decrements the reliability counter. Then, the predicted slack is decreased when the counter value becomes 0, and the predicted slack is increased when the counter value exceeds a certain threshold value.

5). Proposed mechanism This chapter describes the mechanism that implements the proposed method described in the previous section. First, the outline of the proposed mechanism is described. Next, each component of the proposed mechanism will be described. Finally, the overall operation will be described in detail.

5.1. Configuration of the proposed mechanism.
FIG. 41 is a block diagram illustrating a configuration of a proposed mechanism that is the processor 10 including the slack propagation table 80 and the like according to the third embodiment of the present invention. Since it is not related to the description in this section, the inside of the processor 10 and the update unit 30 is omitted, but the detailed configuration of the processor 10 is illustrated in FIG. 6 or FIG. 35, and the detailed configuration of the update unit 30 is illustrated in FIG. It is shown in the figure. Here, the proposed mechanism is configured to further include the following three components in addition to the processor 10.
(1) Slack table 20A,
(2) Slack propagation table 80, and (3) Update unit 30.

  The slack table 20A is stored in a storage device such as a hard disk memory, and holds a propagation flag Pflag, predicted slack, and reliability for each instruction. When the processor 10 fetches an instruction from the main storage device 9, the processor 10 refers to the slack table 20A at the time of fetching, and uses the predicted slack obtained from the slack table 20A as its own predicted slack. The propagation flag Pflag indicates the content of local slack prediction. When the propagation flag Pflag is 0, it indicates that the conventional local slack prediction is being performed. When the propagation flag Pflag is 1, it indicates that the slack prediction based on the sharing information is being performed. The shared information cannot be propagated until local slack is predicted, so the initial value of the propagation flag Pflag is set to zero.

  The slack propagation table 80 is used for propagating the shared information of each instruction to an instruction that does not have local slack, which is directly dependent on the information. This slack propagation table 80 uses the destination register number of the instruction as an index. Each entry holds the program counter value (PC), predicted slack, and reliability of an instruction that does not have local slack for each instruction. The update unit 30 is used to calculate the predicted slack and reliability of the committed instruction based on the behavior at the time of executing the instruction and the sharing information. The value calculated by the update unit 30 is written in the slack table 20A.

5.2. Details of the components.
When the processor 10 fetches an instruction, it refers to the slack table 20A at the time of fetching, and obtains its own predicted slack from the slack table 20A. Then, when the instruction is committed, the propagation flag Pflag, reliability, predicted slack, and execution behavior are sent to the update unit 30. If the instruction propagation flag Pflag is 0, the reliability and predicted slack are calculated based on the heuristic local slack prediction method, and the slack table 20A is updated. At this time, the propagation flag Pflag is not changed.

  Next, the slack propagation table 80 is updated / referenced using the local slack obtained by the calculation. Here, when the propagation flag Pflag is 0 and the predicted slack is 1 or more, the instruction has local slack. Even if the propagation flag Pflag is 0 and the predicted slack is 0, if the reliability is 1 or more, the instruction may have local slack at the next execution. Therefore, in these cases, the entry corresponding to the destination register in the slack propagation table 80 is cleared. On the other hand, if none of the above applies, it can be said that the instruction does not have local slack, and there is no possibility of having local slack at the next execution. Therefore, in this case, the program counter value (PC), predicted slack, and reliability of the instruction are written in the entry corresponding to the destination register of the slack propagation table 80.

  When the instruction has local slack, or when slack becomes available due to sharing, the slack is compared with the propagation threshold value Pth. When the slack is less than the propagation threshold value Pth, the slack propagation table 80 is referred to by the source register number. It can be seen that the instruction obtained as a result of the reference does not receive shared information. Therefore, based on this information, the slack of the instruction is predicted and the referenced entry is cleared. When the slack is equal to or greater than the propagation threshold value Pth, it can be seen that the instruction corresponding to the source register number receives the sharing information from the instruction. However, there is a possibility that shared information cannot be received from the instruction following the instruction. So do nothing at this point. Then, when committing an instruction that redefines the corresponding entry, it can be seen that the instruction of that entry receives sharing information from all the instructions it depends on. Therefore, the slack of the instruction is predicted based on this information.

  Finally, slack prediction based on shared information will be described. In slack prediction based on shared information, reliability and predicted slack are calculated based on information indicating whether shared information has been received, and the slack table 20A is updated. Basically, update data is calculated using the same concept as the heuristic local slack prediction method, except that it is based on shared information rather than target slack arrival conditions.

  The parameters related to updating the slack table and their contents are shown below. Note that the predicted slack minimum value Vmin_s = 0 and the reliability minimum value Cmin_s = 0.

(1) Vmax_s: the maximum value of predicted slack,
(2) Vmin_s: the minimum value of predicted slack (= 0),
(3) Vinc_s: the amount of increase in predicted slack per time,
(4) Vdec_s: the amount of decrease in predicted slack per time,
(5) Cmin_s: minimum value of reliability (= 0),
(6) Cth_s: threshold value of reliability,
(7) Cinc_s: increase amount of reliability per time, and (8) Cdec_s: decrease amount of reliability per time.

  The types and contents of parameters are the same as in local slack prediction. However, since it takes time to propagate the shared information, it should be noted that the values to be taken by the parameters are not necessarily the same.

  The flow of updating the slack table will be described using the above parameters. If the instruction receives the shared information, the reliability is increased by the increase amount Cinc_s, otherwise the reliability is decreased by the decrease amount Cdec_s. When the reliability exceeds the threshold Cths, the predicted slack is increased by the increase amount Vinc_s, and the reliability is reset to zero. On the other hand, when the reliability becomes 0, the predicted slack is decreased by the decrease amount Vdec_s.

  When the predicted slack of the instruction whose propagation flag Pflag is 0 becomes 1 or more by the above operation, it means that the slack can be used by sharing, so the propagation flag Pflag is set to 1. On the contrary, if the predicted slack of the instruction whose propagation flag Pflag is 1 becomes 0, it means that the slack cannot be shared, so the propagation flag Pflag is set to 0.

  FIG. 42 is a flowchart showing local slack prediction processing executed by the update unit 30 of FIG. Steps S32 and S41 are new processes, and (*) is added after the step number. Here, the numerical ranges of predicted slack and reliability are 0 ≦ reliability ≦ Cth_l, 0 ≦ predicted slack ≦ Vmax_l. The arrival condition flag Rflag is a flag used in the first embodiment, and is 1 when the target slack arrival condition is satisfied, and 0 when it is not. The determination flag Sflag is a determination flag for predicted slack of a store instruction newly added in the second embodiment, and indicates whether the predicted slack of the store instruction is equal to or greater than a threshold value Vth. Here, in the case of a load instruction, the flag Sflag has no meaning. The flag Sflag is set to 1 if the predicted slack of the store instruction is equal to or greater than the threshold value Vth, and is reset to 0 otherwise. Setting / resetting of the flag Sflag is performed by the functional unit 61 when a store instruction is assigned to the LSQ 62.

  42, first, the instruction committed in step S31 is acquired. In step S32, it is determined whether or not the propagation flag Pflag = 0, and if YES, the process proceeds to step S33. If NO, the process proceeds to step S41. move on. In step S33, it is determined whether or not the reaching condition flag Rflag = 0. If YES, the process proceeds to step S34. If NO, the process proceeds to step S37. In step S34, the increase amount Cinc_l is added to the reliability value, and the addition result is inserted as the reliability value. In step S35, it is determined whether or not reliability ≧ Cth_l. If YES, the process proceeds to step S36. On the other hand, if NO, the process proceeds to step S40. In step S36, the reliability value is reset to 0, the increase amount Vinc_l is added to the predicted slack value, and the addition result is inserted as the predicted slack value. Then, the process proceeds to step S40. On the other hand, after subtracting the decrease amount Cdec_l from the reliability value in step S37 and inserting the subtraction result as the reliability value, it is determined in step S38 whether or not reliability = 0. While the process proceeds to S39, the process proceeds to Step S40 if NO. In step S39, the reliability value is reset to 0, the decrease amount Vdec_l is subtracted from the predicted slack value, and the subtraction result is inserted as the predicted slack value. Then, the process proceeds to step S40. In step S40, the slack table is updated based on the above calculation result, and in step S41, the sharing information propagation process of FIG. 43 is executed, and then the local slack prediction process is terminated.

  FIG. 43 is a flowchart showing the sharing information propagation process (S41) in the subroutine of FIG.

  In step S42, the predicted slack of the committed instruction is compared with the propagation threshold value Pth. In step S43, it is determined whether or not predicted slack ≧ Pth. If YES, the process proceeds to step S44, while if NO, Proceed to step S52. Refer to the slack propagation table 80 by the destination register number of the instruction committed in step S44, and the program counter value of the preceding instruction that defines the same register as the committed instruction from the entry of the slack propagation table 80 referenced in step S45 ( PC), predicted slack and reliability are read, and it is determined whether or not the information read in step S46 is valid (is not cleared). If YES in step S46, the process proceeds to step S47. If NO, the process proceeds to step S49. The flag Sflag of the preceding instruction that defines the same register as the committed instruction in step S47 is set to 1, and the program counter value (PC), predicted slack, and reliability of the preceding instruction that defines the same register as the committed instruction in step S48 The property and flag Sflag are sent to the update unit 30, and the process proceeds to step S49.

  On the other hand, in step S52, the slack propagation table 80 is referred to by the source register number of the committed instruction, and the program counter value (PC) of the dependency source of the committed instruction from the entry of the slack propagation table 80 referenced in step S53, Read predicted slack and reliability. Next, in step S54, the entry of the referenced slack propagation table 80 is cleared, and in step S55, the dependency source flag Sflag of the committed instruction is reset to 0, and then the dependency source program of the committed instruction in step S56. The counter value (PC), predicted slack, reliability, and flag Sflag are sent to the update unit 30, and the process proceeds to step S44.

  Further, it is determined whether or not the propagation flag Pflag = 1 of the committed instruction in step S49 or the propagation flag Pflag = predicted slack = reliability = 0 of the committed instruction. If YES, the process proceeds to step S50. If NO, the process proceeds to step S51. The PC, predicted slack, and reliability of the committed instruction are written in the entry of the slack propagation table 80 referred to in step S50, and the process returns to the original main routine. On the other hand, the entry of the slack propagation table 80 referred to in step S51 is cleared, and the process returns to the original main routine.

  FIG. 44 is a flow chart showing a shared slack prediction process executed by the update unit 30 of FIG. 41, which is a new control flow. Here, the numerical ranges of predicted slack and reliability are 0 ≦ reliability ≦ Cth_s, 0 ≦ predicted slack ≦ Vmax_s.

  In step S61, first, the command sent to the update unit 30 is acquired by the sharing information propagation process. In step S62, it is determined whether or not the flag Sflag = 1. If YES, the process proceeds to step S63. On the other hand, if NO, the process proceeds to step S66. In step S63, the increase amount Cinc_s is added to the reliability value, and the addition result is inserted into the reliability value. In step S64, it is determined whether or not reliability ≧ Cth_s (threshold value). Advances to step S65, while if NO, advances to step S69. In step S65, the reliability value is reset to 0, the increment Vinc_s is added to the predicted slack value, and the addition result is inserted as the predicted slack value. Then, the process proceeds to step S69. On the other hand, the reduction amount Cdec_s is subtracted from the reliability value in step S66, and the subtraction result is inserted as the reliability value. In step S67, it is determined whether or not reliability = 0. If YES, step S68 is determined. On the other hand, if NO, the process proceeds to step S69. In step S68, the reliability value is reset to 0, the decrease amount Vdec_s is subtracted from the predicted slack value, and the subtraction result is inserted as the predicted slack value. Then, the process proceeds to step S69. In step S69, it is determined whether or not reliability ≧ 1 or predicted slack ≧ 1, and if YES, the process proceeds to step S70, and if NO, the process proceeds to step S71. In step S70, the propagation flag Pflag is set to 1, and the process proceeds to step S72. On the other hand, in step S71, the propagation flag Pflag is reset to 0, and the process proceeds to step S72. In step S72, the slack table 20A is updated based on the calculation result, and the prediction process of the enhanced slack is terminated.

  As described above, according to the third embodiment, the second prediction method, which is a slack prediction method based on shared information, is used, and no local slack is provided based on an instruction having local slack. Propagate shared information that there is slack that can be shared from the dependency destination to the dependency source between the instructions, and use the local heuristics that each instruction uses by using a predetermined heuristic based on the shared information The amount of slack is determined and controlled so that instructions without local slack can use local slack. Therefore, an instruction having no local slack can use the local slack, and the local slack can be used effectively and sufficiently with a simple configuration as compared with the prior art. Predictions can be performed and program instructions can be executed at high speed.

Fourth embodiment.
In the present embodiment, a method for improving the prediction accuracy is proposed by paying attention to the slack distribution. A mechanism to predict local slack using heuristics is proposed. Local slack is the number of cycles that can increase the execution latency of an instruction without affecting other instructions. The proposed mechanism according to the present embodiment is characterized in that the local slack to be predicted is increased or decreased while observing the behavior at the time of instruction execution such as a branch prediction error or operand forwarding, and is brought closer to the actual local slack. .

1. Problems of the prior art and the first embodiment.
Actual local slack (actual slack) changes dynamically. Therefore, a method corresponding to this change has been proposed (see, for example, Non-Patent Document 6 and the first embodiment). However, the change in actual slack cannot be sufficiently followed, and there is a possibility that performance will be degraded. In order to prevent this, a method of moderately increasing the predicted slack has been proposed (see the first embodiment), but the number of instructions that can be predicted to have one or more slack (the number of slack instructions) is reduced. There was a problem of end.

  Therefore, in the present embodiment, a method for improving the prediction accuracy is proposed by paying attention to the slack distribution. In this method, the conventional mechanism is modified so that the parameters used for slack updating can be changed according to the slack value. By doing so, it is possible to suppress the performance degradation while maintaining the number of slack instructions.

2. slack.
The slack has been described in detail in the related art and the first embodiment. As described in the first embodiment, unlike the global slack, the local slack is not only obtained but also easy to use. Therefore, in the present embodiment, the discussion will proceed with “local slack” as a target. Also, “local slack” is simply expressed as “slack”.

3. The slack prediction mechanism of the first embodiment.
The outline and problems of the slack prediction mechanism (hereinafter referred to as a comparative example mechanism) according to the first embodiment will be described. Details of the comparative example mechanism have been described in detail in the first embodiment.

  In the mechanism based on time, slack is calculated from the difference between the time at which an instruction defines data and the time at which the data is referenced by another instruction, and the slack at the next execution is the same as the slack obtained by the calculation. Predict. On the other hand, in the mechanism based on the heuristic method, the predicted slack is increased or decreased while observing the behavior at the time of instruction execution such as a branch prediction error or forwarding, and the predicted slack is made closer to the actual slack. Both methods can achieve the same level of prediction accuracy.

  The conventional method predicts the slack at the next execution based on the past slack. When actual slack (actual slack) changes dynamically and falls below predicted slack (predicted slack), performance is adversely affected. For this reason, the conventional method includes several mechanisms that respond to changes in actual slack. However, when actual slack repeatedly increases and decreases, the change cannot be sufficiently followed. Therefore, in the mechanism based on the heuristic method, the predicted slack is carefully increased and the predicted slack is rapidly reduced, so that the predicted slack does not exceed the actual slack as much as possible (first embodiment). reference.).

  However, if the increase in predicted slack is moderated to prevent performance degradation, there is a problem that the number of instructions that can be predicted to have one or more slacks (the number of slack instructions) decreases. A decrease in the number of slack instructions means a decrease in the opportunity to use slack. Therefore, it is important to build a mechanism that prevents performance degradation while maintaining the number of slack instructions.

4). A technique to improve slack prediction accuracy.
There is a bias in the distribution of slack. Specifically, the distribution of slack has a feature that 0 is the largest and the values thereafter are rapidly reduced. Based on this property, the present inventor has thought that by controlling the increase / decrease in predicted slack increase / decrease, it is possible to suppress performance degradation while maintaining the number of slack instructions as much as possible. In this chapter, we first describe the slack distribution, and then propose a slack prediction method using this distribution.

4.1. Slack distribution.
In order to investigate the distribution of slack, the present inventor executes a known SPECint20 benchmark on a processor simulator, and calculates the difference between the time when an instruction defines data and the time when the data is referenced by another instruction. The slack was calculated. Below, the details of the survey environment are shown first, and then the survey results are described.

4.1.1. Measurement environment.
The environment used to investigate the slack distribution is described. A simulator for a super scalar processor of the known Simple Salr Tool was used as the simulator. As the instruction set, SimpleSalr / PISA, which is an extension of the well-known MIPSR10, was used. As the benchmark program, eight known SPECint2000 bzip2, gcc, gzip, mcf, parser, perlbmk, vortex, and vpr were used. After skipping the 1G instruction in the program gcc and the 2G instruction in the other programs, the 10M instruction was executed. Table 7 shows the measurement conditions.

4.1.2. Investigation result.
FIG. 45 is a graph showing a ratio of the number of executed instructions to actual slack according to the investigation result of the present inventors. FIG. 45 shows the survey results as a benchmark average. The horizontal axis in FIG. 45 is the ratio of all execution instructions, and the vertical axis is slack. From FIG. 45, it can be seen that the ratio of instructions having slack of 0 is the highest, and the ratio of instructions decreases rapidly as the slack increases.

4.2. A prediction accuracy improvement method using slack distribution.
From the survey results, assuming that the value changes randomly, the success rate of slack prediction is considered to be higher as the predicted slack value is smaller. That is, the predicted success rate is highest when the predicted slack is 0, and the predicted success rate is considered to decrease as the predicted slack value increases.

  Therefore, the mechanism based on the conventional heuristic method is modified so that the predicted slack update method can be changed according to the slack value. For example, the predicted slack changes rapidly when increasing from 0 to 1, and is carefully performed when increasing from a value of 1 or more. As a result, it becomes possible to determine the update method of predicted slack in consideration of the probability of success, so that it is possible to simultaneously maintain the number of slack instructions and suppress performance degradation. Further, the change of the update method of the predicted slack is easy to implement because it is only necessary to switch the update parameter according to the slack value. Note that a large number of points for switching update parameters can be set. However, as the number of update parameters increases, the hardware becomes more complex. Therefore, it is necessary to set the points in consideration thereof.

5). Configuration of the proposed mechanism.
FIG. 46 is a block diagram illustrating a configuration of the processor 10 including the update unit 30 according to the first embodiment. FIG. 46 shows an outline of FIG.

  46, the update unit 30 includes two adders 40 and 50, three multiplexers 91, 92, and 110, and four comparators 93, 94, 111, and 112. Here, the parameters input to the multiplexers 91, 92, 110 and the comparators 94, 112 are the same as those described in the first embodiment. The reliability output from the processor 10 is input to the first input terminal of the adder 40, the arrival condition flag Rflag output from the processor 10 is input as a switching control signal for the multiplexer 91, and the multiplexer 91 When the flag Rflag = 0, the increase amount Cinc is selected and output to the second input terminal of the adder 40, while when the arrival condition flag Rflag = 1, −Cdec is selected by adding a minus to the decrease amount Cdec. Output to the second input terminal of the adder 40. The adder 40 adds the two input data values, and outputs the data value of the addition result to the slack table 20 as a reliability update value, and outputs it to the comparators 93 and 94. Further, the predicted slack from the processor 10 is input to the second input terminal of the adder 50.

  The comparator 93 compares the input data value with 0, and outputs a data value 1 to the second control signal input terminal of the multiplexer 92 when it is 0 or less, while outputs a data value 0 of the multiplexer 92 when it is 1 or more. Output to the second control signal input terminal. The comparator 94 compares the input data value with the threshold value Cth, and when the input data value ≧ Cth, the comparator 94 outputs the data value 1 to the first control signal input terminal of the multiplexer 92, while the input data value When <Cth, the data value 0 is output to the first control signal input terminal of the multiplexer 92. Here, a control signal to each control signal input terminal to the multiplexer 92 is represented by CS 91 (A, B), A is an input value to the first control signal terminal, and B is a second control signal input terminal. Input value to. A control signal to each control signal input terminal to the multiplexer 110 is similarly represented by CS 110 (A, B). The multiplexer 92 selects the data value 0 when the control signal CS92 (0, 0) is selected and outputs it to the first input terminal of the adder 50, and adds a minus to the decrease amount Vdec when the control signal CS92 (0, 1). The data value -Vdec is selected and output to the first input terminal of the adder 50, and the control signal CS92 (1, *) (where * indicates an indefinite value; the same applies hereinafter). At this time, the increase amount Vinc is selected and output to the first input terminal of the adder 50. The adder 50 adds the two input data values, and outputs the added data value to the comparators 111 and 112 and the third input terminal of the multiplexer 110.

  The comparator 111 compares the input data value with 0. When the input data value ≦ 0, the comparator 111 outputs the data value 1, while when not, it outputs the data value 0. The comparator 112 compares the input data value with the maximum value Vmax. When the input data value ≧ Vmax, the comparator 112 outputs the data value 1, while otherwise, outputs the data value 0. The multiplexer 110 selects the data value 0 when the control signal CS110 (0, 0) and outputs it to the slack table 20 as the updated value of the predicted slack, and selects the maximum value Vmax when the control signal CS110 (1, *). Then, the updated value of predicted slack is output to the slack table 20, and the data value from the adder 50 is selected and output to the slack table 20 as the updated value of predicted slack when the control signal CS110 (0, 1).

  FIG. 48 is a flowchart showing local slack prediction processing according to the first embodiment. Here, the numerical range of predicted slack and reliability is 0 ≦ reliability ≦ Cth, 0 ≦ predicted slack ≦ Vmax.

  In FIG. 48, the committed instruction is acquired in step S80, and it is determined in step S81 whether the reaching condition flag Rflag = 0 or not. If YES, the process proceeds to step S82, and if NO, the process proceeds to step S85. . In step S82, the increase amount Cinc is added to the reliability value, and the addition result is inserted as reliability. In step S83, it is determined whether or not reliability ≧ Cth (threshold value). If YES in step S83, the process proceeds to step S84. If NO, the process proceeds to step S88. In step S84, the reliability is reset to 0, the increment Vinc is added to the predicted slack value, the addition result is inserted into the predicted slack, and the process proceeds to step S88. On the other hand, the reduction amount Cdec is subtracted from the reliability value in step S85, and the subtraction result is inserted into the reliability. In step S86, it is determined whether or not reliability = 0. If YES in step S86, the process proceeds to step S87. If NO, the process proceeds to step S88. In step S87, the reliability is reset to 0, the decrease amount Vdec is subtracted from the predicted slack value, and the subtraction result is inserted into the predicted slack. Then, the process proceeds to step S88. In step S88, the slack table 20 is updated based on the calculation result, and the local slack prediction process is terminated.

FIG. 47 is a block diagram showing a configuration of the processor 10 including the update unit 30A according to the fourth embodiment of the present invention. The proposed mechanism according to the fourth embodiment is characterized in that the processor 10 is further provided with a slack table 20 and an update unit 30A. Here, the slack table 20 holds the predicted slack and reliability for each instruction. The update unit 30A is a logic circuit for updating the predicted slack and reliability of the slack table 20. The proposed mechanism of FIG. 47 is characterized in that the configuration of the update unit 30A is different from that of the comparison mechanism of FIG. 46 as follows.
(1) A comparator 100 is further provided.
(2) Two multiplexers 101 and 102 are provided between the comparator 100 and the multiplexer 91.
(3) A multiplexer 103 is provided between the comparator 100 and the comparator 94.
(4) Two multiplexers 104 and 105 are provided between the comparator 100 and the multiplexer 92.

  The processor 10 accesses the slack table 20 when fetching an instruction from the main storage device 9, and obtains the predicted slack and reliability of the instruction. When the following behavior is observed when an instruction is executed, it is determined that the predicted slack has reached the actual slack, and the arrival condition flag Rflag corresponding to the instruction is set to 1. Branch misprediction, cache miss, forwarding. At the time of instruction commit, the predicted slack, arrival condition flag Rflag, and reliability of the committed instruction are sent to the update unit 30A. The update unit 30A uses these values received from the processor 10 as inputs, calculates new predicted slack and reliability, and updates the slack table 20. The slack table 20 holds predicted slack and reliability for each instruction. In this embodiment, the behavior at the time of instruction execution is observed to determine whether the predicted slack is smaller than the actual slack. Reliability indicates how reliable this determination is.

  In the present embodiment, in order to simplify the configuration of the update unit 30A as much as possible, the threshold value Sth for switching update parameters is limited to one location. Therefore, each update parameter is divided into two types: a parameter used when slack is less than the threshold value Sth and a parameter used when the slack is equal to or greater than the threshold value Sth. In FIG. 47, s0 is added to each parameter in the former case, and s1 is added in the latter case.

  The update unit 30 uses the comparator 100 to check the magnitude relationship between the predicted slack and the threshold value Sth. Based on the result, the multiplexers 91, 92, and 101-105 are used to select parameters for updating. Calculate reliability and predicted slack using selected parameters. Specifically, the reliability is increased by an increase amount Cinc_s0 (Cinc_s1) when the arrival condition flag Rflag is 0, and is decreased by a decrease amount Cdec_s0 (Cdec_s1) when the arrival condition flag Rflag is 1. The predicted slack is increased by an increase amount Vinc_s0 (Vinc_s1) if the reliability is equal to or higher than the threshold value Cth_s0 (Cth_s1), and is decreased by a decrease amount Vdec_s0 (Vdec_s1) if the reliability is zero. If neither, keep the value as it is. Here, the inside of () is the latter case described above.

  With respect to the configuration of FIG. 47, differences from FIG. 46 will be described in detail below. In FIG. 47, the comparator 100 compares the predicted slack input from the processor 10 with a predetermined threshold value Sth, and when the predicted slack ≧ Sth, the data value 1 is assigned to each control signal of the multiplexers 101, 102, 103, 104. While outputting to the input terminal, otherwise, the data value 0 is output similarly. The multiplexer 101 selects the increase amount Cinc_s0 when the data value of the control signal is 0 and outputs it to the first input terminal of the multiplexer 91, while selecting the increase amount Cinc_s1 when the data value of the control signal is 1 and selects the increase amount Cinc_s1. 1 to the input terminal. The multiplexer 102 selects the minus value −Cdec_s0 of the decrease amount when the data value of the control signal is 0 and outputs it to the second input terminal of the multiplexer 91, while the minus value −Cdec_s1 of the decrease amount when the data value of the control signal is 1. Is output to the second input terminal of the multiplexer 91. The multiplexer 103 selects the threshold value Cth_s0 when the data value of the control signal is 0 and outputs it to the control signal input terminal of the comparator 94, while selecting the threshold value Cth_s1 when the data value of the control signal is 1, the comparator 103 It outputs to 94 control signal input terminals. The multiplexer 104 selects the increase amount Vinc_s0 when the data value of the control signal is 0 and outputs it to the first input terminal of the multiplexer 92, while selecting the increase amount Vinc_s1 when the data value of the control signal is 1 and selects the increase amount Vinc_s1. 1 to the input terminal. The multiplexer 105 selects the minus value −Vdec_s0 of the decrease amount when the data value of the control signal is 0 and outputs it to the second input terminal of the multiplexer 92, while the minus value −Vdec_s1 of the decrease amount when the data value of the control signal is 1. Is output to the second input terminal of the multiplexer 92.

In the fourth embodiment, update parameters related to the adjustment and their contents are listed below.
Vmax: the maximum value of predicted slack,
Vmin: the minimum value of predicted slack (= 0),
Vinc: Increase in predicted slack per time,
Vdec: the amount of decrease in predicted slack per time,
Vmax: maximum value of reliability (= Cth),
Cmin: minimum value of reliability (= 0),
Cth: threshold of reliability,
Cinc: the amount of increase in reliability per time, and Cdec: the amount of decrease in reliability per time.

  However, the maximum value Vmin = 0 and the minimum value Cmin = 0 are always set. Further, since the reliability is reset to 0 when the threshold value is equal to or greater than the threshold value Cth, the maximum value Cmax is always Cth = Cth. Therefore, there are six types of update parameters that can be changed: Vmax, Vinc, Vdec, Cth, Cinc, Cdec.

  The flowchart of FIG. 48 shows a procedure for calculating reliability and predicted slack. As shown in FIG. 48, if the target slack arrival condition of the committed instruction is not satisfied (that is, the arrival condition flag Rflag). If it is 0), the reliability is increased by the increase amount Cinc, and if it is satisfied (that is, if the reaching condition flag Rflag is 1), the reliability is decreased by the decrease amount Cdec. When the reliability exceeds the threshold Cth, the predicted slack is increased by the increase amount Vinc, and the reliability is reset to zero. On the other hand, when the reliability becomes 0, the predicted slack is decreased by the decrease amount Vdec.

  Then, how the update parameter affects the reliability and the update of the predicted slack will be described qualitatively. FIG. 49 is a graph showing the effect of the technique according to the fourth embodiment, and is a graph showing the relationship between the update parameter and the predicted slack change. That is, FIG. 49 shows the relationship between how the predicted slack changes and the update parameters in order to facilitate understanding of the description. For simplicity, assume a program in which the same instruction is executed every certain cycle. Let this cycle be α. In FIG. 49, the vertical axis indicates slack, and the horizontal axis indicates time. In the line graph, the dotted line is real slack and the solid line is predicted slack.

  When the maximum value Vmax of predicted slack is increased, the average of predicted slack (average predicted slack) increases. As a result, the number of slack instructions also increases. However, the probability of occurrence of a misprediction (here, predicted slack exceeds actual slack) increases and performance decreases.

  When the increase amount Vinc is increased, the average predicted slack increases. As a result, the number of slack instructions also increases. However, the rate of occurrence of mispredictions increases and performance decreases. In addition, since the amount of increase in predicted slack cannot be finely controlled, convergence is deteriorated. Here, it indicates that the number of predicted slack values that do not match actual slack increases.

  When the decrease amount Vdec is increased, the occurrence rate of a prediction error is lowered and the performance is improved. However, the average predicted slack becomes smaller. As a result, the number of slack instructions is also reduced. In addition, since the amount of decrease in predicted slack cannot be finely controlled, convergence is deteriorated.

  The threshold value Cth is strongly related to the increase amount Cinc and the decrease amount Cdec, and will be described in combination with them. When Cth / Cinc, which is the ratio between the threshold value Cth and the increase amount Cinc, is increased, the interval for increasing the predicted slack (Cth / Cinc × α in FIG. 49) becomes wider. That is, the frequency of increasing the predicted slack is reduced. As a result, the occurrence rate of prediction errors is reduced, and the performance is improved. However, the average predicted slack becomes smaller. As a result, the number of slack instructions is also reduced.

  When Cth / Cdec, which is the ratio between the threshold value Cth and the reduction amount Cdec, is increased, the interval (Cth / Cdec × α in FIG. 49) at which the predicted slack is decreased becomes wider. In other words, the frequency of decreasing the predicted slack is reduced. This increases the average predicted slack. As a result, the number of slack instructions also increases. However, the rate of occurrence of mispredictions increases and performance decreases.

  As described above, according to the present embodiment, the instruction slack is obtained by referring to the slack table at the time of executing the instruction, and the execution latency is increased by the amount of the obtained predicted slack. Based on the execution behavior of the instruction, it is estimated whether or not the predicted slack has reached the target slack that is the appropriate value of the current local slack of the instruction, and the predicted slack has reached the target slack. Until the above estimation is made, the predicted slack is gradually increased for each execution of the instruction. Therefore, instead of directly calculating the predicted value of local slack of the instruction (predicted slack), the predicted slack is gradually increased until the appropriate value is reached while observing the behavior at the time of execution of the instruction. Therefore, a complicated mechanism required for direct calculation of predicted slack is not required, and local slack can be predicted with a simpler configuration.

  Further, since the parameters used for slack update are changed according to the value of local slack, it is possible to suppress performance degradation while maintaining the number of slack instructions. Therefore, it is possible to perform local slack prediction and execute program instructions at a higher speed with a simpler configuration as compared with the prior art.

  According to the processor device and the processing method thereof according to the present invention, a store instruction having predicted slack equal to or greater than a predetermined threshold is determined by predicting that there is no dependency between the load instruction and data following the store instruction. Even if the memory address of the store instruction is not known, the subsequent load instruction is speculatively executed. Therefore, if the prediction is correct, the use of the slack of the store instruction does not delay the execution of the load instruction having no data dependency with the store instruction, and the adverse effect on the performance of the processor device can be suppressed. In addition, in order to use the output result of the slack prediction mechanism, it is not necessary to prepare new hardware for predicting the dependency between the store instruction and the load instruction. Therefore, local slack can be predicted and program instructions can be executed at a high speed with a simpler configuration compared to the prior art.

  Further, according to the processor device and the processing method thereof according to the present invention, the second prediction method, which is the slack prediction method based on the shared information, is used to have local slack based on an instruction having local slack. Propagating shared information that there is slack that can be shared from the dependency source to the dependency destination among the non-instructions, and using each of the instructions using a predetermined heuristic based on the sharing information Determine the amount of slack and control so that instructions without local slack can use local slack. Therefore, an instruction having no local slack can use the local slack, and the local slack can be used effectively and sufficiently with a simple configuration as compared with the prior art. Predictions can be performed and program instructions can be executed at high speed.

  Further, according to the processor device and the processing method thereof according to the present invention, when executing an instruction, the predicted slack of the instruction is acquired by referring to the slack table, and the execution latency is increased by the acquired predicted slack. Based on the behavior at the time of execution of the instruction, it is estimated whether the predicted slack has reached target slack, which is an appropriate value of the current local slack of the instruction, and the predicted slack reaches the target slack. The predicted slack is gradually increased with each execution of the instruction until it is estimated that the instruction has been reached. Therefore, instead of directly calculating the predicted value of local slack of the instruction (predicted slack), the predicted slack is gradually increased until the appropriate value is reached while observing the behavior at the time of execution of the instruction. Therefore, a complicated mechanism required for direct calculation of predicted slack is not required, and local slack can be predicted with a simpler configuration.

  Further, since the parameters used for slack update are changed according to the value of local slack, it is possible to suppress performance degradation while maintaining the number of slack instructions. Therefore, it is possible to perform local slack prediction and execute program instructions at a higher speed with a simpler configuration as compared with the prior art.

(A) is a figure which shows an example of the program containing several instructions used in order to demonstrate the slack based on a prior art, (b) is a timing chart which shows the process in which each instruction | indication of the said program is performed on a processor apparatus. It is. It is a block diagram which shows the structure of the processor apparatus provided with the local slack prediction mechanism based on a prior art. (A) is a basic operation of the processor device using the method for heuristically predicting local slack according to the first embodiment of the present invention, and is a timing chart showing the first execution operation; b) is a basic operation of the processor device, and is a timing chart showing a second execution operation, and (c) is a basic operation of the processor device, and a timing chart showing a third execution operation. It is. (A) is a graph showing the cycle-to-slack characteristics for explaining the problems of the basic operation of FIG. 3, and (b) is a graph showing the cycle-to-slack characteristics for explaining a solution to the problems. is there. (A) is a graph showing the cycle vs. slack characteristics for explaining the problem of the solution method of FIG. 4, and (b) is a graph showing the cycle vs. slack characteristic for explaining the solution method of the problem. is there. It is a block diagram which shows the structure of the processor 10 provided with the slack table | surface 20 which concerns on the 1st Embodiment of this invention. It is a simulation result of the Example of the proposal mechanism of FIG. 6, Comprising: It is a graph which shows the ratio which occupies for the number of execution instructions with respect to the actual slack in each program. FIG. 7 is a graph showing a simulation result of the embodiment of the proposed mechanism of FIG. 6 and showing a ratio (slack prediction accuracy) in the number of executed instructions with respect to each model at a predicted slack maximum value Vmax = 1. FIG. 7 is a graph showing a simulation result of the embodiment of the proposed mechanism of FIG. 6 and showing a ratio (slack prediction accuracy) in the number of execution instructions for each model at a predicted slack maximum value Vmax = 5. FIG. 7 is a graph showing a simulation result of the embodiment of the proposed mechanism of FIG. 6 and showing a ratio (slack prediction accuracy) in the number of execution instructions for each model at a maximum predicted slack value Vmax = 15. FIG. 7 is a graph showing a simulation result of the embodiment of the proposed mechanism of FIG. 6 and showing a ratio of the number of executed instructions to a difference between actual slack and predicted slack in each model at the maximum predicted slack value Vmax = 1. FIG. 7 is a graph showing a simulation result of the embodiment of the proposed mechanism of FIG. 6 and showing a ratio of the number of executed instructions to a difference between actual slack and predicted slack in each model at the maximum predicted slack value Vmax = 5. FIG. 7 is a graph showing a simulation result of the embodiment of the proposed mechanism of FIG. 6 and showing a ratio of the number of executed instructions to a difference between actual slack and predicted slack in each model at the maximum predicted slack value Vmax = 15. It is a simulation result of the Example of the proposal mechanism of FIG. 6, Comprising: It is a graph which shows IPC (Instructions Per Clock cycle: average number of instructions which can be processed per clock) in each model normalized. It is a simulation result of the Example of the proposal mechanism of FIG. 6, Comprising: It is a graph which shows the ratio of the number of slack instructions in each model. It is a simulation result of the Example of the proposal mechanism of FIG. 6, Comprising: It is a graph which shows the average prediction slack in each model. It is a simulation result of another Example of the proposal mechanism of FIG. 6, Comprising: It is a graph which shows the relationship between the number of slack instructions with respect to each value of the maximum value Vmax of prediction slack, and IPC. It is a simulation result of another Example of the proposal mechanism of FIG. 6, Comprising: It is a graph which shows the total integrated value of the prediction slack with respect to IPC. It is a block diagram which shows the structure of the update unit 30 which concerns on the 1st Embodiment of this invention. It is a simulation result of the conventional mechanism which concerns on a prior art, Comprising: It is a graph which shows the access time of slack length with respect to line size. It is a simulation result of the proposed mechanism provided with the update unit 30 of FIG. 19, Comprising: It is a graph which shows the access time of slack length with respect to line size. It is a simulation result of the proposed mechanism provided with the update unit 30 of FIG. 19, Comprising: It is a graph which shows the access time of the memory definition table with respect to line size. It is a block diagram showing the composition of processor 10A provided with slack table 20 concerning the 1st modification of a 1st embodiment of the present invention. It is a simulation result of the Example of the processor 10A of FIG. 23, Comprising: It is a graph which shows the normalized IPC with respect to each program. FIG. 24 is a graph showing simulation results of the example of the processor 10A of FIG. 23 and showing normalized EDP (Energy Delay Product: product of energy consumption and execution time of the processor 10A) for each program; FIG. 24 is a graph showing simulation results of another example of the processor 10 </ b> A of FIG. 23 and showing normalized IPC for each program. FIG. It is a simulation result of another Example of the processor 10A of FIG. 23, Comprising: It is a graph which shows the normalized EDP (Energy Delay Product: product of consumption energy and processor execution time) with respect to each program. It is a block diagram which shows the structure of the processor 10 provided with the slack table | surface 20 and two index production | generation circuits 22A and 22B based on the 2nd modification of the 1st Embodiment of this invention. It is a figure which shows the operation example when performing slack prediction in the slack prediction mechanism which concerns on 1st Embodiment, without considering a control flow. FIG. 29 is a diagram illustrating a first operation example when slack prediction is performed in consideration of the control flow in the slack prediction mechanism of FIG. 28. It is a figure which shows the 2nd operation example when performing slack prediction in consideration of a control flow in the slack prediction mechanism of FIG. (A) is a figure for demonstrating the problem which arises by the ambiguity of memory when the slack of a store instruction is used in a prior art, Comprising: It is a figure which shows the program before decoding, (b) ) Is a diagram for explaining a problem that occurs due to the ambiguity of the memory when the slack of the store instruction is used in the prior art, and shows a program after decoding. (A) is a diagram used to explain the influence of memory ambiguity on the use of slack in the processing of the processor, and is a timing chart showing the process of executing a program when slack is not used; (B) is a diagram used for explaining the influence of memory ambiguity on the use of slack in the processing of the processor, and is a timing chart showing the process of executing a program when using slack. 6 is a timing chart showing speculative removal of memory ambiguity, according to a second embodiment of the present invention. It is a block diagram which shows the structure of the processor 10B provided with the speculative removal mechanism of the memory ambiguity of FIG. It is a figure which shows the format of the data entered into the load and store queue (LSQ) 62 of FIG. It is a flowchart which shows the process of LSQ62 of FIG. 35 with respect to a load instruction. It is a flowchart which shows the process of LSQ62 of FIG. 35 with respect to a store instruction. It is a timing chart which shows the program used for description of the slack concerning a prior art. (A) is a timing chart which shows the program explaining utilization of the slack which concerns on the technique of a prior art, (b) is the slack of the technique which increases the number of slack instructions based on the 2nd Embodiment of this invention. It is a timing chart which shows the program explaining utilization. It is a block diagram which shows the structure of the processor 10 provided with the slack propagation | transmission table | surface 80 etc. based on the 3rd Embodiment of this invention. 42 is a flowchart showing a local slack prediction process executed by the update unit 30 of FIG. 41. FIG. 43 is a flowchart showing a sharing information propagation process (S41) in the subroutine of FIG. 42. FIG. It is a flowchart which shows the prediction process of the shared slack performed by the update unit 30 of FIG. It is a graph which shows the ratio which occupies for the number of execution instructions with respect to real slack based on the investigation result of this inventor. It is a block diagram which shows the structure of the processor 10 provided with the update unit 30 which concerns on 1st Embodiment. It is a block diagram which shows the structure of the processor 10 provided with the update unit 30A which concerns on the 4th Embodiment of this invention. It is a flowchart which shows the local slack prediction process which concerns on 1st Embodiment. It is a figure which shows the effect by the method which concerns on 4th Embodiment, Comprising: It is a graph which shows the relationship between the update parameter and the change of prediction slack.

Explanation of symbols

1, 1A ... execution core,
2 ... Register definition table,
3 ... Memory definition table,
4 ... Multiplexer,
5 ... subtractor,
6 ... Slack table,
7 ... Front end,
8 ... Backend,
9 ... Main memory device,
10, 10A, 10B ... processor,
11: Fetch unit,
11A ... Instruction cache,
12 ... Decoding unit,
12a ... Instruction decoder unit,
12b ... tag allocation unit,
13 ... Instruction window (I-win),
14: Register file (RF),
14A ... Reservation Station,
15, 15a, 15b, 15A, 15B ... execution unit (EU),
16 ... Reorder buffer (ROB),
17 ... FIFO,
20, 20A ... Slack table,
21A, 21B ... branch history register,
22A, 22B ... Index generation circuit,
30, 30A ... Update unit,
31, 32, 35, 36 ... Andgate,
33,37 ... Or gate,
34, 38, 39 ... Multiplexer,
40, 50 ... adder,
41, 42, 51, 52 ... and gate,
43, 44, 45, 46, 53, 54, 55, 56 ... inverter,
47, 48, 49, 57, 58, 59 ... multiplexer,
60 ... Slack prediction mechanism,
61 ... Functional unit,
62 ... Load and store queue (LSQ),
63 ... data cache,
71 ... opcode,
72, 74, 75, 77 ... flags,
73: Memory address,
76 ... Store data,
80 ... Slack propagation table,
91,95,101,102,103,104,105,110 ... multiplexer,
92, 96 ... adder,
93, 94, 100, 111, 112 ... comparator,
120: Exclusive OR gate.

Claims (21)

In a processor device that predicts predicted slack, which is a predicted value of local slack of an instruction executed in the processor device, and executes the instruction using the predicted slack,
Storage means for storing a slack table including the predicted slack;
Setting means for acquiring predicted slack of the instruction with reference to the slack table upon execution of the instruction and increasing execution latency by the amount of the acquired predicted slack;
An estimation means for estimating whether or not the predicted slack has reached the target slack, which is an appropriate value of the current local slack of the instruction, based on the execution behavior of the instruction;
A processor apparatus comprising: update means for gradually increasing the predicted slack for each execution of the instruction until the estimated means has estimated that the predicted slack has reached the target slack. .   The update means, according to the predicted slack value, changes a parameter used for updating the slack so as to suppress a decrease in performance of the processor device while maintaining the number of slack instructions. The processor device according to 1.   3. The processor device according to claim 2, wherein the updating unit changes a parameter used for updating the slack according to whether or not the predicted slack is equal to or greater than a predetermined threshold value. The estimation means is
(A) A branch prediction error occurred during execution of the instruction,
(B) A cache miss occurred during execution of the instruction;
(C) Operand forwarding for the subsequent instruction has occurred,
(D) that store data forwarding has occurred for the subsequent instruction;
(E) the instruction is the oldest instruction in the instruction window;
(F) the instruction is the oldest instruction in the reorder buffer;
(G) The instruction is an instruction that passes the execution result to the oldest instruction in the instruction window.
(H) The instruction is an instruction that passes the execution result to the most subsequent instructions among the instructions executed in the same cycle;
(I) By passing the execution result of the instruction, at least one of the fact that the number of subsequent instructions that can be executed becomes equal to or greater than a predetermined determination value is used as a condition for establishing the above estimation 4. The processor device according to claim 1, wherein arrival of the predicted slack to the target slack is estimated. The counter value is increased or decreased when the condition that the estimated slack has reached the target slack is satisfied, and the counter value is decreased when the estimated condition is not satisfied. Or further comprising an increased reliability counter;
The updating means increases the prediction slack on the condition that the counter value of the reliability counter becomes an increase determination value, and the prediction on the condition that the counter value of the reliability counter becomes a decrease determination value. 5. The processor device according to claim 1, wherein slack is reduced.   The increment or decrement of the counter value when the estimation satisfaction condition is satisfied in the reliability counter is set larger than the decrease or increase of the counter value when the estimation satisfaction condition is not satisfied. 6. The processor device according to claim 5, wherein:   7. The processor device according to claim 5, wherein the increment and decrement of the counter value are set so as to differ depending on the type of each instruction.   8. The update amount of each predicted instruction slack of each instruction by the updating means is set to be different depending on the type of each instruction. Processor unit.   9. An upper limit value is set in the predicted slack of each instruction updated by the updating means, and the upper limit value is set so as to differ depending on the type of instruction. The processor device according to one. A branch history register for recording the branch history of the program;
10. The processor according to claim 1, wherein the slack table individually records predicted slack of the instruction separately from a branch pattern obtained by referring to the branch history register. apparatus. In a processing method of a processor device that predicts predicted slack, which is a predicted value of local slack of an instruction executed in the processor device, and executes the instruction using the predicted slack.
The instruction executed by the processor unit is executed with the execution latency increased by the value of the predicted slack, and the target slack which is the appropriate value of the current local slack based on the behavior at the time of execution of the instruction. Including a control step of estimating whether or not the predicted slack has been reached and updating the predicted slack so as to gradually increase each time the instruction is executed until it is estimated that the predicted slack has been reached. A processing method of the processor device.   The control step is characterized in that, according to the predicted slack value, a parameter used for updating the slack is changed so as to suppress a decrease in performance of the processor device while maintaining the number of slack instructions. A processing method of the processor device according to 11.   13. The processing method of a processor device according to claim 12, wherein the control step changes a parameter used for updating the slack according to whether or not the predicted slack is equal to or greater than a predetermined threshold value. As a condition for the estimation that the predicted slack has reached the target slack,
(A) A branch prediction error occurred during execution of the instruction,
(B) A cache miss occurred during execution of the instruction;
(C) Operand forwarding for the subsequent instruction has occurred,
(D) that store data forwarding has occurred for the subsequent instruction;
(E) the instruction is the oldest instruction in the instruction window;
(F) the instruction is the oldest instruction in the reorder buffer;
(G) The instruction is an instruction that passes the execution result to the oldest instruction in the instruction window.
(H) The instruction is an instruction that passes the execution result to the most subsequent instructions among the instructions executed in the same cycle;
(I) including at least one of the number of succeeding instructions that can be executed by passing the execution result of the instruction being a predetermined determination value or more. The processing method of the processor apparatus as described in any one of 11 thru | or 13.   15. The processing method of a processor device according to claim 11, wherein the predicted slack is decreased when it is estimated that the predicted slack has reached the target slack.   The increase in the predicted slack is performed on the condition that the number of times that the estimated condition that the predicted slack has reached the target slack is not satisfied reaches the specified number of times. 16. The processing method of a processor device according to claim 15, wherein the processing is performed on condition that the number of times the condition is satisfied becomes a specified number.   17. The processor according to claim 16, wherein the number of times that the satisfaction condition is not satisfied to increase the predicted slack is set to be greater than the number of times that the satisfaction condition is required to decrease the predicted slack. Device processing method.   The increase in the predicted slack is performed on the condition that the number of times that the estimated condition that the predicted slack has reached the target slack is not satisfied reaches the specified number of times. 16. The processing method of a processor device according to claim 15, wherein the processing is performed on condition that the condition is satisfied.   19. The processing method of a processor device according to claim 16, wherein the prescribed number of times is set to be different depending on a type of the instruction.   20. The processing method of the processor device according to claim 11, wherein the update amount of predicted slack per time is set to be different depending on the type of the instruction.   21. The processing method of the processor device according to claim 11, wherein an upper limit value of the predicted slack is set to be different depending on a type of the instruction.

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