JP2007280209A - Monitoring method of multi-core processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems of operating a multi-core processor in a multi-task in an optimal state, operating a signal processing system to response to a real-time request, and monitoring operation of a core processor without losing its real-time performance. <P>SOLUTION: This multi-core processor is constituted so that a plurality of core processor attached with a memory are respectively connected to a plurality of different memories via a selector by an inside bus, and the selector selects one or a plurality of memories of an access destination from the plurality of memories by address designation or the register setting from the core processors, and can make write access between the core processor and the memory; and is realized by outputting the content of the memory to an external part of the multi-core processor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a monitoring method for a multi-core processor, and more particularly to a monitoring method using memory access of each core processor.

Conventionally, a multitasking operation is realized by mounting a multitasking OS (Multitasking Operating System) on a single core processor, and the processing capability is improved by increasing the frequency of the single core processor, thereby improving the real-time performance. In the case of a single-core processor, there is a method of monitoring the processor by outputting the bus to an external pin and capturing or monitoring this signal with another measuring instrument, etc., but this can withstand high-speed bus operation. There is no problem. Also, the method of increasing the processor capacity by increasing the frequency is approaching the limit in terms of heat and power consumption.
In addition, there is a system consisting of a plurality of processors that are not one-chip in the past. In this case, the processors are monitored by socket communication via a shared memory or a communication device, and messages are sent to each other by messages such as health checks. Was monitoring the task. Since this method is simple monitoring, there is a problem that detailed operations such as a signal processing system having a severe time response performance cannot be monitored or analyzed.

  In contrast, a multi-core processor configuration can increase processing capacity without increasing the frequency, and is more advantageous than a single-core processor in terms of heat and power consumption, but memory exclusion, input / output resource exclusion, data There is a demerit that maintaining identity is complicated.

  The problem to be solved is to operate the multi-core processor in an optimal state, perform multi-task operation to respond to real-time requirements such as signal processing systems, and monitor the operation of the core processor without losing its real-time characteristics. It is.

  The present invention has been made in view of the above problems, and in a multi-core processor in which a plurality of core processors are integrated in one package, each of the plurality of core processors is attached with a memory, and the memory is attached. The plurality of core processors are connected to each other by a multi-core processor internal bus and to a plurality of different memories via a selector, and the selector is accessed from the plurality of memories by addressing or register setting from the core processor. The memory access operation of the core processor is monitored by selecting one or a plurality of memories, configured to be write-accessible between the core processor and the memory, and outputting the contents of the memory to the outside of the multi-core processor. .

ADVANTAGE OF THE INVENTION According to this invention, the function which outputs the result of the memory access of a multi-core processor outside can be implement | achieved without applying a load to a core processor with respect to a signal processing system etc. with severe time response performance.
For example, a function that traces function calls by placing a stack in one memory among a plurality of memories connected to a plurality of core processors via a selector and outputting the contents to the outside via a different memory Can be realized.
In addition, a task state block is placed in one memory among a plurality of memories connected to a plurality of core processors via a selector, and the contents are output to the outside via a different memory. Can be monitored.

  Multiple core processors are connected via an internal bus and connected to multiple different memories via a selector, and the selector selects one or more access destination memories from multiple memories by addressing or register setting from the core processor The memory access operation of the core processor is implemented by monitoring the memory access operation of the core processor by outputting the contents of the memory to the outside of the multi-core processor.

An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is an example of a block diagram showing a configuration according to an embodiment of the present invention, and FIG. 2 is an example of a multitask configuration according to an embodiment of the present invention.
Each of the core processor 0 (1), the core processor 1 (2), and the core processor 2 (3) in FIG. 1 includes a core 0, a core 1, and a core 2, and a plurality of cores each having an L1 memory attached to each core. A processor is connected to a plurality of L2 memories 0 (4), L2 memories 1 (5), L2 memories 2 (6), and L2 memories 3 (7) via a selector (11) by an internal bus. A direct memory access DMA (12) is connected between the internal bus and the external bus, and a HOST processor (8), SDRAM (9), and communication device (10) are connected to the external bus. .
FIG. 2 shows an example of a multi-task configuration. Each core processor of the core processor 0 (1), the core processor 1 (2), and the core processor 2 (3) operates on a single task OS. It has one Task, multiple SWI (software interrupts), and multiple HWIs (hardware interrupts), and has a common part (21), Library, IPL (Initial Program Loader), OS, Driver ing.

In the multi-core processor shown in this embodiment, as shown in FIG. 1, the core processor 0 (1), the core processor 1 (2), and the core processor 2 (3) are a plurality of core processors each having an L1 memory attached to each core. Thus, the L2 memory 0 (4), the L2 memory 1 (5), the L2 memory 2 (6), and the L2 memory 3 (7) are connected via the selector (11) by the internal bus. Here, each core processor and each L2 memory are connected via a selector (11) with spatially multiplexed buses. For example, the core processor 0 (1) accesses the L2 memory 0 (4). The connection is such that the core processor 1 (2) can access the L2 memory 1 (5) and the core processor 2 (3) can access the L2 memory 2 (6) simultaneously.
Further, only one Task is allocated to each core processor as shown in FIG. As a result, overhead due to task context switching processing does not occur in the same core.
The common unit (21) is stored in the L2 memory and accessed from the core processor via a cache memory arranged in a part of the L1 memory. By arranging the common part in the L2 memory, it is possible to supplement the L1 memory having a small capacity.

  In the above configuration, the selector (11) selects the access destination from the L2 memory 0 (4), L2 memory 1 (5), and L2 memory 2 (6) by address designation or register setting from the core processor. It should be noted that the selector (11) is provided with the L2 memory 0 (4) and the L2 memory 3 (7), the L2 memory 1 (5) and the L2 memory 3 (7), and the L2 memory 2 according to address designation or register setting from the core processor. A combination of (6) and L2 memory 3 (7) is connected so that a plurality of memories can be simultaneously write-accessed. The selector (11) is connected so that only the L2 memory 3 (7) can be read-accessed by address designation or register setting from the core processor.

  For example, the selector (11) selects access to the L2 memory 0 (4) when the upper bit of the address is 000, L2 memory 1 (5) when the address is 001, and L2 memory 2 (6) when the address is 010. 100, L2 memory 0 (4) and L2 memory 3 (7), 101 is L2 memory 1 (5) and L2 memory 3 (7), 110 is L2 memory 2 (6) and L2 memory 3 (7) is selected for write access. If 111, read access to the L2 memory 3 (7) is selected. The selector (11) may have a register that can be set from the core processor, and selection equivalent to the selection using the upper bits of the address described above may be possible by setting by the register.

  With such a configuration, the L2 memory 3 (7) is regarded as a monitoring memory, and an access equivalent to an access to the L2 memory 0 (4), the L2 memory 1 (5), or the L2 memory 2 (6) is performed in the L2 memory. This is performed for the memory 3 (7). The contents of the L2 memory 3 (7) can be output to the outside by transferring to the SDRAM (9) accessible from the communication device (10) or the HOST processor (8) using the DMA (12). The memory access operation of the core processor can be monitored.

  In addition, although one Example was described about embodiment of this invention above, the structure regarding implementation is not limited to the said Example, Moreover, all the combinations of the structure of this invention are essential. Is not limited.

An example of a block diagram showing a configuration in an embodiment of the present invention An example of a multitask configuration in an embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Core processor 0, 2 ... Core processor 1, 3 ... Core processor 2, 4 ... L2 memory 0, 5 ... L2 memory 1, 6 ... L2 memory 2, 7 ... L2 memory 3, 8 ... HOST processor, 9 ... SDRAM DESCRIPTION OF SYMBOLS 10 ... Communication device, 11 ... Selector, 12 ... DMA, 21 ... Common part

Claims (1)

In a multi-core processor in which a plurality of core processors are integrated in one package, a memory is attached to each of the plurality of core processors, and each of the plurality of core processors to which the memory is attached is connected to an internal bus of the multi-core processor. Connected to a plurality of different memories via a selector, and the selector selects one or a plurality of access destination memories from the plurality of memories by addressing or register setting from the core processor, and the core processor and the memory A method of monitoring a multi-core processor, wherein the memory access operation of the core processor is monitored by outputting the contents of the memory to the outside of the multi-core processor.

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