JP2007280127A - Inter-processor communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To communicate a large amount of data between processors at high speed in an inter-processor communication method in a controller of a loosely coupled multiprocessor configuration. <P>SOLUTION: The overhead of access to a shared memory SM is eliminated by writing transfer data between processing units (PU) in a local memory LM, and a block transfer instruction or a DMA of a processor 1a performs collective transfer from a transfer source local memory LM to the shared memory SM after completing to write transfer data to thereby achieve a large amount of data transfer at a high speed. The completion of writing transfer data is regarded when a release system synchronization basic operation belonging to an OS, etc., is performed. Next, collective transfer is performed from the shared memory SM to a transfer destination local memory LM by a block transfer instruction or a DMA of the processor 1a before reading transfer data. Start of reading the transfer data is regarded when an acquisition system synchronization basic operation of the OS is performed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an interprocessor communication method in a system of a loosely coupled multiprocessor configuration having a shared memory for interprocessor communication.

  Conventionally, in a multiprocessor system in which a plurality of processors are mounted in one system and these processors are operated simultaneously, a tightly coupled multiprocessor system (shared memory system (a)) that shares a main memory device, and a main memory device There is a loosely-coupled multiprocessor system with each processor. In the loosely coupled multiprocessor system, a single address space is shared between processors, and the memory (storage device) of each processor can be accessed from each processor (distributed shared memory system (b)). They can be classified into those having different address spaces (hereinafter simply referred to as “loosely coupled multiprocessor system” (c)).

  (A) In the shared memory method, each processor is equipped with a cache memory in order to reduce the overhead (access time) when accessing the shared memory and the access conflict of the shared memory. In order to maintain the data consistency of the cache memory, a special mechanism (coherent cache; a function of simultaneously rewriting or erasing the cache memory of the shared memory and other processors) is provided. Because of this mechanism, communication between processors is possible simply by writing to and reading from the memory, and an easy-to-use model is provided as a programming model.

  (B) The distributed shared memory method can be performed at high speed when accessing the local shared memory of its own processor, but has a large overhead when accessing the local shared memory of other processors. For this reason, there are many cases in which the contents of the local shared memory of other processors are cached in the memory of the own processor as necessary. Also in this case, a special mechanism (coherent cache) is provided to maintain data consistency. When this mechanism is available, it is possible to communicate between processors simply by writing to and reading from the memory. Therefore, an easy-to-use model is provided as a programming model.

  (C) A loosely coupled multiprocessor system having a separate address space for each processor performs inter-processor communication using a shared memory, such as a normal network personal computer (hereinafter referred to as “PC”). Therefore, it is not necessary to have a mechanism for data consistency (coherent cache), and hardware can be simplified.

  Even in a loosely coupled multiprocessor, there is a system (d) configured to have a shared memory for interprocessor communication in order to increase the bandwidth (that is, transfer rate) of interprocessor communication (for example, the following patent document) 1). In this case, the inter-processor communication using the shared memory is performed, but the main memory device of another processor is also accessed, and the shared memory is not cached. Therefore, it is not necessary to have a data consistency mechanism.

  In the conventional inter-processor communication method in the system having the configuration described in Patent Document 1 or the like, the transmission processor stores a message in the inter-processor communication area on the shared memory, and the transmission processor interrupts the inter-processor communication interrupt to the reception processor. This was done by issuing a request and the receiving processor retrieving the message from the inter-processor communication area.

Japanese Patent Laid-Open No. 11-120156

  However, the conventional inter-processor communication method has the following problems (a) to (d).

(A) Since the shared memory system implements a coherent cache, the system configuration is complicated. In addition, when using a cached processor core licensed as an intellectual property (IP), a core that does not support a mechanism for maintaining cache memory data consistency There is a problem that cannot be used.

(B) The distributed shared memory system also has the same problems as the shared memory system because it implements a coherent cache.

(C) The loosely coupled multiprocessor needs to implement the inter-processor communication function by controlling the communication device by a program, not by reading / writing a memory, and there is a problem that the program becomes complicated. Further, although depending on the communication device, it is generally difficult to realize a transfer with a large bandwidth with a small latency (waiting time).

(D) A loosely coupled multiprocessor having a shared memory for interprocessor communication has the following problems.

  Since access to the shared memory requires bus arbitration (bus arbitration), access takes time. For this reason, in order to transfer a large amount of data to another processor at high speed, the overhead is large and the transfer takes time, and the processing time of the processor is wasted.

  In addition, there is a problem that the program needs to be aware of a special area called an inter-processor communication area, control inter-processor interrupts, etc., and the program becomes complicated.

  Therefore, in order to solve such a problem, the present invention does not complicate the system configuration and the program configuration, and can be used even with a processor core IP that does not provide a mechanism for maintaining data consistency. An object of the present invention is to provide an inter-processor communication method that enables high-speed communication between a large amount of data between processors based on a loosely-coupled multiprocessor configuration having a common memory.

  In order to solve the above problems, the invention according to claim 1 is an interprocessor communication method of a multiprocessor system in which a plurality of processors each having a local memory and a shared memory for interprocessor communication are connected by a shared bus. Thus, when data is transferred from one processor of the plurality of processors to another processor, data is transferred between the local memory and the shared memory in the acquisition synchronous basic operation and the release synchronous basic operation. I am doing so.

  According to the second and third aspects of the present invention, the overhead of shared memory access is eliminated by writing the transfer data to the local memory, and after the transfer data has been written, the processor block transfer instruction or direct memory access ( (Hereinafter referred to as “DMA”)) Transfers data collectively from the transfer source local memory to the shared memory, enabling high-speed transfer of large amounts of data. Completion of transfer data writing is performed by a release synchronous basic operation (for example, semaphore V instruction, signal, signal, uncontrol, which is exclusive control means) possessed by the operating system (hereinafter referred to as “OS”). It is considered that when the lock (unlock, etc.) is performed. Next, prior to reading the transfer data, a block transfer instruction of the processor or DMA transfers the data from the shared memory to the transfer destination local memory. The start of reading the transfer data is considered to be the timing at which the OS acquisition-system synchronous basic operation (for example, semaphore P instruction, wait, lock, etc.) is performed.

  According to the first aspect of the present invention, since data transfer is performed between the local memory and the shared memory in the basic synchronization operation (acquisition basic synchronization operation, release basic synchronization basic operation), the following (i) , (Ii) has the effect.

  (i) Since a certain processor writes data in the local memory while performing a series of arithmetic processing, the program does not need to be aware of the shared memory, and can be written at high speed. When a series of arithmetic processing is completed and a synchronous basic operation is performed, the arithmetic results to be transmitted to other processors are collectively written between the local memory and the shared memory, so that high-speed writing is possible.

  (ii) Since the write operation between the local memory and the shared memory is incorporated during the synchronous basic operation, it is not necessary to describe the write between the local memory and the shared memory in the main program. Therefore, the program can be simplified.

  According to the second and third aspects of the invention, the overhead of accessing the shared memory can be reduced, and high-speed data transfer can be realized. Furthermore, the complexity of the entire program can be reduced by performing the data transfer timing in combination with the synchronous basic operation.

  In a multiprocessor system, a plurality of processors each having a local memory and a shared memory for interprocessor communication are connected by a shared bus. In such an inter-processor communication method of a multiprocessor system, when data is transferred from one processor to another in a plurality of processors, a synchronization basic operation (acquisition synchronization basic operation (wait_sem), release synchronization basic) In the operation (sig_sem), data is transferred between the local memory and the shared memory.

(Configuration of Example 1)
FIG. 1 is a block diagram illustrating a configuration example of a multiprocessor system that implements the inter-processor communication method according to the first embodiment of the invention.

  The multiprocessor system includes a plurality of processing units (hereinafter referred to as “PUs”) 1-0 to 1-n and a shared memory SM used by each of the PUs 1-0 to 1-n. The PUs 1-0 to 1-n and the shared memory SM are connected by the shared bus 3. A DMA controller or the like is connected to the shared bus 3. Each PU 1-0 to 1-n includes a processor 1a and a local memory LM which is a main memory. The address space of the processor 1a is a so-called loosely coupled multiprocessor, which is different for each of the PUs 1-0 to 1-n, and each local memory LM can be accessed only from the processor 1a in the same PU. Each processor 1a may have a cache memory 1b as necessary. The cache memory 1b does not need to guarantee data consistency between processors, and may be a cache memory normally used by a single processor.

  The shared memory SM is mapped to a specific area in the address space of the processor 1a, and each processor 1a can share data through this area. The shared memory area is not cacheable, that is, the cache memory 1b is not used.

  When each processor 1a accesses the shared memory SM, it requests the use right of the shared bus 3 from a bus arbiter (bus arbitration means) (not shown) and accesses the shared memory SM only when the use right of the shared bus 3 is acquired. it can. An interrupt can be generated between the processors 1a.

  An embodiment of interprocessor communication using the shared memory SM in the multiprocessor system having such a configuration will be described.

  On the shared memory SM, a communication area CBUF01 for PU1-0 and PU1-1 is disposed, and an exclusive control variable area SEM_CBUF01 related to the communication area CBUF01 is disposed. The exclusive control variable area SEM_CBUF01 includes, for example, a PU1-0 data read callback routine (collection routine), a PU1-1 data read callback routine, a PU1-0 data write callback routine, and a PU1-1 data callback. Stores the start address of the routine.

  A copy area LBUF0 of the communication area CBUF01 is arranged on the local memory LM of the PU1-0, and a copy area LBUF1 of the communication area CBUF01 is also arranged on the local memory LM of the PU1-1. The copy areas LBUF0 and LBUF1 are used as buffer areas for the communication area CBUF01 on the PU1-0 and PU1-1, respectively. The correspondence between the communication area CBUF01 and the copy areas LBUF0 and LBUF1 is PU1-0. , Managed by PU1-1.

FIG. 2 is a diagram showing the configuration of the communication area CBUF01 in FIG.
The communication area CBUF01 includes a data size 2a and a transfer data area 2b.

  It is assumed that the data size 2a of the communication area CBUF01 is initialized with the initial value 0 by the PU 1-0 or PU 1-1.

(Interprocessor communication method of the first embodiment)
3A and 3B are diagrams illustrating a processing procedure in the inter-processor communication method according to the first embodiment of this invention. In FIG. 3A, for example, the user program on the PU 1-0 transmits data to the PU 1-1, and the user program on the PU 1-1 performs some processing on the contents and returns the result to the PU 1-0. The procedure is shown. FIG. 3-2 shows a processing procedure such as the routine in FIG.

  In the inter-processor communication method according to the first embodiment, it is assumed that the basic synchronization operation (wait_sem, sig_sem) starts a data read callback routine and a data write callback routine defined by the user. In the exclusive control variable area SEM_CBUF01, it is assumed that a data read callback routine and a data write callback routine activated by a synchronous basic operation (wait_sem, sig_sem) are associated with each PU.

  In the inter-processor communication method shown in FIG. 3A, processing is performed according to the following (A) step S1, (B) step S2, and (C) step S3.

(A) PU1-0: Processing of transmission program (step S1)
First, in order to transmit data from PU1-0 to PU1-1, a user transmission program on PU1-0 is activated. The transmission program on PU1-0 first waits for OS resource acquisition using the exclusive control variable area SEM_CBUF01 on the shared memory SM for exclusive control of the communication area CBUF01 located on the shared memory SM. Call the system call wait_sem to try to acquire the communication area CBUF01.

  The OS resource acquisition wait system call wait_sem refers to the exclusive control variable area SEM_CBF01 on the shared memory SM to determine whether or not the communication area CBUF01 can be acquired, and if not, shifts to a wait state. If the communication area CBUF01 can be acquired, the data read callback routine associated with the exclusive control variable area SEM_CBF01 on the shared memory SM is activated.

  The data read callback routine copies the data in the communication area CBUF01 from the communication area CBUF01 to the copy area LBUF0 by the data size written in the communication area CBUF01. Since the data size 2a is 0, no copy is actually performed, the data size 2a is read from the communication area CBUF01 to the copy area LBUF0, and the data read callback routine is terminated.

  When the data read callback routine ends, the OS resource acquisition wait system call wait_sem returns control to the caller.

  After returning from the OS resource acquisition wait system call wait_sem and acquiring the communication area CBUF01, the transmission program writes the transfer data and the data size 2a to LBUF0, which is a copy area of the communication area CBUF01 (previously, , Was writing data to the shared memory SM.)

  After the data writing is completed, in order to release the communication area CBUF01, the OS resource release system call sig_sem is called using the exclusive control variable area SEM_CBF01 on the shared memory SM.

  The OS resource release system call sig_sem starts a data write callback routine before actually releasing the communication area CBUF01.

  The data write callback routine copies the data in the copy area LBUF0 from the copy area LBUF0 to the communication area CBUF01 by the data size written in the copy area LBUF0. Also, the data size itself of the data in the copy area LBUF0 is copied. Copying is performed by starting program transfer or DMA. When copying is complete, the data write callback routine ends.

  When the data write callback routine ends, the OS resource release system call sig_sem releases the communication area CBUF01 and returns control to the caller.

  Next, the transmission program interrupts PU1-1 to PU1-1 and notifies PU1-1 that data has been prepared.

(B) PU1-1: Processing of processing program (step S2)
Upon receiving the interrupt, the PU 1-1 activates the user processing program. The processing program on the PU 1-1 first waits for OS resource acquisition using the exclusive control variable area SEM_CBF01 on the shared memory SM for exclusive control of the communication area CBUF01 arranged on the shared memory SM. Call the system call wait_sem to try to acquire the communication area CBUF01.

  The OS resource acquisition wait system call wait_sem refers to the exclusive control variable area SEM_CBF01 on the shared memory SM to determine whether or not the communication area CBUF01 can be acquired, and if not, shifts to a wait state. If the communication area CBUF01 can be acquired, the data read callback routine associated with the exclusive control variable area SEM_CBF01 on the shared memory SM is activated.

  The data read callback routine copies the data in the communication area CBUF01 from the communication area CBUF01 to the copy area LBUF1 by the data size written in the communication area CBUF01. Copying is performed by starting program transfer or DMA. When copying is complete, the data read callback routine ends.

  When the data read callback routine ends, the OS resource acquisition wait system call wait_sem returns control to the caller.

  If you return from the OS resource acquisition wait system call wait_sem and acquire the communication area CBUF01, the contents of the communication area CBUF01 are copied to LBUF1, which is the copy area of the communication area CBUF01. The transfer data is read from the copy area LBUF1 for the data size. When reading is completed, the data size 2a is changed to zero.

  Next, the processing program performs some processing based on the received data, and writes the resultant data and the data size 2a in the copy area LBUF1.

  After the data writing is completed, in order to release the communication area CBUF01, the OS resource release system call sig_sem is called using the exclusive control variable area SEM_CBF01 on the shared memory SM.

  The OS resource release system call sig_sem starts a data write callback routine before actually releasing the communication area CBUF01.

  The data write callback routine copies the data in the copy area LBUF1 from the copy area LBUF1 to the communication area CBUF01 by the data size written in the copy area LBUF1. Copying is performed by starting program transfer or DMA. When copying is complete, the data write callback routine ends.

  When the data write callback routine ends, the OS resource release system call sig_sem releases the communication area CBUF01 and returns control to the caller.

  Next, the processing program interrupts PU1-1 to PU1-0 and notifies PU1-0 of the completion of the processing.

(C) PU1-0: Received program processing (step S3)
Upon receiving the interrupt, the PU 1-0 activates the user's reception program. The receiving program on PU1-0 first waits for OS resource acquisition using exclusive control variable area SEM_CBF01 on shared memory SM for exclusive control of communication area CBUF01 located on shared memory SM. Call the system call wait_sem to try to acquire the communication area CBUF01.

  The OS resource acquisition wait system call wait_sem refers to the exclusive control variable area SEM_CBF01 on the shared memory SM to determine whether or not the communication area CBUF01 can be acquired, and if not, shifts to a wait state. If the communication area CBUF01 can be acquired, the data read callback routine associated with the exclusive control variable area SEM_CBF01 on the shared memory SM is activated.

  The data read callback routine copies the data in the communication area CBUF01 from the communication area CBUF01 to the copy area LBUF0 by the data size written in the communication area CBUF01. Copying is performed by starting program transfer or DMA. When copying is complete, the data read callback routine ends.

  When the data read callback routine ends, the OS resource acquisition wait system call wait_sem returns control to the caller.

  If you return from the OS resource acquisition wait system call wait_sem and acquire the communication area CBUF01, the contents of the communication area CBUF01 are copied to LBUF0, which is the copy area of the communication area CBUF01. Read the result data for the data size from the copy area LBUF0. When reading is completed, the data size 2a is changed to zero.

  Next, in order to release the communication area CBUF01, the OS resource release system call sig_sem is called using the exclusive control variable area SEM_CBF01 on the shared memory SM.

  The OS resource release system call sig_sem starts a data write callback routine before actually releasing the communication area CBUF01.

  The data write callback routine copies the data in the copy area LBUF0 from the copy area LBUF0 to the communication area CBUF01 by the data size written in the copy area LBUF0. Since the data size is 0, no copy is actually performed, and the data size 2a is written back from the copy area LBUF0 to the communication area CBUF01, and the data write callback routine ends.

  When the data write callback routine ends, the OS resource release system call sig_sem releases the communication area CBUF01 and returns control to the caller.

  The reception program of the calling source is terminated because the reception is completed, and the processing of the user program is continued based on the result data.

(Effect of Example 1)
According to the first embodiment, there are the following effects (a) to (d).

  (A) Data is transferred between the local memory LM and the shared memory SM in the basic synchronous operation (wait_sem, sig_sem). As a result, the data is written to the local memory LM while a series of arithmetic processing is performed in a certain processor 1a, so that it is not necessary to be aware of the shared memory SM by the program, and writing can be performed at high speed. Then, when a series of arithmetic processing is completed and the synchronous basic operation (wait_sem, sig_sem) is performed, the arithmetic results to be transmitted to the other processors 1a are collectively transferred between the local memory LM and the shared memory SM. Can write at high speed.

  (B) In (a), the write operation between the local memory LM and the shared memory SM is incorporated in the basic synchronous operation (wait_sem, sig_sem), so that the main program is between the local memory LM and the shared memory SM. There is no need to describe the writing. Therefore, the program can be simplified.

  (C) With respect to shared memory access, even when using a processor core IP with cache that does not provide a mechanism for maintaining data consistency of the cache memory, with a simple hardware configuration without changing the processor core IP, Communication between processors using the shared memory SM can be performed quickly and efficiently.

  (D) At the timing of the basic synchronization operation (wait_sem, sig_sem), block transfer with the shared memory SM or data transfer by DMA is performed, so that the part that actually transfers data to the shared memory SM from the user program Can be separated, and the complexity of the entire program can be reduced.

(Configuration of Example 2)
FIG. 4 is a block diagram showing a configuration example of a multiprocessor system that implements the inter-processor communication method according to the second embodiment of the present invention. The code | symbol is attached | subjected.

The multiprocessor system of the second embodiment has the same configuration as that of the first embodiment.
In the second embodiment, a case will be described in which data transfer is performed in a stream from one processor to the other processor.

  On the shared memory SM, a communication area CBUF01 between PU1-0 and PU1-1 is arranged, and exclusive control variable areas SEM_EMPTY01 and SEM_READY01 for exclusive control related to the communication area CBUF01 are arranged. Yes. The exclusive control variable area SEM_EMPTY01 is a count semaphore that represents the number of empty transfer data areas, and the exclusive control variable area SEM_READY01 is a count semaphore that represents the number of transfer data areas to which data has been written. Performs exclusive control of CBUF01. The exclusive control variable area SEM_EMPTY01 is initialized with an initial value m, and the exclusive control variable area SEM_READY01 is initialized with an initial value 0.

  In the exclusive control variable area SEM_EMPTY01, for example, a PU1-0 data read callback routine and a PU1-1 data write callback routine are stored. In the exclusive control variable area SEM_READY01, for example, a PU1-0 data write callback routine and a PU1-1 data read callback routine are stored.

  Similar to the first embodiment, the copy area LBUF0 of the communication area CBUF01 is arranged on the local memory LM of the PU1-0, and the copy area LBUF1 of the communication area CBUF01 is also arranged on the local memory LM of the PU1-1. ing. The copy areas LBUF0 and LBUF1 are used as buffer areas for the communication area CBUF01 on the PU1-0 and PU1-1, respectively. The correspondence between the communication area CBUF01 and the copy areas LBUF0 and LBUF1 is PU1-0. , Managed by PU1-1.

FIG. 5 is a diagram showing the configuration of the communication area CBUF01 in FIG.
The communication area CBUF01 includes m transfer data areas 2b-0 to 2b- (m-1). Each transfer data area 2b-0 to 2b- (m-1) is accompanied by an area in which the written data sizes 2a-0 to 2a- (m-1) are written. It is assumed that the data sizes 2a-0 to 2a- (m-1) are initialized with an initial value 0 by the PU1-0 or PU1-1. Further, the communication area CBUF01 includes a head number headbufno at the beginning of the transfer data area 2b in use and a next number tailbufno at the end in order to manage the transfer data area 2b in use.

  These are for managing m transfer data areas 2b-0 to 2b- (m-1) of the communication area CBUF01 as the ring buffer 2B, and the number headbufno is the head of the ring buffer 2B in use. The number of the transfer data area 2b and the number tailbufno hold the next number of the transfer data area at the end of the ring buffer 2B in use. Both are initialized with an initial value of 0.

(Inter-processor communication method of embodiment 2)
6A, 6B, and 6C are diagrams illustrating a processing procedure in the inter-processor communication method according to the second embodiment of this invention. FIG. 6A shows a processing procedure in which, for example, a user program on the PU 1-0 repeatedly transmits data to the PU 1-1 and the PU 1-1 receives the data. FIG. 6B and FIG. 6C show processing procedures such as the routine in FIG.

  As in the first embodiment, the basic synchronous operation (wait_sem, sig_sem) is assumed to start a data read callback routine and a data write callback routine defined by the user. In the exclusive control variable areas SEM_EMPTY01 and SEM_READY01, it is assumed that a data read callback routine and a data write callback routine activated by a synchronous basic operation (wait_sem, sig_sem) are associated with each PU.

  In the inter-processor communication method shown in FIG. 6A, for example, when the user program on the PU 1-0 repeatedly transmits data to the PU 1-1 and the user program on the PU 1-1 receives the data, the following ( A) Processing is performed in accordance with step S10 and (B) step S11.

(A) PU0: Communication program processing (step S10)
First, in order to transmit data from PU1-0 to PU1-1, a user transmission program on PU1-0 is activated. The transmission program on the PU 1-0 first uses the exclusive control variable area SEM_EMPTY01 on the shared memory SM to acquire the free transfer data area of the communication area CBUF01 arranged on the shared memory SM. A resource acquisition wait system call wait_sem is called to try to acquire the free transfer data area 2b of the communication area CBUF01.

  The OS resource acquisition wait system call wait_sem refers to the exclusive control variable SEM_EMPTY01 on the shared memory SM to determine whether the free transfer data area 2b of the communication area CBUF01 can be acquired. Transition. If the free transfer data area 2b of the communication area CBUF01 can be acquired, the data read callback routine of the PU 1-0 associated with the exclusive control variable SEM_EMPTY01 on the shared memory SM is activated.

  The PU1-0 data read callback routine copies the data in the transfer data area 2b specified by the number tailbufno in the communication area CBUF01 to the copy area LBUF0 by the data size written in the transfer data area 2b. To do. Since the data size 2a is initialized to 0, no copy is actually performed, only the data size 2a is read into the copy area LBUF0, and the data read callback routine ends.

  When the data read callback routine ends, the OS resource acquisition wait system call wait_sem returns control to the caller.

  After returning from the OS resource acquisition wait system call wait_sem and acquiring the free transfer data area 2b of the communication area CBUF01, the transmission program writes the transfer data and the data size 2a to the copy area LBUF0. The transfer data and the data size 2a may be written in a plurality of times.

After the data writing is completed, the OS resource release system call sig_sem is called using the exclusive control variable area SEM_READY01 on the shared memory SM to notify the fact.
The OS resource release system call sig_sem activates the data write callback routine of the PU 1-0 associated with the exclusive control variable area SEM_READY01 before actually making a data preparation notification.

  The data write callback routine of PU1-0 transfers the data in the copy area LBUF0 from the copy area LBUF0 by the number tailbufno in the communication area CBUF01 by the data size written in the copy area LBUF0. Copy to area. The data size 2a is also copied. Copying is performed by starting program transfer or DMA. When copying is completed, the value of the number tailbufno is incremented (incremented by +1) so as to indicate a new area. If the value of the number tailbufno exceeds (m−1) so as to constitute the ring buffer 2B, the value is set to zero. When the update of the value of the number tailbufno is completed, the data write callback routine ends.

  When the data write callback routine is completed, the OS resource release system call sig_sem notifies the data source completion in the exclusive control variable area SEM_READY01 and returns control to the caller.

  Next, the transmission program interrupts PU1-1 to PU1-1 and notifies PU1-1 that data has been prepared.

  The transmission program repeats the above processing until transmission of all data is completed.

(B) PU1: Receive program processing (step S11)
When the PU 1-1 receives an interrupt or wants to receive data, the PU 1-1 starts a user reception program. First, the reception program on the PU 1-1 uses the exclusive control variable area SEM_READY01 on the shared memory SM in order to check whether data is prepared in the communication area CBUF01 arranged on the shared memory SM. Use the OS resource acquisition wait system call wait_sem.

  The OS resource acquisition wait system call wait_sem refers to the exclusive control variable area SEM_READY01 on the shared memory SM to determine whether data is prepared in the communication area CBUF01, and waits if data is not prepared. Transition to the state. If the data has been prepared, the data read callback routine of the PU 1-1 associated with the exclusive control variable area SEM_READY01 on the shared memory SM is activated.

  The data read callback routine of the PU 1-1 copies the data in the transfer data area specified by the number headbufno in the communication area CBUF01 to the copy area LBUF1 by the data size written in the transfer data area. . The data size 2a is also copied. Copying is performed by starting program transfer or DMA. When copying is complete, the data read callback routine ends.

  When the data read callback routine ends, the OS resource acquisition wait system call wait_sem returns control to the caller.

  If the return from the OS resource acquisition wait system call wait_sem confirms that the received data is prepared, the receiving program reads the transfer data from the copy area LBUF1 for the data size. The transfer data may be read in a plurality of times. When the reading is completed, the data size 2a is updated to 0.

  When the data reading is completed, the OS resource release system call sig_sem is called using the exclusive control variable area SEM_EMPTY01 on the shared memory SM in order to release the used transfer data area 2b in the communication area CBUF01.

  The OS resource release system call sig_sem starts the data write callback routine of the PU 1-1 before releasing the used transfer data area 2b.

  The data write callback routine of the PU 1-1 copies the data in the copy area LBUF1 by the data size written in the copy area LBUF1 to the transfer data area 2b specified by the number headbufno. Since the data size 2a has been updated to 0, no copy is actually performed, and only the data size 2a is written in the transfer data area 2b specified by the number headbufno. Thereafter, the value of the number headbufno is incremented so as to indicate the next data storage area. If the value of the number headbufno exceeds (m-1) so as to constitute the ring buffer 2B, the value is set to 0. When the update of the value of the number headbufno is completed, the data write callback routine ends.

  When the data write callback routine ends, the OS resource release system call sig_sem notifies the release of the transfer data area in the communication area CBUF01 and returns control to the caller.

  Next, the reception program interrupts PU1-1 to PU1-0 and notifies PU1-0 of reception completion.

The reception program repeats the above processing until all data is received.
The interrupt between PU1-0 and PU1-1 is used to notify the process that has been put into a wait state by the OS resource acquisition wait system call wait_sem that the wait state can be released.

(Effect of Example 2)
According to the second embodiment, there are the same effects as the effects (a) and (b) of the first embodiment, and further, there are the following effects (e) and (f).

  (E) With regard to shared memory access, even when using a processor core IP with cache that does not provide a mechanism for maintaining data consistency of the cache memory, with a simple hardware configuration without changing the processor core IP, Stream data transfer between processors using the shared memory SM can be performed quickly and efficiently.

  (F) By performing block transfer with the shared memory SM or data transfer by DMA at the timing of the synchronous basic operation (wait_sem, sig_sem), the part that actually transfers data to the shared memory SM from the user program is separated And the complexity of the entire program can be reduced.

  In addition, this invention is not limited to the said Example 1, 2, A various deformation | transformation and utilization form are possible. For example, there are the following modifications (I) and (II) as modifications and usage forms.

  (I) In the first and second embodiments, two typical inter-processor communication has been described. However, the communication processing procedure can be changed to a procedure other than that shown in the drawing, and further, between other processors other than the two inter-processor communication. It can also be applied to communication.

  (II) Inter-processor communication between two PUs has been described using an example, but the present invention can also be applied to a case where communication is performed with three or more units.

It is a block diagram which shows the structural example of the multiprocessor system which implement | achieves the communication method between processors which concerns on Example 1 of this invention. It is a figure which shows the structure of communication area | region CBUF01 in FIG. It is a figure which shows the process sequence in the communication method between processors of Example 1 of this invention. It is a figure which shows the process sequence in the communication method between processors of Example 1 of this invention. It is a block diagram which shows the structural example of the multiprocessor system which implement | achieves the communication method between processors which concerns on Example 2 of this invention. FIG. 5 is a diagram showing a configuration of a communication area CBUF01 in FIG. It is a figure which shows the process sequence in the communication method between processors of Example 2 of this invention. It is a figure which shows the process sequence in the communication method between processors of Example 2 of this invention. It is a figure which shows the process sequence in the communication method between processors of Example 2 of this invention.

Explanation of symbols

1-0 to 1-n PU (processing unit)
1a processor 1b cache memory 2a data size 2b transfer data area 3 shared bus
LM local memory
SM shared memory

Claims (3)

A multiprocessor system inter-processor communication method in which a plurality of processors each having a local memory and a shared memory for inter-processor communication are connected by a shared bus,
When transferring data from one of the plurality of processors to another processor, performing data transfer between the local memory and the shared memory in the acquisition-system synchronization basic operation and the release-system synchronization basic operation. A feature of the inter-processor communication method. A plurality of processors each having a local memory and a shared memory for inter-processor communication having a communication data area are connected by a shared bus, and each of the processors has or does not have a cache memory. A multiprocessor system inter-processor communication method that does not have a mechanism for maintaining data consistency,
Associating a communication data area of the shared memory with a transfer source local memory of a transmission processor for transmitting data of the plurality of processors and a transfer destination local memory of a reception processor for receiving data; Having an exclusive control variable for exclusive control of the communication data area of the shared memory;
When the transmission processor transmits data, the shared data is written from the transfer source local memory to the transfer source local memory at the timing when the release synchronous basic operation is performed on the communication data area of the associated shared memory. Perform batch transfer to memory,
When the receiving processor receives data, at the timing when the acquisition synchronization basic operation is performed on the communication data area of the shared memory prior to reading the data, the transfer is collectively transferred from the shared memory to the transfer destination local memory. And inter-processor communication method, wherein data is read from the transfer destination local memory.   3. The inter-processor communication method according to claim 2, wherein a block transfer instruction or direct memory access of the processor is used as a method of transferring data collectively between the local memory and the shared memory.

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