JP2007274224A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor which reduces the access time to a memory and suitably distributes the accesses to process images speedily in a little circuit scale. <P>SOLUTION: A first memory 11 stores macroblock information of already processed macroblocks, a second memory 12 is a simple port memory including acquiring memory areas 12a and saving memory areas 12b, a transfer request decider 13c outputs a saving memory area transfer request A for transferring the macroblock information to the saving memory area 12b and a hold memory fetch transfer request B for transferring the macroblock information in the acquiring memory area 12a to a hold memory 13a, a memory transfer controller 14 outputs a first memory transfer request C for transferring the macroblock information from the saving memory area 12b to a first memory 11 and a second memory transfer request D for transferring the macroblock information from the first memory 11 to the acquiring memory area 12a, an a memory access mediator 15 for controlling the mediation of the port access to the second memory 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that encodes / decodes an image signal in units of macroblocks.

  In recent years, image encoding / decoding systems have been applied to PVRs (Personal Video Recorders), camcorders, etc., and the market for these digital home appliances continues to expand. In order to realize a high-resolution and low-cost product required by the market, it is indispensable to use hardware such as LSI and FPGA (Field Programmable Gate Array), but the encoding / decoding of moving images is enormous. Since a processing amount is required and power consumption is increased, circuit scale reduction and appropriate signal control are required so that power consumption can be reduced.

  On the other hand, in the image coding method, since the amount of information is generally compressed using spatial correlation, the coding is performed by referring to the macroblock information of an already coded macroblock adjacent to the macroblock to be coded. Many methods are used. Examples of the macroblock information include a coding mode, a motion vector value in inter prediction, and the number of effective coefficients after DCT (Discrete Cosine Transform).

  The amount of macroblock information increases in proportion to the screen size. In particular, in a device with a large screen such as a high-definition television, keep the macroblock information only with a high-speed memory such as SRAM (Static Random Access Memory). Then, the circuit scale increases. Therefore, in general, macroblock information is generally held by using a large-capacity DRAM (Dynamic RAM) together with a slower speed than an SRAM.

  FIG. 14 is a diagram showing a schematic configuration of an image processing apparatus including a DRAM and an SRAM. The image processing apparatus 100 includes an encoding / decoding circuit 101, DP (dual port) -SRAMs 102a and 102b, a transfer circuit 103, and a DRAM 104. The DP-SRAMs 102a and 102b are SRAMs that have dual ports and can independently perform writing and reading.

  The encoding / decoding circuit 101 outputs the macroblock information obtained as a result of the processing to the DP-SRAM 102a every time the macroblock is encoded or decoded. Further, the macroblock information of the processed macroblock is extracted from the DP-SRAM 102b as necessary, and used for the encoding / decoding processing of the macroblock.

  The transfer circuit 103 transfers the macro block information to the DP-SRAM 102a so that the DP-SRAM 102a does not overflow and the adjacent macro block information necessary for the encoding / decoding process is always present in the DP-SRAM 102b. From the DRAM 104 to the DP-SRAM 102b in the FIFO (First-In / First-Out) format as appropriate.

  As described above, as the memory peripheral configuration of the image processing apparatus 100, a low-speed memory such as the DRAM 104 is used as the main memory, and only the interface portion with the encoding / decoding circuit 101 is used for latency (delay time) concealment. A general configuration is to use high-speed memories such as SRAMs 102a and 102b.

As a conventional technique for reducing the memory capacity of image processing, it is possible to divide one macroblock into four sub-blocks and process it, without using a shared memory system capable of multiple random access. A technique for performing parallel processing has also been proposed (for example, Patent Document 1).
JP-A-8-9389 (paragraph numbers [0010] to [0020], FIG. 1)

  In the configuration of the conventional image processing apparatus 100 shown in FIG. 14, two dual-port SRAMs are used to prioritize the processing speed. However, in order to reduce power consumption, the number of SRAMs is reduced. It is desirable to adopt a single port SRAM.

  At this time, if one single-port SRAM is used to configure a device that realizes the same operation as in FIG. 14, the device configuration that controls arbitration by time division of access to one port of the SRAM is as follows. Conceivable.

  FIG. 15 is a diagram showing a configuration using a single port SRAM. The image processing apparatus 110 includes an encoding / decoding circuit 111, an SRAM 112, a transfer circuit 113, a DRAM 114, and an arbitration circuit 115.

  The arbitration circuit 115 arbitrates four accesses to the SRAM 112. The four accesses are the write access from the encoding / decoding circuit 111 to the SRAM 112, the read access from the SRAM 112 to the encoding / decoding circuit 111, the write access from the DRAM 114 to the SRAM 112 via the transfer circuit 113, and the transfer. Read access from the SRAM 112 to the DRAM 114 via the circuit 113. The arbitration circuit 115 performs arbitration control for these accesses so that one port of the SRAM 112 is used by the encoding / decoding circuit 111 and the transfer circuit 113 in a time division manner.

  On the other hand, when realizing real-time processing, the processing time per macroblock is limited by the screen size and the frame rate. H. In H.264, the size of a macroblock is 16 × 16 pixels, and in full high-definition (1080 pixels), only about 2 μs can be used for processing of one macroblock.

  Therefore, as shown in FIG. 15, by simply changing to a configuration that performs access arbitration by time division using a single-port SRAM, arbitration waiting time when access conflicts frequently occurs. Compared to the 4-port independent memory configuration shown in FIG. 14, there is a problem that the processing time is increased by the arbitration waiting time.

  In addition, the encoding / decoding circuit 111 also varies in processing time depending on the processing content due to a difference in compression rate for each macroblock. As shown in FIG. 15, in the configuration in which a port is used by time division processing, the encoding / decoding circuit 111 is used if the transfer circuit 113 is using the port even if the encoding / decoding processing is completed in a very short time. Have to wait for the port to be free. This idle waiting time of the port causes an increase in the entire processing time as it is.

  The present invention has been made in view of these points, and reduces the access time to the memory, and performs appropriate access distribution to the high-speed memory or the low-speed memory, so that a high-speed image can be obtained with a small circuit scale. An object of the present invention is to provide an image processing apparatus that performs processing.

  In the present invention, in order to solve the above-described problem, a first memory for storing macroblock information of a processed macroblock in an image processing apparatus 10 for encoding / decoding an image signal as shown in FIG. 11, an acquisition memory area 12 a for storing macroblock information transferred from the first memory 11, and macroblock information to be transferred to the first memory 11 and stored in the first memory 11 A single-port second memory 12 having a memory area divided into two by a save memory area 12b, a holding memory 13a for storing macroblock information, and reading macroblock information from the holding memory 13a Referring to the processing target macroblock encoding / decoding process, the macroblock information obtained after the processing is completed is stored in memory 1 an encoding / decoding processing unit 13b stored in a, and a save memory area for transferring macroblock information in the holding memory 13a to the save memory area 12b when the encoding / decoding process is completed Transfer request determination that outputs a transfer request A and outputs a holding memory fetch transfer request B for transferring the macroblock information in the acquisition memory area 12a to the holding memory 13a when encoding / decoding processing is started. An image processing unit 13 comprising: a unit 13c; and a macroblock information transfer unit 13d that controls transfer of macroblock information if there is a permission response to the save memory area transfer request A or the retained memory capture transfer request B. The occupancy of the first memory 11 is monitored, and if there is an empty space in the first memory 11, the first memory 11 is saved from the save memory area 12b. When the first memory transfer request C for transferring the macroblock information is output and the macroblock information is stored in the first memory 11, the macro is transferred from the first memory 11 to the acquisition memory area 12a. Memory transfer control that outputs a memory area transfer request D for transferring block information and performs transfer control of macroblock information if there is a permission response to the first memory transfer request C or the memory area transfer request D for acquisition Unit 14 and the save memory area transfer request A, the holding memory fetch transfer request B, the first memory transfer request C, and the acquisition memory area transfer request D are received, and if the transfer is possible, a permission response is output. When the arbitration control of the port access of the second memory 12 is performed and the arbitration control is performed, the save memory area transfer request A from the image processing unit 13 and the holding memory acquisition are performed. The first memory transfer request C and the acquisition memory area from the memory transfer control unit 14 so as to prevent the overflow / underflow of the save memory area 12b and the acquisition memory area 12a. There is provided an image processing apparatus 10 including a memory access arbitration unit 15 that gives priority to the transfer request D next.

  Here, the first memory 11 stores macroblock information of processed macroblocks. The second memory 12 stores the acquisition memory area 12a for storing the macroblock information transferred from the first memory 11, and the macroblock information to be transferred to the first memory 11 for storage. This is a single port memory in which the memory area is divided by the save memory area 12b. The holding memory 13a stores macroblock information. The encoding / decoding processing unit 13b reads out and refers to the macroblock information from the holding memory 13a, performs encoding / decoding processing of the processing target macroblock, and stores the macroblock information after the processing is completed in the holding memory 13a. To store. When the encoding / decoding process is completed, the transfer request determination unit 13c outputs a save memory area transfer request A for transferring the macroblock information in the holding memory 13a to the save memory area 12b. When the encoding / decoding process is started, a holding memory capture transfer request B for transferring the macroblock information in the acquisition memory area 12a to the holding memory 13a is output. If there is a permission response to the save memory area transfer request A or the retained memory fetch transfer request B, the macroblock information transfer unit 13d performs macroblock information transfer control. The memory transfer control unit 14 monitors the occupation amount of the first memory 11, and transfers macroblock information from the save memory area 12 b to the first memory 11 if the first memory 11 is free. When the first memory transfer request C is output and the macro block information is stored in the first memory 11, the macro block information is transferred from the first memory 11 to the acquisition memory area 12a. If the memory area transfer request D is output and there is an authorization response to the first memory transfer request C or the acquisition memory area transfer request D, transfer control of the macroblock information is performed. The memory access arbitration unit 15 receives the save memory area transfer request A, the holding memory capture transfer request B, the first memory transfer request C, and the acquisition memory area transfer request D, and if it can be transferred, sends a permission response. Output, perform arbitration control of port access to the second memory 12, and when performing arbitration control, give priority to the save memory area transfer request A and the hold memory capture transfer request B from the image processing unit 13, The first memory transfer request C and the acquisition memory area transfer request D from the memory transfer control unit 14 are prioritized next so as not to cause overflow / underflow of the save memory area 12b and the acquisition memory area 12a.

  An image processing apparatus according to the present invention includes a first memory, a single-port second memory in which a memory area is divided into two parts by an acquisition memory area and a save memory area, and a holding memory. Save memory area transfer request to transfer macroblock information from the holding memory to the save memory area, hold memory capture transfer request to transfer macroblock information in the acquisition memory area to the hold memory, save memory area Generating a first memory transfer request for transferring the macroblock information from the first memory to the first memory, and an acquisition memory area transfer request for transferring the macroblock information from the first memory to the acquisition memory area, The evacuation memory area transfer request and the retention memory fetch transfer request are given top priority, and the first memory transfer request and acquisition memory area transfer request are given priority next. It was configured to perform the arbitration control Te. Thereby, it is possible to reduce the access time to the memory and perform high-speed image processing with a small circuit scale by performing appropriate access distribution to the high-speed memory or the low-speed memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a principle diagram of an image processing apparatus. The image processing apparatus 10 according to the first embodiment includes a first memory 11, a second memory 12, an image processing unit 13, a memory transfer control unit 14, and a memory access arbitration unit 15.

  The image processing apparatus 10 is compatible with MPEG4, H.264. When performing image encoding / decoding processing such as H.264 in hardware in real time, encoding is performed by referring to macroblock information of a macroblock that has already been encoded / decoded adjacent to the macroblock to be processed. / A device that performs a decoding process.

  The macroblock information includes, for example, an encoding mode, a motion vector value at the time of Inter prediction, the number of effective coefficients after DCT, and the like, and information on an encoding process result when an image signal is encoded in units of macroblocks. Or the decoding process result information when the image signal is decoded in units of macroblocks. This macroblock information is used as reference information for a processing target macroblock to be encoded / decoded next. It is used.

  The first memory 11 corresponds to a DRAM that is a low-speed memory, and stores macroblock information of a macroblock that has been processed (encoded / decoded). Hereinafter, the first memory 11 is referred to as a DRAM 11.

  The second memory 12 corresponds to an SRAM, which is a high-speed memory, and temporarily stores an acquisition memory area 12a for storing macroblock information transferred from the DRAM 11 and macroblock information to be transferred to the DRAM 11 for storage. This is a single port memory in which the memory area is divided by the save memory area 12b. Hereinafter, the second memory 12 is referred to as an SRAM 12.

  The image processing unit 13 includes a holding memory 13a (hereinafter, the holding memory is referred to as holding FF), an encoding / decoding processing unit 13b, a transfer request determination unit 13c, and a macroblock information transfer unit 13d. The holding FF 13a is a memory that temporarily stores macroblock information.

  The encoding / decoding processing unit 13b reads and refers to the macroblock information from the holding FF 13a, performs encoding / decoding processing of the macroblock to be processed, and stores the macroblock information after the processing is completed in the holding FF 13a. To do.

  When the encoding / decoding process is completed, the transfer request determination unit 13c outputs a save memory area transfer request A for transferring the macroblock information in the holding FF 13a to the save memory area 12b.

  When the encoding / decoding process is started, a holding FF fetch transfer request B for transferring and fetching macroblock information in the acquisition memory area 12a to the holding FF 13a is output.

  The macroblock information transfer unit 13d transfers the macroblock information in the holding FF 13a to the saving memory area 12b based on the permission response by the saving memory area transfer request A or the holding FF fetch transfer request B, or obtains the acquisition memory area. The macro block information in 12a is transferred to the holding FF 13a.

  The memory transfer control unit 14 monitors the occupation amount of the DRAM 11, and if there is an empty space in the DRAM 11, a first memory transfer request C (hereinafter referred to as DRAM) for transferring macroblock information from the save memory area 12 b to the DRAM 11. (Referred to as transfer request C). When macroblock information is stored in the DRAM 11, an acquisition memory area transfer request D for transferring macroblock information from the DRAM 11 to the acquisition memory area 12a is output. Further, if there is a permission response to the DRAM transfer request C or the acquisition memory area transfer request D, transfer control of the macroblock information is performed.

  The memory access arbitration unit 15 receives the save memory area transfer request A, the holding FF fetch transfer request B, the first memory transfer request C, and the acquisition memory area transfer request D, and sends a permission response if transfer is possible. Output and perform arbitration control of port access to the SRAM 12. In this case, the save memory area transfer request A and the holding FF fetch transfer request B from the image processing unit 13 are given top priority, and an overflow / underflow of the save memory area 12b and the acquisition memory area 12a is not generated. Arbitration control is performed by prioritizing the DRAM transfer request C and the acquisition memory area transfer request D from the memory transfer control unit 14 next.

  Here, a memory storing process related to which macroblock information of a macroblock to be stored in the memory for the macroblock to be processed will be described. FIG. 2 is a diagram illustrating adjacent macroblocks when macroblock information is acquired. During the encoding process, the macroblocks in the screen are processed in the raster order (in the direction of the dotted arrow in the figure). If the current macroblock to be processed is the macroblock MB0, the encoded neighboring areas around the macroblock MB0 are encoded. There are four macro blocks, macro blocks MBr1 to MBr4, which are located on the upper left of the macro block MB0, on the upper left of the line, on the upper right of the line, on the upper right of the line, and on the left of the same line.

  Therefore, when encoding macroblock MB0, the encoding information from each of these macroblocks MBr1-MBr4 is used. In this case, the macroblock information from the macroblock MBr3 onward to the macroblock located in front of the macroblock MBr4 (the macroblock group g1 indicated by the dotted frame in the figure) is the macroblock information processed after the macroblock MB0. Therefore, the macroblock information of the macroblock group g1 needs to be held at the time of processing the macroblock MB0 because it is used for future processing. That is, together with the macro block information of the macro blocks MBr1 to MBr4 referenced at the present time, the macro block information of each macro block indicated by the dotted frame in the figure is also held in the memory.

  After the processing of the macro block MB0, the macro block MB1 is the next processing target, and at this time, the macro block information of the macro blocks MBr2, MBr3, MBr5, and MB0 is referred to.

  An example of the flow of macroblock information in the image processing apparatus 10 will be described with reference to FIG. 2. When the encoding / decoding processing unit 13b starts the encoding / decoding processing of the macroblock MB0, the holding FF 13a However, the macroblock information of the macroblocks MBr1 to MBr4 is held.

  Assuming that the holding FF 13a holds the respective macroblock information of the macroblocks MBr1 to MBr4, after the processing of the macroblock MB0 is completed, the macroblock information of the macroblock MB0 is stored in the holding FF 13a. Further, the macroblock information of the macroblock MBr4 is transferred to the save memory area 12b (when there is a permission response of the save memory area transfer request A), and then transferred to the DRAM 11 and stored therein. Further, in preparation for processing of the next macro block MB1, the macro block information of the macro block MBr5 is transferred from the acquisition memory area 12a to the holding FF 13a (when there is a permission response of the holding FF fetch transfer request B). (In addition to the macro block information of the macro block MBr5, more macro block information in the macro block group g1 may be transferred to the holding FF 13a). The flow of macroblock information between memories and details of memory arbitration will be described later with reference to FIGS.

  Next, the configuration and operation of the image processing apparatus 10 according to the first embodiment will be described in detail. FIG. 3 is a diagram illustrating the configuration of the image processing apparatus 10. The image processing apparatus 10 according to the first embodiment includes a DRAM 11, an SRAM 12, an image processing unit 13, a DRAM transfer control unit 14 (corresponding to the memory transfer control unit 14 in FIG. 1), and a memory access arbitration unit 15. The access arbitration unit 15 is a device that determines port access priority of the SRAM 12.

  The description of the components described above with reference to FIG. In addition, each of the save memory area transfer request A, the holding FF fetch transfer request B, the DRAM transfer request C, and the acquisition memory area transfer request D is hereinafter also simply referred to as transfer requests A, B, C, and D.

  The image processing unit 13 includes a holding FF 13a, an encoding / decoding processing unit 13b, a transfer request determining unit 13c, and transfer circuits 13d-1 and 13d-2. The transfer circuits 13d-1 and 13d-2 are included in the macroblock information transfer unit 13d in FIG.

  When the transfer request determination unit 13c receives the permission response of the save memory area transfer request A transmitted from the memory access arbitration unit 15, the transfer request determination unit 13c gives a transfer instruction to the transfer circuit 13d-1. Based on the transfer instruction, the transfer circuit 13d-1 transfers the macroblock information on the holding FF 13a to the save memory area 12b of the SRAM 12, and the SRAM 12 stores the macroblock information in the save memory area 12b. .

  When the transfer request determination unit 13c receives the permission response of the retained FF fetch transfer request B transmitted from the memory access arbitration unit 15, the transfer request determination unit 13c gives a transfer instruction to the transfer circuit 13d-2. Based on the transfer instruction, the transfer circuit 13d-2 reads the macroblock information stored in the acquisition memory area 12a of the SRAM 12 and transfers it to the holding FF 13a. The holding FF 13a stores the macroblock information.

  The DRAM transfer control unit 14 includes a transfer request determination unit 14a, an occupation amount monitoring circuit 14b, and transfer circuits 14c-1 and 14c-2. The occupation amount monitoring circuit 14b monitors the memory occupation amount of the DRAM 11 and transmits the monitoring result to the transfer request determination unit 14a. As described above with reference to FIG. 1, the transfer request determination unit 14a transmits the DRAM transfer request C or the acquisition memory area transfer request D based on the state of the occupation amount.

  When the transfer request determination unit 14a receives the permission response of the DRAM transfer request C transmitted from the memory access arbitration unit 15, the transfer request determination unit 14a gives a transfer instruction to the transfer circuit 14c-2. Based on the transfer instruction, the transfer circuit 14c-2 reads the macroblock information stored in the save memory area 12b of the SRAM 12 and transfers it to the DRAM 11 (save memory area in the DRAM 11). Stores block information.

  When the transfer request determination unit 14a receives the permission response of the acquisition memory area transfer request D transmitted from the memory access arbitration unit 15, the transfer request determination unit 14a gives a transfer instruction to the transfer circuit 14c-1. The transfer circuit 14c-1 transfers the macroblock information on the DRAM 11 to the acquisition memory area 12a of the SRAM 12 based on the transfer instruction, and the SRAM 12 stores the macroblock information in the acquisition memory area 12a.

  The memory access arbitration unit 15 includes an arbitration control unit 15a and occupation amount monitoring circuits 15b-1 and 15c-1. The occupancy monitoring circuit 15b-1 monitors the memory occupancy of the save memory area 12b and outputs an occupancy notification b1 as a monitoring result. The occupancy monitoring circuit 15c-1 outputs the occupancy monitoring circuit 15c-1 of the acquisition memory area 12a. The memory occupation amount is monitored, and an occupation amount notification c1 as a monitoring result is output.

  When the arbitration control unit 15a recognizes from the occupation amount notification b1 that the save memory area 12b is free and receives the save memory area transfer request A, the arbitration control unit 15a receives a permission response to the save memory area transfer request A. Is transmitted to the image processing unit 13.

  Further, when it is recognized from the occupation amount notification c1 that the macro block information is stored in the acquisition memory area 12a and the holding FF fetch transfer request B is received, an authorization response to the hold FF fetch transfer request B is sent. The image is transmitted to the image processing unit 13.

  Further, the arbitration control unit 15a recognizes that the macroblock information is stored in the save memory area 12b from the occupation amount notification b1 and receives the DRAM transfer request C, permits the DRAM transfer request C. The response is transmitted to the DRAM transfer control unit 14.

  Furthermore, when it is recognized from the occupation amount notification c1 that the acquisition memory area 12a is empty and the acquisition memory area transfer request D is received, an authorization response to the acquisition memory area transfer request D is transferred to the DRAM. It transmits to the control part 14.

  The arbitration control unit 15a basically performs round robin processing (processing by circulating access requests) for the above four access requests. However, if there is a request from the image processing unit 13, this is processed. Arbitration control is performed with the highest priority given to processing access requests so that overflow / underflow does not occur in each of the acquisition memory area 12a and the save memory area 12b. .

  Next, a specific arbitration operation of the image processing apparatus 10 according to the first embodiment will be described using a time chart. FIG. 4 is a time chart showing the arbitration operation of the image processing apparatus 10. As an example of the operation of the image processing apparatus 10, a case where the encoding / decoding process is short is shown in a time chart. The negation of the request signal is not caused by asserting the response signal, but is a protocol negated upon completion of the transfer process.

  In order to make the state of each cycle shown in FIG. 4 easy to understand, FIGS. 5 to 7 show state transition diagrams showing the state of each cycle (in practice, via the memory access arbitration unit 15 and the DRAM transfer control unit 14). Mediation control is performed, but is omitted in the figure). The solid line arrows in FIGS. 5 to 7 indicate that the macroblock information flows when the transfer requests A to D are permitted, and the dotted line arrows indicate the assertion states (only asserted) of the transfer requests A to D. Macro block information is not flowing).

[CYC1]
(Initial state) The encoding / decoding processing unit 13b is immediately after the encoding / decoding processing of one macroblock is completed. The macro block information of the processing result is on the holding FF 13a, and in order to save it, the transfer request A (holding FF 13a → saving memory area 12b) is asserted to the arbitration control unit 15a. In this state, it is assumed that the save memory area 12b is empty and the acquisition memory area 12a is full. Since the DRAM transfer control unit 14 is in a state where neither saving nor acquisition is required, no transfer request is issued.

  (Development) The arbitration control unit 15a receives the transfer request A and permits the transfer. The encoding / decoding processing unit 13b transfers the macroblock information from the holding FF 13a to the save memory area 12b. Upon completion of transfer, transfer request A is negated.

[CYC2]
(Initial state) The encoding / decoding processing unit 13b asserts a transfer request B (acquisition memory area 12a → holding FF 13a) to the arbitration control unit 15a in order to perform encoding / decoding processing of the next macroblock. The save memory area 12b is not empty due to the transfer by CYC1. The DRAM transfer control unit 14 asserts a transfer request C (saving memory area 12b → DRAM 11) to save the macroblock information in the saving memory area 12b in the DRAM 11 (the saving area on the DRAM 11 is not full). Suppose).

  (Development) The arbitration control unit 15a receives the transfer request B having a high priority and permits the transfer. The encoding / decoding processing unit 13b performs transfer from the acquisition memory area 12a to the holding FF 13a. Upon completion of transfer, transfer request B is negated.

[CYC3]
(Initial state) The encoding / decoding processing unit 13b performs encoding / decoding processing using the macroblock information transferred from the acquisition memory area 12a in CYC2. Since processing is in progress, no transfer request is generated. Further, the transfer request C from the DRAM transfer control unit 14 remains asserted. In addition, since the acquisition memory area 12a is not full due to the transfer from the acquisition memory area 12a to the holding FF 13a in the CYC2, a transfer request for taking in new macroblock information on the DRAM 11 in the empty area D (DRAM 11 → acquisition memory area 12a) is asserted (assuming that the save memory area on the DRAM 11 is not empty).

  (Development) The arbitration control unit 15a receives the transfer request C by round robin and permits the transfer. Accordingly, the DRAM transfer control unit 14 performs transfer from the save memory area 12b to the DRAM 11.

[CYC4]
(Initial state) The encoding / decoding processing unit 13b completes the encoding / decoding processing of one macroblock, and asserts the transfer request A (holding FF 13a → saving memory area 12b). The transfer from the save memory area 12b to the DRAM 11 by the DRAM transfer control unit 14 continues from CYC3. Transfer requests C and D remain asserted.

  (Development) Since the transfer from the save memory area 12b from the CYC 3 to the DRAM 11 continues, the arbitration control unit 15a transfers the transfer request A (holding FF 13a → the save memory area 12b) and transfer request D (DRAM 11 → acquisition). The memory area 12a) is left unattended. Upon completion of transfer, transfer request C is negated.

[CYC5]
(Initial state) The encoding / decoding processing unit 13b continues to assert the transfer request A, and the DRAM transfer control unit 14 continues to assert the transfer request D. Since the save memory area 12b is emptied by the transfer of CYC3 and CYC4, the transfer request C is not generated.

  (Development) The arbitration control unit 15a receives the transfer request A having a high priority and permits the transfer. The encoding / decoding processing unit 13b performs transfer from the holding FF 13a to the save memory area 12b. Upon completion of transfer, transfer request A is negated.

[CYC6]
(Initial state) The encoding / decoding processor 13b asserts the transfer request B in order to perform encoding / decoding processing of the next macroblock. The DRAM transfer control unit 14 continues to assert the transfer request D. In addition, the save memory area 12b is not empty due to the transfer in CYC5, and the transfer request C is asserted for saving the DRAM 11 of the macroblock information stored in the save memory area 12b.

  (Development) The arbitration control unit 15a receives the transfer request B having a high priority and permits the transfer. The encoding / decoding processing unit 13b performs transfer from the acquisition memory area 12a to the holding FF 13a. Upon completion of transfer, transfer request B is negated.

[CYC7]
(Initial state) The encoding / decoding processing unit 13b performs encoding / decoding processing using the macroblock information transferred from the acquisition memory area 12a to the holding FF 13a in CYC6. Since processing is in progress, no transfer request is generated. The DRAM transfer control unit 14 continues to assert transfer requests C and D.

  (Development) The arbitration control unit 15a receives the transfer request D by round robin and permits the transfer. The DRAM transfer control unit 14 performs transfer from the DRAM 11 to the acquisition memory area 12a.

[CYC8]
(Initial state) The encoding / decoding processor 13b completes the encoding / decoding processing of one macroblock and asserts the transfer request A. Transfer from the DRAM 11 to the acquisition memory area 12a by the DRAM transfer control unit 14 continues from CYC7. Transfer requests C and D remain asserted.

(Development) Since the transfer from the CYC 7 continues, the arbitration control unit 15a leaves both the transfer requests A and C unattended. Upon completion of the transfer, the transfer request D is negated.
[CYC9]
(Initial state) The encoding / decoding processing unit 13b continues to assert the transfer request A. The DRAM transfer control unit 14 continues to assert the transfer request C. In addition, only the empty space in the acquisition memory area 12a generated in CYC2 is transferred in CYC7 and 8 (transfer from the DRAM 11 to the acquisition memory area 12a), and the empty space (acquisition for acquisition) in CYC6. The transfer request D for taking in the macroblock information on the new DRAM 11 is reasserted in the empty space on the acquisition memory area 12a created when the memory area 12a is transferred to the holding FF 13a.

  (Development) The arbitration control unit 15a receives the transfer request A having a high priority and permits the transfer. The encoding / decoding processing unit 13b performs transfer from the holding FF 13a to the save memory area 12b. Upon completion of transfer, transfer request A is negated.

[CYC10]
(Initial state) The encoding / decoding processor 13b asserts the transfer request B in order to perform encoding / decoding processing of the next macroblock. The DRAM transfer control unit 14 continues to assert transfer requests C and D.

  (Development) The arbitration control unit 15a receives the transfer request B having a high priority and permits the transfer. The encoding / decoding processing unit 13b performs transfer from the acquisition memory area 12a to the holding FF 13a. Upon completion of transfer, transfer request B is negated.

  As a result of the above control, the macroblock processing time of the encoding / decoding processing unit 13b is a certain length, and is the same as the sum of the time required for saving to the DRAM 11 and the time required for acquisition from the DRAM 11 If so, the most stable state in which transfer between the SRAM 12 and the DRAM 11 is performed during the macroblock processing period.

  On the other hand, if the macroblock processing time of the encoding / decoding processing unit 13b is extremely short, the macroblock processing period is not changed unless the save memory area 12b and the acquisition memory area 12a on the SRAM 12 fail. The transfer between the SRAM 12 and the DRAM 11 is only allowed to be saved or acquired.

  As described above, according to the configuration of the first embodiment, the macroblock information output from the encoding / decoding processing unit 13b is written to the holding FF 13a as appropriate during the macroblock processing period. When all of them are confirmed, writing to the SRAM 12 is performed. Also, the macroblock information used by the encoding / decoding processing unit 13b is collectively read from the SRAM 12 into the holding FF 13a before the macroblock processing starts, and the encoding / decoding processing unit 13b performs the macroblock processing period. The processing is performed by appropriately referring to the value on the holding FF 13a. With this configuration, it is possible to shorten the access time to the port of the SRAM 12 from the encoding / decoding processing unit 13b side.

  Next, an image processing apparatus according to a second embodiment will be described. In the second embodiment, port access to the SRAM is performed while exchanging port usage rights between the image processing unit and the DRAM transfer control unit.

  FIG. 8 is a principle diagram of the image processing apparatus. The image processing apparatus 20 includes a DRAM (first memory) 21, an SRAM (second memory) 22, an image processing unit 23, and a memory transfer control unit 24.

  The DRAM 21 stores macroblock information of a macroblock that has been processed (encoded / decoded). The SRAM 22 includes an acquisition memory area 22 a for storing macroblock information transferred from the DRAM 21 and a save memory area 22 b for storing macroblock information to be transferred to the DRAM 21 and stored in the DRAM 21. This is a single-port memory in which the area is divided into two.

  The image processing unit 23 includes a holding FF (holding memory) 23a, an encoding / decoding processing unit 23b, an image processing side port usage right management unit 23c, and an image processing side macroblock information transfer unit 23d.

  The holding FF 23a is a memory that temporarily stores macroblock information. The encoding / decoding processor 23b reads out and refers to the macroblock information from the holding FF 23a, and performs encoding / decoding processing of the macroblock to be processed. Further, the macro block information obtained after the processing is completed is stored in the holding FF 23a.

  The image processing side macroblock information transfer unit 23d is given a memory side port usage right transfer notification B (when the image processing side port usage right management unit 23c receives the memory side port usage right transfer notification B), When the processing unit 23 has a right to use the port that can access the SRAM 22, and when the encoding / decoding processing of the encoding / decoding processing unit 23b is completed, the macroblock information in the holding FF 23a is When the data is transferred to the save memory area 22b and the encoding / decoding processor 23b starts the encoding / decoding process, the macroblock information in the acquisition memory area 22a is transferred to the holding FF 23a.

  The image processing side port usage right management unit 23c transfers the port usage right to the other party (memory transfer control unit 24) when the transfer of the macroblock information from the acquisition memory area 22a to the holding FF 23a is completed. A port usage right transfer notice A is output. When the encoding / decoding process is completed, if the port usage right is not on the image processing unit 23 side, a port usage right request notification C for forcibly requesting the port usage right is output.

  The memory transfer control unit 24 includes a memory side port usage right management unit 24a and a memory side macroblock information transfer unit 24c. The memory-side macroblock information transfer unit 24c receives the image processing-side port usage right transfer notification A (when the memory-side port usage right management unit 24a receives the image processing-side port usage right transfer notification A) and transfers the memory. When the control unit 24 has the right to use the port, the macro block information is transferred from the save memory area 22b to the DRAM 21, and the macro block information is transferred from the DRAM 21 to the acquisition memory area 22a.

  The memory-side port usage right management unit 24a sends a memory-side port usage right transfer notification B when the transfer of macroblock information from the DRAM 21 to the acquisition memory area 22a is completed or when a port usage right request notification C is received. Output the port usage right to the image processing unit 23.

  FIG. 9 is a diagram showing the configuration of the image processing apparatus 20. In addition, description of the same component as the component mentioned above in FIG. 8 is abbreviate | omitted. Further, the image processing side port usage right transfer notification A, the memory side port usage right transfer notification B, and the port usage right request notification C are also simply referred to as transfer notification A, transfer notification B, and request notification C, respectively.

  The image processing unit 23 includes a holding FF 23a, an encoding / decoding processing unit 23b, a usage right management unit 23c (corresponding to the image processing side port usage right management unit 23c in FIG. 8), and transfer circuits 23d-1 and 23d-2. Including. The transfer circuits 23d-1 and 23d-2 are included in the image processing side macroblock information transfer unit 23d in FIG.

  When the usage right management unit 23c receives the memory side port usage right transfer notification B, the usage right management unit 23c acquires the port usage right. At this time, when the encoding / decoding process of the encoding / decoding processing unit 23b is completed, a transfer instruction is given to the transfer circuit 23d-1. Based on the transfer instruction, the transfer circuit 23d-1 transfers the macroblock information on the holding FF 23a to the save memory area 22b of the SRAM 22, and the SRAM 22 stores the macroblock information in the save memory area 22b. .

  When the encoding / decoding processing unit 23b starts the encoding / decoding process, a transfer instruction is given to the transfer circuit 23d-2. Based on the transfer instruction, the transfer circuit 23d-2 reads the macroblock information stored in the acquisition memory area 22a of the SRAM 22 and transfers it to the holding FF 23a. The holding FF 23a stores the macroblock information.

  On the other hand, the DRAM transfer control unit 24 (corresponding to the memory transfer control unit 24 in FIG. 8) includes a usage right management unit 24a-1, a transfer determination unit 24a-2, transfer circuits 24c-1 and 24c-2, and an occupation amount monitoring circuit. 24b-1 to 24b-3. The usage right management unit 24a-1 and the transfer determination unit 24a-2 are included in the memory side port usage right management unit 24a of FIG. 8, and the transfer circuits 24c-1 and 24c-2 are memory side macroblock information of FIG. It is included in the transfer unit 24c.

  The occupation amount monitoring circuit 24b-1 monitors the memory occupation amount of the DRAM 21, and transmits the monitoring result b1 to the transfer determination unit 24a-2. The occupation amount monitoring circuit 24b-2 monitors the memory occupation amount of the acquisition memory area 22a, and transmits the monitoring result b2 to the transfer determination unit 24a-2. The occupation amount monitoring circuit 24b-3 monitors the memory occupation amount of the save memory area 22b and transmits the monitoring result b3 to the transfer determination unit 24a-2.

  When the usage right management unit 24a-1 receives the image processing side port usage right transfer notification A, the usage right management unit 24a-1 notifies the transfer determination unit 24a-2 that the port usage right has been acquired. At this time, if the transfer determination unit 24a-2 recognizes that there is macroblock information in the DRAM 21 from the monitoring result b1 and that the acquisition memory area 22a is free from the monitoring result b2, the transfer determination unit 24a-2 issues a transfer instruction to the transfer circuit 24c. -1. The transfer circuit 24c-1 transfers the macroblock information on the DRAM 21 to the acquisition memory area 22a of the SRAM 22 based on the transfer instruction, and the SRAM 22 stores the macroblock information in the acquisition memory area 22a. .

  When the transfer determination unit 24a-2 recognizes that the DRAM 21 is vacant from the monitoring result b1 and the macroblock information exists in the save memory area 22b from the monitoring result b3, the transfer determination unit 24a-2 issues a transfer instruction to the transfer circuit 24c- 2 to send. The transfer circuit 24c-2 transfers the macroblock information on the save memory area 22b to the DRAM 21 based on the transfer instruction, and the DRAM 21 stores the macroblock information.

  Here, the right to use the port of the SRAM 22 is alternately transferred between the image processing unit 23 and the DRAM transfer control unit 24, but the DRAM transfer control unit 24 transfers the macroblock information between the SRAM 22 and the DRAM 21. Whether or not to do so depends on the memory storage states of the DRAM 21, the acquisition memory area 22a, and the save memory area 22b monitored by the occupation amount monitoring circuits 24b-1 to 24b-3.

  The image processing unit 23 performs “capture of adjacent macroblock information in the acquisition memory area 22a into the holding FF 23a (only when there is an adjacent macroblock)” before starting the macroblock processing, and starts the macroblock processing. To do. When the transfer of the macroblock information from the acquisition memory area 22a to the holding FF 23a is completed (similar to the start of the macroblock processing), the image processing side port usage right transfer notice A is output, and the port usage right is controlled by DRAM transfer control. Pass to part 24.

  After that, the image processing unit 23 waits for the port usage right to return from the DRAM transfer control unit 24 (waits for the memory-side port usage right transfer notification B to be transmitted) and obtains the port usage right. , “Writes the current macroblock information on the holding FF 23a when the macroblock processing is completed to the save memory area 22b”.

  On the other hand, when the DRAM transfer control unit 24 obtains the port usage right, if there is an appropriate amount of macroblock information in the save memory area 22b and the DRAM 21 has a free space, the "transfer memory area 22b to the DRAM 21" Transfer ". Subsequently, if the DRAM 21 is not empty and the acquisition memory area 22a is empty, "transfer from the DRAM 21 to the acquisition memory area 22a" is performed.

  After these operations, the memory side port usage right transfer notice B is output, and the port usage right is transferred to the image processing unit 23. As an exception, if the macroblock encoding / decoding process is completed in the image processing unit 23 before the memory side port usage right transfer notice B is output, the image processing unit 23 Request notification C is output.

  In this case, when the transfer from the SRAM 22 to the DRAM 21 by the DRAM transfer control unit 24 is completed, if the macro block information necessary for the next macro block processing exists in the acquisition memory area 22a, the image is displayed. In order to cancel the processing waiting state of the encoding / decoding processing unit 23b in the processing unit 23, the DRAM transfer control unit 24 outputs a memory-side port usage right transfer notification B without performing transfer from the DRAM 21 to the SRAM 22. Then, the port usage right is transferred to the image processing unit 23.

  Here, an example of the flow of macroblock information in the image processing apparatus 20 will be described with reference to FIG. 2. When the encoding / decoding processing unit 23b starts the encoding / decoding processing of the macroblock MB0, the holding FF 23a Holds at least the macroblock information of each of the macroblocks MBr1 to MBr4.

  Assuming that the holding FF 23a holds the macroblock information of the macroblocks MBr1 to MBr4, after the processing of the macroblock MB0 is completed, the macroblock information of the macroblock MB0 is stored in the holding FF 23a. Further, the macroblock information of the macroblock MBr4 is transferred to the save memory area 22b (when there is a port use right), and then transferred to the DRAM 21 and stored therein. Further, in preparation for processing of the next macroblock MB1, the macroblock information of the macroblock MBr5 is transferred from the acquisition memory area 22a to the holding FF 23a (when there is a right to use the port) and is stored ( Not only the macroblock information of the macroblock MBr5 but also more macroblock information in the macroblock group g1 may be transferred to the holding FF 23a). The flow of macroblock information between memories and details of memory arbitration will be described later with reference to FIGS.

  Next, the operation of the image processing apparatus 20 according to the second embodiment will be described using a time chart. FIG. 10 is a time chart showing the arbitration operation of the image processing apparatus 20. In order to make the state of each cycle shown in FIG. 10 easy to understand, FIGS. 11 to 13 show state transition diagrams showing the state of each cycle (actually, arbitration control is performed via the DRAM transfer control unit 24). (Omitted in the figure). A solid line arrow represents the flow of macroblock information, a dotted line arrow represents transfer notification A or transfer notification B, and a thick line arrow in FIG.

[CYC1]
(Port usage right) Image processing unit 23
(Development) The image processing unit 23 is immediately after the encoding / decoding processing of one macroblock is completed. The macro block information as a result of the processing is on the holding FF 23a, and transfer is performed from the holding FF 23a to the saving memory area 22b in order to save it.

[CYC2]
(Port usage right) Image processing unit 23
(Development) The image processing unit 23 performs transfer from the acquisition memory area 22a to the holding FF 23a in order to perform encoding / decoding processing of the next macroblock. When the transfer is completed, the image processing side port usage right transfer notice A is asserted.

[CYC3]
(Port usage right) DRAM transfer control unit 24
(Development) Since the saving memory area 22b is no longer empty by the transfer in CYC1, the DRAM transfer control unit 24 performs the transfer from the saving memory area 22b to the DRAM 21 (when the saving area on the DRAM 21 is full). Assuming no situation).

[CYC4]
(Port usage right) DRAM transfer control unit 24
(Development) Since the acquisition memory area 22a is not full due to the transfer in CYC2, the DRAM transfer control unit 24 performs transfer from the DRAM 21 to the acquisition memory area 22a (if the save area on the DRAM 21 is empty) Assuming no situation). When the transfer is completed, the memory side port right transfer notice B is asserted.

[CYC5]
(Port usage right) Image processing unit 23
(Development) The image processing unit 23 is in a state of performing macroblock encoding / decoding processing, and nothing is transferred.

[CYC6]
(Port usage right) Image processing unit 23
(Development) The image processing unit 23 completes the encoding / decoding processing of one macroblock, and transfers the data from the holding FF 23a to the save memory area 22b.

[CYC7]
(Port usage right) Image processing unit 23
(Development) The image processing unit 23 performs transfer from the acquisition memory area 22a to the holding FF 23a in order to perform encoding / decoding processing of the next macroblock. When the transfer is completed, the image processing side port usage right transfer notice A is asserted.

[CYC8]
(Port usage right) DRAM transfer control unit 24
(Development) Since the saving memory area 22b is not empty in the transfer in CYC6, the DRAM transfer control unit 24 transfers the saving memory area 22b to the DRAM 21. On the way, the encoding / decoding process for one macroblock of the image processing unit 23 is completed, and the port usage right request notification C is asserted. The DRAM transfer control unit 24 determines whether the remaining data amount in the acquisition memory region 22a is necessary for the next macroblock process when the transfer from the save memory region 22b to the DRAM 21 is completed. If it is determined that the necessary amount exists, the memory-side port usage right transfer notification B is asserted without executing the transfer regardless of whether the transfer from the DRAM 21 to the acquisition memory area 22a is possible.

[CYC9]
(Port usage right) Image processing unit 23
(Development) The image processing unit 23 completes the encoding / decoding processing of one macroblock, and transfers the data from the holding FF 23a to the save memory area 22b.

[CYC10]
(Port usage right) Image processing unit 23
(Development) The image processing unit 23 performs transfer from the acquisition memory area 22a to the holding FF 13a in order to perform encoding / decoding processing of the next macroblock. When the transfer is completed, the port use right transfer notice A is asserted.

  As described above, in the second embodiment, when the encoding / decoding process is completed in a very short time, writing from the SRAM 22 to the DRAM 21 and reading from the DRAM 21 to the SRAM 22 are not essential. The access between the encoding / decoding processing side and the SRAM 22 is prioritized over the access between the DRAM 21 and the SRAM 22. Accordingly, the next macroblock process can be started without waiting for the encoding / decoding process, and an unnecessary increase in the processing time can be suppressed.

  In the above, mainly H.264 is used. The encoding / decoding process has been described as being performed in units of 16 × 16 pixel macroblocks defined in H.264. However, as can be understood from the technical contents of the present invention, the block size is not particularly limited. You may perform an encoding / decoding process by arbitrary block units, such as a pixel x M pixel. In addition, the macroblock information transfer control performed between the DRAM, SRAM, and holding memory in the first and second embodiments described above is an overflow / underflow as a necessary amount in the encoding / decoding process. Therefore, an appropriate amount of macroblock information is transferred between the memories.

1 is a principle diagram of an image processing apparatus. It is a figure which shows the adjacent macroblock at the time of acquiring macroblock information. It is a figure which shows the structure of an image processing apparatus. It is a time chart which shows mediation operation | movement of an image processing apparatus. It is a figure which shows a state transition. It is a figure which shows a state transition. It is a figure which shows a state transition. 1 is a principle diagram of an image processing apparatus. It is a figure which shows the structure of an image processing apparatus. It is a time chart which shows mediation operation | movement of an image processing apparatus. It is a figure which shows a state transition. It is a figure which shows a state transition. It is a figure which shows a state transition. It is a figure which shows schematic structure of the image processing apparatus containing DRAM and SRAM. It is a figure which shows the structure using a single port SRAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Image processing apparatus 11 1st memory 12 2nd memory 12a Acquisition memory area 12b Evacuation memory area 13 Image processing part 13a Holding memory 13b Encoding / decoding processing part 13c Transfer request determination part 13d Macroblock information transfer part 14 Memory Transfer Control Unit 15 Memory Access Arbitration Unit A Save Memory Area Transfer Request B Holding Memory Capture Transfer Request C First Memory Transfer Request D Acquisition Memory Area Transfer Request

Claims (5)

In an image processing apparatus for encoding / decoding an image signal,
A first memory for storing macroblock information of processed macroblocks;
An acquisition memory area for storing the macroblock information transferred from the first memory; and the macroblock information to be transferred to the first memory and stored in the first memory. A second memory of a single port in which the memory area is divided into two by a save memory area to be stored;
A holding memory for temporarily storing the macroblock information; and reading and referring to the macroblock information from the holding memory to perform encoding / decoding processing of the macroblock to be processed, and the macro obtained after the processing is completed An encoding / decoding processor that stores block information in the holding memory, and when the encoding / decoding process is completed, transfers the macroblock information in the holding memory to the save memory area. A storage memory fetch transfer request for transferring the macroblock information in the acquisition memory area to the holding memory when the encoding / decoding process is started. A transfer request determination unit that outputs a permission response to the save memory area transfer request or the retained memory capture transfer request. In a constructed image processing unit from, and the macro block information transfer unit for transferring control of the macro block information,
A first memory transfer for monitoring the occupation amount of the first memory and transferring the macroblock information from the save memory area to the first memory if the first memory is available Output a request, and if the macroblock information is stored in the first memory, an acquisition memory area transfer request for transferring the macroblock information from the first memory to the acquisition memory area Output, if there is a permission response to the first memory transfer request or the acquisition memory area transfer request, a memory transfer control unit that performs transfer control of the macroblock information;
Receiving the save memory area transfer request, the holding memory fetch transfer request, the first memory transfer request, and the acquisition memory area transfer request, and outputting the permission response if transfer is possible, When performing arbitration control of the port access of the memory 2 and performing the arbitration control, the save memory area transfer request and the hold memory fetch transfer request from the image processing unit are given top priority, and the save memory area And a memory access arbitration unit that prioritizes the first memory transfer request and the acquisition memory region transfer request from the memory transfer control unit so as not to cause an overflow / underflow of the acquisition memory region,
An image processing apparatus comprising:   The holding memory stores at least macroblock information of macroblocks adjacent to the macroblock adjacent to the upper left of the line, the upper right of the line, the upper right of the line, and the left of the same line at the start of processing of the macroblock, After the processing of the macro block is completed, the holding memory further stores macro block information of the macro block, and the macro block information transfer unit, if there is a permission response to the save memory area transfer request, If macro block information of a macro block adjacent to the left side of the same line is transferred to the save memory area and there is a permission response to the hold memory fetch transfer request, at least the 1 Macro block for the macro block located to the right of the macro block at the top right of the line Tsu the click information, the image processing apparatus according to claim 1, wherein the forwarding to the holding memory is read from the acquisition memory area. In an image processing apparatus for encoding / decoding an image signal,
A first memory for storing macroblock information of processed macroblocks;
An acquisition memory area for storing the macroblock information transferred from the first memory; and the macroblock information to be transferred to the first memory and stored in the first memory. A second memory of a single port in which the memory area is divided into two by a save memory area to be stored;
A holding memory for storing the macroblock information, and the macroblock information obtained by reading and referring to the macroblock information from the holding memory, performing encoding / decoding processing of the macroblock to be processed, and completing the processing An encoding / decoding processing unit for storing information in the holding memory, and a port usage right accessible to the second memory in response to a memory side port usage right transfer notification, wherein the encoding is performed When the decoding / decoding process is completed, the macroblock information in the holding memory is transferred to the save memory area, and when the encoding / decoding process is started, the acquisition memory area An image processing-side macroblock information transfer unit that transfers the macroblock information in the storage memory to the storage memory from the acquisition memory area An image processing side port usage right management unit that outputs an image processing side port usage right transfer notice for transferring the port usage right to the other party upon completion of transfer of the macroblock information; ,
In the case of receiving the port usage right transfer notification upon receipt of the image processing side port usage right transfer notification, the macro block information is transferred from the save memory area to the first memory, and the first memory is transferred. A memory-side macroblock information transfer unit for transferring the macroblock information from the first memory to the acquisition memory area, and when the transfer of the macroblock information from the first memory to the acquisition memory area is completed, the memory-side port A memory transfer control unit configured to output a usage right transfer notification and transfer the port usage right to the image processing unit;
An image processing apparatus comprising:   The holding memory stores at least macroblock information of macroblocks adjacent to the macroblock adjacent to the upper left of the line, the upper right of the line, the upper right of the line, and the left of the same line at the start of processing of the macroblock, After the processing of the macro block is completed, the holding memory further stores macro block information of the macro block, and the image processing side macro block information transfer unit, if there is the port use right, If macroblock information of a macroblock adjacent to the side is transferred to the save memory area and if the port use right is given, at least the right side of the macroblock on the upper right of the one line is prepared for the next macroblock processing. Macro block information related to the macro block located at The image processing apparatus according to claim 3, wherein the forwarding to the serial holding memory.   The port right management unit on the image processing side outputs a port use right request notification for forcibly requesting the port use right when the encoding / decoding process is completed and the port use right is not present. When the memory side port usage right management unit receives the port usage right request notification, the memory side port usage right management unit outputs the memory side port usage right transfer notification if the macroblock information is stored in the acquisition memory area. The image processing apparatus according to claim 3, wherein the port use right is transferred to the image processing unit.

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