JP2007266871A - Clock data recovery control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock data recovery control circuit capable of more simply applying control of a frequency comparison operation and a phase comparison operation to even a high speed serial interface and including a frequency detection circuit for accurately detecting a frequency. <P>SOLUTION: The clock data recovery control circuit includes: a switching control means for switching between a frequency control system and a phase control system for a prescribed period; and the frequency detection circuit for detecting that received serial data are within an operating range of a clock data recovery circuit when the phase control system is in operation, and the frequency detection circuit a first counter operated on clock extracted from the received data and a second counter operated on the basis of a PLL clock when the phase control system is in operation, and detects the frequency by discriminating whether a count of the first counter is within a prescribed window width of a count of the second counter when the phase control system is in operation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock data recovery control circuit that performs frequency detection of received serial data.

  Conventionally, a parallel interface such as ATA or PCI has been used as an interface in a bus between a host and a device or an internal bus between chipsets. However, in recent years, instead of these, high-speed serial interfaces such as Serial-ATA and PCI-Express that are less likely to cause problems such as signal interference and noise mixing have become mainstream. In addition, speeding up to achieve higher transfer speeds is progressing.

  In Serial-ATA, a hard disk drive (hereinafter referred to as HDD) having a transfer rate of 1.5 Gbps called a first generation and an HDD having a transfer rate of 3 Gbps called a second generation are mixed in the market. In addition, the next generation (third generation) HDD with a transfer rate of 6 Gbps (although the connector shape may be different) is also listed on the roadmap.

  By the way, since it is necessary to maintain upward compatibility as an interface, the host must be able to connect to any generation of devices at a transfer rate corresponding to the host.

  Further, serial interface communication is not performed using data and a clock as in parallel interface communication, but communication is performed using only a differential serial signal. In serial interface communication, data and a clock are embedded in this serial signal, so it is necessary to extract data and a clock from received serial data.

  In general, in high-speed serial interface communication, data and a clock are extracted from received serial data by a clock data recovery circuit (hereinafter referred to as CDR). In an interface such as Serial-ATA that determines the transfer rate from the received data rate at the time of negotiation, the transfer rate (frequency) of each generation is detected, and the transfer rate of the generation that the host and the device support. It is necessary to establish communication.

  In an interface that determines the transfer rate from the received data rate at the time of negotiation, such as Serial-ATA, data is input at a frequency outside the capture range of the PLL, particularly in a CDR with a PLL (Phase Locked Loop) configuration. In such a case, the host must determine that the input data is outside the allowable operation range, and stop the operation to follow the input data.

In the CDR disclosed in Patent Document 1, a PLL circuit is used as means for extracting a clock, a first lock detector that detects that the clock is locked to a reference clock, and a second that detects an unlocked state with respect to data. The detector is provided and the control loop is switched. The delay in the phase lock detector, called the second detector, becomes more critical between the flip-flops when the input frequency increases or when the process varies greatly, making it difficult to control . Also, if the input data rate is an integral multiple of the reference clock, the data is received with a recovered clock that is asynchronous with the data, so depending on the timing, it may or may not be regarded as a phase lock error, and the accuracy is high. Does not become a phase lock detection circuit. Furthermore, when this circuit is applied to the Serial-ATA, it is only necessary to operate in a sequence for detecting the generation of the host and the device, and it is not always necessary to operate.
JP 11-317729 A

  Therefore, in view of the above points, the present invention makes the control of the frequency comparison operation and the phase comparison operation easier and unnecessary even in a clock data recovery control circuit using a PLL circuit even with a high-speed serial interface. The purpose is to install a frequency detection circuit that can be stopped at any time.

The present invention has been made to achieve the above object. The clock data recovery control circuit according to claim 1 according to the present invention includes:
A clock data recovery control circuit for controlling the clock data recovery circuit,
The clock data recovery circuit
A frequency control system that controls the frequency of the clock output from the voltage or current controlled oscillator following the reference clock, and a phase control system that controls the phase of the clock output from the voltage or current oscillator following the received serial data And extracting data and clock from serial data received using an interface that communicates using a serial signal,
The clock data recovery control circuit
Switching control means for switching the frequency control system and the phase control system at a constant cycle;
A frequency detection circuit that detects that the received serial data is within the operating range of the clock data recovery circuit when the phase control system is operating;
The frequency detection circuit includes a first counter that operates based on a clock extracted from received data and a second counter that operates based on a PLL clock when the phase control system operates.
When the phase control system is operating, it is determined whether the counter value of the first counter is within a predetermined window width of the counter value of the second counter, and frequency detection is performed. It is characterized by performing.

The clock data recovery control circuit according to claim 2 according to the present invention includes:
2. The clock data recovery control circuit according to claim 1, wherein the first counter starts counting after being delayed from the second counter when the phase control system is operating. .

The clock data recovery control circuit according to claim 3 according to the present invention includes:
The frequency detection circuit determines whether the counter value of the first counter is within a predetermined window of the counter value of the second counter when the plurality of successive phase control systems operate. 3. The clock data recovery control circuit according to claim 1, wherein frequency detection is performed.

The clock data recovery control circuit according to claim 4 according to the present invention includes:
The clock data recovery control circuit according to any one of claims 1 to 3, wherein the frequency detection circuit includes a comparison unit that sets the window width.

  By utilizing the present invention, a clock data recovery control circuit that more easily controls frequency comparison operation and phase comparison operation even for a high-speed serial interface, and a frequency detection circuit that accurately performs frequency detection. A clock data recovery control circuit can be provided.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings.

  Serial-ATA is taken up as a high-speed serial interface that determines the transfer rate from the received data rate at the time of negotiation. This example of a high speed serial interface is not intended to limit the present invention.

  FIG. 1 is a schematic diagram of the structure of the Serial-ATA interface. The Serial-ATA interface has a hierarchical structure of an application layer (12, 20), a transport layer (10, 18), a link layer (8, 16), and a physical layer (PHY) (6, 14). The application layer 12 communicates with the transport layer 10 through a register interface equivalent to a parallel ATA host adapter. The transport layer 10 and the link layer 8 are core submodules that control the overall operation. The physical layer 6 is a layer that defines the physical connection / transmission method and electrical characteristics of the network, and transmits and receives high-speed serial signals. In particular, in the physical layer 6, a negotiation operation called OOB (Out of Band) is performed in order to establish communication with the connection destination.

  FIG. 2 is a configuration diagram of the physical layer 6 in the general host controller 2. First, the transmission side will be described below. Parallel data (DATAIN) sent from the link layer 8 is serialized by the serializer (SER) 22 and output by the driver 24 as differential (TX +, TX−). Here, the FPS 32 is a fixed pattern source, and is controlled by a control block (Control Block) 32.

  Next, the receiving side will be described below. Differential signals are input from RX + and RX− and serialized by the receiver 38. On the other hand, the squelch receiver 40 detects the voltage level of the differential signal. If the voltage exceeds a certain threshold, the squelch receiver 40 considers that data has been detected and outputs a squelch signal to the control block 32. The signal serialized by the receiver 38 is input to the CDR 42, and data and clock are extracted. One of the extracted data is parallelized by a deserializer (DES) 44 and output to the link layer 8, and the other is detected by a control character by an FPD (fixed pattern detector) 46. The control character is a leading byte of a primitive composed of 4 bytes, and the primitive is a Dword (Double Word) entity for controlling a serial line and providing a status.

  The control block 32 mainly performs control related to transmission / reception of the physical layer 6 in a state machine configuration.

  SYSCLK 48 indicates a reference clock of the PLL 50. PHYRESET 52 is a reset signal for the physical layer 6. PHYREADY 54 is a signal indicating communication. SLUMBER 56 and PARTIAL 58 are signals for shifting to the low power consumption state. RXCLOCK 60 is a received signal. TXCLOCK 62 is a transmission signal. Further, COMMA 64 is a control character detection signal output to the link layer 8. Interface signals with other link layers are omitted. The one-dot broken line indicates the reception clock system, and the two-dot broken line indicates the transmission clock system.

  FIG. 3 is a schematic diagram for explaining the OOB sequence. OOB is a negotiation operation between a host and a device, in which ALIGN primitive burst transfer is performed from a host or a device at a constant idle (common mode level) interval to perform negotiation. Here, the ALIGN primitive is a primitive used for initialization and synchronization with received data, and is a primitive having a K28.5 control character in the first byte.

  First, the physical layer 6 enters a bus idle state (neutral) when the power is turned on, and the host 2 issues a COMRESET. Next, when the device 4 detects COMRESET, it issues COMINIT. When the host 2 detects COMINIT from the device 4, it issues COMWAKE. The device 4 detects the COMWAKE and then transmits the COMWAKE, and then continuously transmits the ALIGN primitive continuously. If there is no response from the host 2 until the device 4 transmits 54.6 μs ALIGN, the speed is reduced and the retry is made. If there is no response even at the slowest speed, an error state occurs.

  Further, after issuing COMWAKE, the host 2 transmits a D10.2 data character, the host 2 locks the received ALIGN, and continuously transmits ALIGN at the same speed. After the device 4 detects this ALIGN, it transmits a Non-ALIGN primitive, and when the host 2 detects this, it notifies PHYREADY = H to the link layer 8 and establishes communication.

  The host 2 and the device 4 are OOB controlled by a state machine. Until the communication is established, the host 2 has state transitions HP1 to HP8, and the device 4 has state transitions DP1 to DP7.

Table 1 below shows the state transition of the host 2 until the communication is established.

The state transition of the device 4 until the communication is established is shown in Table 2 below.

  Incidentally, the state transition shown in FIG. 3 is a case where the transfer rate corresponding to the host 2 and the device 4 is the same, or the transfer rate corresponding to the device 4 is lower than that of the host 2. On the other hand, the state transition shown in FIG. 4 is a case where the transfer rate supported by the device 4 is higher than the transfer rate supported by the host 2. For example, the host 2 corresponds to only the first generation transfer rate, and the device 4 is a second generation HDD. In such a case, as shown in FIG. 4, after the device 4 transmits COMWAKE, the device 4 transmits ALIGN to the host 2 at 3 Gbps at 54.6 μs. At this time, however, the host 2 supports only the first generation. The 3 Gbps ALIGN must be set not to respond.

  The device 4 transmits ALIGN for 54.6 μs, then transitions from DP6 to DP10, decreases speed, transitions to DP6 again, and transmits ALIGN at a reduced transfer rate (in this case, 1.5 Gbps). The DP 10 here is a state (state) called a “DR_Reduce Speed state”, and is a state in which the interface is suspended and the speed is reduced by one generation.

  When the device 4 is compatible with the second generation and the host 2 is compatible with the first generation, in the preferred embodiment of the present invention, as described above, the operation of the device 4 reducing the speed by the DP 10 by one generation. The operation of the CDR 43 and the frequency detection circuit 94 in the physical layer 6 of the host 2 will be described with reference to FIGS. 5, 6, and 7. The frequency detection circuit 94 is a circuit newly set according to the present invention.

  FIG. 5 is a circuit diagram of the CDR 43. FIG. 6 is a partial circuit diagram in the physical layer 6 according to a preferred embodiment of the present invention, and is a circuit diagram mainly showing the CDR 43 and the frequency detection circuit 94. FIG. 7 is a diagram showing the transition of the host state, device state, and various signals when the device 4 operates to reduce the speed by one generation in the preferred embodiment of the present invention.

  First, since the device 4 corresponds to the second generation, as shown in FIG. 7, the device 4 transmits ALIGN to the host 2 at 3 Gbps after COMWAKE transmission for 54.6 μs (device state / DP6). At this time, the host state (state) is HP6.

  Here, the configuration of the CDR 43 in FIG. 5 is shown below.

  In the CDR 43 shown in FIG. 5, FLOCK, SQO, Fr, and serial data InData are input, and CK and restoration data OutData are output. The CDR 43 includes a phase comparator PD, a phase frequency comparator PFD, charge pumps (CP1, CP2), a loop filter LPF, a voltage controlled oscillator VCO, and a divide by two. Here, FLOCK is a signal generated by a FLOCK generation circuit 96 (described later) shown in FIG. 6, and is a signal instructing switching between the frequency comparison operation and the phase comparison operation of the CDR 43. SQO is a signal that becomes L when the squelch receiver 40 detects the voltage level of the serial data as a result of detecting the data, and becomes H when it is detected as idle. Fr is a reference clock, and here has a frequency of 750 MHz. The serial data InData is serial data binarized by the receiver 38. CK is an output clock (output CK).

  In the CDR 43 shown in FIG. 5, first, the FLOCK signal becomes “FLOCK = L” and PDEN = L, and the frequency comparison operation following the reference clock Fr is performed via the phase frequency comparator PFD. When the output CK of the CDR 43 locks to 1.5 GHz (by the action of the 750 MHz reference clock Fr and the frequency divider 2), the CDR 43 once ends the frequency comparison operation. Then, the FLOCK generation circuit 96 in the frequency detection circuit 94 that controls the CDR 43 sets the FLOCK signal to “H”. As a result, the CDR 43 and the frequency detection circuit 94 shift to the phase comparison operation via the phase comparator PD (FIG. 7, F1). The FLOCK generation circuit 96 will be described later.

  When shifting to the phase comparison operation, the CDR 43 operates so as to follow the input data (InData) (which is 3 Gbps), so that the frequency of the output CK of the CDR 43 increases. If the output CK is out of the capture range, an erroneous lock operation occurs at that point. This malfunction is suppressed by the counter enable signal to be described later.

  In order to detect the transfer rate, in the preferred embodiment of the present invention, two counters (counting the output CK of the CDR 43 and the PLL clock during the phase comparison operation (FLOCK = H) in the frequency detection circuit 94 ( RX counter 100 and TX counter 102) are set. These counters operate by being supplied with an enable signal from the counter enable generation circuit 104, and are reset except for the HP6.

  First, immediately after the transition from the frequency comparison operation of the CDR 43 to the phase comparison operation when the transfer rate of 3 Gbps is received, the frequency of the output CK of the CDR 43 is in the vicinity of 1.5 GHz. In order to prevent the RX counter 100 from counting this state, the enable signal of the RX counter 100 is delayed by the first shift register 106 and the first AND circuit 108 (R1 in FIG. 7).

  The operation clocks of the RX and TX counters (100, 102) may be divided by N (N is an integer) to reduce the frequency. Further, the counter enable generation circuit 104, the FLOCK generation circuit 96, and the state machine 112 use the PLL clock 50. These signals may also be divided by M (M is an integer). The counter enable generation circuit generates a counter enable signal at a constant period when HP6 and toggles the counter enable signal at a period in consideration of the accuracy of each counter and the above N and M. In the example of FIG. 7, the toggle is performed at 54.6 μs ÷ 8 = 6.825 μs. The FLOCK generation circuit 96 is a circuit in which FLOCK = H when the counter enable signal is H or when the state (state) is from HP6 to HP8.

  If the counter value of the RX counter 100 at a certain point in time (N1 in FIG. 7) is within a predetermined window of the TX counter 102, it is assumed that a transfer rate of 1.5 Gbps has been received, and the predetermined value If it is outside the window, it is assumed that a transfer rate other than 1.5 Gbps has been received (for example, the device 4 is compatible with the second generation). The window width here is set to a value that takes into account errors for absorbing asynchronous signals, jitter of input data, and the like. Further, in setting the window width, it is necessary to consider the delay provided when the enable signal of the RX counter 100 is generated. In the circuit shown in FIG. 6, the window width is set in the comparison unit 118.

  Now, since the ALIGN having a transfer rate of 3 Gbps is transmitted from the device 4, the count value of the RX counter 100 at a certain point in time (N1, N2, N3, N4) is outside the window of the TX counter 102, The frequency detection circuit 94 determines that “1.5 Gbps is not detected”. In the example illustrated in FIG. 7, the frequency detection operation is performed four times during 54.6 μs in which ALIGN having a transfer rate of 3 Gbps is transmitted from the device 4.

  Device 4 then transmits ALIGN with a transfer rate of 1.5 Gbps for a maximum of 54.6 μs. In F5 of FIG. 7, a phase comparison operation is started at a transfer rate of 1.5 Gbps, the TX counter 102 is enabled at T5, and the RX counter 100 is enabled at R5. Here, it is assumed that the frequency detection circuit 94 confirms that the count value of the RX counter 100 is within the window of the TX counter 102 at N5. Then, the frequency detection circuit 94 detects that the transfer rate is 1.5 Gbps.

  The frequency detection circuit 94 may determine the detection only when the detection is continued a plurality of times. In the example of FIG. 7, the setting is required to detect twice continuously (N5, N6). The number of consecutive times is set by the second shift register 116 shown in FIG.

  Since the ALIGN detection circuit 120 shown in FIG. 6 is always operating on the HP 6, if 1.5 Gbps is detected twice consecutively at N 6, the ALIGN detection result is correct and the ALIGN input to the second AND circuit 122 is correct. Enable the detection signal. Receiving this, the state machine 112 shifts to the next state HP7. Therefore, even when ALIGN is erroneously detected (G1 and G2 in FIG. 7) at the time of receiving ALIGN at a transfer rate of 3 Gbps, the state machine 112 maintains HP6. Here, the ALIGN detection circuit 120 shown in FIG. 6 means the FPD 46 shown in FIG. 6 does not show the DES 44 shown in FIG. Further, FLOCK is fixed to H up to HP8 when transitioning from HP6 to the next state.

  When the host 2 moves to HP7, it sends ALIGN to the device 4 at a transfer rate of 1.5 Gbps, and the device 4 responding to it sends a Non-ALIGN primitive and then moves to DP7 to establish communication (PHYREADY = H). After receiving the Non-ALIGN primitive, the host 2 moves to HP8 and establishes communication (PHYREADY = H).

It is a schematic diagram of the structure of the conventional Serial-ATA interface. It is a block diagram of a physical layer in a general host controller. It is a schematic diagram for demonstrating a general OOB sequence. The state transition shown here is a case where the transfer rate supported by the host and the device is the same, or the transfer rate supported by the device is lower than that of the host. It is a schematic diagram for demonstrating a general OOB sequence. The state transition shown here is when the transfer rate supported by the device is higher than the transfer rate supported by the host. It is a circuit diagram of CDR. It is a partial circuit diagram in the physical layer concerning a preferred embodiment of the present invention, and is a circuit diagram mainly showing a CDR and a frequency detection circuit. In a preferred embodiment of the present invention, it is a diagram showing the transition of the host state, device state, and various signals when the device operates to reduce the speed by one generation.

Explanation of symbols

2 ... Host (controller), 4 ... Device, 6, 14 ... Physical layer, 8, 16 ... Link layer, 38 ... Receiver, 40 ... Squelch receiver, 42, 43 .. CDR (clock data recovery), 50... PLL, 94... Frequency detection circuit, 96... FLOCK generation circuit, 100... RX counter, 102. Enable generation circuit, 112... State machine.

Claims (4)

A clock data recovery control circuit for controlling the clock data recovery circuit,
The clock data recovery circuit
A frequency control system that controls the frequency of the clock output from the voltage or current controlled oscillator following the reference clock, and a phase control system that controls the phase of the clock output from the voltage or current oscillator following the received serial data And extracting data and clock from serial data received using an interface that communicates using a serial signal,
The clock data recovery control circuit
Switching control means for switching the frequency control system and the phase control system at a constant cycle;
A frequency detection circuit that detects that the received serial data is within the operating range of the clock data recovery circuit when the phase control system is operating;
The frequency detection circuit includes a first counter that operates based on a clock extracted from received data and a second counter that operates based on a PLL clock when the phase control system operates.
When the phase control system is operating, it is determined whether the counter value of the first counter is within a predetermined window width of the counter value of the second counter, and frequency detection is performed. A clock data recovery control circuit characterized in that:   2. The clock data recovery control circuit according to claim 1, wherein the first counter starts counting after being delayed from the second counter when the phase control system is operating.   The frequency detection circuit determines whether the counter value of the first counter is within a predetermined window of the counter value of the second counter when the plurality of successive phase control systems operate. The clock data recovery control circuit according to claim 1, wherein frequency detection is performed. The clock data recovery control circuit according to claim 1, wherein the frequency detection circuit includes a comparison unit that sets the window width.

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