JP2007266376A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which controls a threshold voltage of a transistor by controlling a composition at the time of depositing by forming a gate electrode caused by a TaSiN-based film or a TiSiN-based film by a CVD method, and to provide the semiconductor device. <P>SOLUTION: The method of manufacturing the semiconductor device comprises the steps of: supplying hydrogenation silicon as a Si material, one selected from amide compound, imido compound or halide of Ta as a Ta material, titanium tetrachloride as a Ti material, and NH<SB>3</SB>as an N material, respectively; alternately laminating Si deposition film layer of 0.2 to 2.0 nm and TaN or TiN deposition film layer of 0.5 to 3.0 nm; and setting TaSi<SB>x</SB>N<SB>y</SB>or TiSi<SB>x</SB>N<SB>y</SB>film layer (here, x resides in a range of 0.1 to 3.0, y resides in a range of 0.5 to 5.0) to a layer thickness of 1 to 20 nm. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a gate electrode and a semiconductor device manufactured thereby, and more particularly to a method for manufacturing a semiconductor device having a gate electrode capable of controlling a work function.

In the current information society, semiconductor devices used for communication equipment and information equipment are becoming smaller and smaller. For this reason, processing technology for manufacturing semiconductor devices is further developed, and individual semiconductor devices are increasingly miniaturized. At the same time, the transistor structure has been miniaturized, and the thickness of the gate insulating film has reached about several tens of nm. When the gate insulating film is thinned to this extent, the quantum effect becomes obvious, and the leak current increases rapidly due to the tunnel effect. As a result, there arises a problem that the off-current increases and the power consumption increases or the circuit operation stops. In order to suppress such a leakage current, specifically, for example, aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta) having a high dielectric constant is used. High dielectric materials such as ₂ O ₅ ) are mentioned as gate insulating film materials. In order to fully exploit the effects of adopting these high dielectric constant gate insulating films, it is desirable to use metal electrodes instead of the conventional polysilicon electrodes.

  Development of chemically and thermally stable TaN-based and TaSiN-based films has been promoted as materials corresponding to these high dielectric material gate insulating film materials. For example, Non-Patent Document 1 discloses that characteristics required for an n-type MOSFET are matched by combining a TaN or TaSiN film and a high dielectric constant material. Non-Patent Document 2 discloses a method of depositing a TaN or TaSiN film by a CVD method or an ALD method.

  Patent Document 1 discloses a semiconductor device in which a low threshold voltage MISFET is formed using a material having an optimum work function as a metal gate electrode. Further, in Patent Document 2, the work function viewed from the gate insulating film side of the gate electrode is freely and continuously controlled to a value different from the characteristic value of the material of the gate electrode, whereby Vth is continuously increased. An MIS transistor to be controlled is disclosed. Patent Document 3 discloses a stacked metal gate MOSFET in which a common material can be used for the PMOS and NMOS gates, and different work functions can be generated using the same gate metal material, and a manufacturing method thereof. Patent Document 4 discloses a semiconductor device that can suppress the threshold voltage to a low level when a metal film or a film made of a metal compound having a work function that does not deteriorate the adhesion is used as a gate electrode. In Patent Document 5, a method for protecting a gate electrode from a gate insulating film thereunder and a corresponding transistor structure are disclosed.

  However, when these TaSiN films are employed instead of polysilicon, it is necessary to optimize the film composition of the TaSiN films. As can be seen from the example of Non-Patent Document 1, the TaSiN system has a large composition dependency on the threshold voltage, that is, the TaSiN system has a large change in work function depending on the composition. Its composition must be controlled. In general, the film composition of a metal film can be adjusted relatively easily by sputtering, but the CVD method for forming a TaSiN-based film has film forming conditions with good film quality and film forming conditions for depositing a film with a desired composition. It does not always match. In the case of a TaSiN-based film, the composition that provides the optimum threshold voltage strongly depends on the thermal history of the entire process, and the optimum composition often exists in a region where the film becomes very high resistance. Therefore, in order to form a TaSiN-based film by the CVD method, it must be controlled so as to have an optimum composition.

JP 2000-118175 A JP 2003-23152 A JP 2004-221596 A JP 2004-289061 A JP 2005-244186 A Y. Suh, G. Heuss, J. Lee, and V. Misra: “Effect of the Composition on the Electrical Properties of TaSixNy Metal Gate Electrodes”, IEEE Elec. Dev. Lett. 24 (2003) p439. H. Kim: “Atomic layer deposition of metal and nitride thin films: Current research efforts and applications for semiconductor device processing”, J. Vac. Sci. Technol. B21 (2003) p2231.

As described above, the gate electrode of the semiconductor device is desirably formed by a CVD method with little damage to the insulating film. However, it is not easy to freely control the film composition of the gate electrode by the CVD method as described above.
Therefore, the present invention has been made in view of the above problems, and the problem is that a gate electrode is formed by a TaSiN-based or TiSiN-based film by a CVD method, and a desired threshold voltage is controlled by controlling the composition at the time of film formation. The manufacturing method of the semiconductor device which has this.

The features of the present invention, which is a means for solving the above problems, are listed below.
In the method for manufacturing a semiconductor device of the present invention, a Si deposited film is formed when forming a TaSiN-based or TiSiN-based (hereinafter simply referred to as “TaSiN-based”) gate electrode formed on a semiconductor substrate by a CVD method. The layer and the TaN deposited film layer or the TiN deposited film are alternately laminated. In the present invention, in order to control the composition of the TaSiN-based film, in particular, only the source gas, the flow rate ratio, and the like are not controlled as in the prior art. The inventor of the present invention investigated the film composition of the TaSiN-based film with increased resistance and the chemical state of the metal in the film, and in particular, the Si atom in the Si ₃ N ₄ film in which the Si atom in the film is a typical insulating film It was found that the material was nitrided to the same degree. This is a result of a sufficient reaction between N and Si during film formation. This reaction is inevitable as long as a film forming method such as a CVD method is employed. Therefore, in the present invention, the Si raw material is thermally decomposed to deposit an extremely thin Si layer, and the Ta raw material or Ti raw material and the N raw material NH ₃ are reacted to deposit an extremely thin TaN-based or TiN-based film. By alternately performing the adjustment, the ratio of the thicknesses of the respective films was adjusted to form a TaSiN-based film having a desired composition.
In a film deposited by controlling the composition ratio of the source gas as in the prior art, N reacts with Si, and Si is nitrided to the same extent as in a stoichiometric Si ₃ N ₄ film, resulting in an electrical resistance. A big rise. However, in the method for manufacturing a semiconductor device according to the present invention, the deposited TaSiN-based film is different from the conventional case, since Si in the film is not completely nitrided (SiN _x , x <4/3), so that the film resistance is greatly increased. A good electrode can be formed without increasing.

Furthermore, a semiconductor substrate, a gate electrode having a metal film formed on a channel region of the semiconductor substrate via a gate insulating film, and a pair of diffusion regions formed on both sides of the gate electrode on the semiconductor substrate it is a semiconductor device comprising a gate electrode formed by CVD on a semiconductor substrate, a gate electrode, between the TaSi _x N _y, or TiSi _x N _y film layer and the low resistance metal film, TaSi _x N _y or TiSi _x N _y film layer (where x is in the range of 0.1 to 3.0 and y is in the range of 0.5 to 5.0) and TaN _z layer or TiN _z layer (where z is Can be provided in a range of 0.8 to 1.3). This semiconductor device has a gate electrode having a multilayer structure in which a low resistance metal layer is further deposited on the gate electrode directly in contact with the gate insulating film.

In the method for manufacturing a semiconductor device of the present invention, by using the above-mentioned means, the composition of the TaSiN-based film layer provided on the gate insulating film can be controlled, and as a result, a semiconductor device in which the threshold voltage is controlled can be manufactured. .
Further, in the semiconductor device, the gate electrode has a multilayer structure with a low-resistance metal, so that the resistance of the gate electrode can be lowered.

  The best mode for carrying out the present invention will be described below with reference to the drawings. Note that it is easy for a person skilled in the art to make other embodiments by changing or correcting the present invention within the scope of the claims, and these changes and modifications are included in the scope of the claims. The following description is an example of the best mode of the present invention, and does not limit the scope of the claims.

Here, the gate electrode 30 manufactured by the method for manufacturing a semiconductor device of the present invention is used for a field effect (FET) MOS transistor.
FIG. 1 is a schematic view for explaining a method for manufacturing a semiconductor device of the present invention.
As shown in FIG. 1 (1), an element active region 11 is defined in a semiconductor substrate 10. As the semiconductor substrate 10, a silicon single crystal silicon substrate is used.
Specifically, after forming a trench to be the element isolation region 11 of the semiconductor substrate 10 and depositing an insulator (SiO ₂ or the like) to a thickness to fill the trench, the semiconductor substrate 10 is formed by CMP (Chemical Mechanical Polishing) method. An STI (Shallow Trench Isolation) element isolation region 11 having a trench filled with an insulating material is formed thereon.
Next, as shown in (2), an insulating film 20 is formed on the semiconductor substrate 10. After the natural oxide film formed on the surface of the semiconductor substrate 10 is removed, a thin film made of a high dielectric constant material having a film thickness of about several nm is formed as the insulating film 20 on the semiconductor substrate 10 by the CVD method.
Next, as shown in (3), a TaSiN-based film layer 31 for forming the gate electrode 30 is deposited by CVD, and further a low-resistance metal layer 32 is formed and patterned to form gate insulation. A gate electrode 30 is formed on the film 21. Further, ion implantation of an n-type or p-type impurity element is performed in the semiconductor substrate 10 using the gate electrode 30 as a self-aligned mask, and an n-type or p-type source extension region 41 is formed on both sides of the gate electrode 30 in the semiconductor substrate 10. Alternatively, the drain extension region 51 is formed.

Further, as shown in (4), an insulating film such as a SiO ₂ film is formed on the semiconductor substrate 10 so as to cover the gate electrode 30 by the CVD method, and further etched back to thereby form both sides of the gate electrode 30. A sidewall insulating film 33 is formed on the wall surface. Further, the gate insulating film 21 is formed by patterning by lithography and subsequent RIE (Reactive Ion Etching).
Further, as shown in (5), n-type or p-type impurity element ions are implanted into the semiconductor substrate 10 using the gate electrode 30 and the sidewall insulating film 33 as a mask. The n-type or p-type source or drain diffusion regions 41 and 51 are formed outside the substrate.
In the step of forming the insulating film 20, it is possible to form an oxide film, a nitride film, or an oxynitride film having a high dielectric constant alone or in a stacked manner. In particular, by providing the gate insulating film 21 made of the insulating film 20 having a high dielectric constant, the leakage current can be reduced, the gate length can be further reduced, and the operating speed of the semiconductor device 1 can be improved. .

The gate electrode 30 formed in the process of the method for manufacturing a semiconductor device of the present invention is a TaSi _x N _y or TiSi _x N _y film layer (where x is 0.1 to 3.0 and y is 0.1. 5 to 5.0.)).
Here, the means for forming the film layer includes chemical methods such as a vacuum deposition method, a sputtering method, and a laser ablation method, and a CVD method such as a sol-gel method, a solution method, a thermal CVD method, a plasma CVD method, and an ALD method. In the present invention, the CVD method is used.
In the CVD method, a thin film is formed by supplying a gas to the semiconductor substrate 10 supported on a plate having a heating unit and reacting on the semiconductor substrate 10. As the gas, in addition to the raw material gas, a carrier gas for transport and a purge gas for discharging the raw material gas remaining inside are supplied.

As the Si source gas, SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ or the like, or silicon hydride or silicon halide such as SiH ₂ Cl ₂ , SiCl ₄ , or SiHCl ₃ is used. In particular, it is advantageous because silicon hydride is easily decomposed and H and the like hardly remain. Ti tetrachloride is used as a raw material for Ti. The Ta source gas is selected from Ta amide compounds, imide compounds or halides. Specifically, as the amide compound of Ta, PDMAT (Pentakis-dimethylamino-tantalum), and as the imide compound of Ta, TAIMATA (Tertiary-amylimido-tris-dimethylamido-tantalum), TBTDET (Tertiary-butylimido-tris-dietylamido- tantalum) and halides include TaF ₅ , TaCl ₅ , TaBr _{5 and the} like. NH ₃ is used as the N source gas.
As the carrier gas, for example, an inert gas such as He, Ar, N ₂ and / or H ₂ is used. These inert gases do not react with substances constituting the semiconductor device 1. Further, a small amount of reducing gas that does not react with oxygen in the substance constituting the semiconductor device 1 may be added to the carrier gas. For example, a small amount of hydrogen H ₂ may be added to the He gas.

The treatment by the CVD method is performed under conditions using Ar gas as a carrier gas. At this time, instead of supplying and reacting these raw material gases simultaneously, Si raw material gas and Ta raw material gas or Ti raw material gas and N raw material gas are separately supplied, and the respective CVD methods are used. A thin film is formed. By supplying the Si source gas alone, the Si film layer is supplied simultaneously with the Ta source gas or the Ti source gas and the N source gas, so that the source gas reacts in the apparatus of the CVD method, and the TaN film layer or TiN A film layer is formed. The Si film thickness is set to 0.2 to 2.0 nm, the deposited film thickness of the TaN or TiN film layer is set to 0.5 to 3.0 nm, and these thin film layers are alternately stacked. When these thin film layers are alternately deposited, Si and TaN or TiN are mixed or reacted to form a compound by forming the TaSi _x N _y or TiSi _x N _y film layer 31. To do. At this time, if the deposited film thickness of Si is less than 0.2 nm and the deposited film thickness of TaN is less than 0.5 nm, it becomes too thin to form a uniform film layer. When the deposited film thickness of Si exceeds 2.0 nm and the deposited film thickness of TaN or TiN exceeds 3.0 nm, each layer structure becomes clear and does not become a single film layer.

Further, the composition of the integrated TaSi _x N _y or TiSi _x N _y film layer 31 is such that x is in the range of 0.1 to 3.0 and y is in the range of 0.5 to 5.0. In the TaSiN system, the work function can be controlled by its composition, and the threshold for driving the semiconductor device 1 can be adjusted. The work function decreases as x increases. Specifically, the work function has an almost constant value of 4.3 eV when x is 0.5 and y is 2.0, and becomes 4.6 eV when x is 0.1 and y is 2.0.
At this time, the thickness of the TaSi _x N _y or TiSi _x N _y film layer 31 is set to 1 to 20 nm. If the layer thickness is less than 1 nm, defects are likely to occur at the boundary, and the operating voltage tends to increase. Furthermore, the mobility of electrons is degraded due to phonon scattering. On the other hand, if the layer thickness exceeds 20 nm, the gate resistance increases, which is disadvantageous for high-speed operation.

Further, the lower portion of the gate electrode 30 is selected from the group including high oxide or nitride including SiO ₂ , HfO ₂ , ZrO ₂ , Al ₂ O ₃ , La ₂ O ₃ , HfAlO and HfAlON and oxynitride. The gate insulating film 21 is formed of a material having a high dielectric constant. Specifically, HfAl ₁ O _m N _n , HfSi ₁ O _m , HfSi ₁ O _m N _n , HfO ₂ or HfO _m N _n (where l is 0.8 to 1.2, m is 1 to 4 and n are in the range of 0.8 to 4.0), and a gate insulating film 21 is provided. These oxides and oxynitrides have high electrical insulation and dielectric constant, and can reduce leakage current. Further, since the dielectric constant is high, the gate insulating film 21 can be thinned to obtain a certain insulating property. In addition, these oxides and oxynitrides have a high crystallization temperature and thermal stability.

In the gate electrode 30, Mo or W or polycrystalline silicon is used as the low resistance metal layer 32 on the electrode layer 31. Until now, polycrystalline silicon has been used singly, but since this material is a semiconductor, the surface of the gate electrode 30 is slightly depleted, which is disadvantageous for high-speed operation of the device. Correspondingly, nickel silicide, titanium silicide, etc. from polycrystalline silicon have been studied as current terminal electrode materials for transistors. For example, NiSi is a typical compound, but the threshold voltage is high and the low voltage operation of the transistor is difficult. Therefore, the use of other metals has been studied. For example, when a metal having a large work function, such as Ni or Co, is used, the threshold value is reduced in the p-type MOS, but is increased in the n-type MOS. On the other hand, for a metal having a small work function such as Hf or Zr, the threshold value is small for an n-type MOS, but is large for a p-type MOS. TaSi _x N _y or TiSi _x N _y focused in the present invention corresponds to a metal having a small work function.

The gate electrode 30 includes a TaN _z layer 34 (where z is in the range of 0.8 to 1.3) between the low-resistance metal film 32 and the TaSi _x N _y or TiSi _x N _y film layer 31. Can be provided). When the TaSi _x N _y film layer 31 of the electrode layer is deposited thick, the film composition may change or phase separation may occur due to heat treatment. Therefore, by providing the TaN _z layer 34, the crystallized TaN _z layer film generally has a tendency to have a columnar structure while keeping a constant effective film thickness thin, but the TaSi _x N _y film layer 31 is provided at the upper and lower portions. By providing, it is possible to compensate for the disadvantages of the columnar structure. Therefore, the present invention can be widely applied not only to chemical stability but also to process improvements and changes necessary for improving the performance and reliability of transistors. In the TaN _z layer, z is in the range of 0.8 to 1.3. If z is less than 0.8 and z is more than 1.2, diffusion of oxygen O and the like cannot be prevented due to lack of denseness.

As described above, in the method for manufacturing a semiconductor device of the present invention, a high dielectric constant oxide or oxynitride is used for the gate insulating film 21, and a TaSiN-based or TaTiN-based nitride compound is used as the electrode layer by the CVD method. A semiconductor having a low resistance metal layer formed thereon was manufactured. With the TaSiN-based or TaTiN-based nitride compound of the electrode layer, composition control that has been difficult to form by the conventional CVD method can be prepared in order to adjust the threshold value.
In the semiconductor device 1, the TaSi _x N _y or TiSi _x N _y film layer 31 (where x is 0.1 to 3.0 and y is 0.5 to 5.0) is directly above the gate insulating film 21. An electrode layer having a range) was provided. By laminating W, Mo, or polycrystalline silicon on this electrode layer, the gate electrode 30 can be thinned, and further, a stable operation can be secured by suppressing an increase in gate resistance.

Hereinafter, the method for manufacturing a semiconductor device of the present invention will be described more specifically.
Example 1
1: First, p-type single crystal silicon is used for the semiconductor substrate 10 as the semiconductor substrate 10 which becomes the channel of the n-type MOS-FET. On the semiconductor substrate 10, as a gate insulating film 21, HfSi _l O _m N _n (l is 1, m is 2, n is 2) is formed to a thickness of 2 to 5 nm by a CVD method.
2: Next, it introduce | transduces into a CVD apparatus. SiH ₄ , Si ₂ H ₆ , and Si ₃ H ₈ are supplied as Si source gas together with Ar as a carrier gas to perform a CVD process. The conditions of the CVD apparatus at this time are 30 to 120 seconds under conditions using a temperature of 400 to 600 ° C., a chamber vacuum of 13 to 133 Pa, and Ar gas having a flow rate of 500 to 2000 sccm. Thus, a Si deposited layer having a thickness of about 1 nm was obtained.
3: Next, the supplied gas was switched to Ta amide compound PDMAT as the Ta source gas and NH ₃ as the N source gas and supplied simultaneously. The conditions of the CVD apparatus at this time are 20 to 100 seconds under conditions using a temperature of 400 to 600 ° C., a chamber vacuum of 13 to 133 Pa, and Ar gas having a flow rate of 500 to 2000 sccm. Thus, a TaN deposited layer having a thickness of about 3 nm was obtained.
4: By repeating this alternately, a Si film layer of 3 nm and a TaN film layer of 9 nm are laminated to a total of 12 nm, x having a thickness of 12 nm is 0.5, and y is TaSi having a composition of 2.0. _{The xNy} film layer 31 could be formed. The reason why the composition does not become a simple average of the Si layer and the TaN layer is that a reaction occurs on the surface when the films are alternately deposited. FIG. 2 is a schematic view showing the structure of the gate electrode 30 formed in the first embodiment.
5: Next, in order to lower the gate resistance, a low resistance metal layer 32 on which tungsten W is deposited with a thickness of 50 to 100 nm is provided as a further low resistance wiring metal. Thereafter, gate processing was performed to manufacture a semiconductor device 1 having a MIS structure.
As a result, in the conventional CVD method, the TaSiN film 31 having a desired composition cannot be manufactured from the beginning by simultaneously supplying the source gas, but the layer thicknesses of the Si film layer and the TaN film layer are controlled. As a result, the composition control of the TaSiN film 31 could be easily performed.

(Example 2)
1: First, p-type single crystal silicon is used for the semiconductor substrate 10 as the semiconductor substrate 10 which becomes the channel of the n-type MOS-FET. On the semiconductor substrate 10, as a gate insulating film 21, HfSi _l O _m N _n (l is 1, m is 2, n is 2) is formed to a thickness of 2 to 5 nm by a CVD method.
2: Next, it introduce | transduces into a CVD apparatus. SiH ₄ , Si ₂ H ₆ , and Si ₃ H ₈ are supplied as Si source gas together with Ar gas as a carrier gas to perform CVD processing. The conditions of the CVD apparatus at this time are 30 to 120 seconds under conditions using a temperature of 400 to 600 ° C., a chamber vacuum of 13 to 133 Pa, and Ar gas having a flow rate of 500 to 2000 sccm. Thus, a Si deposited layer having a thickness of about 0.5 nm was obtained.
3: Next, the supplied gas was switched to Ta amide compound PDMAT as the Ta source gas and NH ₃ as the N source gas and supplied simultaneously. The conditions of the CVD apparatus at this time are 20 to 100 seconds under conditions using a temperature of 400 to 600 ° C., a chamber vacuum of 13 to 133 Pa, and Ar gas having a flow rate of 500 to 2000 sccm. Thus, a TaN deposited layer having a thickness of about 1.5 nm was obtained.
4: By repeating this alternately, a Si film layer of 1 nm and a TaN film layer of 3 nm are laminated to a total of 4 nm, TaSi having a composition of x having an 8 nm thickness of 0.5 and y of 2.0. _{An xNy} film layer could be formed.
5: Next, the supplied gas was switched to Ta amide compound PDMAT as Ta source gas and NH ₃ as N source gas and supplied simultaneously. The conditions of the CVD apparatus at this time are performed for 120 to 240 seconds under conditions using a temperature of 400 to 600 ° C., a chamber vacuum of 13 to 133 Pa, and Ar gas having a flow rate of 500 to 2000 sccm. Thus, a TaN deposited layer 34 having a thickness of about 10 nm was obtained.

6: Then, by repeating the process in the same manner as in 2, 3, 4, with x 0.5 having a thickness of 4nm on the TaN film layer 34, TaSi _x having a composition of y is 2.0 The _Ny film layer 31 could be formed. At this time, since the TaN film layer 34 in the middle is thick, the TaN film layer 34 can exist without phase separation even when high-temperature treatment is performed. FIG. 3 is a schematic view showing the structure of the gate electrode 30 formed in the second embodiment.
7: Next, in order to lower the gate resistance, a low resistance metal layer 32 on which tungsten W is deposited with a thickness of 50 to 100 nm is provided as a further low resistance wiring metal. Thereafter, gate processing was performed to manufacture a semiconductor device 1 having a MIS structure.
As a result, in the conventional CVD method, a TaSiN film having a desired composition cannot be manufactured from the beginning by simultaneously supplying source gases, but the layer thicknesses of the Si film layer and the TaN film layer are controlled. As a result, the composition control of the TaSiN film 31 could be easily performed. Furthermore, by providing the TaN film layer 34, the stability of the TaSiN-based film 31 was improved, and diffusion of oxygen or the like during manufacturing could be prevented.

It is a schematic diagram shown in order to demonstrate the manufacturing method of the semiconductor device of this invention. 3 is a schematic view showing the structure of a gate electrode formed in Example 1. FIG. 6 is a schematic diagram showing the structure of a gate electrode formed in Example 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate 11 STI element isolation region 20 Insulating film 21 Gate insulating film 30 Gate electrode 31 TaSi _x N _y or TiSi _x N _y film layer 32 Low resistance metal layer 33 Side wall insulating film 34 TaN _z layer 40 Source extension region 41 Source diffusion region 50 Drain extension region 51 Drain diffusion region 60 Channel region

Claims (5)

In a method for manufacturing a semiconductor device in which a gate electrode is formed on a semiconductor substrate by a CVD method,
The gate electrode has a TaSi _x N _y or TiSi _x N _y film layer (where x is in the range of 0.1 to 3.0 and y is in the range of 0.5 to 5.0).
The TaSi _x N _y or TiSi _x N _y film layer is
Si hydride as a Si raw material, titanium tetrachloride as a Ti raw material, or one selected from an amide compound, an imide compound or a halide of Ta as a Ta raw material, and NH ₃ as an N raw material,
A method of manufacturing a semiconductor device, characterized by being formed by laminating a Si deposited film layer and a TiN deposited film layer or a TaN deposited film layer. In the manufacturing method of the semiconductor device according to claim 1,
The TaSi _x N _y or TiSi _x N _y film layer is
Si deposited film layers are alternately stacked with 0.2 to 2.0 nm, TaN or TiN deposited film layers are 0.5 to 3.0 nm,
A method for manufacturing a semiconductor device, wherein the semiconductor device is formed to have a layer thickness of 1 to 20 nm. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The gate insulating film is made of HfAl ₁ O _m N _n , HfSi ₁ O _m , HfSi ₁ O _m N _n , HfO ₂ and HfO _m N _n (where l is 0.8 to 1.2, m is 1 -4 and n are in the range of 0.8-4.). A method of manufacturing a semiconductor device, characterized in that: In the manufacturing method of the semiconductor device according to claim 1 and 2,
A method of manufacturing a semiconductor device, wherein a low-resistance metal film or a polycrystalline silicon layer made of W or Mo is laminated on the gate electrode. In the manufacturing method of the semiconductor device according to claim 4,
The gate electrode may be a TaN _z layer or a TiN _z layer (where z is in the range of 0.8 to 1.3) between the TaSi _x N _y or TiSi _x N _y film layer and the low-resistance metal film. ) Is formed. A method for manufacturing a semiconductor device, comprising:

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