JP2007257837A - Nonvolatile memory circuit and nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that a nonvolatile memory circuit to be used as a redundant address storage circuit, etc., of a semiconductor storage device becomes large-scale due to the increase of a storage capacity of the semiconductor storage device and the occupied area is increased. <P>SOLUTION: The nonvolatile memory circuit is configured to comprise: a plurality of memory cells 10-13 having first terminals, second terminals and control terminals; a level shift circuit 2 for applying voltages of predetermined levels to the first terminals of the plurality of nonvolatile memory cells; and a plurality of switching transistors 40-43 respectively arranged on the second terminals of the plurality of nonvolatile memory cells. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory circuit and a nonvolatile semiconductor memory device, and more particularly to a nonvolatile memory circuit used as a redundant address memory circuit of the nonvolatile semiconductor memory device.

  In recent years, nonvolatile semiconductor memory devices have been widely used in various electronic devices, and low voltage and low power consumption have been promoted in various semiconductor products such as portable devices. In addition, in a nonvolatile semiconductor memory device such as a flash memory, a content addressable memory (CAM) is used as a redundant address memory circuit or the like. Such a CAM (nonvolatile memory circuit) is a nonvolatile memory circuit. As the storage capacity of semiconductor memory devices has increased, the size has increased, and there has been a demand for providing a nonvolatile memory circuit with a small occupation area.

  In recent years, nonvolatile semiconductor memory devices have been widely used in various electronic devices, and demands for low voltage and low power consumption for these electronic devices have also increased. By the way, for example, in a nonvolatile semiconductor memory device such as a flash memory, a redundant address memory circuit that stores an address of a defective cell in a memory cell array of the nonvolatile semiconductor memory device and an address of a redundant cell that replaces the defective cell, The purpose is to store the set values of parameters such as resistance and capacitance that determine the level and delay of internal signals in semiconductor memory devices, and to adjust the level and delay of internal signals by changing the contents of the set values An associative memory (CAM: nonvolatile memory circuit) is used as the trimming information storage circuit or the write address prohibition information storage circuit for storing address information for prohibiting writing. (See Patent Document 1 for a nonvolatile semiconductor memory device having a redundant address memory circuit). Such a non-volatile memory circuit is becoming larger with an increase in the storage capacity of the non-volatile semiconductor memory device, and an increase in the occupied area has become a problem.

  FIG. 1 is a circuit diagram showing an example of a conventional nonvolatile memory circuit (CAM: associative memory). As a nonvolatile memory cell (CAM cell), a flash memory (that is, a memory cell) having a charge trap layer in a gate insulating film is shown. In the figure, a charge memory region is applied to a flash memory cell using a trap level such as an ONO film (oxide film / nitride film / oxide film). However, the CAM cell is not limited to this. For example, a memory cell using a floating gate such as a polysilicon electrode as a charge storage region can be applied.

  In FIG. 1, reference numeral 110 is a CAM cell, 120 is a level shift circuit, 121 and 131 are P-channel MOS transistors (PMOS transistors), 122, 132 to 134 and 140 are N-channel MOS transistors (NMOS transistors). ing. Here, the CAM cell has an ONO (oxide film / nitride film / oxide film) structure electron capture layer provided on a semiconductor substrate, and has two bits for one memory cell (N-channel transistor). It is possible to store information. However, when used in a nonvolatile memory circuit (CAM), normally, 1-bit information is stored and used for one CAM cell.

  As shown in FIG. 1, the level shift circuit 120 is configured as a CMOS inverter including a PMOS transistor 121 and an NMOS transistor 122, and has a high voltage (normal power supply voltage: for example, 3V) higher than a high voltage (normal power supply voltage: 3V). For example, it is connected between a 5V power supply line VPROG and a low potential power supply line Vss (for example, 0V). That is, the level shift circuit 120 inverts the signal level of the input node N10 and shifts the level to apply a high voltage (for example, 5V) or a low potential power supply voltage (for example, 0V) to one end of the CAM cell 110. Note that the other end of the CAM cell 110 is connected to the low potential power supply line Vss via the switching transistor 140.

  Between the input node N10 of the level shift circuit 120 and the high-voltage power supply line VPROG, a PMOS transistor (pull-up transistor) 131 having a low-potential power supply voltage (Vss) applied to the gate is provided. And a low potential power supply line Vss are provided with an NMOS transistor 132 and NMOS transistors 134 and 133 connected in series. Here, a high-voltage power supply line VPROG is connected to the back gates (corresponding to the substrate bias voltage or well potential) of the PMOS transistors 121 and 131.

  An erase enable signal CAMERS is supplied to the gate of the transistor 132. At the time of erasure, the erase enable signal CAMERS becomes a high level “H” to turn on the transistor 132, and a high voltage (VPROG) is applied to one end of the CAM cell 110. It is supposed to be. In addition, a program enable signal RYS is supplied to the gate of the transistor 133, and a program cell selection signal SELn is supplied to the gate of the transistor 134. During the programming, both the program enable signal RYS and the program cell selection signal SELn are high. At level “H”, the transistors 133 and 134 are turned on, and a high voltage (VPROG) is applied to one end of the CAM cell 110 in the same manner as in erasing. The program signal REPH is supplied to the gate of the transistor 140. At the time of programming, the program signal REPH is set to a high level “H” to turn on the transistor 140, and a low-potential power supply voltage (Vss) is connected to the other end of the CAM cell 110. ) Is applied.

  FIG. 2 is a diagram for explaining a program and erase operation of an example of a nonvolatile memory cell, and an example in which a memory cell of a type using a trap level such as an ONO film as a charge storage region is applied. Explain. Here, FIG. 2A shows the program operation of the memory cell, and FIG. 2B shows the erase operation of the memory cell.

  First, as shown in FIG. 2A, when a CAM cell is programmed (data is written), 5V (output voltage of the level shift circuit) is applied to one end of the CAM cell, and the other CAM cell. The terminal is set to 0 V (connected to Vss: the transistor 140 is turned on by a high level “H” programming signal REPH), and 9 V (gate voltage RG) is applied to the control terminal of the CAM cell. That is, writing (programming) is performed by injecting electrons into one end side (side to which 5 V is applied) of the electron trapping layer of the ONO structure of the CAM cell (memory cell) using channel thermal electron injection.

Next, as shown in FIG. 2B, when erasing the CAM cell, 5 V is applied to one end of the CAM cell and the other end of the CAM cell is floated (for low-level “L” programming). The transistor 140 is turned off by the signal REPH), and −6 V (gate voltage RG) is applied to the control terminal of the CAM cell. That is, erasing is performed by injecting holes generated by the band-to-band tunnel effect into the electron trap layer through the lower oxide film.
JP 2000-123591 A

  As described above, the nonvolatile memory circuit having nonvolatile memory cells, for example, the associative memory (CAM) shown in FIG. 1 is a level shift circuit for programming and erasing each memory cell (CAM cell) 110. 120 was needed.

  Here, since the PMOS transistor 121 constituting the level shift circuit 120 applies a high voltage (VPROG) to one end of the CAM cell 110 via the transistor 121, the gate width W is set to a large value such as 30 μm, for example. It must be manufactured, and the area occupied by the associative memory was to increase.

  In addition, the transistor 132 that pulls down the input node N10 of the level shift circuit 120 at the time of erasing, the pull-down path thereof, or the transistors 133 and 134 need to be provided for each CAM cell 110. It was supposed to increase.

  Furthermore, in recent years, for example, associative memories (nonvolatile memory circuits) built into a nonvolatile semiconductor memory device such as a flash memory have become larger as the storage capacity of the nonvolatile semiconductor memory device has increased. The increase in the area occupied by the circuit has hindered the high integration of the nonvolatile semiconductor memory device. Note that the nonvolatile memory circuit according to the present invention is not limited to the associative memory built in the nonvolatile semiconductor memory device, and is widely applied to various other semiconductor memory devices and general semiconductor devices. can do.

  An object of the present invention is to provide a non-volatile memory circuit and a non-volatile semiconductor memory device with a reduced occupation area in view of the problems of the conventional non-volatile memory circuit described above.

  According to the first aspect of the present invention, a plurality of nonvolatile memory cells having a first terminal, a second terminal, and a control terminal, and a predetermined level with respect to the first terminals of the plurality of nonvolatile memory cells There is provided a non-volatile memory circuit comprising: a level shift circuit for applying a voltage of 1; and a plurality of switching transistors respectively provided at second terminals of the non-volatile memory cells.

  According to the second aspect of the present invention, a memory cell array having a plurality of memory cells, a decoder circuit for accessing a predetermined memory cell of the memory cell array in response to an external address signal, and a defective cell in the memory cell array A nonvolatile semiconductor memory device is provided which includes a redundant address storage circuit for storing the address of the redundant cell in order to access the redundant cell instead of accessing the redundant cell. The redundant address storage circuit includes a plurality of nonvolatile memory cells having a first terminal, a second terminal, and a control terminal, and a predetermined level with respect to the first terminals of the plurality of nonvolatile memory cells. A level shift circuit for applying a voltage; and a plurality of switching transistors respectively provided at second terminals of the plurality of nonvolatile memory cells.

  According to the present invention, it is possible to provide a non-volatile semiconductor memory device including a non-volatile memory circuit with a reduced occupied area or a redundant address memory circuit with a reduced occupied area.

  As described above in detail, according to the present invention, the area occupied by the nonvolatile memory circuit used as the associative memory can be reduced.

  Hereinafter, embodiments of a nonvolatile memory circuit and a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a circuit diagram showing an example of a non-volatile memory circuit (CAM: associative memory) according to the present invention. As a non-volatile memory cell (CAM cell), a memory cell having a charge trap layer in a gate insulating film (that is, ONO) A flash memory cell using a trap level such as a film as a charge storage region is shown. However, the CAM cell is not limited to this. For example, a memory cell using a floating gate such as a polysilicon electrode as a charge storage region can be applied.

  In FIG. 3, reference numeral 2 is a level shift circuit, 10 to 13 are CAM cells, 21 and 31 are PMOS transistors, and 22, 32, 33 and 40 to 43 are NMOS transistors. Here, the CAM cell is the same as that described above with reference to FIGS. 1 and 2, and has an ONO structure electron trap layer provided on a semiconductor substrate, and has one memory cell. 2 bits of information can be stored. However, when used in a nonvolatile memory circuit, normally, 1-bit information is stored and used for one CAM cell.

  As is clear from comparison between FIG. 3 and FIG. 1, in the nonvolatile memory circuit of the present embodiment, four CAM cells 10 to 13 are provided for one level shift circuit 2 and transistors 31, 32 and 33. It has been.

  That is, as shown in FIG. 3, the level shift circuit 2 is configured as a CMOS inverter composed of a PMOS transistor 21 and an NMOS transistor 22, and has a high voltage (normal power supply voltage: for example, 3V) higher than a high potential power voltage (for example, 3V). For example, it is connected between a 5V power supply line VPROG and a low potential power supply line Vss (for example, 0V). The level shift circuit 2 inverts the signal level of the input node N1 and shifts the level to apply a high voltage (for example, 5 V) or a low potential power supply voltage (for example, 0 V) to one end of the four CAM cells 10 to 13. Are applied in common. The other ends of the CAM cells 10 to 13 are connected to the low potential power supply line Vss via the corresponding switching transistors 40 to 43, respectively.

  The program cell selection signals REPH (0) to REPH (3) supplied to the gates of the switch transistors 40 to 43 are signals obtained by decoding the program cell selection signal SELn and the program signal REPH in FIG. The program cell selection signals REPH (0) to REPH (3) become high level “H” to turn on the transistors 40 to 43, and the low potential power supply voltage (Vss) is applied to the other end of the corresponding CAM cells 10 to 13. Is applied.

  Here, for example, when a non-volatile memory circuit having the same storage capacity is manufactured by applying a 0.38 μm CMOS process, the non-volatile memory circuit to which the present embodiment shown in FIG. The occupied area can be reduced by about 30% compared to the nonvolatile memory circuit.

  The PMOS transistor 31 and the NMOS transistors 32 and 33 in the nonvolatile memory circuit of this embodiment are the same as the PMOS transistor 131 and the NMOS transistors 132 and 133 in the conventional nonvolatile memory circuit shown in FIG. The program and erase operations of the cell are the same as those described with reference to FIGS. 2 (a) and 2 (b).

  In the nonvolatile memory circuit of this embodiment shown in FIG. 3, when erasing is performed, the erase enable signal CAMERS is set to a high level “H”, the NMOS transistor 32 is turned on, and the input node N1 of the level shift circuit 2 is set to a low potential. Pull down to the power supply voltage (Vss). Thereby, the output of the level shift circuit 2 becomes a high voltage (VPROG), and the high voltage (VPROG) is applied to one end of all the CAM cells 10 to 13. Further, at the time of erasing, all the program cell selection signals REPH (0) to REPH (3) are set to the low level “L”, the NMOS transistors 40 to 43 are turned off, the other ends of the CAM cells 10 to 13 are floated, and All the CAM cells 10 to 13 are erased at once by setting the gate voltage RG to -6V. Note that the CAM cells to be erased collectively are not all the CAM cells in the nonvolatile memory circuit. For example, when the CAM cells are divided into blocks, the CAM cells can be erased for each block.

  Next, when programming is performed, the program enable signal RYS is set to a high level “H”, the transistor 33 is turned on, and the input node N1 of the level shift circuit 2 is pulled down to the low potential power supply voltage (Vss) in the same manner as in erasing. To do. Thereby, the output of the level shift circuit 2 becomes a high voltage (VPROG), and the high voltage (VPROG) is applied to one end of all the CAM cells 10 to 13. Further, at the time of programming, by independently controlling the program cell selection signals REPH (0) to REPH (3) supplied to the gates of the NMOS transistors 40 to 43, the other ends of the corresponding CAM cells 10 to 13 are individually lowered. CAM cells 10 to 13 selected (turned on) by program cell selection signals REPH (0) to REPH (3) by controlling whether or not to be connected to potential power supply wire Vss and setting gate voltage RG to 9V. Only program (write by injecting electrons into the electron capture layer).

  In the above, in the embodiment shown in FIG. 3, four CAM cells 10 to 13 are provided for one level shift circuit 2, but the number of CAM cells is not limited to four. . However, if the number of CAM cells is increased, not only the size (gate width W) of the PMOS transistor 21 in the level shift circuit 2 has to be increased, but also the NMOS in the level shift circuit 2 in order to ensure performance at the time of reading. The size of the transistor 22 must also be increased.

  FIG. 4 is a block diagram showing an example of a nonvolatile semiconductor memory device to which the nonvolatile memory circuit of the present invention is applied, and shows a configuration example of a flash memory. In FIG. 4, reference numeral 201 is a command buffer, 202 is an address buffer, 203 is an address decoder, 204 is a chip enable / output enable control circuit, 205 is a PGM voltage generation circuit, 206 is an ERASE voltage generation circuit, and 207 is a switch circuit. 208, a memory cell array, 209 a sense amplifier, 210 a data latch circuit, 211 an input / output buffer, 212 a redundant address storage circuit, and 213 a coincidence detection circuit. Reference symbol / WE indicates a write enable signal, / CE indicates a chip enable signal, and / OE indicates an output enable signal. Note that the nonvolatile memory circuit according to the present invention corresponds to the redundant address storage circuit 212.

  In the nonvolatile semiconductor memory device shown in FIG. 4, when data stored in a predetermined memory cell in the memory cell array 208 is read, the write enable signal / WE is deactivated to a high level “H” and the chip enable signal / CE is deactivated. The output enable signal / OE is activated to a low level “L”, and an address signal corresponding to a predetermined memory cell to be read is input. At this time, the address decoder 203 receiving the address signal via the address buffer 202 decodes the address signal, and a predetermined memory cell in the memory cell array 208 is accessed according to the decoding result.

  Data from a predetermined memory cell in the memory cell array 208 is read by the sense amplifier 209, and the read data is sequentially output to the outside via the data latch circuit 210 and the input / output buffer 211. The chip enable / output enable control circuit 204 sets the input / output buffer 211 as an output upon receiving the chip enable signal / CE and the output enable signal / OE.

  Next, when a program / erase operation is executed, that is, when data is written in a predetermined memory cell of the memory cell array 208 (or when a memory cell included in a predetermined block of the memory cell array 208 is erased), The enable signal / WE and the chip enable signal / CE are activated as a low level “L”, the output enable signal / OE / is deactivated as a high level “H”, and an address corresponding to a predetermined memory cell to be written Input the signal. At this time, the write data is held in the sense amplifier 209 via the input buffer 211 and the data latch circuit 210, and at the same time, the address decoder 203 receiving the address signal via the address buffer 202 decodes the address signal.

  Thereafter, the memory cell array 208 writes the write data held in the sense amplifier 209 to the memory cell corresponding to the output of the address decoder 203. The chip enable / output enable control circuit 204 sets the input / output buffer 211 as an input when it receives the chip enable signal / CE and the output enable signal / OE.

  Here, at the time of data writing, the PGM voltage generation circuit 205 generates a high voltage such as 9 V, for example. When erasing data, the ERASE voltage generation circuit 206 generates a voltage such as −6 V, for example, and the switch circuit 207 selects a block to be erased.

  The redundant address storage circuit (nonvolatile memory circuit: CAM) 212 includes a plurality of nonvolatile memory cells similar to the memory cells of the memory cell array 208, and stores initial information and the like of the nonvolatile semiconductor memory device. This initial information is, for example, information on defective memory cells in the memory cell array 208 generated in the manufacturing process or the like. That is, the information stored in the redundant address storage circuit 212 and the address signal to be accessed are compared by the coincidence detection circuit 213, and if they match, the address decoder 203 determines that the defective cell is accessed by the redundant cell. The operation of automatically switching to is performed.

  In the above description, an example in which the nonvolatile memory circuit according to the present invention is applied as a redundant address storage circuit of a nonvolatile semiconductor memory device is described, and further, a flash memory is described as an example of the nonvolatile semiconductor memory device. However, it is needless to say that the nonvolatile memory circuit of the present invention is not limited to these applications and can be widely applied to various semiconductor devices.

(Supplementary Note 1) A plurality of nonvolatile memory cells having a first terminal, a second terminal, and a control terminal;
A level shift circuit that applies a predetermined level of voltage to the first terminals of the plurality of nonvolatile memory cells;
A non-volatile memory circuit, comprising: a plurality of switching transistors respectively provided at second terminals of the non-volatile memory cells.

  (Additional remark 2) The non-volatile memory circuit of Additional remark 1 WHEREIN: Four of these non-volatile memory cells are provided with respect to said one level shift circuit, The non-volatile memory circuit characterized by the above-mentioned.

  (Supplementary note 3) In the nonvolatile memory circuit according to supplementary note 1, the level shift circuit is a CMOS inverter connected between a high-voltage power supply line and a low-potential power supply line higher than the voltage of the high-potential power supply line. There is a non-volatile memory circuit.

(Supplementary Note 4) In the nonvolatile memory circuit according to Supplementary Note 3,
A P-channel MOS transistor connected between the high-voltage power supply line and the input node of the level shift circuit and having a control terminal connected to the low-potential power supply line;
A first N-channel connected between an input node of the level shift circuit and the low-potential power line, and having an erase enable signal input to a control terminal for erasing the plurality of nonvolatile memory cells at once. A nonvolatile memory circuit comprising a type MOS transistor.

(Supplementary Note 5) In the nonvolatile memory circuit according to Supplementary Note 4,
A second N-channel MOS transistor connected between an input node of the level shift circuit and the low-potential power supply line and having a program enable signal for programming the plurality of nonvolatile memory cells input to a control terminal A non-volatile memory circuit comprising:

  (Supplementary Note 6) In the nonvolatile memory circuit according to Supplementary Note 5, each of the switching transistors has a third configuration in which a program cell selection signal for individually programming a corresponding nonvolatile memory cell is input to a control terminal. A non-volatile memory circuit comprising an N-channel MOS transistor.

  (Supplementary note 7) The nonvolatile memory circuit according to any one of supplementary notes 1 to 6, wherein the nonvolatile memory circuit is an associative memory circuit.

  (Supplementary note 8) The nonvolatile memory circuit according to supplementary note 7, wherein the associative memory circuit is a redundant address storage circuit that stores a redundant address in a memory cell array of a semiconductor storage device.

  (Supplementary note 9) In the nonvolatile memory circuit according to supplementary note 8, the semiconductor memory device is a nonvolatile semiconductor memory device, and the nonvolatile memory cell of the nonvolatile memory circuit includes a memory cell array of the nonvolatile semiconductor memory device. A non-volatile memory circuit, characterized in that it is the same as a memory cell constituting it.

  (Additional remark 10) The non-volatile memory circuit of Additional remark 1 WHEREIN: The said non-volatile memory cell is erased for every group or all at once, The non-volatile memory circuit characterized by the above-mentioned.

  (Supplementary note 11) The nonvolatile memory circuit according to supplementary note 1, wherein the nonvolatile memory cell is selectively programmed.

  (Supplementary note 12) In the nonvolatile memory circuit according to supplementary note 1, the nonvolatile memory cell performs an erase and program operation when a predetermined high voltage higher than a high potential power supply voltage is applied as a substrate bias voltage. A nonvolatile memory circuit.

  (Supplementary note 13) The nonvolatile memory circuit according to supplementary note 1, wherein the nonvolatile memory cell is a memory cell using a trap level such as an ONO film as a charge storage region.

(Supplementary note 14) a memory cell array having a plurality of memory cells;
A decoder circuit for accessing a predetermined memory cell of the memory cell array in response to an external address signal;
A non-volatile semiconductor storage device comprising a redundant address storage circuit for storing the address of the redundant cell in order to access the redundant cell instead when the address of the defective cell in the memory cell array is accessed;
The redundant address storage circuit includes:
A plurality of non-volatile memory cells having a first terminal, a second terminal and a control terminal;
A level shift circuit that applies a predetermined level of voltage to the first terminals of the plurality of nonvolatile memory cells;
A non-volatile semiconductor memory device comprising: a plurality of switching transistors respectively provided at second terminals of the non-volatile memory cells.

  (Supplementary note 15) The nonvolatile semiconductor memory device according to supplementary note 14, wherein four of the plurality of nonvolatile memory cells are provided for the one level shift circuit. .

  (Supplementary note 16) In the nonvolatile semiconductor memory device according to supplementary note 14, the level shift circuit includes a CMOS inverter connected between a high-voltage power supply line and a low-potential power supply line higher than a voltage of the high-potential power supply line A non-volatile semiconductor memory device characterized by the above.

(Supplementary note 17) In the nonvolatile semiconductor memory device according to supplementary note 16, the redundant address storage circuit further includes:
A P-channel MOS transistor connected between the high-voltage power supply line and the input node of the level shift circuit and having a control terminal connected to the low-potential power supply line;
A first N-channel connected between an input node of the level shift circuit and the low-potential power line, and having an erase enable signal input to a control terminal for erasing the plurality of nonvolatile memory cells at once. A nonvolatile semiconductor memory device comprising: a MOS transistor.

(Supplementary note 18) In the nonvolatile semiconductor memory device according to supplementary note 17, the redundant address storage circuit further includes:
A second N-channel MOS transistor connected between an input node of the level shift circuit and the low-potential power supply line and having a program enable signal for programming the plurality of nonvolatile memory cells input to a control terminal A non-volatile semiconductor memory device comprising:

  (Supplementary note 19) In the nonvolatile semiconductor memory device according to supplementary note 18, each of the switch transistors has a third configuration in which a program cell selection signal for individually programming a corresponding nonvolatile memory cell is input to a control terminal. A non-volatile semiconductor memory device comprising the N-channel MOS transistor.

  (Supplementary note 20) The nonvolatile semiconductor memory device according to supplementary note 14, wherein the nonvolatile memory cell of the redundant address storage circuit is selectively programmed.

  (Supplementary note 21) In the nonvolatile semiconductor memory device according to supplementary note 14, the nonvolatile memory cell of the redundant address storage circuit is erased and programmed by applying a predetermined high voltage higher than a high potential power supply voltage as a substrate bias voltage. A non-volatile semiconductor memory device that performs an operation.

  (Supplementary note 22) In the nonvolatile semiconductor memory device according to supplementary note 14, the nonvolatile semiconductor memory device is a memory cell that uses a trap level such as an ONO film as a charge storage region, and the redundant address memory circuit includes: The nonvolatile memory cell is a memory cell that uses a trap level such as an ONO film as a charge storage region.

  (Supplementary Note 23) In the nonvolatile semiconductor memory device according to any one of Supplementary Notes 14 to 22, the plurality of nonvolatile memory cells of the redundant address storage circuit are the same as the memory cells constituting the memory cell array. A non-volatile semiconductor memory device.

It is a circuit diagram which shows an example of the conventional non-volatile memory circuit. It is a figure for demonstrating the program and erase operation of an example of a non-volatile memory cell. It is a circuit diagram showing an example of a nonvolatile memory circuit according to the present invention. 1 is a block diagram illustrating an example of a nonvolatile semiconductor memory device to which a nonvolatile memory circuit of the present invention is applied.

Explanation of symbols

2. Level shift circuit (CMOS inverter)
10-13 ... Non-volatile memory cell 31 ... P channel type MOS transistor (PMOS transistor)
32. First N-channel MOS transistor (NMOS transistor)
33 ... Second N-channel MOS transistor (NMOS transistor)
40 to 43 ... Third N-channel MOS transistor (NMOS transistor)
201 ... command buffer 202 ... address buffer 203 ... address decoder 204 ... chip enable / output enable control circuit 205 ... PGM voltage generation circuit 206 ... ERASE voltage generation circuit 207 ... Switch circuit 208 ... Memory cell array 209 ... Sense amplifier 210 ... Data latch circuit 211 ... Input / output buffer 212 ... Redundant address storage circuit 213 ... Match detection circuit

Claims (12)

A plurality of non-volatile memory cells having a first terminal, a second terminal and a control terminal;
A level shift circuit that applies a predetermined level of voltage to the first terminals of the plurality of nonvolatile memory cells;
A non-volatile memory circuit, comprising: a plurality of switching transistors respectively provided at second terminals of the non-volatile memory cells.   2. The nonvolatile memory circuit according to claim 1, wherein four of the plurality of nonvolatile memory cells are provided for the one level shift circuit. 3.   2. The nonvolatile memory circuit according to claim 1, wherein the level shift circuit is a CMOS inverter connected between a high-voltage power line and a low-potential power line higher than a voltage of the high-potential power line. A non-volatile memory circuit. The nonvolatile memory circuit according to claim 3, further comprising:
A P-channel MOS transistor connected between the high-voltage power supply line and the input node of the level shift circuit and having a control terminal connected to the low-potential power supply line;
A first N-channel connected between an input node of the level shift circuit and the low-potential power line, and having an erase enable signal input to a control terminal for erasing the plurality of nonvolatile memory cells at once. A nonvolatile memory circuit comprising a type MOS transistor. The nonvolatile memory circuit according to claim 4, further comprising:
A second N-channel MOS transistor connected between an input node of the level shift circuit and the low-potential power supply line and having a program enable signal for programming the plurality of nonvolatile memory cells input to a control terminal A non-volatile memory circuit comprising:   6. The nonvolatile memory circuit according to claim 5, wherein each of the switching transistors is a third N-channel type in which a program cell selection signal for individually programming a corresponding nonvolatile memory cell is input to a control terminal. A non-volatile memory circuit comprising a MOS transistor.   The non-volatile memory circuit according to claim 1, wherein the non-volatile memory circuit is an associative memory circuit.   8. The nonvolatile memory circuit according to claim 7, wherein the associative memory circuit is a redundant address memory circuit that stores an address of a defective cell in a memory cell array of a semiconductor memory device and an address of a redundant cell to be replaced with the defective cell. A non-volatile memory circuit. A memory cell array having a plurality of memory cells;
A decoder circuit for accessing a predetermined memory cell of the memory cell array in response to an external address signal;
A nonvolatile semiconductor memory device comprising a redundant address storage circuit for storing an address of a defective cell in the memory cell array and an address of a redundant cell to be replaced with the defective cell,
The redundant address storage circuit includes:
A plurality of non-volatile memory cells having a first terminal, a second terminal and a control terminal;
A level shift circuit that applies a predetermined level of voltage to the first terminals of the plurality of nonvolatile memory cells;
A non-volatile semiconductor memory device comprising: a plurality of switching transistors respectively provided at second terminals of the non-volatile memory cells.   10. The nonvolatile semiconductor memory device according to claim 9, wherein the plurality of nonvolatile memory cells of the redundant address storage circuit are the same as the memory cells constituting the memory cell array. . The nonvolatile memory circuit according to any one of claims 1 to 8,
When programming the nonvolatile memory cell, the predetermined level of voltage is applied to the first terminal, and the second terminal is grounded,
When outputting data from the nonvolatile memory cell, a voltage is applied to the first terminal, and the second terminal is grounded. The nonvolatile memory circuit according to claim 11,
The nonvolatile memory circuit, wherein when outputting data from the nonvolatile memory cell, the voltage of the predetermined level is applied to the first terminal.

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