JP2007257363A - Information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve power saving or high-performance of an information processing apparatus by optimally controlling an operation clock frequency of a processor and a bus regardless of a processing unit without changing a software configuration. <P>SOLUTION: The information processing apparatus comprises: a bus I/F 30 for performing access arbitration of the processor 20 to a memory 50; a variable processing clock generator 105 for supplying a clock to the processor 20; a variable bus clock generator 106 for supplying a clock to the bus I/F 30; a processing busy/leisure state identifying part 103 for identifying the busy/leisure state of the operation of the processor 20; a bus busy/leisure state identifying part 104 for identifying the busy/leisure state of the operation of the bus I/F 30; and a clock adjusting part 102 for issuing a clock generation command to a variable processing clock generating part 105 and a variable bus clock generating part 106 on the basis of processing busy/leisure information, bus busy/leisure information and a clock adjustment rule for optimally operating the processor 20 and the bus I/F 30. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus that supplies a clock having an optimal frequency to a processor and a bus interface as a processing load changes.

2. Description of the Related Art Conventionally, there is a technique in which a change in the operating frequency of a processor is realized by adding some processing for determining a processing load in software processing operating on the processor (see, for example, Patent Document 1). . In addition, there is a technique in which the operation clock frequency of a processor is changed for each unit of software that operates on the processor (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 2002-278643 JP 2002-41179 A

  In the prior art, the operating frequency of the processor is set for each software unit (hereinafter referred to as “processing unit”). However, the processing conditions in the processing unit change each time, such as MPEG decoding processing in which the processing load changes due to the change in the bit rate, and the processing load changes each time, or the time series within the single processing unit When the processing load changes, it is impossible to set the detailed operating frequency.

  Also, a conventional technique for embedding a process for notifying a processor that a processing condition is changed in a processing unit and changing the operating condition such as the processor operating clock frequency and the external bus operating clock frequency each time the process is executed. However, every time the hardware configuration including the processor is changed, the existing software needs to be corrected.

  The present invention reduces the power consumption or performance of an information processing apparatus by optimally controlling the operation state such as the operation clock frequency of the processor and the bus regardless of the processing unit without changing the software configuration. It aims to be realized.

  An information processing apparatus according to the present invention includes a processor, a memory, a bus interface that arbitrates access to the memory of the processor, and a variable processing clock generator that supplies an operation clock necessary for the operation of the processor to the processor. A variable bus clock generator for supplying the bus interface with an operation clock necessary for the operation of the bus interface, a processing busy state identifying unit for identifying busyness of the operation of the processor, and busyness of the operation of the bus interface. A bus busy state identification unit for identifying a bus, and a clock in which a plurality of clock control information for optimally operating the processor and the bus interface according to the busy time of each of the processor and the bus interface is described A rule storage in which adjustment rules are stored; Among the clock adjustment rules, the processing busy information indicating the results obtained by the processing busy state identifying unit and the bus busy state identifying unit, and clock control information corresponding to the bus busy information, the variable processing A clock adjusting unit that outputs to the variable bus clock generating unit, and the variable processing clock generating unit and the variable bus clock generating unit generate an operation clock according to clock control information from the clock adjusting unit. .

  With this configuration, the processing load on the processor is judged from the busy state of the processor and bus interface regardless of the software processing unit, and when the bus access is low for processing, the operating clock frequency of the bus interface is lowered and processing is performed. On the other hand, when there are many bus accesses, behavior such as lowering the processor operating clock frequency becomes possible.

  That is, the processor and the bus interface can be operated at the minimum necessary operating frequency, and high performance and power saving of the information processing apparatus are realized.

  The present invention can be realized as a clock control method using the characteristic configuration means of the information processing apparatus of the present invention as a step, or as an integrated circuit including the characteristic configuration means.

  According to the present invention, it is possible to determine the processing load based on the busy state of the processor and the bus during the actual operation and adjust the operation clock frequency of the processor and the bus, and the processing load regardless of the software configuration. More precise operation state control corresponding to

  Embodiments of the present invention will be described below with reference to the drawings.

  In addition, each figure has shown each component only to such an extent that this invention can be understood, Therefore, this invention is not limited to the example of illustration.

(First embodiment)
FIG. 1 is an explanatory diagram of the configuration and usage of the information processing apparatus according to the first embodiment of the present invention.

  In FIG. 1, the clock control unit 10 includes a clock adjustment unit 102 and a rule storage unit 109 that holds a clock adjustment rule 101. The processor 20 is a part having a main arithmetic processing function in the information processing apparatus, and the memory bus interface 30 is capable of reading / writing information from the processor 20 and accessing the memory 50 connected to the memory bus 40. This is the site for mediation. Based on the processing busy state information 111 from the processing busy state identifying unit 103 and the bus busy state information 112 from the bus busy state identifying unit 104, the clock adjustment rule 101 determines whether the processor 20 and the memory bus interface 30 are connected. This is a rule for controlling the operation clock frequency for optimal operation. The clock adjustment unit 102 receives information on the busy state of the processor 20 and the memory bus interface 30 and outputs an instruction to change the clock supplied to each of the processor 20 and the memory bus interface 30 according to the busy state. To do. The processing busy state identifying unit 103 is a device having a function of identifying the busy state of the processor 20 and outputting the result to the clock adjusting unit 102. The bus busy state identifying unit 104 is a function of the memory bus interface 30. The device has a function of identifying a busy state and outputting the result to the clock adjusting unit 102.

  The variable processing clock generator 105 is a control device that supplies an operation clock having a frequency based on the processing clock control information 113, which is a control signal for determining an operation clock frequency supplied to the processor 20, to the processor 20. The variable bus clock generator 106 is a control device that supplies the memory bus interface 30 with an operation clock having a frequency based on the bus clock control information 114 that is a control signal that determines the operation clock frequency supplied to the memory bus interface 30.

  The busy / busy state information 111 is a signal indicating the result of observing the busy / busy state of the processor 20 that is necessary for determining the clock frequency necessary and sufficient for the operation of the processor 20. The bus busy / busy state information 112 is a signal indicating a result of observing the busy / busy state of the memory bus interface 30 necessary for determining the clock frequency necessary and sufficient for the operation of the memory bus interface 30. The processing clock control information 113 is a processing clock control signal for controlling the change of the processor supply clock 115 notified from the clock adjusting unit 102 to the variable processing clock generator 105. The bus clock control information 114 is a bus clock control signal for controlling the change of the bus supply clock 116 notified from the clock adjusting unit 102 to the variable bus clock generator 106. The processor supply clock 115 is an operation clock supplied from the variable processing clock generator 105 to the processor 20, and the bus supply clock 116 is an operation clock supplied from the variable bus clock generator 106 to the memory bus interface 30.

  The operation of the information processing apparatus of the present embodiment configured as described above will be described below.

  The processing busy state identifying unit 103 observes the busy state of the processor 20 and outputs processing busy state information 111 as an observation result to the clock adjusting unit 102. For example, the processing busy state identifying unit 103 counts the number of times the internal register of the processor 20 is used per unit time and compares it with a reference value held in advance to identify the busy state of the processing of the processor 20. The busy / busy state information 111 is information representing the degree of busyness of processing of the processor 20 output from the busy / busy state identification unit 103 in binary or multivalued form.

  The bus busy state identifying unit 104 observes the busy state of the memory bus interface 30 and outputs the bus busy state information 112 as an observation result to the clock adjusting unit 102. The bus busy state identification unit 104 measures the amount of data per unit time communicated between the memory bus interface 30 and the memory 50, for example, and compares it with a reference value held in advance. 30 busy and busy times are identified. The bus busy / busy state information 112 is information representing the degree of busyness of processing of the memory bus interface 30 output from the bus busy / busy state identifying unit 104 in binary or multivalued manner.

  Based on the processing busy state information 111, the bus busy state information 112, and the clock adjustment rule 101, the clock adjustment unit 102 provides processing clock control information 113 for instructing the variable processing clock generator 105 to generate an operation clock. At the same time, the bus clock control information 114 for instructing the variable bus clock generator 106 to generate an operation clock is output.

  FIG. 2 shows an example of the clock adjustment rule 101. In this example, the degree of busyness indicated by the processing busy state information 111 and the bus busy state information 112 is exemplified by three values of high, medium and low. The processor busyness degree 201 is the busyness degree of the processor 20 indicated by the processing busyness state information 111, and the bus busyness degree 202 is the busyness degree of the memory bus interface 30 indicated by the bus busyness state information 112. is there. The processing clock control information output 203 is the content of the processing clock control information 113 output from the clock adjustment unit 102 to the variable processing clock generator 105. The bus clock control information output 204 is the contents of the bus clock control information 114 output from the clock adjustment unit 102 to the variable bus clock generator 106.

  The clock adjustment rule 101 includes a processor busy degree 201 and a bus busy degree 202 indicated by the processing busy state information 111 and the bus busy state information 112, a processing clock control information output 203 and a bus clock control information output 204. This is information indicating a correspondence relationship.

  The variable processing clock generator 105 adjusts the frequency of the processor supply clock 115 necessary for the operation of the processor 20 based on the processing clock control information 113 from the clock adjustment unit 102. For example, the variable processing clock generator 105 is a frequency multiplication circuit that multiplies the original oscillation frequency by a multiplier based on the processing clock control information 113.

  The variable bus clock generator 106 adjusts the frequency of the bus supply clock 116 necessary for the operation of the memory bus interface 30 based on the bus clock control information 114 from the clock adjustment unit 102. For example, the variable bus clock generator 106 is a frequency multiplication circuit that multiplies the original oscillation frequency by a multiplier based on the bus clock control information 114.

  With the above operation, optimum control of the operating state of the processor 20 and the memory bus interface 30 is realized regardless of the processing unit of software executed by the processor 20.

  Note that the processing busy state identifying unit 103 may identify the busy state of the processor 20 based on the frequency of access to the memory cache of the processor 20. The high access frequency to the cache of the processor 20 means that the processing amount of the processor 20 is large. In addition, when the cache of the processor 20 is a write-back cache, it is well known that the access frequency to the cache and the access frequency to the memory 50 do not always match.

  In the above configuration, the busy / busy state identification unit 103 can obtain the busy / busy state of the processor 20 by observing the access frequency to the cache in the processor 20. The bus busy state identification unit 104 can obtain the busy state of the memory bus interface 30 used by the cache in the processor 20 by observing the frequency of data transfer from the cache to the memory 50.

  Accordingly, the clock adjustment unit 102 performs processing busy state information 111 including the access frequency to the cache from the processing busy state identifying unit 103 and data transfer from the cache to the memory 50 from the bus busy state identifying unit 104. By using the bus busy state information 112 including the frequency as an input and using the clock adjustment rule 101, a control value is derived so that an optimum clock is supplied to each of the processor 20 and the memory bus interface 30. Is possible.

  By adopting this configuration, it is possible to supply a clock with an optimal frequency to the processor 20 and the memory bus interface 30 with a simpler configuration than when measuring the frequency of use of the processor built-in registers. Can be obtained.

  In the above configuration, the busy state identification unit 103 may identify the busy state of the processor 20 by observing the accumulator access frequency of the processor 20. It is well known that when the calculation amount of the processor 20 is large, the accumulator in the processor 20 is frequently used. When the accumulator access frequency of the processor 20 is observed, the processor 20 and the memory bus interface 30 are most suitable for the processor 20 and the memory bus interface 30 with a simpler configuration than the case of measuring the frequency of use of a plurality of processor built-in registers. It is possible to obtain an effect that a clock having a proper frequency can be supplied.

  Furthermore, although the configuration of the processor 20 has been described above, the configuration of the processor 20 is not limited to the above content.

  It is well known that a strobe signal is output when the memory bus interface 30 accesses the memory 50. Therefore, the number of occurrences per unit time of the strobe signal generated by the memory bus interface 30 is measured. When the generation ratio of the strobe signal is low, the memory 50 is less accessed, and when the generation ratio of the strobe signal is high, the memory 50 The bus busy state identifying unit 104 may identify the busy state of the memory bus interface 30 using the fact that it can be determined that there are many accesses to the memory bus interface 30. With this configuration, it is possible to supply a clock with an optimal frequency to the processor 20 and the memory bus interface 30 with a simpler configuration than when measuring the flow rate of data flowing through the memory bus 40. An effect can be obtained.

  In the above configuration, the processing of the clock adjustment unit 102 may be realized by software executed by the processor 20. The operation of the clock adjustment unit 102 can be described in a program as software processing in a general processor. When the processing of the clock adjustment unit 102 is realized by software executed by the processor 20, the clock adjustment unit 102 is configured with a simpler configuration than the case where the clock adjustment unit 102 is arranged outside the processor 20. It is possible to obtain an effect equivalent to the effect obtained when the battery is arranged outside of the above.

  In the above configuration, the clock adjustment rule 101 may be recorded in the memory 50, in the processor 20, or in a memory that can read and write other information. When the processing configuration of the software executed by the processor 20 is changed, the clock adjustment rule 101 is also changed, so that more precise operation state control of the processor 20 and the memory bus interface 30 can be performed.

  In the configuration of FIG. 1, the execution position of the software in the processor 20 when starting the observation of the busy state of the processor 20 and the memory bus interface 30, and the variable processing clock generator 105 and the variable bus clock generator calculated from the observation result The clock control information issued to 106 is stored, and a clock control value is set based on the stored clock control information, thereby enabling clock adjustment without waiting for the observation period.

  In the following, “the busy state of the processor 20 and the memory bus interface 30” is also referred to as “the busy state of processing and buses”.

(Second embodiment)
The second embodiment will be described below with reference to FIGS.

  The clock adjustment storage unit 302 is calculated from the execution position of the software in the processor 20 at the time of starting the observation of the busy state of the processing and the bus, and the variable processing clock generator 105 and the variable bus clock generator 106 calculated from the observation result. The clock control information 303 including the clock control information issued to is stored. The software execution position comparison unit 401 compares the current software execution position with the stored software execution position described above, and issues an execution position match signal 412 to the clock adjustment unit 102 when the two match. The clock adjustment unit 102 has a function of notifying the variable processing clock generator 105 of the processing clock control information 113 and also notifying the variable bus clock generator 106 of the bus clock control information 114 in response to the execution position coincidence signal 412. Device.

  The current software execution position 311 can be obtained by referring to the program counter 301. The clock control information 312 is calculated from the execution position of the software in the processor 20 at the time of starting the processing output from the clock adjusting unit 102 and the observation of the busy state of the bus, and the result of the observation, and the variable processing clock generator 105. And clock control information 113 and 114 issued to the variable bus clock generator 106. The clock control information 312 may include the top execution position of software, the processing at the time of observation, and the busy state of the bus. The execution position coincidence signal 412 is a signal issued by the software execution position comparison unit 401 to the clock adjustment unit 102 when the current execution position of the software matches the execution position of the stored software described above.

  The operation of the information processing apparatus of the present embodiment configured as described above will be described below.

  Based on the busy state information 111 from the busy state identifying unit 103, the busy state information 112 from the busy state identifying unit 104, and the clock adjustment rule 101, the clock adjusting unit 102 The control information 113 and 114 are calculated (S401). Then, the clock adjustment unit 102 calculates the execution position of the software in the processor 20 when observing the busy state of processing and buses, and the variable processing clock generator 105 and the variable bus clock generator calculated from the observation result. The clock control information 312 including the clock control information 113 and 114 issued to 106 is output to the clock adjustment storage unit 302 (S402). The clock adjustment storage unit 302 generates and stores clock control information 303 based on the clock control information 312 from the clock adjustment unit 102 (S403).

  The software execution position comparison unit 401 compares the current software execution position with the previously stored software execution position (S501), and when the two match, the software execution position comparison signal 412 is sent to the clock adjustment unit 102. Is issued (S502).

  The clock adjustment unit 102 determines the presence / absence of the execution position coincidence signal 412 (S601), and when the execution position coincidence signal 412 is generated (Yes in S601), the stored clock control information 113 and 114 are variably processed. The clock generator 105 and variable bus clock generator 106 are notified (S602).

  Further, when the current processing and the busy state of the bus are different from the stored processing and the busy state of the bus (No in S603), the clock adjustment unit 102 performs processing busy based on the newly observed result. A clock control value is calculated from the idle state information 111, the bus busy state information 112, and the clock adjustment rule 101, and notified to the variable processing clock generator 105 and the variable bus clock generator 106 (S604).

  An example of the clock control information 303 stored in FIG. 7 is shown. In this example, the top 501 of the software execution position in the processor 20, the software execution position 502 when the clock is changed, the busy state 503 and the busy state 504 when the clock is changed, and the processing clock control when the clock is changed A value 505 and a bus clock control value 506 are shown. In this example, the processing busy state 503 and the bus busy state 504 at the time of the clock change are indicated by three levels of high, medium and low, and the processing clock control value 505 and the bus clock control value 506 at the time of the clock change are three values of XYZ. This is illustrated in The stored clock control information 303 is information indicating a correspondence relationship between the processing busy state 503 and the bus busy state 504, the processing clock control value 505, and the bus clock control value 506 at the software execution position 502 at the time of clock switching. is there. Further, by adding the head 501 of the software execution position, it is possible to reduce the processing for comparing the software execution position with the stored software execution position.

  With the above operation, when the busy state observation result is the same as the previous execution, the clock control is possible without delaying by the observation period. When the busy state observation result is different from the previous execution, the clock is adjusted with the newly calculated clock control value. Therefore, it is possible to adjust the processor frequency by determining the processing load based on the busy state of the processor 20 and the memory bus interface 30 during actual operation, and the processor 20 and the memory bus interface 30 can be adjusted regardless of the software configuration. Power saving control corresponding to the processing load becomes possible.

  In the configuration of FIG. 1, by notifying the clock adjusting unit 102 of the occurrence of software interrupt processing, the processing load is increased based on the busy state of the processor 20 and the memory bus interface 30 during actual operation without delaying the interrupt processing. Thus, the frequency of the processor 20 can be adjusted and power saving control corresponding to the processing load of the processor 20 and the memory bus interface 30 can be performed regardless of the software configuration.

(Third embodiment)
The third embodiment will be described below with reference to FIGS.

  The interrupt detection unit 901 detects the occurrence of a software interrupt. The interrupt detection unit 901 is a device having a function of notifying the clock adjustment unit 102 of completion of interrupt processing when processing completion is detected from an interrupt processing unit of the OS or an rti instruction of the processor. When receiving an interrupt generation signal from the interrupt detection unit 901 that detects the occurrence of interrupt processing, the clock adjustment unit 102 is a device having a function of switching the clock adjustment rule 101 to a specific clock adjustment rule 101a and generating clock control information. is there.

  The interrupt information 911 is information indicating the type of interrupt that has been notified to the clock adjustment unit 102 when the occurrence of software interrupt processing is detected. The interrupt information 911 is information indicating the type of interrupt that has been completed and is notified to the clock adjustment unit 102 when the completion of the software interrupt process is detected.

  The operation of the information processing apparatus of the present embodiment configured as described above will be described below.

  When detecting occurrence of software interrupt processing (S901), the interrupt detection unit 901 notifies the clock adjustment unit 102 of interrupt information 911 (S902). The clock adjustment unit 102 determines whether or not an interrupt process has occurred (S1001). If an interrupt process has occurred (Yes in S1001), the clock adjustment rule 101 is set to a specific clock adjustment based on the interrupt information 911. Change to rule 101a. The clock adjustment unit 102 determines a clock control value from the specific clock adjustment rule 101a and the busy state of processing and bus (S1002), and performs clock control to the variable processing clock generator 105 and the variable bus clock generator 106. Each of the information 113 and 114 is notified (S1004). If interrupt processing has not occurred (No in S1001), the clock adjustment unit 102 determines a clock control value from the normal clock adjustment rule 101 and the busy state of processing and buses (S1003), and the variable processing clock. The clock control information 113 and 114 are notified to the generator 105 and the variable bus clock generator 106 (S1004).

  The specific clock adjustment rule 101a can be defined for each interrupt type. By defining a specific clock adjustment rule 101a for each interrupt type, it is possible to prevent unnecessary power consumption.

  FIG. 11 shows an example of a specific clock adjustment rule 101a. In the example of the clock adjustment rule 101 in FIG. 2, when the value of the processor busy degree 201 or the bus busy degree 202 is medium or low, the processing clock control information output 203 and the bus clock control information output 204 The value is changed to "Increase clock frequency" setting.

  With the above operation, it is possible to adjust the frequency of the processor 20 by judging the processing load based on the busy state of the processor 20 and the memory bus interface 30 during actual operation without delaying interrupt processing. Regardless, the power saving control corresponding to the processing load of the processor 20 and the memory bus interface 30 is possible.

  In addition, by notifying the clock adjusting unit 102 of completion of interrupt processing, it is possible to perform specific clock adjustment only for interrupt processing.

  When the interrupt detection unit 901 detects completion of interrupt processing (Yes in S1201), the interrupt detection unit 901 notifies the clock adjustment unit 102 of interrupt information 911 (S1202). The clock adjustment unit 102 determines whether or not the interrupt processing is completed (S1303), and when the interrupt processing is completed and the interrupt information 911 indicating completion of the interrupt processing is obtained from the interrupt detection unit 901 (Yes in S1303). The specific clock adjustment rule 101a is changed to the normal clock adjustment rule 101. The clock adjustment unit 102 determines a clock control value from the normal clock adjustment rule 101 and the busy state of processing and bus (S1304), and performs clock control to the variable processing clock generator 105 and the variable bus clock generator 106. Each of the information 113 and 114 is notified (S1305).

  With the above operation, when software interrupt processing occurs, it becomes possible to set only the interrupt processing to a specific clock control value, and the processor 20 and the memory bus interface 30 are busy during actual operation without delaying the interrupt processing. Thus, it is possible to determine the processing load based on the above and adjust the frequency of the processor 20, and power saving control corresponding to the processing load of the processor 20 and the memory bus interface 30 becomes possible regardless of the software configuration.

  In the configuration of FIG. 1, by setting a priority for each software with respect to the software switching information and the clock adjustment rule, the clock control according to the priority becomes possible, and the software that must be completed within a certain time If there is, operation can be guaranteed.

(Fourth embodiment)
The fourth embodiment will be described below with reference to FIGS.

  The software module switching detection unit 1301 detects switching of software units operating on the processor 20 and notifies the clock adjustment unit 102 of the detected identification information 1311. Further, the software module switching detection unit 1301 defines a clock adjustment rule with a priority in which a priority is set for each software with respect to the clock adjustment rule 101. The clock adjustment unit 102 is a device having a function of determining a clock control value from a clock adjustment rule with priority corresponding to software to be executed next from the software identification information 1311 and a busy state of processing and buses.

  The software identification information 1311 is information indicating a switching time (switching timing) of software operating on the processor 20 and a software unit to be executed next.

  The operation of the information processing apparatus of the present embodiment configured as described above will be described below.

  The software module switching detection unit 1301 detects switching of software units operating on the processor 20 from the scheduler of the OS (Yes in S1501), and determines the switching time (switching timing) and the software unit to be executed next. The identification information 1311 shown is notified to the clock adjustment unit 102 (S1502). Further, the software module switching detection unit 1301 defines a priority-adjusted clock adjustment rule in which priority is set for each software with respect to the clock adjustment rule 101 (S1502). The clock adjustment unit 102 searches the software identification information 1311 for a clock adjustment rule corresponding to the software to be executed next (S1503), and the software described in the clock adjustment rule with priority is the software indicated by the software identification information 1311. If they match (Yes in S1503), a clock control value is determined from the clock adjustment rule with priority, the processing and the busy state of the bus (S1504), and the variable processing clock generator 105 and the variable bus clock generator 106 Is notified of the clock control information 113 and 114, respectively. On the other hand, when the software described in the clock adjustment rule with priority does not match the software indicated by the software identification information 1311 (No in S1503), the clock control value is determined from the normal clock adjustment rule and processing and the busy state of the bus. (S1505) and notify the variable processing clock generator 105 and the variable bus clock generator 106 of the clock control information 113 and 114, respectively.

  If the software notified from the software module switching detection unit 1301 is not in the priority clock adjustment rule, a function for adapting the normal clock adjustment rule is provided to reduce the memory for storing the priority clock adjustment rule. It becomes possible.

  In the above configuration, when multiple interrupts occur, the clock can be adjusted according to the priority of the interrupt. For example, in the case of high priority interrupt processing, high speed processing can be performed by setting the clock high.

  FIG. 16 shows an example of a clock adjustment rule with priority. In this example, the software or process name 1401 is defined by binary values A and B, the software or process priority 1402 is defined by binary values of medium and high, and the processor busyness 201 and bus busyness 202 for each software. And the processing clock control information output 203 and the bus clock control information output 204.

  With the above operation, setting the priority for each software with respect to the software switching information and the clock adjustment rule enables clock control according to the priority, and software that must complete the processing within a certain time. If there is, the operation can be guaranteed.

  In the configuration of FIG. 14, the clock adjustment can be performed more smoothly as the processing and bus busy state observation period is shorter. However, if the busy state observation period is shortened, the observation circuit must be operated at a high speed, so that power consumption is required for the busy state observation. Therefore, smooth clock control is possible by providing an observation period that matches the characteristics of the software.

(Fifth embodiment)
The fifth embodiment will be described below with reference to FIGS.

  The observation cycle rule 1601 for each software module defines a processing observation cycle value and a bus observation cycle value for each software unit operating on the processor 20. The processing busy state identifying unit 103 and / or the bus busy state identifying unit 104, or both, is a device having a function of observing by changing the above-described observation period every time the software is switched.

  The operation of the information processing apparatus of the present embodiment configured as described above will be described below.

  The observation cycle rule 1601 for each software module defines a processing observation cycle value and a bus observation cycle value for each software unit operating on the processor 20. The software module switching detection unit 1301 determines whether or not software switching has occurred from the scheduler of the OS (S1801), and when software switching occurs (Yes in S1801), the software identification information 1311 is transferred to the clock adjustment unit 102. (S1802). The processing busy state identifying unit 103 or the bus busy state identifying unit 104 determines whether or not the software indicated by the software identification information 1311 notified from the software module switching detection unit 1301 is described in the observation cycle rule 1601 for each software. Judgment is made (S1803). The processing busy state identifying unit 103 or the bus busy state identifying unit 104 is defined by the observation cycle rule when the software indicated by the notified software identification information 1311 is described in the observation cycle rule 1601 (Yes in S1803). According to the observation cycle, the busy state of processing and buses is observed (S1804).

  When the software indicated by the software identification information 1311 notified from the software module switching detection unit 1301 does not exist in the observation cycle rule 1601 for each software (No in S1803), the busy state of processing and buses is observed at a normal observation cycle. (S1805). Thereby, the memory used for defining the observation cycle rule for each software can be reduced.

  FIG. 19 shows an example of processing for each software and a bus busy state observation cycle rule. In this example, the processing for the software type 1901 and the observation cycle 1902 of the bus are exemplified by three values of XYZ. An observation cycle rule for processing busy state observation and an observation cycle rule for bus busy state observation may be individually defined.

  With the above operation, it is possible to adjust the frequency of the processor 20 by judging the processing load based on the busy state of the processor 20 and the memory bus interface 30 during actual operation while performing smooth clock control. Regardless of the configuration, power consumption corresponding to the processing load of the processor 20 and the memory bus interface 30 becomes possible.

  The information processing apparatus of the present invention is useful as an apparatus for performing image processing such as MPEG decoding processing.

Configuration diagram of information processing apparatus in first embodiment Illustration of clock adjustment rule 101 Configuration diagram of information processing apparatus in second embodiment Clock control value calculation flow explanation diagram when storing clock control information Flow diagram when software execution position coincidence signal is generated Clock control value calculation flow explanatory diagram when reading stored clock control information The figure which shows an example of the stored clock control information 303 Configuration diagram of information processing apparatus in third embodiment First explanatory diagram of the flow of calculating the clock control value when the occurrence of an interrupt is detected Second explanatory diagram of the flow of calculating the clock control value when the occurrence of an interrupt is detected The figure which shows an example of the specific clock adjustment rule 101a First explanatory diagram of a flow of calculating a clock control value when detecting completion of an interrupt Second explanatory diagram of the flow of calculating the clock control value when the completion of interrupt is detected Configuration diagram of information processing apparatus according to fourth embodiment Clock control value calculation flow explanation when software switching is detected The figure which shows an example of the clock adjustment rule with a priority Configuration diagram of information processing apparatus according to fifth embodiment Illustration of flow of calculation of observation period when processing for each software and bus busy state observation period is set The figure which shows an example of the processing for every software, and the busy state observation cycle rule of a bus

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Clock control part 20 Processor 30 Memory bus interface 40 Memory bus 50 Memory 101 Clock adjustment rule 102 Clock adjustment part 103 Processing busy state identification part 104 Bus busy state identification part 105 Variable processing clock generator 106 Variable bus clock generator 111 Processing busy state information 112 Bus busy state information 113 Processing clock control information 114 Bus clock control information 115 Processor supply clock 116 Bus supply clock 301 Program counter 302 Clock adjustment storage unit 303 Stored clock control information 401 Software execution position comparison unit 311 Current software execution position 312 Clock control information 412 Software execution position match information 901 Interrupt detection unit 911 Interrupt information 1301 Soft Software module switching detection unit 1601 observation period rule for each software module 1311 software identification information 201 processor busyness 202 bus busyness 203 processing clock control information output 204 bus clock control information output 501 top of execution position of software 502 clock change Software execution position 503 Measured processing busyness 504 Measured bus busyness 505 Processing clock control value 506 Bus clock control value 1401 Software or processing name 1402 Software or processing priority 1901 Software type 1902 Observation period

Claims (14)

A processor;
Memory,
A bus interface that arbitrates access to the memory of the processor;
A variable processing clock generator for supplying an operation clock necessary for the operation of the processor to the processor;
A variable bus clock generator for supplying an operation clock necessary for the operation of the bus interface to the bus interface;
A processing busy state identifying unit for identifying busyness of operation of the processor;
A busy / busy state identifying unit for identifying busy / busy operation of the bus interface;
A rule storage unit storing a clock adjustment rule in which a plurality of clock control information for optimally operating the processor and the bus interface according to the busyness of each of the processor and the bus interface is stored;
Among the clock adjustment rules, the processing busy information indicating the result obtained by the processing busy state identifying unit and the bus busy state identifying unit and the clock control information corresponding to the bus busy information are the variable processing. A clock generation unit and a clock adjustment unit that outputs to the variable bus clock generation unit,
The variable processing clock generation unit and the variable bus clock generation unit generate an operation clock according to clock control information from the clock adjustment unit. The processor has a cache;
The information processing apparatus according to claim 1, wherein the processing busy state identifying unit identifies busyness of operation of the processor based on an access state to the cache. The processor has an accumulator;
The information processing apparatus according to claim 1, wherein the processing busy state identifying unit identifies busyness of operation of the processor based on a use frequency of the accumulator. 2. The information processing apparatus according to claim 1, wherein the bus busy state identifying unit identifies a busy state of operation of the bus interface based on a number of occurrences per unit time of a strobe signal generated by the bus interface to the memory. . The information processing apparatus according to claim 1, wherein the clock adjustment unit is configured by software in the processor. The information processing apparatus according to claim 1, wherein the clock adjustment rule is stored in the processor. The information processing apparatus according to claim 6, wherein the clock adjustment rule is rewritable by the processor. Furthermore,
The execution position of the software in the processor at the start of identification of busyness of the operation of the processor by the busy state identification unit of processing and identification of busyness of the operation of the bus interface by the busy state identification unit of bus A clock adjustment storage unit that stores clock control information calculated from the identification result and issued to the variable processing clock generation unit and the variable bus clock generation unit;
A software execution position comparison unit that compares the execution position of the current software with the execution position of the software stored in the clock adjustment storage unit, and issues an execution position match signal to the clock adjustment unit when the two match And
The information processing apparatus according to claim 1, wherein the clock adjustment unit issues clock control information stored in the clock adjustment storage unit when the execution position coincidence signal is issued. Furthermore, an interrupt detection unit for detecting occurrence of software interrupt processing is provided,
The information processing apparatus according to claim 1, wherein the clock adjustment unit issues specific clock control information when receiving a software interrupt generation notification from the interrupt detection unit. When detecting the end of the interrupt process, the interrupt detection unit issues an interrupt end notification to the clock adjustment unit,
When the clock adjustment unit receives the interrupt end notification from the interrupt detection unit, the clock adjustment information in the clock adjustment rule includes clock control information corresponding to the processing busy information and the bus busy information in the variable processing. The information processing apparatus according to claim 9, wherein the information processing apparatus outputs the data to a clock generation unit and the variable bus clock generation unit. Further, a switching detection unit that detects switching of software operating on the processor and notifies the clock adjustment unit of switching time and identification information of software to be executed next,
When the clock adjusting unit receives a notification from the switching detection unit, the clock corresponding to the processing busy information and the bus busy information in the clock adjustment rule corresponding to the software to be executed next The information processing apparatus according to claim 1, wherein control information is output to the variable processing clock generation unit and the variable bus clock generation unit. And a storage unit for storing observation period values for each piece of software running on the processor,
The at least one of the processing busy state identifying unit and the bus busy state identifying unit identifies the busy state of operation by changing the observation period based on the observation period value every time the software is switched. The information processing apparatus described. A variable processing clock generation step for supplying an operation clock necessary for the operation of the processor to the processor;
A variable bus clock generation step for supplying the bus interface with an operation clock necessary for the operation of the bus interface for arbitrating access to the memory of the processor;
A processing busy state identifying step for identifying busyness of operation of the processor;
A bus busy state identifying step for identifying busyness of operation of the bus interface;
The processing busy state identification in a clock adjustment rule in which a plurality of clock control information for optimally operating the processor and the bus interface according to busyness of each of the processor and the bus interface is described. A clock adjustment step of outputting clock control information corresponding to the bus busy information and processing busy information indicating the result obtained in the step and the bus busy state identifying step,
In the variable processing clock generation step and the variable bus clock generation step, an operation clock is generated according to the clock control information output in the clock adjustment step. A bus interface that arbitrates access to the processor's memory;
A variable processing clock generator for supplying an operation clock necessary for the operation of the processor to the processor;
A variable bus clock generator for supplying an operation clock necessary for the operation of the bus interface to the bus interface;
A processing busy state identifying unit for identifying busyness of operation of the processor;
A busy / busy state identifying unit for identifying busy / busy operation of the bus interface;
A rule storage unit storing a clock adjustment rule in which a plurality of clock control information for optimally operating the processor and the bus interface according to the busyness of each of the processor and the bus interface is stored;
Among the clock adjustment rules, the processing busy information indicating the result obtained by the processing busy state identifying unit and the bus busy state identifying unit and the clock control information corresponding to the bus busy information are the variable processing. A clock generation unit and a clock adjustment unit that outputs to the variable bus clock generation unit,
The variable processing clock generation unit and the variable bus clock generation unit generate an operation clock according to clock control information from the clock adjustment unit.

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