JP2007257067A - Automatic design device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic design device which can design a semiconductor integrated circuit having satisfactory characteristics by carrying out rough wiring under the consideration of process information. <P>SOLUTION: This automatic design device is provided with a layout information preparing part 1 for arranging a plurality of delay cells by folding them multiple times by using delay cell layout having a plurality of transistor patterns and an rough wiring part 12 for carrying out the rough wiring of the plurality of delay cells by deciding the deviation of the inter-gate capacity of each of the plurality of transistor patterns from the process information. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a design technique of a semiconductor integrated circuit, and more particularly to an automatic design apparatus and an automatic design method for designing an analog circuit and an analog / digital mixed circuit.

  The television signal processing circuit normally includes a delay circuit that delays the video signal with high accuracy in the horizontal synchronization period. There are both analog signals and digital signals as video signals. A delay circuit for delaying a digital signal with high accuracy can be constituted by a multistage connection of inverters, a CR delay circuit, and the like. A delay circuit that delays an analog signal with high accuracy can be configured by connecting a plurality of delay cells each including a capacitor and a write / read transistor connected to the capacitor.

  In addition, the automatic design technology in digital circuits has progressed dramatically, and the layout creation of semiconductor integrated circuits has been automated. When designing a delay circuit, various methods have been proposed for automatic design of a delay circuit that delays a digital signal (see, for example, Patent Document 1). On the other hand, a technology for automatically designing the layout of an analog circuit and an analog / digital mixed circuit has been put into practical use.

However, in an analog circuit and an analog / digital mixed circuit, it is necessary to sufficiently satisfy required characteristics and accuracy. Therefore, when automatically designing the layout of analog circuits and analog / digital mixed circuits, a small error that does not cause a problem with digital circuits, that is, an error between the circuit constant of each element and the design value due to process variation It is also necessary to consider.
JP 2001-230324 A

  An object of the present invention is to provide an automatic design apparatus and an automatic design method capable of designing a semiconductor integrated circuit having good characteristics by performing schematic wiring in consideration of process information.

  The first feature of the present invention is that (a) an arrangement information generating unit that arranges a plurality of delay cells by using a delay cell layout having a plurality of transistor patterns, and (b) a plurality of transistor patterns from process information. The gist of the invention is that the automatic design apparatus includes a schematic wiring unit that performs schematic wiring of a plurality of delay cells by determining the deviation of the capacitance between the gates.

  The second feature of the present invention is that (a) the arrangement information creating unit arranges a plurality of delay cells by diffusing a plurality of delay cells using a delay cell layout having a plurality of transistor patterns stored in the data storage device. (B) The schematic wiring unit determines the bias of the inter-gate capacitance of each of the plurality of transistor patterns from the process information stored in the data storage device, and determines the schematic wiring of the plurality of delay cells. The gist of the present invention is an automatic design method including a step of determining a pattern and storing it in a data storage device.

  ADVANTAGE OF THE INVENTION According to this invention, the automatic design apparatus and automatic design method which can design the semiconductor integrated circuit which has a favorable characteristic by performing the rough wiring which considered process information can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings in this embodiment, the same or similar parts are denoted by the same or similar reference numerals.

(Automatic design equipment)
As shown in FIG. 1, an automatic design apparatus according to an embodiment of the present invention includes a central processing unit (CPU) 1, a data storage device 6, an input device 2, an output device 3, a main storage device 4, and an auxiliary storage. A device 5 is provided. The data storage device 6, the input device 2, the output device 3, the main storage device 4, and the auxiliary storage device 5 are connected to the CPU 1, respectively. The CPU 1 includes an arrangement information creation unit 11 and a schematic wiring unit 12. The arrangement information creation unit 11 arranges a plurality of delay cells by diffracting a plurality of delay cells using a delay cell layout having a plurality of transistor patterns. The schematic wiring unit 12 determines the bias of the inter-gate capacitance of each of the plurality of transistor patterns from the process information, and performs schematic wiring of the plurality of delay cells. Here, “process information” means, for example, process information adopted in the manufacturing process of the circuit to be designed. “Gate-capacitance” means, for example, a gate-source capacitance _CGS and a gate-drain capacitance _CGD .

As an example of the process information, for example, information on an incident angle of ion implantation with respect to a chip surface of a semiconductor chip in an ion implantation process is given. When the incident angle of ion implantation is not perpendicular to the chip surface of the semiconductor chip, there is a difference in characteristics between the source and drain of the transistor mounted on the semiconductor chip. For example, when ion implantation is performed when forming the drain and gate of a MOS transistor, the impurity density in the region behind the gate polysilicon on the semiconductor chip is lowered. As a result, the gate-source capacitance and the gate-drain capacitance of the MOS transistor mounted on the semiconductor chip are biased. Schematic wiring section 12 determines each of the bias of the gate-source capacitance C _GS and the gate-drain capacitance C _GD of the plurality of transistors patterns from the process information, the capacity C _GS and the gate-drain between the gate and the source by a wire Compensate for the bias of the inter-capacitance _CGD .

The automatic design apparatus shown in FIG. 1 is used when, for example, as shown in FIG. 2, a schematic layout of a delay circuit having repetitions of circuit blocks (delay cells) having the same configuration is automatically designed. The delay circuit shown in FIG. 2 includes a plurality of (first to kth) delay cells 7a to 7k connected in series, and a charge / voltage conversion circuit connected to the last delay cell 7k of the plurality of delay cells 7a to 7k. 73 (k; an integer of 2 or more). The first delay cell 7a includes a read transistor M1a, a write transistor M2a, first and second clocked inverters 71a and 72a, and a capacitor C1. An n-channel MOS transistor is used as the read transistor M1a and the write transistor M2a. One end of the capacitor C1 is connected to the ground. The read transistor M1a has a drain connected to the second signal line 75, a gate connected to the sampling data line 76, and a source connected to the capacitor C1. The read transistor M1a has a source connected to the second signal line 75, a gate connected to the inputs of the first and second clocked inverters 71a and 72a, and a drain connected to the capacitor C1. The write transistor M2a has a source connected to the capacitor C1, a gate connected to the outputs of the first and second clocked inverters 71a and 72a, and a drain connected to the first signal line 74. As shown in FIG. 3, the write transistor M2a has a gate-drain capacitance between the drain connected to the first signal line 74 and the gate connected to the outputs of the first and second clocked inverters 71a and 72a. _{Has CGD} . The read transistor M1a has a gate-source capacitance C _GS between the source connected to the second signal line 75 and the gate connected to the inputs of the first and second clocked inverters 71a and 72a.

  Also, the first and second clocked inverters 71a and 72a shown in FIG. 2 control the operation timing of the write transistor M2a and the read transistor M1a by shifting the sampling data pulse SP from the outside. The write transistor M2a transmits the input voltage Vi from the first signal line 74 to the capacitor C1. The capacitor C1 charges the transmitted input voltage Vi. The read transistor M1a transmits the charge charged in the capacitor C1 to the second signal line 75. The charge / voltage conversion circuit 73 converts the charge from the second signal line 75 into a voltage and generates an output voltage Vo.

The arrangement information creation unit 11 illustrated in FIG. 1 includes a data acquisition unit 111, a cell number calculation unit 112, a folding number calculation unit 113, and an arrangement unit 114. The data acquisition unit 111 acquires request delay time, delay cell layout, process information, and sampling frequency information. “Sampling frequency” means a frequency required for sampling an analog signal input to a circuit to be designed. The cell number calculation unit 112 calculates the required number of delay cells from the required delay time and sampling frequency information. Here, if the required delay time is T _delay and the sampling frequency is f _s , the required number of cells N _cell is:

_{N cell = f s / (1} / T delay) ··· (1)

It becomes. The folding number calculation unit 113 calculates the number of folding times of a plurality of delay cells from the required number of cells. The placement unit 114 places a plurality of delay cells according to the number of times of folding using the delay cell layout. As a result, arrangement information is created by the arrangement unit 114.

  The delay cell layout LR used when automatically designing the layout of the delay circuit shown in FIG. 2 includes a capacitor pattern CP, a first transistor pattern ML1, a second transistor pattern ML2, a first clock, as shown in FIG. And a second clocked inverter pattern INV2. In the example shown in FIG. 3, the internal layout of the first clocked inverter pattern INV1 and the second clocked inverter pattern INV2 is not shown. The first transistor pattern ML1 includes a first source / drain region S / D1, a gate region G1, and a second source / drain region S / D2. The second transistor pattern ML2 is configured similarly to the first transistor pattern ML1.

  Further, as shown in FIG. 1, the schematic wiring unit 12 includes a signal line wiring unit 121, a gate capacitance determination unit 122, a wiring pattern selection unit 123, and an internal wiring unit 124. The signal line wiring unit 121 performs wiring processing for a plurality of signal lines via each of the plurality of arranged delay cell layouts. Based on the process information, the gate capacitance determination unit 122 determines regions having the same inter-gate capacitance value in the plurality of transistor patterns in the plurality of arranged delay cell layouts. The wiring pattern selection unit 123 selects internal wiring patterns of a plurality of delay cells based on the determination result of the gate capacitance determination unit. The internal wiring unit 124 performs internal wiring of a plurality of delay cells using the internal wiring pattern.

  Further, as shown in FIG. 5, the data storage device 6 shown in FIG. 1 has a required delay time storage area 61, a sampling frequency storage area 62, a delay cell layout storage area 63, a process information storage area 64, and an arrangement information storage area 65. A signal line library storage area 66, an internal wiring pattern storage area 67, and a schematic layout storage area 68. The request delay time storage area 61 stores request delay time data. The sampling frequency storage area 62 stores sampling frequency information. The delay cell layout storage area 63 stores a delay cell layout. The process information storage area 64 stores process information. The arrangement information storage area 65 stores arrangement information created by the arrangement unit 114 shown in FIG. The signal line library storage area 66 stores the signal line library. The internal wiring pattern storage area 67 stores internal wiring pattern data. The schematic layout storage area 68 stores a schematic layout created by the internal wiring unit 124 shown in FIG. However, the information stored in the data storage device 6 may be included in the auxiliary storage device 5 shown in FIG.

  The automatic design apparatus shown in FIG. 1 includes a database control device and an input / output control device that are not shown. The database control device searches the data storage device 6 for necessary file storage locations, and performs reading and writing. On the other hand, the input / output control device receives data from the input device 2 and transmits it to the CPU 1. That is, the input / output control device is an interface that connects the CPU 1 to the input device 2, the output device 3, or the reading device of the auxiliary storage device 5 such as a CD-ROM, a magneto-optical disk (MO), or a flexible disk. From the viewpoint of data flow, the input / output control device serves as an interface between the input device 2, the output device 3, the auxiliary storage device 5, and the external storage device reading device and the main storage device 4. The input / output control device receives data from the CPU 1 and transmits it to the output device 3, the auxiliary storage device 5, and the like.

  Further, as the input device 2 shown in FIG. 1, for example, a recognition device such as a keyboard, a mouse, an optical character reader (OCR), a graphic input device such as an image scanner, and a special input device such as a voice recognition device are used. it can. As the output device 3, for example, a display device such as a liquid crystal display or a CRT display, or a printing device such as an ink jet printer or a laser printer can be used. The main storage device 4 includes a ROM and a RAM. The ROM functions as a program storage device that stores a program executed in the CPU 1. On the other hand, the RAM functions as a temporary data memory or the like that temporarily stores data used during the program execution process in the CPU 1 or is used as a work area.

(Automatic design method)
Next, an automatic design method according to an embodiment of the present invention will be described with reference to the flowchart of FIG.

  (A) In step S101 of FIG. 6, the data acquisition unit 111 shown in FIG. 1 makes a request from the requested delay time storage area 61, sampling frequency storage area 62, delay cell layout storage area 63, and process information storage area 64 shown in FIG. Delay time, delay cell layout, process information, and sampling frequency information are acquired. In step S102, the cell number calculation unit 112 calculates the required cell number of the plurality of delay cells 7a to 7k shown in FIG. 2 from the equation (1) based on the required delay time and sampling frequency acquired in step S101. For example, when the required delay time is 64 [μs] and the sampling frequency is 2.5 [MHz], the required number of cells is 160 cells from Equation (1).

  (B) In step S103, the folding number calculation unit 113 calculates the number of foldings of the plurality of delay cells 7a to 7k from the required number of cells calculated in step S102. The folding number calculation unit 113 calculates the number of foldings so that, for example, the layout when the plurality of delay cells 7a to 7k are folded back and arranged is within a rectangular area. In step S104, the placement unit 114, as shown in FIG. 7, uses the delay cell layout shown in FIG. 4 and a plurality of delay cell layouts LR1,..., LR2, LR3,. ..., LR4, ... are arranged. The arrangement information created in step S104 is stored in the arrangement information storage area 65 shown in FIG.

  (C) In step S105, the signal line wiring unit 121 shown in FIG. 1 uses the signal line library stored in the signal line library storage area 66 shown in FIG. A plurality of signal lines, that is, the sampling data line 76, the first signal line 74, and the second signal line 75 are subjected to wiring processing on the arrangement information stored in the data. In FIG. 8, only the delay cell layouts LR2 and LR3 shown in FIG. 7 are illustrated.

  (D) In step S106, the gate capacity determination unit 122 determines the delay cell layouts LR1,... LR2, LR3,. .. Inside of plural transistor patterns ML1a, ML2a,..., ML1b, ML2b, ML1c, ML2c,..., ML1d, ML2d,. Regions having the same gate-to-gate capacitance value are determined. For example, inclined ion implantation is performed from the delay cell layouts LR2 and LR3 side of the plurality of delay cell layouts LR1,..., LR2, LR3,. When the process information is obtained, each of the first source / drain shared areas S / D1a, S / D3a, S / D1b, S / D3b, S / D1c, S / D3c, S / D1d, and S / D3d It is determined that the inter-gate capacitance is equal. Similarly, the capacitances between the gates of the second source / drain shared areas S / D2a, S / D4a, S / D2b, S / D4b, S / D2c, S / D4c, S / D2d, and S / D4d are the same. It is determined.

  (E) In step S107, the wiring pattern selection unit 123 connects each of the first signal line 74 and the second signal line 75 shown in FIG. 8 to the region having the same inter-gate capacitance value according to the determination result in step S106. The wiring pattern to be selected is selected from the internal wiring pattern library. As a result, in the example shown in FIG. 9, the internal wiring pattern for connecting the second source / drain shared areas S / D2b and S / D4c and the first signal line 74 is selected. The internal wiring pattern that connects the first source / drain shared regions S / D3b and S / D1c and the second signal line 75 is selected. In the example shown in FIG. 10, the internal wiring pattern that connects the second source / drain shared areas S / D2b and S / D2c and the first signal line 74 is selected. The internal wiring pattern that connects the first source / drain shared areas S / D3b and S / D3c and the second signal line 75 is selected. In step S108, the internal wiring unit 124 performs wiring processing on the other internal wirings shown in FIGS. The schematic layout created in step S108 is stored in the schematic layout storage area 68 shown in FIG.

  As described above, according to the embodiment of the present invention, it is possible to provide an automatic design apparatus and an automatic design method capable of designing a semiconductor integrated circuit having good characteristics by performing schematic wiring in consideration of process information. In addition, since a plurality of delay cell layouts are arranged in a folded manner, a delay circuit can be designed with the same delay cell layout.

(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the above-described embodiment, the delay cell layout has been described as being stored in advance in the delay cell layout storage area 63 shown in FIG. However, a delay cell layout may be automatically created from a program description, a hardware description language (HDL), or the like.

  Further, the n-channel MOS transistors are used as the write transistors M2a to M2k and the read transistors M1a to M1k shown in FIG. 2, but p-channel MOS transistors may be used.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

It is a block diagram which shows the structure of the automatic design apparatus which concerns on embodiment of this invention. It is a circuit diagram which shows an example of the delay circuit to which the automatic design apparatus which concerns on embodiment of this invention is applied. FIG. 3 is a circuit diagram showing a part of the delay circuit shown in FIG. 2. It is a schematic diagram which shows an example of the delay cell layout which concerns on embodiment of this invention. It is a block diagram which shows the structure of the data storage device which concerns on embodiment of this invention. It is a flowchart which shows the automatic design method which concerns on embodiment of this invention. It is a schematic diagram for demonstrating the automatic design method which concerns on embodiment of this invention. It is a schematic diagram for demonstrating the automatic design method which concerns on embodiment of this invention. It is a schematic diagram for demonstrating the automatic design method which concerns on embodiment of this invention. It is a schematic diagram for demonstrating the automatic design method which concerns on embodiment of this invention.

Explanation of symbols

1 ... CPU
DESCRIPTION OF SYMBOLS 11 ... Arrangement information creation part 12 ... Outline wiring part 111 ... Data acquisition part 112 ... Cell number calculation part 113 ... Return count calculation part 114 ... Arrangement part 121 ... Signal line wiring part 122 ... Gate capacity determination part 123 ... Wiring pattern selection part 124 ... Internal wiring part

Claims (5)

An arrangement information creating unit that folds a plurality of delay cells using a delay cell layout having a plurality of transistor patterns, and
An automatic design apparatus comprising: a schematic wiring unit that determines a bias of inter-gate capacitance of each of the plurality of transistor patterns from process information and performs schematic wiring of the plurality of delay cells. The arrangement information creating unit
A data acquisition unit for acquiring the required delay time, the delay cell layout, the process information, and sampling frequency information;
A delay cell number calculating unit for calculating a required number of the plurality of delay cells from the required delay time and the sampling frequency information;
A number-of-returns calculation unit for calculating the number of times of return of the plurality of delay cells from the required number of cells;
The automatic design apparatus according to claim 1, further comprising: an arrangement unit that arranges the plurality of delay cells according to the number of times of folding using the delay cell layout. The schematic wiring portion is
A signal line wiring unit for wiring a plurality of signal lines through each of the plurality of delay cell layouts arranged using a signal line library;
Based on the process information, a gate capacitance determination unit that determines a region having the same inter-gate capacitance value inside the plurality of transistor patterns in the plurality of arranged delay cell layouts;
A wiring pattern selection unit that selects an internal wiring pattern of the plurality of delay cells from an internal wiring pattern library based on a determination result of the gate capacitance determination unit;
The automatic design apparatus according to claim 1, further comprising: an internal wiring unit that performs internal wiring of the plurality of delay cells using the internal wiring pattern.   The automatic design apparatus according to claim 3, wherein the wiring pattern selection unit selects the internal wiring pattern that connects each of the plurality of signal lines and a region having the same inter-gate capacitance value. A step of arranging a plurality of delay cells by using a delay cell layout having a plurality of transistor patterns stored in the data storage device by the arrangement information creating unit, and storing the arrangement information in the data storage device;
The schematic wiring unit determines a bias pattern of the inter-gate capacitance of each of the plurality of transistor patterns from the process information stored in the data storage device, determines a schematic wiring pattern of the plurality of delay cells, and the data storage device And storing the data in an automatic design method.

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