JP2007251576A - Communication switch device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication switch device which can use a general industrial network (for example, Ethernet(R), etc.) without the necessity of a special function for each node composing the network, moreover can guarantee a real time property of cyclic information. <P>SOLUTION: The device is provided with a buffer which stores cyclic information received from a high rank port in a circuit-use time zone of the other communication switch device, and I/O data received from low rank ports at any time; and a means which reads out the newest information of the I/O data stored in the buffer in an own circuit-use time zone, and transmits it to the high rank port. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a communication switch device (switching hub) suitable for a network (for example, Ethernet (registered trademark) / IP) that cyclically communicates real-time data (I / O data and the like).

Conventionally, in industrial Ethernet (registered trademark), in order to guarantee the real-time property of cyclic information, a method of performing QOS control using a communication switch device (first method) or Ethernet (registered trademark) is used. In each of the corresponding devices, a method (second method) for avoiding congestion by time-dividing the transmission timing is adopted (see Patent Document 1).
JP 2001-244987

  However, in the first method described above, the worst state of traffic applied to the communication switch device is when all nodes perform transmission operations simultaneously. Also in this case, in order to guarantee no packet loss and latency, only a very small bandwidth is used by limiting the transmission operation of the node (for example, setting the transmission interval to 10 msec). In some cases, the number of nodes may be limited. This tendency becomes remarkable when a lot of multicast is used.

  On the other hand, in the above-mentioned second method, since the clocks synchronized with the entire system must be held at each node, the synchronization function must be realized in hardware, and with a considerably high accuracy. This is usually required. For this reason, each node must have a special function, which increases the cost of each node.

  In addition, each node must transmit a packet only at the time set by the bus management station in the initial setting, and each node must have a special function. This also increases the cost of the node. Is done.

  The present invention has been made by paying attention to such conventional problems, and the object of the present invention is that each node constituting the network does not require a special function and is used for general industrial use. It is an object of the present invention to provide a communication switch device that can use a network (for example, Ethernet (registered trademark)) and can guarantee the real-time property of cyclic information.

  Other objects and effects of the present invention will be easily understood by those skilled in the art by referring to the following description of the specification.

  In order to achieve the above object, the present invention employs the following configuration. That is, the communication switch device of the present invention is a means for sequentially allocating a cyclic line use time zone between an upper port for connecting to another communication switch device and another communication switch device. A lower port for connecting a node that handles I / O data, cyclic information received from the upper port during the line usage time of another communication switching device, and I / O data received from the lower port as needed And a means for reading the latest information of the I / O data stored in the buffer during its own line use time period and transmitting it to the upper port.

  According to such a configuration, the buffer for storing the cyclic information received from the upper port and the I / O data received from the lower port at any time during the line use time of another communication switch device, and the own line use time Since it has a means to read the latest information of I / O data stored in the buffer in the band and send it to the upper port, each node constituting the network does not need a special function, and can be used in general industries. Network (for example, Ethernet (registered trademark)) can be used, and the real-time property of cyclic information can be guaranteed.

  In a preferred embodiment, it may further have a start register and an end register for registering the start time and end time of the line use time zone. According to such a configuration, by connecting an appropriate support tool, the line usage time zone can be freely set according to the communication scheduled packet of each node.

  In the preferred embodiment, the node connected to the lower port may be a PLC. According to such a configuration, the real-time property of the cyclic information in the PLC system can be guaranteed.

  According to the communication switch device of the present invention, each node constituting the network can use a general industrial network (for example, Ethernet (registered trademark)) without requiring a special function. Moreover, the real-time property of the cyclic information can be guaranteed.

  Hereinafter, a preferred embodiment of a communication switch device according to the present invention will be described in detail with reference to the accompanying drawings.

  An example of a system configuration to which the communication switch device of the present invention is applied is shown in FIG.

  In the illustrated system, three communication switch devices 11, 12, and 13 are shown. These communication switch devices 11, 12, and 13 are connected via an industrial network (for example, Ethernet (registered trademark) / IP).

  In this example, each of the communication switch devices 11, 12, 13 is provided with a maximum of four lower ports P11, P12, P13, P14 and two upper ports P01, P02.

  More specifically, in the case of the communication switch device 11 located at the left end in the figure, the lower port P11 has a programmable controller (hereinafter referred to as PLC) 111 as a node, the lower port P12 has a node 112, and the lower port. Nodes 113 are connected to P13. Examples of these nodes 112 and 113 include a remote I / O unit connected to the PLC 11.

  Similarly, in the case of the communication switch device 12 located in the middle in the figure, nodes 121, 122, 123, and 124 are connected to the lower ports P11, P12, P13, and P14, respectively. As these nodes, for example, a remote I / O unit of the PLC 11 can be cited.

  Similarly, in the case of the communication switch device 13 positioned at the right end, the lower port P11 is connected to the node 131, and the other lower ports are also connected to the node.

  On the other hand, the upper port P02 of the communication switch device 12 located in the middle of the figure is connected to the upper port P01 of the communication switch device 11 located at the left end in the figure. Similarly, the upper port P02 of the communication switch device 13 located at the right end in the figure is connected to the upper port P01 of the communication switch device 12 located in the middle of the figure.

  As described above, according to this network, a single PLC 111 and a plurality of nodes 112, 113, 121 to 124, 131 are connected by a network, and cyclic data exchange is performed between these nodes. Has been made possible.

  In the following description, four nodes 121, 122, 123, and 124 connected to the communication switch device 12 located at the center in the figure have addresses #a, #b, #c, and # as addresses. Each d is assigned. The node 121 to which the address #a is assigned is set to handle two types of real-time packets including a real-time packet (priority # 1) and a real-time packet (priority # 2).

  Similarly, the node 122 to which the address #b is assigned is set to handle one type of real-time packet that is a real-time packet (priority # 1). Similarly, the node 123 to which the address #c is assigned is set to handle one type of real-time packet that is a real-time packet (priority # 2). Similarly, the node 124 to which the address #d is assigned is set to handle one type of real-time packet that is a real-time packet (priority # 1).

  A configuration diagram of the communication switch devices 11, 12, and 13 is shown in FIG. As shown in the figure, each of the communication switch devices 11, 12, and 13 has the same configuration, and a real-time guarantee processing unit A, a time synchronization processing unit B, a switch logic unit C, It has four lower ports P11 to P14 and two upper ports P01 and P02.

  In the real-time guarantee processing unit A, a transfer packet registration table TBL is provided as shown in FIG. In the registration table TBL, as shown in FIGS. 2 and 3, a buffer for #a, a buffer for #b, a buffer for #c corresponding to the node address connected to each of the lower ports P01 to P04. , #D buffers are provided.

  An explanatory diagram of the transfer packet registration table is shown in FIG. As is clear from the figure, the type of transfer packet and the packet size are registered in each of the #a to #d buffers. That is, as described above, for node address #a, real-time packet # 1 having a packet size of 128 bytes and real-time packet # 2 having a packet size of 64 bytes are registered. Similarly, a real-time packet # 1 having 64 bytes is registered for the node address #b. Similarly, for node address #c, real-time packet # 2 having 256 bytes is registered. Similarly, for node address #d, real-time packet # 1 having 256 bytes is registered. Note that a MAC address or an IP address is used as the node address referred to here.

  On the other hand, in the time synchronization processing unit B, the synchronization time generation unit B1, the own switch line use permission start time register B21, the own switch line use permission end time register B22, the idle start time register B23, An end time register B24 is incorporated.

  The synchronization time generation unit B1 generates time information synchronized in the system (for example, time synchronization by IEEE 1588 is supported). Note that packet transfer related to time synchronization is performed during idle time. This is for avoiding the influence of the processing of the switch in the present invention. Hereinafter, a packet related to time synchronization is described as being included in a general packet.

  That is, in each of the registers B21, B22, B23, and B24, as shown in FIGS. 11 to 13, the line use permission start time of the own switch, the line use permission end time of the own switch, Start time and idle end time are set respectively. In these setting examples, when the minimum unit of time is changed to 1 μsec, the line use permission time and the idle time of each switch are assigned to the range of 1 to 65 msec. The time synchronization processing unit B is configured to generate a timing signal for realizing the determined time management based on the setting data of the registers B21 to B24 and the synchronization time generation unit B1. Has been.

  FIG. 14 is an explanatory diagram showing an example of the format shown in FIGS. 11 to 13 and an example of a timetable generated correspondingly. As shown in the figure, according to the present invention, the line usage permission time of the switch A → the line of the switch B based on the contents of the lower 16 bits of the synchronization time of each setting data shown in FIGS. Use permission time → Switch C line use permission time → Idle → Switch A line use permission time → Switch B line use permission time → Switch C line use permission time Time is allocated. Here, as shown in FIG. 9, the switches A, B, and C mean three communication switch devices arranged from the left in the figure.

  Returning to FIG. 2, the switch logic unit C is composed of, for example, a switch LSI, and controls the connection between the four lower ports P11 to P14 and the two upper ports P01 and P02 connected thereto. Is. Here, the upper ports P01 and P02 are ports that forward received packets to other ports (both the upper port and the lower port), and also perform normal switching operations. On the other hand, the lower ports P11 to P14 are ports having a function of buffering received real-time packets for each node address or the like. Here, when the destination of the packet received at the lower port is a unicast addressed to the lower port, the packet may be forwarded without being stored in the buffer. In this case, if it is multicast, it is stored in the cyclic transfer buffer. Also, all packets addressed from the upper port to the lower port are immediately forwarded regardless of the time zone.

  As will be described in detail later, the real-time cyclic transfer packets received by the lower ports P11 to P14 are stored in the corresponding buffers (#a buffer to #d buffer). Note that there is one buffer assigned to #a to #c, and when a cyclic transfer packet newly arrives from a lower port, the real-time packet is overwritten on the buffer.

  Each switch performs processing for each time domain based on the synchronization time, as shown in the table of FIG. In other words, with respect to “the line usage permission time of the own switch”, the contents of the cyclic transfer buffer are forwarded to all ports. Also, the general transfer packet received from the lower port is discarded. As for the line use permission time of other switches (switch A and switch C), the cyclic transfer packet received from the lower port is stored (overwritten / updated) in the cyclic transfer buffer. Also, the general transfer packet received from the lower port is discarded. As for the idle time, the general transfer packet received from the lower port is forwarded. The term “forwarding” used herein refers to forwarding as a function of a general communication switch device. Further, the cyclic transfer packet received from the lower port is stored (overwritten / updated) in the cyclic transfer buffer.

  Next, FIG. 5 shows a flowchart showing processing relating to the lower port. When the processing is started in the same figure, it enters a state of waiting for packet reception (step 501). In this state, when a packet is received (YES in step 501), a determination is made as to which region is the current time region (step 502).

  At this time, if it is determined that it is the line use permission time of the own switch, the packet type is subsequently determined (step 503). Here, there are a case where it is determined as a real-time packet and a case where it is determined as a general transfer packet.

  If it is determined as a real-time packet, the packet is stored (overwritten / updated) in the cyclic transfer buffer (step 506). Thereafter, the packet stored in the cyclic transfer buffer is forwarded (step 507). On the other hand, when the packet type is determined to be a general transfer packet, the packet is discarded (step 508).

  If it is determined that the current time region is the line use permission time of another switch, it is determined whether the type of the packet is a general transfer packet or a real-time packet (step 504). If it is determined that the packet is a general transfer packet, the packet is discarded. On the other hand, if it is determined that the packet is a real-time packet, it is stored (overwritten / updated) in the cyclic transfer buffer (step 509).

  If it is determined that the current time region is idle time, it is subsequently determined whether the packet type is a real-time packet or a general transfer packet (step 505). If it is determined that the packet is a real-time packet, the packet is then stored (overwritten / updated) in the cyclic transfer buffer (step 509). On the other hand, when it is determined that the packet is a general transfer packet, the packet is forwarded (general switching processing).

  The above processing (steps 501 to 510) is repeated each time a packet is received, so that cyclic information is transmitted and received while guaranteeing real-time performance for each time slot assigned in advance.

  As shown in FIG. 6, the processing related to the upper port waits for reception of a packet (step 601). If the packet is received, the packet is forwarded (general switching processing) (step 602). . That is, as far as the upper port is concerned, general switching processing is also performed in the present invention.

  FIG. 7 shows an explanatory diagram showing the flow of a packet when the lower port P11 receives the packet. As shown in the figure, in this case, the packet received by the lower port P11 is transmitted from the lower port P13 and the upper port P02.

  FIG. 8 shows an explanatory diagram (part 2) of the packet flow when the host port P02 receives the packet. As shown in the figure, when the upper port P02 receives a packet, the packet is transmitted from the lower port P12 and the upper port P01.

  Finally, an explanatory diagram showing an example of scheduling is shown in FIG. In this example, a network (under time management by 1588) is configured via three communication switch devices SW-1, SW-2, and SW-3. In addition to the three nodes (slaves) 1-A, 1-B, 1-C, one PLC is connected to the communication switch SW-1.

  Similarly, three nodes (slaves) 2-A, 2-B, and 2-C are connected to the communication switch device SW-2. Similarly, three nodes (slaves) 3-A, 3-B, and 3-C are connected to the communication switch device SW-3.

  Each of these communication switch devices SW-1 to SW-1 to 3 communicates in the order of (SW-1 time zone) → (SW-2 time zone) → (SW-3 time zone) → (idle). (1 communication cycle example-1) or (SW-1 time zone)-> (idle)-> (SW-2 time zone)-> (idle)-> (SW-3 time zone) → Communication cycles are configured in the order of (idle) (Example of one communication cycle-2).

  In the nodes connected to the same group (same switch), packets can be basically exchanged freely. Further, a packet to be transmitted to the outside through each switch is once buffered in each switch. However, only cyclic data is buffered at this time. Cyclic data from the same source is overwritten with the buffer contents. Furthermore, no buffering is performed on the packets entering the switch from the outside, and a free path is made using the conventional switching method. On the other hand, when the time zone determined for each communication switch device arrives, the buffered cyclic data is transmitted to the destination.

  During the above operation, each node (slave) is not aware of time management (1588) or cycle. Therefore, according to the present invention, there is no burden of time management for each node, and the real-time property of cyclic information is reduced while avoiding the cost increase by providing each node with special hardware. Can be guaranteed.

  As is apparent from the above description, according to the communication switch device according to the present invention, the packet entering from the upper port is assured of a free path in the same manner as the previous communication switch device, but to the outside. For outgoing packets, only cyclic data is buffered and sent to the outside with the arrival of the time zone assigned to each switch, so at the node connected to each lower port It is not necessary to perform time management synchronized with the system, and the cost of those nodes can be reduced. On the other hand, the entire system can guarantee the real-time property of cyclic information. Therefore, according to the present invention, the real-time property of cyclic information can be reliably ensured in an industrial network such as Ethernet (registered trademark).

It is explanatory drawing which shows a system configuration example. It is a block diagram of this invention apparatus. It is explanatory drawing which shows the buffer structural example. It is explanatory drawing of the transfer packet registration table. It is a flowchart which shows the process regarding a low-order port. It is a flowchart which shows the process regarding a high-order port. It is explanatory drawing (the 1) which shows the flow of a packet. It is explanatory drawing (the 2) which shows the flow of a packet. It is explanatory drawing which shows one specific example of a system configuration. It is explanatory drawing which shows the process example for every time area | region in switch-B. It is explanatory drawing (the 1) of a format example. It is explanatory drawing (the 2) of a format example. It is explanatory drawing (the 3) of a format example. It is explanatory drawing which shows the example of the timetable based on the example of a setting. It is explanatory drawing which shows the Example of scheduling.

Explanation of symbols

11, 12, 13 Switch device for communication 111 PLC
112, 113 nodes 121, 122, 123, 124 nodes 131 nodes A real-time guarantee processing unit B time synchronization processing unit B1 synchronization time generation unit B21 own switch line use permission start time register B22 own switch line use permission end time register B23 Idle start time register B24 Idle end time register C Switch logic part TBL Transfer packet registration table P01, P02 Upper port P11, P12, P13, P14 Lower port

Claims (3)

An upper port for connecting to another communication switch device,
Means for sequentially allocating cyclic line usage time with other communication switch devices;
A lower port for connecting a node that handles I / O data; and
A buffer for storing the cyclic information received from the upper port and the I / O data received from the lower port at any time during the line usage time of another communication switch device;
A communication switch device comprising means for reading the latest information of I / O data stored in a buffer during its own line use time period and transmitting the information to an upper port.   2. The communication register device according to claim 1, further comprising a start register and an end register for registering a start time and an end time of the line use time zone.   2. The communication register device according to claim 1, wherein the node connected to the lower port is a PLC.

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