JP2007250960A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007250960A
JP2007250960A JP2006074265A JP2006074265A JP2007250960A JP 2007250960 A JP2007250960 A JP 2007250960A JP 2006074265 A JP2006074265 A JP 2006074265A JP 2006074265 A JP2006074265 A JP 2006074265A JP 2007250960 A JP2007250960 A JP 2007250960A
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electrode pads
semiconductor device
semiconductor chip
main surface
signal electrode
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JP4828270B2 (en
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Yasuo Shimizu
康雄 清水
Shigenori Otake
成典 大竹
Tatsuya Umeda
達也 梅田
Kazuo Kato
和雄 加藤
Koichi Yokomizo
剛一 横溝
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device constituted of a plurality of semiconductor chips, for which an operation speed is accelerated. <P>SOLUTION: Three semiconductor chips 1, 3 and 5 are mounted on the main surface 10x of a wiring board 10. A plurality of electrode pads 2a for signals arranged along the first side 1a of the semiconductor chip 1 are disposed by holding the electrode pad 2b of other functions therebetween so as not to be adjacent to each other. The plurality of electrode pads 2a for the signals are arranged at an array pitch wider than the plurality of electrode pads 2 including them. As the electrode pad 2b, an electrode pad is used for power supply. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、配線基板に複数の半導体チップが実装された半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a plurality of semiconductor chips are mounted on a wiring board.

半導体装置として、例えばＳｉＰ（Ｓystem in Ｐackage：システム・イン・パッケージ）型と呼称される半導体装置が知られている。ＳｉＰ型半導体装置は、機能が異なる複数の半導体チップを配線基板に実装し、１つの回路システムを構築している。ＳｉＰ型半導体装置においても、様々な構造のものが提案され、製品化されている。例えば、特開２００３−２０４０３０号公報には、論理演算回路が搭載された半導体チップと、ＤＲＡＭ（Ｄynamic Ｒandom Ａccess Ｍemory：ダイナミック・ランダム・アクセス・メモリ）が搭載された半導体チップとを配線基板に平面的に並列して実装したＳｉＰ型半導体装置が開示されている。また、特開２００４−２２８３２３号公報には、論理演算回路が搭載された半導体チップと、ＤＲＡＭが搭載された半導体チップとを配線基板に立体的に積層して実装したＳｉＰ型半導体装置が開示されている。   As a semiconductor device, for example, a semiconductor device called a SiP (System in Package) type is known. In a SiP type semiconductor device, a plurality of semiconductor chips having different functions are mounted on a wiring board to construct one circuit system. As for the SiP type semiconductor device, devices having various structures have been proposed and commercialized. For example, in Japanese Patent Laid-Open No. 2003-204030, a semiconductor chip on which a logic operation circuit is mounted and a semiconductor chip on which a DRAM (Dynamic Random Access Memory) is mounted on a wiring board are planar. In particular, a SiP type semiconductor device mounted in parallel is disclosed. Japanese Patent Application Laid-Open No. 2004-228323 discloses a SiP type semiconductor device in which a semiconductor chip on which a logic operation circuit is mounted and a semiconductor chip on which a DRAM is mounted are three-dimensionally stacked and mounted on a wiring board. ing.

特開２００３−２０４０３０号公報JP 2003-204030 A 特開２００４−２２８３２３号公報JP 2004-228323 A

本発明者は、ＳｉＰ型半導体装置について検討した結果、以下の問題点を見出した。
図８乃至図１０は、従来のＳｉＰ型半導体装置に係る図であり、
図８は、各半導体チップ間の結線状態を示す模式的平面図、
図９は、配線基板の内部構造を示す図（（ａ）は模式的斜視図，（ｂ）は模式的断面図）、
図１０は、リターン電流を説明するための模式的斜視図である。 As a result of examining the SiP type semiconductor device, the present inventor has found the following problems.
8 to 10 are diagrams related to a conventional SiP type semiconductor device.
FIG. 8 is a schematic plan view showing a connection state between semiconductor chips,
FIG. 9 is a diagram showing the internal structure of the wiring board ((a) is a schematic perspective view, (b) is a schematic cross-sectional view),
FIG. 10 is a schematic perspective view for explaining the return current.

図８乃至図１０において、
符号４１は、論理演算回路が搭載された半導体チップ（ロジック用チップ）、
符号４１ａは、第１の辺、
符号４２は、ロジック用チップ４１の主面に配置された信号用電極パッド、
符号４３は、ＤＲＡＭ回路が搭載された半導体チップ（ＤＲＡＭ用チップ）、
符号４３ａは、第１の辺、
符号４４は、ＤＲＡＭ用チップ４３の主面に配置された信号用電極パッド、
符号５０は、配線基板、
符号５１は、配線基板５０の第１層目の導電層（配線層）に形成された信号用配線、
符号５１ａ，５１ｂは、配線基板５０の第１層目の導電層に形成されたＧＮＤ用配線、
符号５２は、配線基板５０の第２層目の導電層（配線層）に形成されたＧＮＤ用プレーン、
符号５２ａは、ＧＮＤ用プレーン５２に形成された貫通孔、
符号５３は、配線基板５０の第３層目の導電層（配線層）に形成された信号用配線、
符号５４は、貫通孔５２ａを通して信号用配線５１と信号用配線５３とを電気的に接続するスルーホール配線（ビア）、
符号５５ａは、ＧＮＤ用配線５１ａとＧＮＤ用プレーン５２とを電気的に接続するスルーホール配線（ビア）、
符号５５ｂは、ＧＮＤ用配線５１ｂとＧＮＤ用プレーン５２とを電気的に接続するスルーホール配線（ビア）である。 8 to 10,
Reference numeral 41 denotes a semiconductor chip (logic chip) on which a logic operation circuit is mounted,
Reference numeral 41a denotes a first side,
Reference numeral 42 denotes a signal electrode pad disposed on the main surface of the logic chip 41;
Reference numeral 43 denotes a semiconductor chip (DRAM chip) on which a DRAM circuit is mounted,
Reference numeral 43a denotes a first side,
Reference numeral 44 denotes a signal electrode pad disposed on the main surface of the DRAM chip 43;
Reference numeral 50 denotes a wiring board,
Reference numeral 51 denotes a signal wiring formed on the first conductive layer (wiring layer) of the wiring board 50;
Reference numerals 51a and 51b denote GND wirings formed in the first conductive layer of the wiring board 50,
Reference numeral 52 denotes a GND plane formed in the second conductive layer (wiring layer) of the wiring board 50;
Reference numeral 52a denotes a through hole formed in the GND plane 52.
Reference numeral 53 denotes a signal wiring formed on the third conductive layer (wiring layer) of the wiring board 50;
Reference numeral 54 denotes a through-hole wiring (via) for electrically connecting the signal wiring 51 and the signal wiring 53 through the through hole 52a.
Reference numeral 55a denotes a through-hole wiring (via) that electrically connects the GND wiring 51a and the GND plane 52;
Reference numeral 55b denotes a through-hole wiring (via) that electrically connects the GND wiring 51b and the GND plane 52.

なお、図８では、各半導体チップの電極パッドを透視して示している。
（１）図８に示すように、ロジック用チップ４１及びＤＲＡＭ用チップ４３は、各々の第１の辺（４１ａ，４３ａ）が互いに向かい合い、かつ各々の主面が配線基板５０の主面と向かい合う状態で、配線基板５０の主面に実装されている。 In FIG. 8, the electrode pads of each semiconductor chip are shown through.
(1) As shown in FIG. 8, in the logic chip 41 and the DRAM chip 43, the first sides (41 a, 43 a) face each other, and the respective main surfaces face the main surface of the wiring substrate 50. In this state, it is mounted on the main surface of the wiring board 50.

ＤＲＡＭ用チップ４３の主面には、第１の辺４３ａに沿って複数の信号用電極パッド４４が互いに隣り合って配置されている。ロジック用チップ４１の主面には、ＤＲＡＭ用チップ４３の複数の信号用電極パッド４４と夫々電気的に接続される複数の信号用電極パッド４２が第１の辺４１ａに沿って互いに隣り合って配置されている。ＤＲＡＭ用チップ４３の複数の信号用電極パッド４４とロジック用チップ４１の複数の信号用電極パッド４２との電気的な接続は、配線基板５０の第１層目の導電層（配線層）に形成された複数の信号用配線５１を介して行われている。   On the main surface of the DRAM chip 43, a plurality of signal electrode pads 44 are arranged adjacent to each other along the first side 43a. On the main surface of the logic chip 41, a plurality of signal electrode pads 42 electrically connected to the plurality of signal electrode pads 44 of the DRAM chip 43 are adjacent to each other along the first side 41a. Is arranged. Electrical connection between the plurality of signal electrode pads 44 of the DRAM chip 43 and the plurality of signal electrode pads 42 of the logic chip 41 is formed in the first conductive layer (wiring layer) of the wiring substrate 50. The plurality of signal lines 51 are used.

ＳｉＰ型半導体装置においては、低コスト化を図るため既存のＤＲＡＭ用チップ４３を使用し、用途に合わせてロジック用チップ４１を新設計している。ロジック用チップ４１の設計では、配線基板５０での信号伝達経路を短くするため、ＤＲＡＭ用チップ４３の第１の辺４３ａに沿って配置された複数の信号用電極パッド４４と電気的に接続される複数の信号用電極パッド４２をロジック用チップ４１の第１の辺４１ａに沿って配置している。   In the SiP type semiconductor device, the existing DRAM chip 43 is used in order to reduce the cost, and the logic chip 41 is newly designed according to the application. In the design of the logic chip 41, in order to shorten the signal transmission path in the wiring substrate 50, the logic chip 41 is electrically connected to the plurality of signal electrode pads 44 arranged along the first side 43a of the DRAM chip 43. A plurality of signal electrode pads 42 are arranged along the first side 41 a of the logic chip 41.

しかしながら、ロジック用チップ４１のパッド配列ピッチは、ＤＲＡＭ用チップ４３のパッド配列ピッチよりも狭くなっており、しかも、ロジック用チップ４１の複数の信号用電極パッド４２は、互いに隣り合って配置されている。これは、ロジック用チップ４１の場合、実装基板とＤＲＡＭ用チップ４３とのインタフェースとして信号処理を制御するため、ＤＲＡＭ用チップと電気的に接続される複数の信号用電極パッド４２以外に、実装基板と電気的に接続される複数の電極パッドを有している。これにより、ロジック用チップ４１の電極パッドの数はＤＲＡＭ用チップ４３に比べ多いため、パッド配列ピッチもＤＲＡＭ用チップより狭く配置されている。このため、ＤＲＡＭ用チップ４３の複数の信号用電極パッド４２と、ロジック用チップ４１の複数の信号用電極パッド４２とを夫々電気的に接続する複数の信号用配線５１がロジック用チップ４１側からＤＲＡＭ用チップ４３側に向かって扇状（放射状）に広がり、ＤＲＡＭ用チップ４３の複数の信号用電極パッド４２と、ロジック用チップ４１の複数の信号用電極パッド４２とを夫々電気的に接続する複数の信号用配線５１の等長性確保が困難である。これらの信号用配線５１の等長性は、半導体装置の動作速度に影響するため、出来るだけ信号用配線５１の等長性を確保する必要がある。   However, the pad arrangement pitch of the logic chip 41 is narrower than the pad arrangement pitch of the DRAM chip 43, and the plurality of signal electrode pads 42 of the logic chip 41 are arranged adjacent to each other. Yes. In the case of the logic chip 41, the signal processing is controlled as an interface between the mounting board and the DRAM chip 43, and therefore, in addition to the plurality of signal electrode pads 42 electrically connected to the DRAM chip, the mounting board A plurality of electrode pads electrically connected to each other. As a result, the number of electrode pads of the logic chip 41 is larger than that of the DRAM chip 43, and therefore, the pad arrangement pitch is arranged narrower than that of the DRAM chip. Therefore, a plurality of signal wirings 51 that electrically connect the plurality of signal electrode pads 42 of the DRAM chip 43 and the plurality of signal electrode pads 42 of the logic chip 41 are provided from the logic chip 41 side. A plurality of signal electrode pads 42 of the DRAM chip 43 and a plurality of signal electrode pads 42 of the logic chip 41 are electrically connected to each other, spreading in a fan shape (radially) toward the DRAM chip 43 side. It is difficult to ensure the equal length of the signal wiring 51. Since the equal length of the signal wiring 51 affects the operation speed of the semiconductor device, it is necessary to ensure the equal length of the signal wiring 51 as much as possible.

（２）２つのＤＲＡＭ用チップ４３を搭載する場合、ロジック用チップ４１の複数の信号用電極パッド４２は、他のＤＲＡＭ用チップの複数の信号用電極パッドにも夫々電気的に接続される。他のＤＲＡＭ用チップとの電気的な接続は、図９（ｂ）に示すように、配線基板５０の第３層目の信号用配線５３と、この信号用配線５３と第１層目の信号用配線５１とを電気的に接続するためのスルーホール配線５４とを使って行われる。配線基板５０の第２層目の導電層（配線層）には、第１層目の信号用配線５１を流れる信号と第３層目の信号用配線５３を流れる信号との干渉を抑制するため、ＧＮＤ用プレーン５２が形成されている。このＧＮＤ用プレーン５２には、図９（（ａ），（ｂ））に示すように、スルーホール配線５４を通すための貫通孔５２ａが形成されており、この貫通孔５２ａを通るスルーホール配線５４によって上層の信号用配線５１と下層の信号用配線５３とが電気的に接続される。 (2) When two DRAM chips 43 are mounted, the plurality of signal electrode pads 42 of the logic chip 41 are electrically connected to the plurality of signal electrode pads of other DRAM chips, respectively. As shown in FIG. 9B, the third DRAM signal wiring 53 of the wiring substrate 50 and the signal wiring 53 and the first layer signal are electrically connected to other DRAM chips. This is performed using a through-hole wiring 54 for electrically connecting the wiring 51 for use. In the second conductive layer (wiring layer) of the wiring board 50, in order to suppress interference between a signal flowing through the first signal wiring 51 and a signal flowing through the third signal wiring 53. A GND plane 52 is formed. As shown in FIGS. 9A and 9B, the GND plane 52 is formed with a through hole 52a through which the through hole wiring 54 passes, and the through hole wiring passing through the through hole 52a. 54, the upper signal wiring 51 and the lower signal wiring 53 are electrically connected.

スルーホール配線５４は、ＤＲＡＭ用チップ４３及び他のＤＲＡＭ用チップへの信号用配線の等長性を確保するために、ロジック用チップ４１側に寄せて配置されている。ロジック用チップ４１の信号用電極パッド４２は、ＤＲＡＭ用チップ４３の信号用電極パッド４４よりも狭い配列ピッチで配置されているため、複数の信号用配線５１の配列ピッチがロジック用チップ側で狭くなっている。このため、本来ならスルーホール配線５４毎に独立して貫通孔５２ａが形成されるが、図９（（ａ），（ｂ））に示すように、複数の貫通孔５２ａが繋がってしまい、貫通孔５２ａの間にＧＮＤ用プレーン５２が存在しなくなる。   The through-hole wiring 54 is arranged close to the logic chip 41 side in order to ensure the equal length of the signal wiring to the DRAM chip 43 and other DRAM chips. Since the signal electrode pads 42 of the logic chip 41 are arranged at a narrower arrangement pitch than the signal electrode pads 44 of the DRAM chip 43, the arrangement pitch of the plurality of signal wirings 51 is narrower on the logic chip side. It has become. For this reason, although the through-hole 52a is originally formed independently for every through-hole wiring 54, as shown to FIG. 9 ((a), (b)), several through-holes 52a will be connected and it will penetrate. The GND plane 52 does not exist between the holes 52a.

一方、ロジック用チップ４１の信号用電極パッド４２から出力された電気信号は、図１０に示すように、信号用配線５１を通ってＤＲＡＭ用チップ４３の信号用電極パッド４４に伝達される。この時、電気信号が一方向にのみ流れると、その電気信号経路においてノイズが発生し易い。そこでこのようなノイズを抑えるために、同じタイミングで逆方向に電気信号を帰還させるリターン電流を流すことで、電気信号経路において発生し易いノイズ源を相殺させることが可能である。リターン電流は、ＤＲＡＭ用チップ４３のＧＮＤ用電極パッドから、ＧＮＤ用配線５１ａ、スルーホール配線５５ａ、ＧＮＤ用プレーン５２、スルーホール配線５５ｂ、及びＧＮＤ用配線５１ｂを通ってロジック用チップ４１のＧＮＤ用電極パッドに流れる。   On the other hand, the electrical signal output from the signal electrode pad 42 of the logic chip 41 is transmitted to the signal electrode pad 44 of the DRAM chip 43 through the signal wiring 51 as shown in FIG. At this time, if an electric signal flows only in one direction, noise is likely to occur in the electric signal path. Therefore, in order to suppress such noise, it is possible to cancel a noise source that is likely to occur in the electric signal path by flowing a return current that feeds back the electric signal in the reverse direction at the same timing. The return current flows from the GND electrode pad of the DRAM chip 43 to the GND of the logic chip 41 through the GND wiring 51a, the through-hole wiring 55a, the GND plane 52, the through-hole wiring 55b, and the GND wiring 51b. Flows to the electrode pad.

リターン電流が流れる電流経路に、互いに繋がった複数の貫通孔５２ａがリターン電流の流れる方向に対して横切るように配置されていた場合、これらの貫通孔を迂回してリターン電流が流れるため、同じタイミングでリターン電流が戻って来られなくなり、ノイズ発生の要因となる。このことは、半導体装置の信頼性を低下させる要因となるため、高機能や多機能化に伴い配線の本数が増加しても、複数の貫通孔５２ａが繋がらないようにする工夫が必要である。   When a plurality of through holes 52a connected to each other are arranged in the current path through which the return current flows so as to cross the direction in which the return current flows, the return current flows by bypassing these through holes. As a result, the return current cannot be returned, causing noise. Since this causes a decrease in the reliability of the semiconductor device, it is necessary to devise a method for preventing the plurality of through holes 52a from being connected even if the number of wirings increases with the increase in functionality and multifunction. .

本発明の目的は、半導体装置の動作速度の高速化を図ることが可能な技術を提供することにある。
本発明の他の目的は、半導体装置の信頼性向上を図ることが可能な技術を提供することにある。
本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。 An object of the present invention is to provide a technique capable of increasing the operating speed of a semiconductor device.
Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

（１）；
配線基板と、
前記配線基板の主面に、各々の一辺同士が所定の間隔をおいて向かい合い、かつ各々の主面が前記配線基板の主面と向かい合う状態で搭載された第１及び第２の半導体チップと、
前記第１の半導体チップの主面に前記第１の半導体チップの一辺に沿って配置された複数の第１の電極パッドと、
前記第２の半導体チップの主面に前記第２の半導体チップの一辺に沿って前記複数の第１の電極パッドよりも広い配列ピッチで配置された複数の第２の電極パッドとを有し、
前記複数の第２の電極パッドは、互いに隣り合って配置された複数の第２の信号用電極パッドを含み、
前記複数の第１の電極パッドは、前記配線基板の主面に形成された複数の配線を介して前記複数の第２の信号用電極パッドと夫々電気的に接続された複数の第１の信号用電極パッドを含み、
前記複数の第１の信号用電極パッドは、互いに隣り合わないように他の機能の電極パッドを間に挟んで配置されていることを特徴とする半導体装置。 (1);
A wiring board;
First and second semiconductor chips mounted on the main surface of the wiring board in such a manner that each side faces each other at a predetermined interval and each main surface faces the main surface of the wiring board;
A plurality of first electrode pads disposed along one side of the first semiconductor chip on a main surface of the first semiconductor chip;
A plurality of second electrode pads disposed on a main surface of the second semiconductor chip along a side of the second semiconductor chip at an array pitch wider than the plurality of first electrode pads;
The plurality of second electrode pads include a plurality of second signal electrode pads arranged adjacent to each other,
The plurality of first electrode pads are a plurality of first signals electrically connected to the plurality of second signal electrode pads via a plurality of wirings formed on the main surface of the wiring board. Including electrode pads for
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other.

（２）;
配線基板と、
平面が第１の辺及び前記第１の辺と交わる第２の辺を有する方形状で形成された第１の半導体チップであって、主面が前記配線基板の主面と向かい合う状態で前記配線基板の主面に搭載された第１の半導体チップと、
第１の辺が前記第１の半導体チップの第１の辺と向かい合い、かつ主面が前記配線基板の主面と向かい合う状態で前記配線基板の主面に搭載された第２の半導体チップと、
第１の辺が前記第１の半導体チップの第２の辺と向かい合い、かつ主面が前記配線基板の主面と向かい合う状態で前記配線基板の主面に搭載された第３の半導体チップと、
複数の第１の信号用電極パッドを含む複数の第１の電極パッドであって、前記第１の半導体チップの主面に、前記第１の半導体チップの第１の辺に沿って配置された複数の第１の電極パッドと、
複数の第２の信号用電極パッドを含む複数の第２の電極パッドであって、前記第２の半導体チップの主面に、前記第２の半導体チップの第１の辺に沿って前記第１の電極パッドよりも広い配列ピッチで配置された複数の第２の電極パッドと、
複数の第３の信号用電極パッドを含む複数の第３の電極パッドであって、前記第３の半導体チップの主面に、前記第３の半導体チップの第１の辺に沿って前記複数の第１の電極パッドよりも広い配列ピッチで配置された複数の第３の電極パッドと、
前記配線基板の主面に形成され、かつＸ方向に沿って延在する複数の第１の配線であって、各々の一端側が前記複数の第１の信号用電極パッドと電気的に接続され、各々の一端側と反対側の他端側が前記複数の第２の信号用電極パッドと電気的に接続された複数の第１の配線と、
前記配線基板の主面に形成され、かつ各々の一端側が前記第３の信号用電極パッドと電気的に接続された複数の第２の配線と、
前記配線基板の前記第１の配線よりも下層に形成された導電プレートと、
前記導電プレートに形成された複数の第１の貫通孔と、
前記導電プレートに形成された複数の第２の貫通孔と、
前記配線基板の前記導電プレートよりも下層に形成され、かつＹ方向に沿って延在する複数の第３の配線と、
各々が前記複数の第１の貫通孔を通って前記複数の第１の配線と前記複数の第２の配線の一端側とを夫々電気的に接続する複数の第１のスルーホール配線と、
各々が前記複数の第２の貫通孔を通って前記複数の第２の配線の他端側と前記複数の第３の配線の他端側とを夫々電気的に接続する複数の第２のスルーホール配線とを有し、
前記複数の第２及び第３の信号用電極パッドは、各々が互いに隣り合って配置され、
前記複数の第１の信号用電極パッドは、互いに隣り合わないように他の機能の電極パッドを間に挟んで配置されていることを特徴とする半導体装置。 (2);
A wiring board;
A first semiconductor chip formed in a rectangular shape having a first side and a second side intersecting with the first side, wherein the main surface faces the main surface of the wiring board. A first semiconductor chip mounted on the main surface of the substrate;
A second semiconductor chip mounted on the main surface of the wiring board with a first side facing the first side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A third semiconductor chip mounted on the main surface of the wiring board with a first side facing the second side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A plurality of first electrode pads including a plurality of first signal electrode pads, the first electrode pads being disposed on a main surface of the first semiconductor chip along a first side of the first semiconductor chip. A plurality of first electrode pads;
A plurality of second electrode pads including a plurality of second signal electrode pads, wherein the first electrode is formed on a main surface of the second semiconductor chip along a first side of the second semiconductor chip; A plurality of second electrode pads arranged at a wider array pitch than the electrode pads of
A plurality of third electrode pads including a plurality of third signal electrode pads, wherein the plurality of third electrode pads are formed on the main surface of the third semiconductor chip along the first side of the third semiconductor chip. A plurality of third electrode pads arranged at a wider array pitch than the first electrode pads;
A plurality of first wirings formed on the main surface of the wiring substrate and extending along the X direction, each one end of which is electrically connected to the plurality of first signal electrode pads; A plurality of first wires in which the other end side opposite to each one end side is electrically connected to the plurality of second signal electrode pads;
A plurality of second wirings formed on the main surface of the wiring board and having one end side electrically connected to the third signal electrode pad;
A conductive plate formed below the first wiring of the wiring board;
A plurality of first through holes formed in the conductive plate;
A plurality of second through holes formed in the conductive plate;
A plurality of third wirings formed below the conductive plate of the wiring board and extending along the Y direction;
A plurality of first through-hole wirings each electrically connecting the plurality of first wirings and one end side of the plurality of second wirings through the plurality of first through holes;
A plurality of second throughs each electrically connecting the other end side of the plurality of second wires and the other end side of the plurality of third wires through the plurality of second through holes, respectively. Hall wiring and
The plurality of second and third signal electrode pads are arranged adjacent to each other,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
本発明によれば、配線基板の配線密度向上を図ることができる。
本発明によれば、半導体装置の信頼性向上を図ることができる。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, the wiring density of the wiring board can be improved.
According to the present invention, the reliability of a semiconductor device can be improved.

以下、図面を参照して本発明の実施例を詳細に説明する。なお、発明の実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

本実施例１では、配線基板に複数の半導体チップを平面的に並列して実装したＳｉＰ型半導体装置に本発明を適用した例について説明する。   In the first embodiment, an example in which the present invention is applied to a SiP type semiconductor device in which a plurality of semiconductor chips are mounted in parallel on a wiring board will be described.

図１乃至図６は、本発明の実施例１であるＳｉＰ型半導体装置に係る図であり、
図１は、半導体装置の概略構成を示す図（（ａ）は樹脂封止体の一部を省略した模式的平面図，（ｂ）は（ａ）のａ−ａ線に沿う模式的断面図）、
図２は、半導体チップ間の結線状態を示す模式的平面図、
図３は、半導体チップ間の結線状態を示す模式的断面図、
図４は、配線基板の第１層目の導電層に形成された配線パターンの一部を示す模式的平面図、
図５は、配線基板の第２層目の導電層（配線層）に形成されたＧＮＤ用プレーン（導電プレート）を示す模式的平面図、
図６は、配線基板の第３層の導電層（配線層）に形成された配線パターンの一部を示す模式的平面図である。 1 to 6 are diagrams related to a SiP type semiconductor device that is Embodiment 1 of the present invention.
1A and 1B are diagrams illustrating a schematic configuration of a semiconductor device (FIG. 1A is a schematic plan view in which a part of a resin sealing body is omitted, and FIG. 1B is a schematic cross-sectional view taken along the line aa in FIG. ),
FIG. 2 is a schematic plan view showing a connection state between semiconductor chips,
FIG. 3 is a schematic cross-sectional view showing a connection state between semiconductor chips,
FIG. 4 is a schematic plan view showing a part of a wiring pattern formed in the first conductive layer of the wiring board;
FIG. 5 is a schematic plan view showing a GND plane (conductive plate) formed in the second conductive layer (wiring layer) of the wiring board;
FIG. 6 is a schematic plan view showing a part of the wiring pattern formed in the third conductive layer (wiring layer) of the wiring board.

なお、図２では、各半導体チップの電極パッドを透視して示している。また、図４では、各半導体チップの電極パッドも図示している。   In FIG. 2, the electrode pads of each semiconductor chip are shown through. FIG. 4 also shows the electrode pads of each semiconductor chip.

本実施例１のＳｉＰ型半導体装置は、図１（（ａ），（ｂ））に示すように、インターポーザとも呼ばれる配線基板１０の主面１０ｘに３つの半導体チップ（１，３，５）が実装され、配線基板１０の主面１０ｘと反対側の裏面１０ｙに外部接続用端子としてボール形状の半田バンプ２２が複数配置された構造になっている。３つの半導体チップ（１，３，５）は、配線基板１０の主面１０ｘ上に形成された樹脂封止体２１によって樹脂封止されている。   As shown in FIGS. 1 (a) and 1 (b), the SiP type semiconductor device according to the first embodiment has three semiconductor chips (1, 3, 5) on the main surface 10x of the wiring substrate 10 also called an interposer. A plurality of ball-shaped solder bumps 22 are arranged as external connection terminals on the back surface 10y on the opposite side of the main surface 10x of the wiring board 10 that is mounted. The three semiconductor chips (1, 3, 5) are resin-sealed by a resin sealing body 21 formed on the main surface 10x of the wiring board 10.

配線基板１０は、厚さ方向と交差する平面形状が方形状になっている。半導体チップ１は、厚さ方向と交差する平面形状が、互いに反対側に位置する２つの辺（第１の辺１ａ，第２の辺１ｂ）と、この２つの辺と交わり、かつ互いに反対側に位置する２つの辺（第３の辺１ｃ，第４の辺１ｄ）とを有する方形状になっている。半導体チップ３は、厚さ方向と交差する平面形状が、互いに反対側に位置する２つの辺（第１の辺３ａ，第２の辺３ｂ）と、この２つの辺と交わり、かつ互いに反対側に位置する２つの辺（第３及び第４の辺）とを有する方形状になっている。半導体チップ５は、厚さ方向と交差する平面形状が、互いに反対側に位置する２つの辺（５ａ，５ｂ）と、この２つの辺と交わり、かつ互いに反対側に位置する２つの辺（第３及び第４の辺）とを有する方形状になっている。   The wiring substrate 10 has a square shape that intersects the thickness direction. The semiconductor chip 1 has a planar shape intersecting the thickness direction, two sides (first side 1a and second side 1b) located on opposite sides, and the two sides and opposite sides. It has a rectangular shape having two sides (third side 1c and fourth side 1d) located at. The semiconductor chip 3 has two sides (a first side 3a and a second side 3b) that are opposite to each other in a planar shape that intersects the thickness direction, and the two sides are opposite to each other. It has a rectangular shape having two sides (third and fourth sides) located in the area. The semiconductor chip 5 has two sides (5a, 5b) that are opposite to each other in a plane shape that intersects the thickness direction, and two sides that are opposite to each other (second sides) 3 and the fourth side).

半導体チップ１の主面側には、集積回路として例えば論理演算回路が搭載されており、半導体チップ３及び５には、集積回路として例えば同一機能のＤＲＡＭ回路が搭載されている。   For example, a logic operation circuit is mounted as an integrated circuit on the main surface side of the semiconductor chip 1, and a DRAM circuit having the same function is mounted as an integrated circuit on the semiconductor chips 3 and 5.

半導体チップ１の主面には、図２に示すように、４つの辺（１ａ〜１ｄ）に沿って複数の電極パッド２が配置されている。半導体チップ（３，５）の主面には、２つの辺（３ａ及び３ｂ，５ａ及び５ｂ）に沿って複数の電極パッド４が配置されている。半導体チップ１の複数の電極パッド４は、半導体チップ（３，５）の複数の電極パッド４よりも狭い配列ピッチで配置されている。   On the main surface of the semiconductor chip 1, as shown in FIG. 2, a plurality of electrode pads 2 are arranged along four sides (1a to 1d). A plurality of electrode pads 4 are arranged along two sides (3a and 3b, 5a and 5b) on the main surface of the semiconductor chip (3, 5). The plurality of electrode pads 4 of the semiconductor chip 1 are arranged at a narrower arrangement pitch than the plurality of electrode pads 4 of the semiconductor chip (3, 5).

半導体チップ１は、その主面が配線基板１０の主面１０ｘと向かい合う状態で配線基板１０の主面１０ｘに実装されている。半導体チップ３は、その第１の辺３ａが半導体チップ１の第１の辺１ａと向かい合い、かつその主面が配線基板１０の主面１０ｘと向かい合い状態で配線基板１０の主面１０ｘに実装されている。半導体チップ５は、その第１の辺５ａが半導体チップ１の第３の辺１ｃと向かい合い、かつその主面が配線基板１０の主面１０ｘと向かい合う状態で配線基板１０の主面１０ｘに実装されている。半導体チップ３及び５は、半導体チップ１から離れた位置に配置されている。   The semiconductor chip 1 is mounted on the main surface 10x of the wiring substrate 10 with its main surface facing the main surface 10x of the wiring substrate 10. The semiconductor chip 3 is mounted on the main surface 10x of the wiring substrate 10 with the first side 3a facing the first side 1a of the semiconductor chip 1 and the main surface facing the main surface 10x of the wiring substrate 10. ing. The semiconductor chip 5 is mounted on the main surface 10x of the wiring substrate 10 with its first side 5a facing the third side 1c of the semiconductor chip 1 and its main surface facing the main surface 10x of the wiring substrate 10. ing. The semiconductor chips 3 and 5 are arranged at positions away from the semiconductor chip 1.

半導体チップ３及び５において、第１の辺（３ａ，５ａ）に沿って配置された複数の電極パッド４には、互いに隣り合って配置された複数の信号用電極パッド４ａが含まれている。半導体チップ１において、第１の辺１ａに沿って配置された複数の電極パッド２には、半導体チップ３及び５の複数の信号用電極パッド４ａと夫々電気的に接続される複数の信号用電極パッド２ａが含まれている。   In the semiconductor chips 3 and 5, the plurality of electrode pads 4 arranged along the first side (3a, 5a) include a plurality of signal electrode pads 4a arranged adjacent to each other. In the semiconductor chip 1, a plurality of signal pads that are electrically connected to the plurality of signal electrode pads 4 a of the semiconductor chips 3 and 5 are respectively connected to the plurality of electrode pads 2 arranged along the first side 1 a. A pad 2a is included.

半導体チップ１において、第１の辺１ａに沿って配置された複数の電極パッド２に含まれる複数の信号用電極パッド２ａは、互いに隣り合わないように他の機能の電極パッド２ｂを間に挟んで配置されている。即ち、複数の信号用電極パッド２ａは、これらを含む複数の電極パッド２よりも広い配列ピッチで配置されている。電極パッド２ｂとしては、例えば電源用電極パッドを用いる。   In the semiconductor chip 1, the plurality of signal electrode pads 2 a included in the plurality of electrode pads 2 arranged along the first side 1 a sandwich the electrode pads 2 b having other functions so as not to be adjacent to each other. Is arranged in. That is, the plurality of signal electrode pads 2a are arranged at a wider arrangement pitch than the plurality of electrode pads 2 including them. As the electrode pad 2b, for example, a power electrode pad is used.

配線基板１０は、これに限定されないが、例えば、図３に示すように、主面１０ｘ及び裏面１０ｙ、並びに内部に配線層を有する多層配線構造になっており、本実施例１では例えば６層配線構造になっている。   For example, as shown in FIG. 3, the wiring substrate 10 has a multilayer wiring structure having a main surface 10x and a back surface 10y and a wiring layer therein. In the first embodiment, for example, six layers are provided. It has a wiring structure.

配線基板１０の主面１０ｘから数えて第１層目の配線層には、図３及び図４に示すように、半導体チップ１の第１の辺１ａに沿って配置された複数の信号用電極パッド２ａと、半導体チップ３の第１の辺４ａに沿って配置された複数の信号用電極パッド４ａとを夫々電気的に接続する複数の信号用配線１１ａが形成されている。この複数の信号用配線１１ａは、半導体チップ１と半導体チップ３との間において、Ｘ方向に沿って延在している。
なお、第１層目の配線層には、複数の信号用配線１１ａの他に、信号用配線１１ｂ、１１ｃ、１１ｄ等も形成されている。 The first wiring layer counted from the main surface 10x of the wiring substrate 10 has a plurality of signal electrodes arranged along the first side 1a of the semiconductor chip 1 as shown in FIGS. A plurality of signal wirings 11 a are formed to electrically connect the pads 2 a and the plurality of signal electrode pads 4 a arranged along the first side 4 a of the semiconductor chip 3. The plurality of signal wirings 11 a extend along the X direction between the semiconductor chip 1 and the semiconductor chip 3.
In addition to the plurality of signal lines 11a, signal lines 11b, 11c, 11d and the like are also formed in the first wiring layer.

配線基板１０の主面１０ｘから数えて第２の層目の配線層には、図３及び図５に示すように、平面的に広がるプレーン（プレート）１２が形成されている。このプレーン１２は、第１層目の信号用配線を流れる電気信号と、第３層目の信号配線を流れる電気信号との干渉を抑制する目的で設けられており、電源電位として例えば基準電位（例えば０Ｖ）に電位固定される。   As shown in FIGS. 3 and 5, a plane (plate) 12 that spreads in a plane is formed in the second wiring layer counted from the main surface 10 x of the wiring substrate 10. The plane 12 is provided for the purpose of suppressing interference between the electric signal flowing through the first-layer signal wiring and the electric signal flowing through the third-layer signal wiring. For example, the potential is fixed at 0V).

配線基板１０の主面１０ｘから数えて第３層目の配線層には、図３及び図６に示すように、複数の信号用配線１３が形成されている。この複数の信号用配線１３は、同一平面内において、Ｘ方向と直行するＹ方向に沿って延在している。   As shown in FIGS. 3 and 6, a plurality of signal wirings 13 are formed in the third wiring layer counting from the main surface 10 x of the wiring substrate 10. The plurality of signal wirings 13 extend along the Y direction perpendicular to the X direction in the same plane.

配線基板１０の主面１０ｘから数えて第４層目の配線層には、図示していないが複数の信号用配線が形成されており、配線基板１０の主面１０ｘから数えて第５層目の配線層には、図３に示すように、第２層目のプレーン１２と同様に、平面的に広がるプレーン１５が形成されている。このプレーン１５は、電源電位として、例えば基準電位若しくは基準電位よりも高い動作電位（例えば３．３Ｖ）に電位固定される。   Although not shown, a plurality of signal wirings are formed in the fourth wiring layer counting from the main surface 10x of the wiring board 10, and the fifth layer counting from the main surface 10x of the wiring board 10 is provided. In this wiring layer, as shown in FIG. 3, similarly to the second-layer plane 12, a plane 15 that extends in a plane is formed. The plane 15 is fixed as a power supply potential, for example, at a reference potential or an operation potential higher than the reference potential (eg, 3.3 V).

配線基板１０の主面１０ｘから数えて第６層目の配線層には、図３に示すように、複数の電極パッド１６が形成されている。この複数の電極パッド１６には、複数の半田バンプ２２が夫々電気的にかつ機械的に接続されている。   As shown in FIG. 3, a plurality of electrode pads 16 are formed in the sixth wiring layer counted from the main surface 10 x of the wiring substrate 10. A plurality of solder bumps 22 are electrically and mechanically connected to the plurality of electrode pads 16, respectively.

半導体チップ１の第１の辺１ａに沿って配置された複数の信号用電極パッド２ａは、図３及び図４に示すように、夫々導電性バンプ（突起状電極）２０を介在して、対応する複数の信号用配線１１ａの一端側に夫々電気的に接続されている。半導体チップ３の第１の辺３ａに沿って配置された複数の信号用電極パッド４ａは、夫々導電性バンプ２０を介在して、対応する複数の信号用配線１１ａの他端側（一端側とは反対側）に夫々電気的に接続されている。即ち、半導体チップ１の第１の辺１ａに沿って配置された複数の信号用電極パッド２ａは、配線基板１０の第１の配線層に形成された複数の信号用配線１１ａを介して、半導体チップ３の第１の辺３ａに沿って配置された複数の信号用電極パッド４ａと夫々電気的に接続されている。   A plurality of signal electrode pads 2a arranged along the first side 1a of the semiconductor chip 1 are respectively compatible with conductive bumps (protruding electrodes) 20 as shown in FIGS. Are electrically connected to one end sides of the plurality of signal wirings 11a. The plurality of signal electrode pads 4a arranged along the first side 3a of the semiconductor chip 3 are respectively connected to the other end side (one end side) of the corresponding plurality of signal wirings 11a with the conductive bumps 20 interposed therebetween. Are electrically connected to the other side. That is, the plurality of signal electrode pads 2 a arranged along the first side 1 a of the semiconductor chip 1 are connected to the semiconductor via the plurality of signal wirings 11 a formed on the first wiring layer of the wiring substrate 10. Each of the signal electrode pads 4a arranged along the first side 3a of the chip 3 is electrically connected.

図２に示すように、半導体チップ１の第３の辺１ｃに沿って配置された複数の電極パッド２にも半導体チップ３の第１の辺３ａに配置された信号用電極パッド４ａと電気的に接続される信号用電極パッド２ａが含まれている。この電極パッドは、図４に示すように、配線基板１０の第１層目の配線層に形成された信号用配線１１ｄを介して、半導体チップ３の第１の辺３ａに配置された信号用電極パッド４ａと電気的に接続されている。   As shown in FIG. 2, the plurality of electrode pads 2 arranged along the third side 1 c of the semiconductor chip 1 are electrically connected to the signal electrode pads 4 a arranged on the first side 3 a of the semiconductor chip 3. The signal electrode pad 2a connected to is included. As shown in FIG. 4, the electrode pad is used for a signal disposed on the first side 3 a of the semiconductor chip 3 via a signal wiring 11 d formed in the first wiring layer of the wiring substrate 10. It is electrically connected to the electrode pad 4a.

配線基板１０において、第３層目の複数の信号用配線１３は、図３、図４及び図６に示すように、各々の一端側が夫々スルーホール配線１７ａを介して第１層目の複数の信号用配線１１ａの中間部に夫々電気的に接続されている。また、第３層目の複数の信号用配線１３は、各々の他端側が夫々スルーホール配線１７ｂを介して、第１層目の複数の信号用配線１１ｂの一端側に夫々電気的に接続されている。第１層目の複数の信号用配線１１ｂの他端側は、図３及び図４に示すように、夫々導電性バンプ２０を介在して、半導体チップ５の第１の辺５ａに沿って配置され複数の信号用電極パッド４ａと夫々電気的に接続されている。   In the wiring board 10, the plurality of signal wirings 13 in the third layer are connected to the plurality of first layer wirings through the through-hole wirings 17 a, as shown in FIGS. 3, 4, and 6. Each is electrically connected to an intermediate portion of the signal wiring 11a. Further, the plurality of signal wirings 13 in the third layer are electrically connected to one end sides of the plurality of signal wirings 11b in the first layer through the through-hole wirings 17b, respectively. ing. As shown in FIGS. 3 and 4, the other end side of the plurality of signal wirings 11 b in the first layer is disposed along the first side 5 a of the semiconductor chip 5 with the conductive bumps 20 interposed therebetween. The plurality of signal electrode pads 4a are electrically connected to each other.

即ち、半導体チップ１の第１の辺１ａに沿って配置された複数の信号用電極パッド２ａは、配線基板１０の配線を介して、半導体チップ３の第１の辺３ａに沿って配置された複数の信号用電極パッド４ａと夫々電気的に接続され、更に半導体チップ５の第１の辺５ａに沿って配置された複数の信号用電極パッド４ａと夫々電気的に接続されている。   That is, the plurality of signal electrode pads 2 a arranged along the first side 1 a of the semiconductor chip 1 are arranged along the first side 3 a of the semiconductor chip 3 through the wiring of the wiring substrate 10. The plurality of signal electrode pads 4 a are electrically connected to each other, and are further electrically connected to the plurality of signal electrode pads 4 a arranged along the first side 5 a of the semiconductor chip 5.

図３及び５に示すように、第２層目のプレーン１２には、スルーホール配線１７ａを通すための貫通孔１２ａがスルーホール配線１７ａの数に対応して複数形成されており、この貫通孔１２ａを通るスルーホール配線１７ａによって上層の信号用配線１１ａと下層の信号用配線１３との電気的な接続が成されている。また、第２層目のプレーン１２には、スルーホール配線１７ｂを通すための貫通孔１２ｂがスルーホール配線１７ｂの数に応じて複数形成されており、この貫通孔１２ｂを通るスルーホール配線１７ｂによって上層の信号用配線１７ｂと下層の信号用配線１３との電気的な接続が成されている。   As shown in FIGS. 3 and 5, the second-layer plane 12 has a plurality of through holes 12a corresponding to the number of the through hole wirings 17a through which the through hole wirings 17a pass. The upper-layer signal wiring 11a and the lower-layer signal wiring 13 are electrically connected by the through-hole wiring 17a passing through 12a. Further, a plurality of through holes 12b for passing through-hole wirings 17b are formed in the second layer plane 12 in accordance with the number of through-hole wirings 17b. By the through-hole wirings 17b passing through the through-holes 12b, The upper signal wiring 17b and the lower signal wiring 13 are electrically connected.

各半導体チップ（１，３，５）の複数の電極パッド（２，４）には、電源電位のうち基準電位に電位固定されるグランド用電極パッドが含まれている。これらのグランド用電極パッドは、配線基板１０において、第１層目の配線層に形成されたグランド用配線、このグランド配線と第２層目のプレーン１２とを電気的に接続するスルーホール配線を介してプレーン１２と電気的に接続されている。   The plurality of electrode pads (2, 4) of each semiconductor chip (1, 3, 5) include a ground electrode pad whose potential is fixed to the reference potential among the power supply potentials. These electrode pads for ground are ground wiring formed in the first wiring layer and through-hole wiring for electrically connecting the ground wiring and the second plane 12 in the wiring substrate 10. And electrically connected to the plane 12.

半導体チップ１の信号用電極パッド２ａから出力された電気信号は、配線基板１０の第１層目の信号用配線１１ａを通って半導体チップ３の信号用電極パッド４ａに伝達される。この時の電気信号に伴ってリターン電流が流れる。リターン電流は、半導体チップ３のグランド用電極パッドから、グランド用電極パッド、スルーホール配線、プレーン１２、スルーホール配線、及びグランド用電極パッドを通して半導体チップ１のグランド用電極パッドに流れる。   The electric signal output from the signal electrode pad 2 a of the semiconductor chip 1 is transmitted to the signal electrode pad 4 a of the semiconductor chip 3 through the signal wiring 11 a of the first layer of the wiring substrate 10. A return current flows along with the electrical signal at this time. The return current flows from the ground electrode pad of the semiconductor chip 3 to the ground electrode pad of the semiconductor chip 1 through the ground electrode pad, the through-hole wiring, the plane 12, the through-hole wiring, and the ground electrode pad.

本実施例１において、半導体チップ１の第１の辺１ａに沿って配置された複数の信号用電極パッド２ａは、互いに隣り合わないように他の機能の電極パッド４ｂを間に挟んで配置されている。このような構成にすることにより、半導体チップ１の第１の辺１ａに沿って配置された複数の信号用電極パッド２ａと、半導体チップ３の第１の辺３ａに沿って配置された複数の信号用電極パッド４ａとを夫々電気的に接続する複数の信号用配線１１ａが半導体チップ１側から半導体チップ３側に向かって扇状（放射状）に広がる広がり度を緩やか若しくは無くすことができるため、複数の信号用配線１１ａの等長性を容易に確保でき、ＳｉＰ型半導体装置の動作速度の高速化を図ることができる。   In the first embodiment, the plurality of signal electrode pads 2a arranged along the first side 1a of the semiconductor chip 1 are arranged with the electrode pads 4b having other functions interposed therebetween so as not to be adjacent to each other. ing. With such a configuration, a plurality of signal electrode pads 2 a disposed along the first side 1 a of the semiconductor chip 1 and a plurality of signals disposed along the first side 3 a of the semiconductor chip 3. Since a plurality of signal wirings 11a that are electrically connected to the signal electrode pads 4a can be gradually or eliminated from spreading in a fan shape (radially) from the semiconductor chip 1 side toward the semiconductor chip 3 side, Thus, the equal length of the signal wiring 11a can be easily secured, and the operation speed of the SiP type semiconductor device can be increased.

また、複数の信号用配線１１ａの半導体チップ１側における配列ピッチが広がり、２つの半導体チップ（３，５）への信号用配線の等長性を確保するために、第１層目の信号用配線１１ａと第３層目の信号用配線１３との電気的な接続を行うスルーホール配線１７ａを半導体チップ１側に寄せて配置しても、スルーホール配線を通すための貫通孔が繋がってしまうといった不具合を抑制することができる。従って、半導体チップ１の信号用電極パッド２ａから信号用配線１１ａを通って半導体チップ３の信号用電極パッド４ａに伝達された電気信号に伴ってプレーンを流れるリターン電流が複数の貫通孔１２ａの繋がりによって迂回するといった不具合の発生を回避することができ、リターン電流が同じタイミングで戻って来れないことに起因するノイズの発生を抑制できるため、ＳｉＰ型半導体装置の信頼性向上を図ることができる。   Further, the arrangement pitch of the plurality of signal wirings 11a on the semiconductor chip 1 side is widened, and in order to ensure the equal length of the signal wirings to the two semiconductor chips (3, 5), the signal wiring for the first layer is used. Even if the through-hole wiring 17a for electrical connection between the wiring 11a and the third-layer signal wiring 13 is arranged close to the semiconductor chip 1, the through-hole for passing the through-hole wiring is connected. Such a problem can be suppressed. Accordingly, the return current flowing through the plane in accordance with the electrical signal transmitted from the signal electrode pad 2a of the semiconductor chip 1 to the signal electrode pad 4a of the semiconductor chip 3 through the signal wiring 11a is connected to the plurality of through holes 12a. Therefore, it is possible to avoid the occurrence of problems such as detouring, and to suppress the generation of noise due to the return current not returning at the same timing, so that the reliability of the SiP type semiconductor device can be improved.

なお、複数の信号用電極パッド（２ａ，４ａ）には、複数のデータ信号用電極パッドや複数のアドレス信号用電極パッドが含まれている。データ信号は、アドレス信号よりも高速に伝達する必要がある。従って、半導体チップ１の第１の辺１ａに沿って配置された複数の信号用電極パッド４ａのうち、複数のデータ信号用電極パッドが互いに隣り合うことなく、他の機能の電極パッドを間に挟んで配置することが望ましい。この場合、アドレス信号用電極パッドを間に挟んでもよい。間に挟む他の機能の電極パッドは、１つ若しくは複数であってよい。   The plurality of signal electrode pads (2a, 4a) include a plurality of data signal electrode pads and a plurality of address signal electrode pads. The data signal needs to be transmitted faster than the address signal. Accordingly, among the plurality of signal electrode pads 4a arranged along the first side 1a of the semiconductor chip 1, the plurality of data signal electrode pads are not adjacent to each other, and the electrode pads having other functions are interposed therebetween. It is desirable to place them between them. In this case, an address signal electrode pad may be interposed therebetween. There may be one or a plurality of electrode pads having other functions sandwiched therebetween.

本実施例２では、配線基板に複数の半導体チップを立体的に積み重ねて実装したＳｉＰ型半導体装置に本発明を適用した例について説明する。   In the second embodiment, an example in which the present invention is applied to a SiP type semiconductor device in which a plurality of semiconductor chips are three-dimensionally stacked and mounted on a wiring board will be described.

図７は、本発明の実施例２であるＳｉＰ型半導体装置の概略構成を示す図（（ａ）は模式的平面図，（ｂ）は模式的断面図）である。   7A and 7B are diagrams (a) a schematic plan view and (b) a schematic cross-sectional view showing a schematic configuration of a SiP type semiconductor device that is Embodiment 2 of the present invention.

本実施例２のＳｉＰ型半導体装置は、図７（（ａ），（ｂ））に示すように、配線基板１０の主面に２つの半導体チップ（１，３）が立体的に積み重ねて実装（スタック実装）されている。下段の半導体チップ１は、実施例１と同様に、その主面が配線基板１０の主面と向かい合う状態で配線基板１０の主面に実装されている。上段の半導体チップ３は、実施例１とは異なり、その主面と反対側の裏面が半導体チップ１の裏面と向かい合う状態で半導体チップ１の裏面に接着固定されている。半導体チップ３の複数の電極パッド４は、複数のボンディングワイヤ３０を介して、配線基板１０の第１層目の配線層に形成された複数の電極パッド３１と夫々電気的に接続されている。   As shown in FIGS. 7A and 7B, the SiP type semiconductor device according to the second embodiment is mounted with two semiconductor chips (1, 3) stacked three-dimensionally on the main surface of the wiring board 10. (Stack implementation). The lower semiconductor chip 1 is mounted on the main surface of the wiring substrate 10 with its main surface facing the main surface of the wiring substrate 10 as in the first embodiment. Unlike the first embodiment, the upper semiconductor chip 3 is bonded and fixed to the back surface of the semiconductor chip 1 with the back surface opposite to the main surface facing the back surface of the semiconductor chip 1. The plurality of electrode pads 4 of the semiconductor chip 3 are electrically connected to the plurality of electrode pads 31 formed on the first wiring layer of the wiring substrate 10 via the plurality of bonding wires 30, respectively.

このようなスタック実装の場合、上段の半導体チップ３の複数の信号用電極パッド４ａの間隔に合わせて、下段の半導体チップ１の複数の信号用電極パッド２ａが互いに隣り合わないように他の電極パッドを間に挟むことで、複数の信号用電極パッド２ａと複数の電極パッド３１とを夫々電気的に接続する複数の信号用配線の等長性を容易に確保することができるため、本実施例２のＳｉＰ型半導体装置においても動作速度の高速化を図ることができる。   In the case of such stack mounting, other electrodes are arranged so that the plurality of signal electrode pads 2a of the lower semiconductor chip 1 are not adjacent to each other in accordance with the interval between the plurality of signal electrode pads 4a of the upper semiconductor chip 3. Since the plurality of signal electrode pads 2a and the plurality of electrode pads 31 are electrically connected to each other, it is possible to easily ensure the equal length of the plurality of signal wirings by sandwiching the pads therebetween. Also in the SiP type semiconductor device of Example 2, the operation speed can be increased.

なお、前述の実施例１及び２では、論理演算回路が搭載された半導体チップと、ＤＲＡＭ回路が搭載された半導体チップとの電気的な接続について説明したが、本発明は、これに限定されるものではなく、例えば論理演算回路が搭載された２つの半導体チップ間の電気的な接続においても適用することができる。   In the first and second embodiments, the electrical connection between the semiconductor chip on which the logic operation circuit is mounted and the semiconductor chip on which the DRAM circuit is mounted has been described. However, the present invention is limited to this. For example, the present invention can also be applied to electrical connection between two semiconductor chips on which a logic operation circuit is mounted.

以上、本発明者によってなされた発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の実施例１であるＳｉＰ型半導体装置の概略構成を示す図（（ａ）は樹脂封止体の一部を省略した模式的平面図，（ｂ）は（ａ）のａ−ａ線に沿う模式的断面図）である。The figure which shows schematic structure of the SiP type semiconductor device which is Example 1 of this invention ((a) is a schematic plan view which abbreviate | omitted a part of resin sealing body, (b) is the aa line | wire of (a). FIG. 図１のＳｉＰ型半導体装置において、半導体チップ間の結線状態を示す模式的平面図である。FIG. 2 is a schematic plan view showing a connection state between semiconductor chips in the SiP type semiconductor device of FIG. 1. 図１のＳｉＰ型半導体装置において、半導体チップ間の結線状態を示す模式的断面図である。FIG. 2 is a schematic cross-sectional view showing a connection state between semiconductor chips in the SiP type semiconductor device of FIG. 1. 図１のＳｉＰ型半導体装置において、配線基板の第１層目の導電層に形成された配線パターンの一部を示す模式的平面図である。FIG. 2 is a schematic plan view showing a part of a wiring pattern formed in a first conductive layer of a wiring board in the SiP type semiconductor device of FIG. 1. 図１のＳｉＰ型半導体装置において、配線基板の第２層目の導電層に形成されたＧＮＤ用プレーン（導電プレート）を示す模式的平面図である。FIG. 2 is a schematic plan view showing a GND plane (conductive plate) formed in a second conductive layer of the wiring board in the SiP type semiconductor device of FIG. 1. 図１のＳｉＰ型半導体装置において、配線基板の第３層の導電層に形成された配線パターンの一部を示す模式的平面図である。2 is a schematic plan view showing a part of a wiring pattern formed in a third conductive layer of a wiring board in the SiP type semiconductor device of FIG. 本発明の実施例２であるＳｉＰ型半導体装置の概略構成を示す図（（ａ）は模式的平面図，（ｂ）は模式的断面図）である。It is a figure ((a) is a typical top view, (b) is a typical sectional view) which shows schematic structure of the SiP type semiconductor device which is Example 2 of this invention. 従来のＳｉＰ型半導体装置において、各半導体チップ間の結線状態を示す模式的平面図である。In the conventional SiP type semiconductor device, it is a schematic plan view which shows the connection state between each semiconductor chip. 図８のＳｉＰ型半導体装置において、配線基板の内部構造を示す図（（ａ）は模式的斜視図，（ｂ）は模式的断面図）である。In the SiP type semiconductor device of FIG. 8, it is a figure ((a) is a typical perspective view, (b) is a typical sectional view) which shows the internal structure of a wiring board. 図８のＳｉＰ型半導体装置において、リターン電流を説明するための模式的斜視図である。FIG. 9 is a schematic perspective view for explaining a return current in the SiP type semiconductor device of FIG. 8.

符号の説明Explanation of symbols

１，３，５…半導体チップ、２，４…電極パッド、２ａ，４ａ…信号用電極パッド、１０…配線基板、１１ａ，１１ｂ，１３…配線、１２，１５…プレーン（プレート）、１２ａ…貫通孔、１６…電極パッド、１７ａ，１７ｂ…スルーホール配線、２０…バンプ、２１…樹脂封止体、２２…半田バンプ、３０…ボンディングワイヤ、３１…電極パッド。   DESCRIPTION OF SYMBOLS 1, 3, 5 ... Semiconductor chip, 2, 4 ... Electrode pad, 2a, 4a ... Signal electrode pad, 10 ... Wiring board, 11a, 11b, 13 ... Wiring, 12, 15 ... Plane (plate), 12a ... Through Hole: 16 ... Electrode pad, 17a, 17b ... Through-hole wiring, 20 ... Bump, 21 ... Resin sealing body, 22 ... Solder bump, 30 ... Bonding wire, 31 ... Electrode pad.

Claims (16)

配線基板と、
前記配線基板の主面に、各々の一辺同士が所定の間隔をおいて向かい合い、かつ各々の主面が前記配線基板の主面と向かい合う状態で搭載された第１及び第２の半導体チップと、
前記第１の半導体チップの主面に前記第１の半導体チップの一辺に沿って配置された複数の第１の電極パッドと、
前記第２の半導体チップの主面に前記第２の半導体チップの一辺に沿って前記複数の第１の電極パッドよりも広い配列ピッチで配置された複数の第２の電極パッドとを有し、
前記複数の第２の電極パッドは、互いに隣り合って配置された複数の第２の信号用電極パッドを含み、
前記複数の第１の電極パッドは、前記配線基板の主面に形成された複数の配線を介して前記複数の第２の信号用電極パッドと夫々電気的に接続された複数の第１の信号用電極パッドを含み、
前記複数の第１の信号用電極パッドは、互いに隣り合わないように他の機能の電極パッドを間に挟んで配置されていることを特徴とする半導体装置。 A wiring board;
First and second semiconductor chips mounted on the main surface of the wiring board in such a manner that each side faces each other at a predetermined interval and each main surface faces the main surface of the wiring board;
A plurality of first electrode pads disposed along one side of the first semiconductor chip on a main surface of the first semiconductor chip;
A plurality of second electrode pads disposed on a main surface of the second semiconductor chip along a side of the second semiconductor chip at an array pitch wider than the plurality of first electrode pads;
The plurality of second electrode pads include a plurality of second signal electrode pads arranged adjacent to each other,
The plurality of first electrode pads are a plurality of first signals electrically connected to the plurality of second signal electrode pads via a plurality of wirings formed on the main surface of the wiring board. Including electrode pads for
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other. 請求項１に記載の半導体装置において、
前記複数の第１の信号用電極パッドは、前記複数の第１の電極パッドよりも広い配列ピッチで配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with a wider arrangement pitch than the plurality of first electrode pads. 請求項１に記載の半導体装置において、
前記複数の配線は、前記第１の半導体チップと前記第２の半導体チップとの間に配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The plurality of wirings are arranged between the first semiconductor chip and the second semiconductor chip. 請求項１に記載の半導体装置において、
前記複数の第１の信号用電極パッドは、前記複数の配線の一端側に夫々バンプを介在して接続され、
前記複数の第２の信号用電極パッドは、前記複数の配線の一端側とは反対側の他端側に夫々バンプを介在して接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The plurality of first signal electrode pads are connected to one end sides of the plurality of wirings via bumps, respectively.
The plurality of second signal electrode pads are connected to the other end side opposite to one end side of the plurality of wirings via bumps, respectively. 請求項１に記載の半導体装置において、
前記複数の第１及び第２の信号用電極パッドは、データ信号用電極パッドであることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of first and second signal electrode pads are data signal electrode pads. 請求項１に記載の半導体装置において、
前記複数の第１及び第２の信号用電極パッドは、データ信号用電極パッドであり、
前記他の機能の電極パッドは、アドレス信号用電極パッドであることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The plurality of first and second signal electrode pads are data signal electrode pads;
2. The semiconductor device according to claim 1, wherein the other function electrode pad is an address signal electrode pad. 請求項１に記載の半導体装置において、
前記第１の半導体チップは、論理演算回路が搭載されたチップであり、
前記第２の半導体チップは、ＤＲＡＭが搭載されたチップであることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first semiconductor chip is a chip on which a logic operation circuit is mounted,
The semiconductor device, wherein the second semiconductor chip is a chip on which a DRAM is mounted. 配線基板と、
平面が第１の辺及び前記第１の辺と交わる第２の辺を有する方形状で形成された第１の半導体チップであって、主面が前記配線基板の主面と向かい合う状態で前記配線基板の主面に搭載された第１の半導体チップと、
第１の辺が前記第１の半導体チップの第１の辺と向かい合い、かつ主面が前記配線基板の主面と向かい合う状態で前記配線基板の主面に搭載された第２の半導体チップと、
第１の辺が前記第１の半導体チップの第２の辺と向かい合い、かつ主面が前記配線基板の主面と向かい合う状態で前記配線基板の主面に搭載された第３の半導体チップと、
複数の第１の信号用電極パッドを含む複数の第１の電極パッドであって、前記第１の半導体チップの主面に、前記第１の半導体チップの第１の辺に沿って配置された複数の第１の電極パッドと、
複数の第２の信号用電極パッドを含む複数の第２の電極パッドであって、前記第２の半導体チップの主面に、前記第２の半導体チップの第１の辺に沿って前記第１の電極パッドよりも広い配列ピッチで配置された複数の第２の電極パッドと、
複数の第３の信号用電極パッドを含む複数の第３の電極パッドであって、前記第３の半導体チップの主面に、前記第３の半導体チップの第１の辺に沿って前記複数の第１の電極パッドよりも広い配列ピッチで配置された複数の第３の電極パッドと、
前記配線基板の主面に形成され、かつＸ方向に沿って延在する複数の第１の配線であって、各々の一端側が前記複数の第１の信号用電極パッドと電気的に接続され、各々の一端側と反対側の他端側が前記複数の第２の信号用電極パッドと電気的に接続された複数の第１の配線と、
前記配線基板の主面に形成され、かつ各々の一端側が前記第３の信号用電極パッドと電気的に接続された複数の第２の配線と、
前記配線基板の前記第１の配線よりも下層に形成された導電プレートと、
前記導電プレートに形成された複数の第１の貫通孔と、
前記導電プレートに形成された複数の第２の貫通孔と、
前記配線基板の前記導電プレートよりも下層に形成され、かつＹ方向に沿って延在する複数の第３の配線と、
各々が前記複数の第１の貫通孔を通って前記複数の第１の配線と前記複数の第２の配線の一端側とを夫々電気的に接続する複数の第１のスルーホール配線と、
各々が前記複数の第２の貫通孔を通って前記複数の第２の配線の他端側と前記複数の第３の配線の他端側とを夫々電気的に接続する複数の第２のスルーホール配線とを有し、
前記複数の第２及び第３の信号用電極パッドは、各々が互いに隣り合って配置され、
前記複数の第１の信号用電極パッドは、互いに隣り合わないように他の機能の電極パッドを間に挟んで配置されていることを特徴とする半導体装置。 A wiring board;
A first semiconductor chip formed in a rectangular shape having a first side and a second side intersecting with the first side, wherein the main surface faces the main surface of the wiring board. A first semiconductor chip mounted on the main surface of the substrate;
A second semiconductor chip mounted on the main surface of the wiring board with a first side facing the first side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A third semiconductor chip mounted on the main surface of the wiring board with a first side facing the second side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A plurality of first electrode pads including a plurality of first signal electrode pads, the first electrode pads being disposed on a main surface of the first semiconductor chip along a first side of the first semiconductor chip. A plurality of first electrode pads;
A plurality of second electrode pads including a plurality of second signal electrode pads, wherein the first electrode is formed on a main surface of the second semiconductor chip along a first side of the second semiconductor chip; A plurality of second electrode pads arranged at a wider array pitch than the electrode pads of
A plurality of third electrode pads including a plurality of third signal electrode pads, wherein the plurality of third electrode pads are formed on the main surface of the third semiconductor chip along the first side of the third semiconductor chip. A plurality of third electrode pads arranged at a wider array pitch than the first electrode pads;
A plurality of first wirings formed on the main surface of the wiring substrate and extending along the X direction, each one end of which is electrically connected to the plurality of first signal electrode pads; A plurality of first wires in which the other end side opposite to each one end side is electrically connected to the plurality of second signal electrode pads;
A plurality of second wirings formed on the main surface of the wiring board and having one end side electrically connected to the third signal electrode pad;
A conductive plate formed below the first wiring of the wiring board;
A plurality of first through holes formed in the conductive plate;
A plurality of second through holes formed in the conductive plate;
A plurality of third wirings formed below the conductive plate of the wiring board and extending along the Y direction;
A plurality of first through-hole wirings each electrically connecting the plurality of first wirings and one end side of the plurality of second wirings through the plurality of first through holes;
A plurality of second throughs each electrically connecting the other end side of the plurality of second wires and the other end side of the plurality of third wires through the plurality of second through holes, respectively. Hall wiring and
The plurality of second and third signal electrode pads are arranged adjacent to each other,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other. 請求項８に記載の半導体装置において、
前記複数の第１の信号用電極パッドは、前記複数の第１の電極パッドよりも広い配列ピッチで配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with a wider arrangement pitch than the plurality of first electrode pads. 請求項８に記載の半導体装置において、
前記複数の第１の配線は、前記第１の半導体チップと前記第２の半導体チップとの間に配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first wirings are arranged between the first semiconductor chip and the second semiconductor chip. 請求項８に記載の半導体装置において、
前記複数の第２の配線は、前記複数の第１の配線の外側に配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of second wirings are disposed outside the plurality of first wirings. 請求項８に記載の半導体装置において、
前記複数の第１のスルーホール配線は、前記第１の半導体チップと第２の半導体チップとの間に配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first through-hole wirings are arranged between the first semiconductor chip and the second semiconductor chip. 請求項８に記載の半導体装置において、
前記複数の第１の信号用電極パッドは、前記複数の第１の配線の一端側に夫々バンプを介在して接続され、
前記複数の第２の信号用電極パッドは、前記複数の第１の配線の他端側に夫々バンプを介在して接続され、
前記複数の第３の信号用電極パッドは、前記複数の第２の配線の一端側に夫々バンプを介在して接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The plurality of first signal electrode pads are connected to one end side of the plurality of first wirings via bumps, respectively.
The plurality of second signal electrode pads are connected to the other ends of the plurality of first wirings via bumps, respectively.
The plurality of third signal electrode pads are connected to one end sides of the plurality of second wirings through bumps, respectively. 請求項８に記載の半導体装置において、
前記複数の第１、第２、及び第３の信号用電極パッドは、データ信号用電極パッドであることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first, second, and third signal electrode pads are data signal electrode pads. 請求項８に記載の半導体装置において、
前記複数の第１、第２、及び第３の信号用電極パッドは、データ信号用電極パッドであり、
前記他の機能の電極パッドは、アドレス信号用電極パッドであることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The plurality of first, second, and third signal electrode pads are data signal electrode pads;
2. The semiconductor device according to claim 1, wherein the other function electrode pad is an address signal electrode pad. 請求項８に記載の半導体装置において、
前記第１の半導体チップは、論理演算回路が搭載されたチップであり、
前記第２及び第３の半導体チップは、ＤＲＡＭが搭載されたチップであることを特徴とする半導体装置。 The semiconductor device according to claim 8,
The first semiconductor chip is a chip on which a logic operation circuit is mounted,
2. The semiconductor device according to claim 1, wherein the second and third semiconductor chips are chips on which a DRAM is mounted.
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JP2014220374A (en) * 2013-05-08 2014-11-20 富士通株式会社 Integrated device and manufacturing method therefor and wiring data generation device, wiring data generation method and wiring data generation program
JP2016063199A (en) * 2014-09-22 2016-04-25 イビデン株式会社 Package substrate

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JP2005183561A (en) * 2003-12-18 2005-07-07 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor device
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JP2005340724A (en) * 2004-05-31 2005-12-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit

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Publication number Priority date Publication date Assignee Title
JP2014220374A (en) * 2013-05-08 2014-11-20 富士通株式会社 Integrated device and manufacturing method therefor and wiring data generation device, wiring data generation method and wiring data generation program
JP2016063199A (en) * 2014-09-22 2016-04-25 イビデン株式会社 Package substrate

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