JP2007249666A - Information processor, information processing program and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently process instructions different in data length in an information processor. <P>SOLUTION: In the information processor 1, a CPU 8 includes a numerical expression form storage circuit 104 storing a value showing a numerical expression form and an argument conversion circuit 105 converting the argument of an instruction to a form matched to the numerical expression form. When instructions different in data length, for example, an instruction to perform detailed coordinate calculation of less than 1 pixel in processing for drawing a character image and an instruction to perform massive coordinate calculation are treated, an instruction for designating the numerical expression form is executed, whereby the operation of the CPU 8 is switched to perform change in interpretation of the argument and conversion of data length of the argument in the CPU 8. Therefore, instructions different in data length can be efficiently processed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an information processing program, and an information processing method that perform an operation by interpreting and executing an input instruction.

Conventionally, a general-purpose processor has been used as an information processing apparatus that executes software. When software is executed by a general-purpose processor, software described in a format compatible with the instruction set of the general-purpose processor is decoded by a decoding unit of the general-purpose processor, and specific arithmetic processing is performed in each arithmetic circuit.
Also, the software handles a mixture of numerical expression formats such as 8-bit type, 16-bit type, and 32-bit type as arguments, so that the processor side can also handle these numerical expression formats. Different instructions are prepared according to the numerical expression format of the arguments.

On the other hand, a high-resolution printing apparatus such as a printer processes image data of a large physical size at a high resolution, and therefore performs image processing while handling a wide range of coordinate values. In order to express such coordinate values, Instructions with long bit length arguments are used.
Furthermore, in recent years, a display called electronic paper, which has a resolution as high as that of a printed matter and can express multi-tone gradation with one pixel, has appeared.
In image processing in such an information processing apparatus, it is necessary to calculate coordinates with an accuracy of less than one pixel in order to accurately draw at the originally expected position.

  In a display capable of expressing multiple gradations, a coordinate value of less than one pixel may be calculated in order to perform antialiasing processing. That is, in the anti-aliasing process, the original one pixel which is the smallest expression unit in the display is virtually divided into a plurality of fine pixels, and the drawing point is virtually divided among the original one pixels. Depending on how much the pixel is colored, the density value of the point represented by the original one pixel is determined. Therefore, in the anti-aliasing process, it is necessary to express both a decimal part indicating a coordinate value of less than one pixel and an integer part indicating a wide range of coordinates, and the numerical expression format inside the processor has a long bit length combining them. It has become.

Coordinate calculation is performed using a numerical expression format that can handle data having a data length equal to or greater than the combined integer part and decimal part of the prepared numerical expression form.
For example, when the coordinate values necessary for image processing are an integer part 20 bits and a decimal part 4 bits, the total is 24-bit numeric data, but the processor is an 8-bit, 16-bit, or 32-bit numeric value. When only the representation format is supported and the 24-bit numeric representation format is not supported, the coordinate calculation is performed by the 32-bit numeric representation format that is the smallest among the 24-bit numeric representation formats.

Note that a technique for processing instructions in a processor is described in Japanese Patent Application Laid-Open No. 11-53187, and the technique described in this publication aims to reduce an execution cycle when instructions are executed in a processor. It is what.
Japanese Patent Laid-Open No. 11-53187

However, it is known that coordinate data in image processing tends to appear biased in a specific coordinate range. For example, as described above, when calculating a fine coordinate of less than one pixel, since the coordinate data with the same integer part of the command argument is processed, the upper bits (integer part) indicating a wide range of coordinates are used. Not.
In such a case, in the conventional technique including the technique described in Patent Document 1, for example, a 32-bit type instruction is obtained by inserting all zeros in the upper bits of the argument, and actually represents the decimal part. The approach is to use only data.

Therefore, by inserting zero, a redundant area is generated in the instruction data, the memory area for storing the instruction is increased, resulting in an increase in cost, and the number of memory accesses is increased when reading the instruction. By doing so, a situation in which power consumption increases is caused.
Such a situation is common not only when calculating coordinate data but also when handling instructions having different data lengths in a mixed manner.

Thus, with the conventional technology, it has been difficult to efficiently process instructions having different data lengths in the information processing apparatus.
An object of the present invention is to enable an information processing apparatus to efficiently process instructions having different data lengths, and to reduce the memory cost for storing the instructions and the power consumption during memory access.

In order to solve the above problems, the present invention provides:
An information processing apparatus (for example, the information processing apparatus 1 in FIG. 1) in which a processor (for example, the CPU 8 in FIG. 1) reads out and stores an instruction stored in a memory (for example, the memory 4 in FIG. 1), Data length setting means for setting the data length of the argument included in the instruction read from the memory (for example, the memory 4 storing the “FMT” instruction in the first embodiment and the numerical expression format in the CPU 8 when executing it) Storage circuit 104) and data length conversion means (for example, “LD.W in the first embodiment) for converting an argument included in the instruction read from the memory into a data length set by the data length setting means. An argument conversion circuit 105 in the CPU 8 when executing the instruction, and the processor uses the data length conversion means. It is characterized by performing the arithmetic processing on the converted data length argument Te.

With such a configuration, the data length in the arithmetic processing can be set by the data length setting means, and the argument of the instruction stored in the memory is converted into the predetermined data length in the arithmetic processing by the data length converting means. The above can be executed by the processor.
Therefore, it is possible to efficiently process instructions having different data lengths in the information processing apparatus.

The present invention also provides:
In the processor, a setting data length storage circuit (for example, the numerical expression format storage circuit 104 in FIG. 3) for storing the data length setting in the arithmetic processing and an argument included in the instruction are set in the data length setting means. A data length conversion circuit (for example, the argument conversion circuit 105 in FIG. 3) that converts the data length into a data length, and the data length setting means reads an instruction for the processor to set the data length in the arithmetic processing from the memory The data length indicated in the instruction is stored in the data length storage circuit, and the data length converting means reads and executes the instruction for the processor to perform arithmetic processing from the memory. The data length conversion circuit converts an argument in the instruction into a data length stored in the data length storage circuit.

  With such a configuration, when handling instructions having different data lengths, the data length setting and the argument data length conversion in the arithmetic processing can be performed in the processor, and the arithmetic processing can be performed at high speed. .

The present invention also provides:
The data length setting means stores the data length indicated in the instruction in the memory when the processor reads and executes an instruction for setting the data length in the arithmetic processing from the memory, and the data length conversion means Is characterized by referring to a data length stored in the memory and converting an argument in the instruction to the data length when the processor reads and executes an instruction for performing an arithmetic process from the memory.

  With such a configuration, even when a general-purpose processor is used, the functions of the present invention can be realized only by changing the software, and instructions with different data lengths can be efficiently processed in the information processing apparatus. It becomes.

The present invention also provides:
The instruction stored in the memory includes an arithmetic processing instruction whose argument is a value expressed by a part of upper bits and lower bits among arguments of a predetermined bit length, and is expressed by a part of upper bits. A data length setting instruction for storing a value represented by a part of the upper bits as a data length in the arithmetic processing is stored in advance of an instruction having a value as an argument, and is represented by a part of the lower bits. A data length setting instruction for storing a value represented by a part of the lower bits as a data length in the arithmetic processing is stored prior to the instruction having the value as an argument, and the data length setting means includes the processor Sets the data length for converting the value expressed by the upper bit or a part of the lower bit when the data length setting instruction is read and executed, When the processor reads and executes an arithmetic processing instruction having a value represented by the upper bit or a part of the lower bit as an argument, the data length converting means shifts the argument included in the arithmetic processing instruction. The data length is converted into the data length set by the data length setting means by the process of inserting zeros.

  With such a configuration, for data including an integer part and a decimal part, there are a mixture of instructions for handling the upper bit side data indicating a wide range of values and the lower side data indicating a detailed value separately. Even in this case, when performing arithmetic processing in the processor, it is possible to convert them into a predetermined data length and to process them, thereby preventing an unnecessary data area from being generated in the instruction data.

The present invention also provides:
An information processing program for controlling an information processing apparatus in which a processor reads an instruction stored in a memory and performs arithmetic processing, and sets a data length of an argument included in the instruction read from the memory And a data length conversion function for converting an argument included in an instruction read from the memory into a data length set by the data length setting function, and converting the processor by the data length conversion function It is characterized in that an arithmetic process is performed on the argument of the data length.

Furthermore, the present invention provides
An information processing method in an information processing apparatus in which an instruction stored in a memory is read and processed by a processor, and a data length setting instruction for setting a data length of an argument included in the instruction read from the memory A data length setting step to be executed, a data length conversion step for converting an argument included in the instruction read from the memory into a data length set in the data length setting step, and the processor And an arithmetic processing step for performing arithmetic processing on the argument of the data length converted by the converting means.

  Thus, according to the present invention, it is possible to efficiently process instructions having different data lengths in the information processing apparatus.

Embodiments of an information processing apparatus according to the present invention will be described below with reference to the drawings.
<First Embodiment>

<Configuration of information processing apparatus>
The information processing apparatus according to the present embodiment has a function of executing an operation after converting a data length inside the processor and adjusting the data length to a predetermined data length when instructions having different data lengths are input. Here, as an example of a command having a different data length, an integer part (20 bits) for calculating a wide range of coordinates and a detailed coordinate of less than one pixel are used when coordinate calculation is performed in a character image drawing process. In the following description, it is assumed that two different data lengths of the decimal part (4 bits) for computing are handled.

First, the configuration will be described.
FIG. 1 is a block diagram illustrating an internal configuration of the information processing apparatus 1 according to the present embodiment. As shown in FIG. 1, the information processing apparatus 1 includes an input unit 2, an input unit controller 3, a memory 4, a memory controller 5, an external storage 6, an external storage controller 7, a CPU (Central Processing Unit) 8, and a display controller 9. , The display 10, the bus controller 11, and the power supply controller 12.

The input unit 2 is a device that is operated when inputting a command such as drawing a character, such as a mouse or a keyboard. When an operation for inputting a command is performed, the input unit 2 outputs the input command to the CPU 8 via the input unit controller 3.
The input means controller 3 controls data transfer between the input means 2 and the CPU 8.
The memory 4 forms a work area for developing various programs when the CPU 8 executes the programs, and also forms a storage area for storing data related to the various programs executed by the CPU 8 and data of information to be displayed. To do. In the present embodiment, the memory 4 stores a series of instructions (programs) shown in FIG.

FIG. 2 is a diagram showing a program stored in the memory 4.
As shown in FIG. 2, the memory 4 has
FMT 0
LD. WR3, # 10.125
LD. WR4, # 20.375
ADD. L R5, R3, R4
FMT 8
LD. WR6, # 820000
LD. WR7, # 128000
ADD. L R8, R6, R7
Are stored, and each instruction is expressed by a data length of 16 bits for one word.

Returning to FIG. 1, the memory controller 5 controls data transfer between the memory 4 and the CPU 8.
The external storage 6 stores various programs such as a basic control program and application program executed by the CPU 8 and data related to these various programs.
The external storage controller 7 controls data transfer between the external storage 6 and the CPU 8.

The CPU 8 reads various programs stored in the external storage 6, develops them into a work area formed in the memory 4, and controls the units 2 to 12.
For example, when a character drawing instruction is output from the input unit 2, the CPU 8 executes a predetermined process for drawing a character. Then, by a predetermined process for drawing a character, drawing command data is acquired based on the character code of the character, and the drawing command data is interpreted (decoded) and executed, whereby the bitmap of the character for which the drawing instruction has been given Is generated.

  FIG. 3 is a block diagram showing the internal configuration of the CPU 8. As shown in FIG. 3, the CPU 8 includes a control circuit 101, an input register 102, an instruction decoder 103, a numerical expression format storage circuit 104, an argument conversion circuit 105, a register file 106, an ALU (Arithmetic and Logical). Unit) 107, an output register 108, a program counter 109, and an incrementer 110, and each part in the CPU 8 is connected by a bus or a dedicated signal line. The CPU 8 is connected to each part of the information processing apparatus 1 by an external data bus and an external address bus.

The control circuit 101 is a circuit that controls each module in the CPU 8 such as operation timing and operation type. For example, the control circuit 101 reads an instruction from the memory address indicated by the program counter 109 and stores the instruction in the input register 102, or writes data stored in the output register 108 to a predetermined address in the memory.
The input register 102 temporarily stores an instruction (instruction code and instruction data) read from the memory 4 via the external data bus, and outputs the stored instruction to the instruction decoder 103 or an instruction argument Are output to the numerical expression format storage circuit 104 or the argument conversion circuit 105.

The instruction decoder 103 decodes the instruction content based on the instruction code of the instruction input from the input register 102, and outputs the decoded result to the control circuit 101. The instruction decoder 103 outputs the address of the input / output register to the control circuit based on the instruction data of the instruction input from the input register.
The numerical expression format storage circuit 104 receives an argument (a value indicating a numerical expression format) included in a numerical expression format switching instruction (an FMT instruction described later) from the input register 102, and stores a value indicating the expression format.

  The argument conversion circuit 105 reads a value indicating a numerical expression format stored in the numerical expression format storage circuit 104, receives an argument indicating a numerical value from the input register 102, and converts the numerical expression format into a numerical expression format storage circuit. 104 converts to a format suitable for the stored value. For example, if the value indicating the numerical expression format stored in the numerical expression format storage circuit 104 is 8, the argument conversion circuit 105 shifts the value input from the input register 102 to the left by 8 bits, resulting in an insufficient bit. Is converted to a 32-bit value by adding 0 to. If a 16-bit argument is received from the input register 102, an 8-bit shift is performed to the left, and “0” is added to the lacking upper 8 bits and lower 8 bits, so that the 16-bit type data is 32. Convert to bit type.

Then, the argument conversion circuit 105 outputs the converted numerical data to the register file 106.
The register file 106 is composed of a plurality of registers, and stores the numerical data input from the argument conversion circuit 105 and the calculation result of the ALU 107 in the register at the address specified by the control circuit 101. The register file 106 also outputs numerical data stored in the register at the address designated by the control circuit 101 to the ALU 107 or the output register 108.

The ALU 107 performs logical / arithmetic operations that perform operations such as addition / subtraction or multiplication on the numerical data output from the register file 106. Then, the ALU 107 outputs the calculation result to the register file 106.
The output register 108 temporarily stores the data output from the register file 106 and outputs the data to the memory 4 via the external data bus.

The program counter 109 stores the address of the memory 4 in which an instruction to be executed next by the CPU 8 is stored. Each time the instruction is read from the memory 4, the stored address is incremented by “1”. Is done.
Each time the CPU 8 reads one instruction from the memory 4, the incrementer 110 adds “1” to the address stored in the program counter 109.

Returning to FIG. 1, when a bitmap is generated by the CPU 8, the display controller 9 draws the bitmap on the display body 10.
The display body 10 is configured to include a memory display body (cholesteric liquid crystal) that can retain display contents even when power supply is stopped. The display contents of the display body 10 are rewritten by the drawing operation of the display controller 9.
The bus controller 11 controls data transfer between the CPU 8 and the units 2 to 12.
The power controller 12 controls power supply to the units 2 to 12 of the information processing apparatus 1 in accordance with a command from the CPU 8.

<Operation of information processing apparatus>
As shown in FIG. 2, the memory 4 of the information processing apparatus 1 stores a series of instructions (programs) described by a programmer. When the instruction to execute the program is input, the CPU 8 Are sequentially read and executed.

Specifically, the memory 4 has
FMT 0
LD. WR3, # 10.125
LD. WR4, # 20.375
ADD. L R5, R3, R4
FMT 8
LD. WR6, # 820000
LD. WR7, # 128000
ADD. L R8, R6, R7
Are stored, and the CPU 8 of the information processing apparatus 1 reads out and executes the program.

Among the above programs, the first line to the fourth line are instructions for performing detailed coordinate calculation of less than one pixel, and the fifth line to the eighth line are instructions for performing a wide range of coordinate calculation.
When the execution of the program is instructed, the CPU 8 starts execution in order from the instruction “FMT 0” on the first line.
When executing the “FMT 0” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs a memory address for fetching the next instruction (memory address storing the “FMT 0” instruction) to the external address bus.
2. The “FMT 0” instruction (F00xxxxx) is fetched from the address indicated by the program counter 109 and stored in the input register 102. ("Xxxxx" is an undefined field, so the value is not important.
3. The instruction decoder 103 decodes the first field (instruction code: F) of the input register 102, and as a result, the control circuit 101 starts the operation of the FMT instruction.
4). The value 0 of the second field (bit shift amount: 00) is output from the input register 102 to the numerical expression format storage circuit 104.
5). The incrementer 110 adds “1” to the value of the program counter 109.

By executing the “FMT 0” instruction, the bit shift amount “0” is set in the numerical expression format storage circuit 104, and the subsequent argument is subjected to 0-bit processing.
When executing the “LD.WR3, # 10.125” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs a memory address at which the next instruction is fetched (memory address where the “LD.WR3, # 10.125” instruction is stored) to the external address bus.
2. The “LD.WR3, # 10.125” instruction (13xx00A2) is fetched from the address indicated by the program counter 109 and stored in the input register 102.
3. The instruction decoder 103 decodes the first field (instruction code: 1) of the input register 102. As a result, the control circuit 101 outputs the LD. Start the operation of the W instruction.
4). The instruction decoder 103 decodes the second field (register number: 3) of the input register 102, and the control circuit 101 holds the result.
5). The value of the fourth field (constant value: 00A2) is output from the input register 102 to the argument conversion circuit 105.
6). The argument conversion circuit 105 shifts the input value (00A2) to the left by 0 bits in accordance with the value 0 instructed from the numerical expression format storage circuit 104, and makes up 0 for missing bits. As a result, the argument conversion circuit 105 outputs 000000A2 (the value 000000A2 is a numerical value representing 10.125 in a 4-bit shift fixed point format).
7). The value 000000A2 output by the argument conversion circuit 105 is stored in the register (R3) of the register file 106.
8). The incrementer 110 adds “1” to the value of the program counter 109.

By executing the “LD.W R3, # 10.125” instruction, the argument 00A2 in the instruction is converted into 000000A2 (decimal 10.125) and stored in the register R3.
When executing the “LD.WR4, # 20.375” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs a memory address at which the next instruction is fetched (memory address where the “LD.WR4, # 20.375” instruction is stored) to the external address bus.
2. The “LD.WR4, # 20.375” instruction (14xx0146) is fetched from the address indicated by the program counter 109 and stored in the input register 102.
3. The instruction decoder 103 decodes the first field (instruction code: 1) of the input register 102. As a result, the control circuit outputs the LD. Start the operation of the W instruction.
4). The instruction decoder 103 decodes the second field (register number: 4) of the input register 102, and the control circuit holds the result.
5). The value of the fourth field (constant value: 0146) is output from the input register 102 to the argument conversion circuit 105.
6). The argument conversion circuit 105 shifts the input value (0146) to the left by 0 bits in accordance with the value 0 instructed from the numerical expression format storage circuit 104, and makes up 0 for the missing bits. As a result, 00000146 is output (value 00000146 is a numerical value representing 20.375 in the 4-bit shift fixed point format).
7). The value 00000146 output from the argument conversion circuit 105 is stored in the register (R4) of the register file 106.
8). The incrementer 110 adds “1” to the value of the program counter 109.

By executing the “LD.W R4, # 20.375” instruction, the argument 0146 in the instruction is converted to 00000146 (decimal 20.375) and stored in the register R4.
When executing the “ADD.L R5, R3, R4” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs a memory address for fetching the next instruction (memory address storing the “ADD.L R5, R3, R4” instruction) to the external address bus.
2. The “ADD.L R5, R3, R4” instruction (2534xxxx) is fetched from the address indicated by the program counter 109 and stored in the input register 102.
3. The instruction decoder 103 decodes the first field (instruction code: 2) of the input register 102, and as a result, the control circuit 101 causes the ADD. The operation of the L instruction is started.
4). The instruction decoder 103 decodes the second field (register number: 5) of the input register 102, and the control circuit 101 holds the result.
5). The instruction decoder 103 decodes the third field (register number: 3) of the input register 102, and the control circuit 101 holds the result.
6). The instruction decoder 103 decodes the fourth field (register number: 4) of the input register 102, and the control circuit 101 holds the result.
7). The register file 106 outputs the values of the register (R3) and the register (R4) to the ALU 107.
8). The ALU 107 adds the value of the register (R3) and the value of the register (R4) and outputs the result to the register file 106.
9. The register file 106 stores the input value in the register (R5). At this time, the value of the register (R5) is 000001E8 representing 30.5, which is the result of adding the value 000000A2 representing 10.125 and the value 00000146 representing 20.375.
10. The incrementer 110 adds “1” to the value of the program counter 109.

By executing “ADD.L R5, R3, R4”, the value 000000A2 stored in the register R3 and the value 00000146 stored in the register R4 are added, and the value 000001E8 as the addition result is added to the register R5. Remembered.
When executing the “FMT 8” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs a memory address for fetching the next instruction (memory address storing the “FMT 8” instruction) to the external address bus.
2. The “FMT 8” instruction (F08xxxxx) is fetched from the address indicated by the program counter 109 and stored in the input register 102.
3. The instruction decoder 103 decodes the first field (instruction code: F) of the input register 102, and as a result, the control circuit 101 starts the operation of the FMT instruction.
4). The value of the second field (bit shift amount: 08) is stored in the numerical expression format storage circuit 104 from the input register 102.
5). The incrementer 110 adds “1” to the value of the program counter 109.

When the “FMT 8” instruction is executed, the bit shift amount “8” is set in the numerical expression format storage circuit 104, and the subsequent arguments are subjected to 8-bit processing.
When executing the “LD.WR6, # 820000” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs the memory address at which the next instruction is fetched (the memory address where the “LD.WR6, # 820000” instruction is stored) to the external address bus.
2. The “LD.WR6, # 820000” instruction (16xxC832) is fetched from the address indicated by the program counter 109 and stored in the input register 102.
3. The instruction decoder 103 decodes the first field (instruction code: 1) of the input register 102. As a result, the control circuit 101 outputs the LD. Start the operation of the W instruction.
4). The instruction decoder 103 decodes the second field (register number: 6) of the input register 102, and the control circuit 101 holds the result.
5). The value of the fourth field (constant value: C832) is output from the input register 102 to the argument conversion circuit 105.
6). The argument conversion circuit 105 shifts the input value (C832) to the left by 8 bits according to the value 8 instructed from the numerical expression format storage circuit 104, and makes up 0 for the missing bits. As a result, the argument conversion circuit 105 outputs 00C83200 (value 00C83200 is a numerical value representing 820000 in a 4-bit shift fixed point format).
7). The value 00C83200 output from the argument conversion circuit 105 is stored in the register (R6) of the register file 106.
8). The incrementer 110 adds “1” to the value of the program counter 109.

By executing the “LD.WR6, # 820000” instruction, the argument C832 in the instruction is converted into 00C83200 (decimal 820000) and stored in the register R6.
When executing the “LD.WR7, # 128000” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs a memory address for fetching the next instruction (memory address storing the “LD.WR7, # 128000” instruction) to the external address bus.
2. The “LD.WR7, # 128000” instruction (17xx1F40) is fetched from the address indicated by the program counter 109 and stored in the input register 102.
3. The instruction decoder 103 decodes the first field (instruction code: 1) of the input register 102. As a result, the control circuit 101 outputs the LD. Start the operation of the W instruction.
4). The instruction decoder 103 decodes the second field (register number: 7) of the input register 102, and the control circuit 101 holds the result.
5). The value of the fourth field (constant value: 1F40) is output from the input register 102 to the argument conversion circuit 105.
6). The argument conversion circuit 105 shifts the input value (1F40) to the left by 8 bits according to the value 8 instructed from the numerical expression format storage circuit 104, and makes up 0 for the missing bits. As a result, the argument conversion circuit 105 outputs 001F4000 (value 001F4000 is a numerical value representing 128000 in a 4-bit shift fixed point format).
7). The value 001F4000 output from the argument conversion circuit 105 is stored in the register (R7) of the register file 106.
8). The incrementer 110 adds “1” to the value of the program counter 109.

By executing the “LD.W R7, # 128000” instruction, the argument 1F40 in the instruction is converted into 001F4000 (decimal 128000) and stored in the register R7.
When executing the “ADD.L R8, R6, R7” instruction, the CPU 8 operates in the following procedure.

1. The program counter 109 outputs the memory address at which the next instruction is fetched (memory address storing the “ADD.L R8, R6, R7” instruction) to the external address bus.
2. The “ADD.L R8, R6, R7” instruction (2867xxxx) is fetched from the address indicated by the program counter 109 and stored in the input register 102.
3. The instruction decoder 103 decodes the first field (instruction code: 2) of the input register 102, and as a result, the control circuit 101 causes the ADD. The operation of the L instruction is started.
4). The instruction decoder 103 decodes the second field (register number: 8) of the input register 102, and the control circuit 101 holds the result.
5). The instruction decoder 103 decodes the third field (register number: 6) of the input register 102, and the control circuit 101 holds the result.
6). The instruction decoder 103 decodes the fourth field (register number: 7) of the input register 102, and the control circuit 101 holds the result.
7). The register file 106 outputs the values of the register (R6) and the register (R7) to the ALU 107.
8). The ALU 107 adds the value of the register (R6) and the value of the register (R7) and outputs the result to the register file 106.
9. The register file 106 stores the input value in the register (R8). At this time, the value of the register (R8) is 00E77200 representing 948000, which is the result of adding the value 00C83200 representing 820,000 and the value 001F4000 representing 128000.
10. The incrementer 110 adds “1” to the value of the program counter 109.

By executing the “ADD.L R8, R6, R7” instruction, the value 00C83200 stored in the register R6 and the value 001F4000 stored in the register R7 are added, and the value 00E77200 as the addition result is stored in the register R8. Is remembered.
By operating in this way, for example, in order to handle a number in a 4-bit shift fixed-point format with an integer part 20 bits and a decimal part 4 bits, conventionally, as shown in FIG. Since it is necessary to use an instruction (LD.L) that handles a bit-type constant value, and the instruction word becomes longer by that amount, in the present invention, as shown in FIG. Bit type etc.) can be used.

  That is, by using the above-described FMT instruction, the argument conversion circuit 105 generates a value that is too small (four instructions in the first half) or a value that is too large (four instructions in the second half) that cannot be expressed in 16-bit length. Convert to 32-bit value in bit-shifted fixed-point format. As a result, it is possible to use a shorter instruction (LD.W) that handles a 16-bit constant value that only requires a length of one word, and the overall instruction length can be reduced.

  As described above, in the information processing apparatus 1 according to the present embodiment, the numeric expression format storage circuit 104 that stores a value indicating the numeric expression format in the CPU 8, and the instruction argument in a format that conforms to the numeric expression format And an argument conversion circuit 105 for converting. An instruction having a different data length, for example, an instruction for performing detailed coordinate calculation of less than one pixel in the process of drawing a character image (instructions on the second to fourth lines) and an instruction for performing a wide range of coordinate calculations (above described above) When the instructions from the sixth line to the eighth line) are handled, the operation of the CPU 8 is switched by executing the instruction designating the numerical expression format. That is, prior to executing the instructions from the second line to the fourth line, the instruction of the first line for adapting the numerical expression format to the coordinate calculation of less than one pixel is executed. Prior to the execution of the 8-line instruction, the interpretation of the argument in the CPU 8 and the conversion of the argument data length are performed by executing the instruction in the fifth line for adapting the numerical expression format to a wide range of coordinate calculations. Is done.

Therefore, when handling instructions having different data lengths, it becomes possible to use an instruction that handles a shorter data length, the instruction data length can be shortened, and the numeric expression format is managed and the data length is converted in the CPU 8. Therefore, high-speed processing can be performed.
That is, according to the information processing apparatus 1 according to the present embodiment, it is possible to efficiently process instructions having different data lengths, and it is possible to reduce the memory cost by reducing the memory area for storing the instructions. Further, power consumption can be reduced by reducing the number of memory accesses when reading an instruction.

Second Embodiment
The information processing apparatus according to the present embodiment realizes the functions of the information processing apparatus according to the first embodiment by software while maintaining a general-purpose processor structure.
The information processing apparatus according to the present embodiment is a general configuration of the information processing apparatus except that a general-purpose processor is used (that is, the numerical expression format storage circuit 104 and the argument conversion circuit 105 in the first embodiment are not provided). Is the same as in the first embodiment.
Therefore, it will be described with reference to FIG. 1 in the first embodiment.
In FIG. 1, since the configuration other than the CPU 8 is the same as that of the first embodiment, the configuration of the CPU 8 will be mainly described.

The CPU 8 reads various programs stored in the external storage 6, develops them into a work area formed in the memory 4, and controls the units 2 to 12.
Specifically, the CPU 8 executes a character drawing process when a character drawing instruction is output from the input unit 2. Then, by the character drawing process, drawing command data (data indicating a combination of a plurality of mnemonics for drawing each element constituting the character and an argument attached to the command) based on the character code of the character. ), Data in which a mnemonic is arranged in a predetermined order), and mnemonics are acquired one by one from the drawing command data according to the predetermined order, and the drawing instruction is based on the mnemonic Generate a bitmap of characters.

Further, when a mnemonic (mode setting mnemonic) for setting the drawing mode is acquired, the CPU 8 configures each element constituting the character for which the drawing instruction is acquired later according to the mode setting mnemonic. The method of handling coordinate values (bit strings) included in the mnemonic corresponding to (element corresponding mnemonic) is set.
That is, the mnemonic constituting the drawing command data is provided with a mnemonic for handling coordinate values according to the drawing mode after the mode setting mnemonic. The drawing mode set by the mode setting mnemonic is stored as a predetermined variable value in the memory 4.

Here, the mode setting mnemonics include ChangeRelInt, ChangeRelFix, ChangeAbsInt, and ChangeAbsFix, as shown in FIG.
ChangeRelInt instructs to treat the coordinate value of the element-corresponding mnemonic as a relative coordinate with the coordinate value of the end point of the element drawn immediately before in the integer format (a format including only the integer part).

ChangeRelFix treats the coordinate value of the element-corresponding mnemonic as a relative coordinate with the coordinate value of the end point of the element drawn immediately before in the decimal format (a format that includes both the integer part and the decimal part). Instruct.
ChangeAbsInt instructs to handle the coordinate value of the element corresponding mnemonic as an absolute coordinate expressed in integer form.

ChangeAbsFix indicates that the coordinate value of the element-corresponding mnemonic is handled as a representation of absolute coordinates in decimal format.
In FIG. 5, EndOfCode is a code indicating that it is the last mnemonic constituting the drawing command data.
As shown in FIGS. 6 to 9, the element-corresponding mnemonics include MoveTo_S, MoveTo_M, MoveTo_L, HorLineTo_S, HorLineTo_M, HorLineTo_L, VerLineTo_S, VerLineTo_M, VerLineTo_L, LineTo_S, LineTo_L, ConicCveTo, LTo CubicCurveTo_M and CubicCurveTo_L.

MoveTo_S, MoveTo_M, and MoveTo_L are codes including the number of arguments (2) and coordinate values (X1, Y1). When the last read mode setting mnemonic is ChangeRelInt or ChangeRelFix, it is instructed to move to the point where the relative coordinates from the end point of the element drawn immediately before are the coordinate values (X1, Y2) To do. When the mode setting mnemonic read last is ChangeAbsInt or ChangeAbsFix, it is instructed to move to the coordinate value (X1, Y2) in the absolute coordinate system.
In the present embodiment, the origin of absolute coordinates is set at the upper left corner of the display body 10, the X axis is formed in the right direction in plan view, and the Y axis is formed in the down direction in plan view.

  HorLineTo_S, HorLineTo_M, and HorLineTo_L are codes including the number of arguments (1) and the coordinate value X1 in the X direction. If the last read mode setting mnemonic is ChangeRelInt or ChangeRelFix, it is instructed to draw a horizontal line of length X1 in the X direction from the start point of the last drawn element as the start point To do. If the last read mode setting mnemonic is ChangeAbsInt or ChangeAbsFix, the end point of the element drawn immediately before is the start point, the start point is the same as the Y coordinate, and the X coordinate value is X1. Instructs to draw a horizontal line as the end point.

  VerLineTo_S, VerLineTo_M, and VerLineTo_L are codes including the number of arguments (1) and the coordinate value Y1 in the Y direction. If the last read mnemonic for mode setting is ChangeRelInt or ChangeRelFix, start the end point of the element drawn immediately before, and draw a vertical line of length Y1 from the start point in the Y direction. Instruct. When the last read mode setting mnemonic is ChangeAbsInt or ChangeAbsFix, the end point of the element drawn immediately before is the start point, the start point is the same as the X coordinate, and the Y coordinate value is Y1. Instructs to draw a vertical line as the end point.

  LineTo_S, LineTo_M, and LineTo_L are codes including the number of arguments (2) and one coordinate value (X1, Y1). When the last read mode setting mnemonic is ChangeRelInt or ChangeRelFix, the starting point is the end point of the element drawn immediately before, and the relative coordinates from the starting point are the coordinate values (X1, Y1). To draw a straight line with the end point. If the last read mode setting mnemonic is ChangeAbsInt or ChangeAbsFix, draw a straight line with the end point of the element drawn immediately before as the start point and the coordinate value (X1, Y1) as the end point. Instruct.

  ConicCurveTo_S, ConicCurveTo_M and ConicCurveTo_L are codes including the number of arguments (4) and coordinate values (X1, Y1) (X2, Y2). When the last read mode setting mnemonic is ChangeRelInt or ChangeRelFix, the starting point is the end point of the element drawn immediately before, and the relative coordinates from the starting point are the coordinate values (X1, Y1). Is designated as a control point, and it is instructed to draw a quadratic Bezier curve whose end point is a point whose relative coordinates from the control point are coordinate values (X2, Y2). When the last read mode setting mnemonic is ChangeAbsInt or ChangeAbsFix, the end point of the element drawn immediately before is used as the start point, the coordinate values (X1, Y1) are used as control points, and the coordinate values (X2, Instructs to draw a quadratic Bezier curve with Y2) as the end point.

  CubicCurveTo_S, CubicCurveTo_M, and CubicCurveTo_L are codes including the number of arguments (6) and coordinate values (X1, Y1) (X2, Y2) (X3, Y3). When the last read mode setting mnemonic is ChangeRelInt or ChangeRelFix, the starting point is the end point of the element drawn immediately before, and the relative coordinates from the starting point are the coordinate values (X1, Y1). Is a first control point, a point at which the relative coordinate from the first control point is a coordinate value (X2, Y2) is a second control point, and the relative coordinate from the second control point is a coordinate value (X3, Y3). Instructs to draw a cubic Bezier curve whose end point is a point. When the last read mode setting mnemonic is ChangeAbsInt or ChangeAbsFix, the end point of the element drawn immediately before is the start point, the coordinate values (X1, Y1) are the first control points, and the coordinate value ( It is instructed to draw a cubic Bezier curve having X2, Y2) as the second control point and (X3, Y3) as the end point.

  For MoveTo_S, HorLineTo_S, VerLineTo_S, LineTo_S, ConicCurveTo_S, and CubicCurveTo_S, if the mode setting mnemonic read last is ChangeRelInt or ChangeAbsInt, a 7-bit bit string is used as the coordinate value. When the mode setting mnemonic read last is ChangeRelFix or ChangeAbsFix, a 3-bit bit string is used for the integer part and a 4-bit bit string is used for the decimal part as coordinate values.

  MoveTo_M, HorLineTo_M, VerLineTo_M, LineTo_M, ConicCurveTo_M, and CubicCurveTo_M use a 10-bit bit string as a coordinate value when the last-read mode setting mnemonic is ChangeRelInt or ChangeAbsInt. When the mode setting mnemonic read last is ChangeRelFix or ChangeAbsFix, a 6-bit bit string is used as an integer part and a 4-bit bit string is used as a decimal part as coordinate values.

  MoveTo_L, HorLineTo_L, VerLineTo_L, LineTo_L, ConicCurveTo_L, and CubicCurveTo_L use a 16-bit bit string as the coordinate value when the last-read mode setting mnemonic is ChangeRelInt or ChangeAbsInt. When the mode setting mnemonic read last is ChangeRelFix or ChangeAbsFix, a 20-bit bit string is used as the coordinate part and a 4-bit bit string is used as the decimal part.

<CPU operation>
Next, the character drawing process executed by the CPU 8 will be described based on the flowchart of FIG.
This character drawing process is executed when a character drawing instruction is issued. First, in step S101, the character code of the character instructed to be drawn is acquired, and the character code is used as an index of font data. Convert.

Next, the process proceeds to step S102, where drawing command data (data composed of a plurality of mnemonics arranged in a predetermined order) is acquired based on the index converted in step S101.
Next, the process proceeds to step S103, and after executing a bitmap generation process (described later) for generating a bitmap of the character for which the rendering instruction has been given based on the rendering command data acquired in step S102, The computation process ends.

Next, the bitmap generation process executed in step S103 of the character drawing process will be described based on the flowchart of FIG.
In this bitmap generation process, first, in step S201, the coordinate value (current coordinate value) v indicating the pixel to be processed is set to (0, 0).
In step S202, the parameter Mode indicating the drawing mode is set to (Rel, Int) (a state in which the mode setting mnemonic “ChangeRelInt” is read).

In step S203, one mnemonic is acquired in accordance with a predetermined order from the drawing command data acquired in step S102.
In step S204, it is determined whether the mnemonic acquired in step S203 is EndOfCode. If it is EndOfCode (Yes), the process proceeds to step S206. If it is not EndOfCode (No), the process proceeds to step S205.

In step S205, based on the mnemonic acquired in step S203, outline data generation processing (described later) for generating outline data indicating the outline of the character for which the drawing instruction has been given is executed, and then in step S203. Transition.
On the other hand, in step S206, a bit map of the character for which the drawing instruction has been given is generated based on the contour data generated in step S205, and then the calculation process is terminated.

Next, the contour data generation process executed in step S205 of the bitmap generation process will be described based on the flowchart of FIG.
In this contour data generation process, first, in step S301, it is determined whether or not the mnemonic acquired in step S203 is any one of ChangeRelInt, ChangeRelFix, ChangeAbsInt, ChangeAbsFix, and EndOfCode. If it is any of ChangeRelInt or the like (Yes), the process proceeds to step S302, and if it is not any of ChangeRelInt or the like (No), the process proceeds to step S303.

In step S302, the parameter Mode is set according to the mnemonic acquired in step S203, and then the calculation process is terminated.
On the other hand, in step S303, the number of arguments is acquired from the mnemonic acquired in step S203, and set as a parameter argnum indicating the number of coordinate values.
In step S304, it is determined whether the parameter argnum set in step S303 is “0”. If it is “0” (Yes), the process proceeds to step S313. If it is not “0” (No), the process proceeds to step S305.

In step S305, one coordinate value is acquired from the mnemonic acquired in step S203 in a predetermined order.
Next, the process proceeds to step S306, and it is determined whether or not Int is included in the Mode set in step S302. If Int is included (Yes), the process proceeds to step S307. If Int is not included (No), the process proceeds to step S308.

In step S307, the coordinate value (bit string) acquired in step S305 is converted into an integer value d, and then the process proceeds to step S309.
On the other hand, in step S307, the coordinate value acquired in step S305 is converted into a decimal value d, and then the process proceeds to step S309.
In step S309, it is determined whether or not Rel is included in the Mode set in step S302. If Rel is included (Yes), the process proceeds to step S310. If Rel is not included (No), the process proceeds to step S311.

In step S310, the coordinate value d converted in step S307 or S308 is added to the current coordinate value v so far to calculate a new current coordinate value v, and then the process proceeds to step S312.
On the other hand, in step S311, the coordinate value d converted in step S307 or S308 is set as a new current coordinate value v, and then the process proceeds to step S312.

In step S312, "1" is subtracted from the parameter argnum to calculate a new argnum, and then the process proceeds to step S304.
On the other hand, in step S313, based on the current coordinate value v sequentially set in step S310 or S311, the outline data of the character for which the drawing instruction has been given is generated, and then this calculation process is terminated.
When MoveTo is included in the mnemonic acquired in step S203, only the coordinate value is calculated, and no character outline data is generated.

<Operation of information processing apparatus>
Next, the operation of the information processing apparatus 1 according to the present embodiment will be described based on a specific situation.
First, it is assumed that the user performs an operation for instructing the drawing of characters, and the input unit 2 outputs a character drawing instruction to the CPU 8. Then, a character drawing process is executed by the CPU 8, and as shown in FIG. 10, first, in step S101, the character code of the character instructed to be drawn is acquired, and the character code is converted into an index of font data. In step S102, drawing command data is acquired based on the index, and in step S103, bitmap generation processing is executed based on the drawing command data.

  When the bitmap generation processing is executed, as shown in FIG. 11, first, in step S201, the coordinate value (current coordinate value) v indicating the pixel to be processed is set to (0, 0), and step S202. Then, the parameter Mode indicating the drawing mode is set to (Rel, Int), and in step S203, one mnemonic is acquired from the acquired drawing command data in a predetermined order, and the determination in step S204 is “No”. In step S205, contour data generation processing is executed based on the acquired mnemonic.

As shown in FIG. 13, when the acquired mnemonic is ChangeRelInt, when the contour data generation process is executed, first, as shown in FIG. 12, the determination in step S301 is “Yes”. In S302, the parameter Mode (Rel, Int) is set in accordance with the acquired mnemonic, and then the calculation process is terminated.
Then, the next mnemonic is acquired through the steps S203 and S204, and the contour data generation process is executed based on the mnemonic in the step S205.

  When the acquired mnemonic is MoveTo_S, when the contour data generation process is executed, the determination in step S301 becomes “No” as shown in FIG. 12, and the acquired mnemonic is determined in step S303. The number of arguments (2) is acquired, and is set as a parameter argnum indicating the number of coordinate values. The determination in step S304 is “No”, and in step S305, one coordinate value is obtained from the acquired mnemonic according to a predetermined order. Is acquired, the determination in step S306 is “Yes”, the acquired coordinate value is converted into an integer value d in step S307, the determination in step S309 is “Yes”, and the converted coordinate is determined in step S310. The value d is added to the current coordinate value v so far, and a new current coordinate value v is calculated. "1" is subtracted from the meter argnum (1), the new argnum (0) is calculated, after the determination of the step S304 has undergone "Yes", the step S313, and ends the operation process.

Then, through the steps S203 and S204, the next mnemonic is acquired, the above flow is repeatedly executed, and character outline data is generated.
Assume that EndOfCode is acquired while the above flow is repeated. Then, the determination in step S204 is “Yes”, and in step S206, a bitmap of the character for which the drawing instruction has been given is generated based on the generated contour data.
Then, the generated bitmap is drawn on the display body 10 by the display controller 9, and the character instructed to be drawn is displayed on the display body 10.

  Thus, in the information processing apparatus according to the present embodiment, when ChangeRelInt and ChangeRelFix are acquired, the coordinate value included in the mnemonic acquired later is relative to the coordinate value of the end point of the element drawn immediately before. Handled as expressed in the coordinate format, and when ChangeAbsInt and ChangeAbsFix were acquired, the coordinate value included in the mnemonic acquired later was handled as expressed in the absolute coordinate format. Also, when ChangeRelInt and ChangeAbsInt are acquired, the coordinate value included in the mnemonic acquired later is handled as expressed only by the integer part, and when ChangeRelFix and ChangeAbsFix are acquired, it is included in the mnemonic acquired later Coordinate values were handled as those expressed as a combination of an integer part and a decimal part. Therefore, the mnemonic that treats the coordinate value included in the mnemonic as expressed in relative coordinates (or only the integer part) and the mnemonic that treats it as expressed in absolute coordinates (or a combination of the integer part and the decimal part) are the same. Since mnemonics can be used, the number of mnemonics can be reduced, and as a result, the compression ratio of the drawing command data can be improved.

  As shown in FIG. 14, the cumulative number of bits of the drawing command data is increased by the mode setting mnemonic by using a mode setting mnemonic such as ChangeRelInt. However, since the frequency of changing the drawing mode is usually low. The amount of increase in the number of bits is slight.

  In addition, when ChangeRelFix and ChangeAbsFix are acquired, a larger bit width (24 bits) is assigned to the coordinate values included in the mnemonic acquired later than when ChangeRelInt and ChangeAbsInt are acquired. I treated it as a thing. Therefore, for example, by obtaining ChangeRelFix and ChangeAbsFix before obtaining a mnemonic for drawing a figure, 24 bits can be assigned to the coordinate values included in the mnemonic, and the figure is drawn on the entire display 10. In this case, precise drawing can be performed without changing the enlargement / reduction ratio. For example, it is not necessary to divide a straight line or a Bezier curve, and as a result, it is possible to prevent the total number of mnemonics from increasing.

<Drawing data generation method>
Next, a method for generating drawing command data used in the information processing apparatus of the present invention will be described.

<Generation method using ChangeRelInt>
FIG. 15 is a flowchart showing RelInt drawing command generation processing for generating drawing command data in which the drawing mode is set by ChangeRelInt.
This RelInt drawing command generation process is a process executed by a drawing command generation computer. First, in step S401, all data stored in the write buffer is discarded (the write buffer is cleared).

In step S402, ChangeRelInt is stored as the first mnemonic constituting the drawing command data.
In step S403, the current coordinate value v is set to (0, 0).
Next, the process proceeds to step S404, and it is determined whether or not there remains a mnemonic used for the configuration of the drawing command data. If it remains (Yes), the process proceeds to step S405. If it does not remain (No), the process proceeds to step S406.

In step S405, a RelInt instruction storage process (described later) for storing data corresponding to the mnemonic determined to remain in step S404 in the write buffer is executed, and then the process proceeds to step S404.
On the other hand, in step S406, EndOfCode is stored as the last mnemonic constituting the drawing command data.

Next, the process proceeds to step S407, and after the data stored in the write buffer in the instruction storage process of step S405 is output as an element constituting the drawing command data (after the write buffer is flushed), this calculation is performed. The process ends.
Next, the RelInt instruction storage process executed in step S405 of the RelInt drawing instruction generation process will be described based on the flowchart of FIG.
In the RelInt instruction storing process, first, in step S501, the type of mnemonic determined to remain in step S404 is determined.
In step S502, the variable n is set to “0”.

In step S503, it is determined whether all the mnemonic arguments (eg, X1, Y1, etc.) determined in step S501 have been processed in steps S504 to S507 described later. If all arguments have been processed (Yes), the process proceeds to step S508. If all arguments have not been processed (No), the process proceeds to step S504.
In step S504, the mnemonic argument arg whose type is determined in step S501 is acquired.

In step S505, a difference d [n] from the current coordinate value v is calculated.
In step S506, the argument arg acquired in step S504 is set as a new current coordinate value v.
Next, the process proceeds to step S507, "1" is added to the variable n to calculate a new variable n, and then the process proceeds to step S503.

On the other hand, in step S508, an instruction corresponding to the argument bit length is acquired.
In step S509, the instruction code corresponding to the type determined in step S501 is stored in the write buffer.
Next, the process proceeds to step S510, and each difference d [n] calculated in step S505 is stored in the write buffer.

In step S511, it is determined whether the total amount of data stored in the write buffer in step S509 or S510 is 32 bits or more. If it is 32 bits or more (Yes), the process proceeds to step S512, and if it is less than 32 bits (No), this calculation process is terminated.
In step S512, the data stored in the write buffer in step S509 or S510 is output as 32 bits as a component of the drawing command data, and then the process proceeds to step S511.

<Generation method using ChangeAbsInt>
FIG. 17 is a flowchart showing AbsInt drawing command generation processing for generating drawing command data in which the drawing mode is set by ChangeAbsInt.
This AbsInt drawing command generation processing is processing executed by a drawing command generation computer. First, in step S601, ChangeAbsInt is stored as the first mnemonic constituting the drawing command data.

Next, the process proceeds to step S602, where it is determined whether or not there remains a mnemonic used for the configuration of the drawing command data. And when it remains (Yes), it transfers to step S603, and when it does not remain (No), it transfers to step S604.
In step S603, an AbsInt instruction storage process (described later) for storing data corresponding to the mnemonic determined to remain in step S602 in the write buffer is executed, and then the process proceeds to step S602.

On the other hand, in step S604, EndOfCode is stored as the last mnemonic constituting the drawing command data, and then this calculation process is stored.
Next, the AbsInt instruction storage process executed in step S603 of the AbsInt drawing instruction generation process will be described with reference to the flowchart of FIG.
In this AbsInt instruction storing process, first, in step S701, the type of mnemonic determined to remain in step S602 is determined.

In step S702, the instruction code corresponding to the type determined in step S701 is stored in the write buffer.
In step S703, it is determined whether all the mnemonic arguments (for example, X1, Y1, etc.) determined in step S701 have been processed in steps S704 and 705 described later. If all the arguments have been processed (Yes), this calculation process is terminated. If all have not been processed (No), the process proceeds to step S704.

In step S704, the mnemonic argument arg whose type is determined in step S701 is acquired.
Next, the process proceeds to step S705, each argument arg acquired in step S704 is stored in the write buffer, and then the process proceeds to step S703.
With this flow configuration, by executing the RelInt drawing instruction generation process or the ChangeAbsInt drawing instruction generation process, after the mode setting mnemonic (ChangeRelInt, ChangeAbsInt) as the drawing instruction data, according to the drawing mode A mnemonic that handles coordinate values can be generated.

In the above embodiment, steps S301 and S302 in FIG. 12 constitute the setting function described in the claims, and similarly, steps S306 to S311 in FIG. 12 constitute the display function, and the CPU 8 in FIG. 12, steps S301 and S302 constitute the setting means, and the CPU 8, display controller 9, and display body 10 in FIG. 1 and steps S306 to S311 in FIG. 12 constitute the display means.
Further, the display program, data structure, and information processing apparatus of the present invention are not limited to the contents of the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  In the above embodiment, when a mode setting mnemonic (ChangeRelInt, ChangeAbsInt, etc.) is acquired, an example in which a coordinate value included in a mnemonic acquired later is treated as expressed in either relative coordinate or absolute coordinate format However, the present invention is not limited to this. For example, as a drawing mode, newly acquired coordinate values are designated as low-compressed coordinates (the sum of the mnemonic instruction bit length and coordinate bit length is a multiple of the number of bits easy to handle for software processing, such as 8, 16, 32, etc. A mode that treats a newly acquired coordinate value as if expressed in a high compression coordinate specification (an instruction system other than a low compression coordinate specification). And when a specific mode setting mnemonic is acquired, the coordinate value included in the mnemonic acquired later is treated as being expressed in either the low-compression coordinate specification or the high-compression coordinate specification. It may be. In such a case, by using the low-compression coordinate designation, when an instruction is dynamically generated by software, a bit operation is not required, so that high-speed processing can be performed.

It is a block diagram which shows the internal structure of the information processing apparatus 1 of 1st Embodiment. It is a figure which shows the program stored in the memory. 2 is a block diagram showing an internal configuration of a CPU 8. FIG. It is a figure which shows the conventional description format of the program stored in the memory 4. It is explanatory drawing for demonstrating the mnemonic for mode setting. It is explanatory drawing for demonstrating the handling of the element corresponding | compatible mnemonic after ChangeRelInt is acquired. It is explanatory drawing for demonstrating the handling of the element corresponding | compatible mnemonic after ChangeAbsInt is acquired. It is explanatory drawing for demonstrating the handling of the element corresponding | compatible mnemonic after ChangeRelFix is acquired. It is explanatory drawing for demonstrating the handling of the element corresponding | compatible mnemonic after ChangeAbsFix is acquired. It is a flowchart which shows the flow of a character drawing process. It is a flowchart which shows the flow of a bitmap production | generation process. It is a flowchart which shows the flow of an outline data generation process. It is explanatory drawing for demonstrating the operation | movement of this embodiment. It is explanatory drawing for demonstrating the operation | movement of this embodiment. It is a flowchart which shows the flow of a RelInt drawing command production | generation process. It is a flowchart which shows the flow of a RelInt instruction | indication storage process. It is a flowchart which shows the flow of an AbsInt drawing command production | generation process. It is a flowchart which shows the flow of AbsInt instruction | indication storage processing.

Explanation of symbols

1 is an information processing apparatus, 2 is an input means, 3 is an input means controller, 4 is a memory, 5 is a memory controller, 6 is an external storage, 7 is an external storage controller, 8 is a CPU, 9 is a display controller, and 10 is a display body , 11 is a bus controller, 12 is a power supply controller, 101 is a control circuit, 102 is an input register, 103 is an instruction decoder, 104 is a numerical expression storage circuit, 105 is an argument conversion circuit, 106 is a register file, 107 is an ALU, 108 Is an output register, 109 is a program counter, 110 is an incrementer

Claims (6)

An information processing apparatus in which an instruction stored in a memory is read by a processor and processed.
Data length setting means for setting the data length of an argument included in the instruction read from the memory;
A data length conversion means for converting an argument included in the instruction read from the memory into a data length set by the data length setting means;
An information processing apparatus comprising: the processor performing an arithmetic process on an argument having a data length converted by the data length conversion unit. Inside the processor,
A setting data length storage circuit for storing the setting of the data length in the arithmetic processing;
A data length conversion circuit for converting an argument included in the instruction into a data length set in the data length setting means;
The data length setting means stores the data length indicated in the instruction in the data length storage circuit when the processor reads and executes an instruction for setting the data length in the arithmetic processing from the memory,
When the processor reads and executes an instruction to perform arithmetic processing from the memory, the data length conversion means converts the argument in the instruction into the data length stored in the data length storage circuit by the data length conversion circuit. The information processing apparatus according to claim 1, wherein the information processing apparatus performs conversion. The data length setting means stores the data length indicated in the instruction in the memory when the processor reads and executes an instruction for setting the data length in the arithmetic processing from the memory,
The data length conversion means refers to a data length stored in the memory and converts an argument in the instruction into the data length when the processor reads and executes an instruction for performing an arithmetic process from the memory. The information processing apparatus according to claim 1. The instruction stored in the memory includes an arithmetic processing instruction whose argument is a value represented by a part of the upper bits and a part of the lower bits among arguments having a predetermined bit length, and is represented by a part of the upper bits. A data length setting instruction for storing a value represented by a part of the upper bits as a data length in the arithmetic processing is stored in advance of an instruction having a value as an argument, and is represented by a part of the lower bits. A data length setting instruction for storing a value represented by a part of the lower bits as a data length in the arithmetic processing is stored in advance of an instruction having a value as an argument.
The data length setting means sets a data length for converting a value represented by the upper bit or a part of the lower bit when the processor reads and executes the data length setting instruction,
The data length converting means shifts an argument included in the arithmetic processing instruction when the processor reads out and executes an arithmetic processing instruction having a value represented by the upper bit or a part of the lower bit as an argument. The information processing apparatus according to any one of claims 1 to 3, wherein the data length is set to the data length set by the data length setting means by a process and a process of inserting zeros. An information processing program for controlling an information processing apparatus in which a processor reads an instruction stored in a memory and performs arithmetic processing,
A data length setting function for setting the data length of an argument included in the instruction read from the memory;
A data length conversion function for converting an argument included in the instruction read from the memory into a data length set by the data length setting function;
And an information processing program for causing the processor to perform arithmetic processing on an argument of the data length converted by the data length conversion function. An information processing method in an information processing apparatus in which a processor reads an instruction stored in a memory and performs arithmetic processing,
A data length setting step for causing the processor to execute a data length setting instruction for setting a data length of an argument included in the instruction read from the memory;
A data length conversion step for converting an argument included in the instruction read from the memory into the data length set in the data length setting step;
An arithmetic processing step in which the processor performs arithmetic processing on an argument of the data length converted by the data length converting means;
An information processing method comprising:

Images