JP2007249357A - Information processor, distributed processing system, and task management method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a distributed processing system for improving the predictability of a time required for the transmission/reception processing of communication data. <P>SOLUTION: An MCU 10 is provided with a CPU 101 and a communication I/F 104, and a real time OS 20 for carrying out the scheduling of a task to be performed by the CPU 101 is mounted. When an interruption request to the CPU 101 is generated by the data reception of the communication I/F 104, the CPU 101 starts an interruption handler. The interruption handler determines the wake-up order of a plurality of tasks in a standby status for data reception based on priority information applied to reception data arriving at the communication I/F 104, and makes performable a task RTA in a standby status for the reception of reception data applied with high priority based on the priority information. Furthermore, a real time OS20 determines the task assigned to the CPU 101 based on the priority of the plurality of tasks in an executable status. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus effective for realizing real-time communication in which transmission / reception processing between information processing apparatuses is completed within a predetermined time.

  Real-time communication means communication in which transmission / reception processing is completed within a certain time. Real-time communication is particularly necessary for transmitting and receiving data between computers in a distributed processing system such as a control system in which a plurality of information processing apparatuses, that is, computers are connected to each other and require hard real-time. . Such distributed processing systems that require hard real-time include, for example, a robot control system that performs posture control using sensor information, and an automobile control system such as brake control.

  As a communication interface capable of realizing the above-mentioned real-time communication, CAN (Controller Area Network), ARCNET (registered trademark), FlexRay (registered trademark), and the like are known. However, application of these communication interfaces to the control system requires special know-how, and the cost of the system development environment is high. Furthermore, the upper limit of the data transfer rate of these communication interfaces is about 10 Mbit / s, and does not support high-speed communication.

  On the other hand, there are interfaces such as Ethernet (registered trademark), USB (Universal Serial Bus) 2.0, and IEEE 1394 as communication interfaces corresponding to high-speed communication. In this specification, 10BASE-T, 100BASE-TX, 1000BASE-T and the like standardized by the IEEE 802.3 committee are collectively referred to as Ethernet (registered trademark). Since these interfaces are widely used as communication interfaces for PCs, there is an advantage that the development environment is substantial. However, since it does not have a real-time communication function, it has been difficult to apply it to a control system that requires hard real-time.

  In order to realize real-time communication or approach real-time communication in a high-speed communication interface such as Ethernet (registered trademark), it is necessary to increase the predictability of time required for transmission / reception processing of communication data.

  Here, the time required for the transmission / reception process of communication data includes the time required for the data transmission process on the data transmission side, the transfer time of the communication network between the communication interface on the transmission side and the communication interface on the reception side, and the data on the reception side. The time required for the reception process is determined comprehensively. In order to improve the predictability of the time required for transmission / reception processing of communication data, it is necessary to suppress variations in the processing time of each of these elements.

  Furthermore, communication data transferred between computers constituting a control system such as a robot is not limited to data that requires hard real time. That is, data transmission / reception at a constant cycle is not necessarily required, but there is communication data that requires a high transfer rate because of a large amount of data.

  In such a situation where various communication data with different real-time requirement levels arrive at one communication interface and there are a plurality of tasks waiting for the arrival of communication data, reception of a task with a high real-time requirement level is received. It is difficult to increase the predictability of the time required for the data reception processing of a task that requires real-time performance so that the processing is waited by reception processing of other communication data that has arrived at the communication interface first.

Patent Document 1 discloses a communication device that prevents a delay in data communication by real-time communication in an environment where both real-time communication and non-real-time communication can be performed. Specifically, a buffer for storing data for real-time communication and a buffer for storing data for non-real-time communication are provided, and priority is given to the buffer for storing data for real-time communication when data is transmitted or received. Thus, data is taken out and data transmission or data reception is performed.
JP 2005-198023 A

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to improve the predictability of time required for transmission / reception processing of communication data in a distributed processing system in which a plurality of computers are connected.

  An information processing apparatus according to the present invention includes a CPU that executes a task, a communication device that can transmit and receive data, an event processing unit, and a scheduling unit. Here, the event processing means determines the wake-up order of a plurality of tasks waiting for data reception based on the priority information given to the received data arriving at the communication device, and the priority It is possible to preferentially execute a task waiting for reception of received data to which a high priority is given by the degree information. Further, the scheduling means determines a task to be assigned to the CPU based on a priority order of a plurality of tasks in an executable state.

  With such a configuration, a task having a high priority can be quickly transitioned to an executable state by the event processing unit, and the task can be dispatched to an execution state quickly by the scheduling unit. For this reason, priority is given to requesting real-time communication even when a plurality of tasks are waiting to receive data for one communication device and a plurality of received data have arrived at the communication device. High priority tasks can be executed preferentially. As a result, the processing time from the arrival of received data to the execution of a receiving task with a high priority can be defined, and the predictability of the time required for the transmission / reception processing of communication data can be improved.

  It is desirable that the priority of the received data indicated by the priority information is determined by reflecting the priority order of tasks that process the received data.

  The event processing means is preferably realized by executing an interrupt handler program that is activated in response to an interrupt request from the communication device to the CPU. When implemented by an interrupt handler in this way, there is an advantage that no special improvement of the real-time OS for performing task scheduling is required when implementing the function performed by the event processing means.

  Furthermore, the information processing apparatus according to the present invention described above preferably includes a task management unit that manages a state of a task executed by the CPU. Here, the task management means is executable in the first state assigned and executed by the CPU, but is not assigned to the CPU because another task is being executed in the CPU. The second state, the third state stopped due to the reception of data arriving at the communication device, and the other state other than the waiting for the reception of data arriving at the communication device; If the task is managed in at least four states of the fourth state, and the data waiting for reception of the task in the third state does not arrive at the communication device within a predetermined time, The task is transited to the second state.

  As described above, when the received data is not obtained within a predetermined time, the task waiting for reception is changed to the state assigned to the CPU, thereby periodically processing the task that requires real-time performance. Can continue.

  The information processing apparatus according to the present invention described above executes a timer for generating an interrupt request at a constant period and a transmission task for executing a data transmission process from the communication device in response to the interrupt request generated by the timer. It is desirable to provide a means for making it possible. Thereby, it is possible to control the start time of data transmission necessary for realizing real-time communication, and it is possible to further improve the predictability of the time required for communication data transmission / reception processing.

  Furthermore, in the data transmission process in the information processing apparatus according to the present invention, the data transmitted from the communication device may be DMA-transferred from the user memory area accessible to the transmission task to the communication device by the transmission task. desirable. With such a configuration, since transmission of transmission data can be started without data copying by the CPU, a delay associated with memory copying can be avoided and transmission processing can be performed at high speed. Further, it is desirable that the transmission task continuously uses the user memory area allocated according to the generation of the transmission task for the DMA transfer until the end of the transmission task. As a result, an unpredictable delay caused by repeatedly securing and releasing the memory area each time transmission data is generated can be eliminated, so that the predictability of the processing time required for the transmission process can be improved.

  The distributed processing system according to the present invention includes a plurality of information processing apparatuses according to the present invention described above, and the communication devices included in the plurality of information processing apparatuses are Ethernet (registered trademark) devices, and the plurality of information The processing devices are communicably connected via a layer 2 switch. With such a configuration, the link connecting the layer 2 switch and the information processing apparatus is in a full-duplex exclusive state. For this reason, there is no room for waiting for data transmission due to a MAC frame collision, and the data transfer time in the network connecting the information processing apparatuses can be predicted.

  The task management method according to the present invention is a task management method in an information processing apparatus equipped with a real-time OS that schedules an assignment order of a plurality of tasks in an executable state to a CPU based on task priority. Specifically, first, the CPU activates an interrupt handler in response to an interrupt request indicating that data has arrived at a communication device included in the information processing apparatus. Next, the interrupt handler scans the priority information given to the plurality of reception data arriving at the communication device, so that the reception data given the highest priority by the priority information is obtained. Select and preferentially transition the task waiting for reception of the selected received data to an executable state. Finally, the real-time OS performs scheduling of tasks that are made executable by the interrupt handler and assigns them to the CPU.

  By such a method, it is possible to specify the processing time from when the received data arrives at the communication device until the reception task with a higher priority is executed, and to improve the predictability of the time required for the transmission / reception processing of the communication data Is possible.

  According to the present invention, it is possible to provide an information processing apparatus, a distributed processing system, and a task management method capable of improving the predictability of time required for communication data transmission / reception processing.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

Embodiment 1 of the Invention
A configuration example of the control system 1 according to the present embodiment is shown in FIG. The control system 1 is a distributed control system in which a plurality of micro controller units (MCUs) 10 are connected to each other. FIG. 1 shows a configuration example in which two micro controller units (MCUs) 10a and 10b are connected to each other by Ethernet (registered trademark), specifically, 100BASE-TX. The MCU 10 a is a computer that performs image processing on image data input by the camera 11. The MCU 11b inputs the image processing result of the MCU 10a via the Ethernet (registered trademark), and uses the image processing result (for example, position information of the target) of the MCU 10a to drive a movable part of the robot. 12 is a computer for controlling 12. The configuration of FIG. 1 is an example, and MCUs 10a and 10b that exchange data necessary for control via Ethernet (registered trademark) can be used for the purpose of controlling various objects. Below, the hardware configuration of the MCUs 10a and 10b, the software configuration, processing effective for realizing real-time communication, and the like will be described. In the following, MCUs 10a and 10b are collectively referred to as MCU10.

  The hardware configuration of the MCU 10 is shown in FIG. The CPU 101 is an arithmetic processing unit that executes a system program stored in a ROM (Read Only Memory) 102 or a nonvolatile memory such as a flash memory (not shown) and an application program for controlling an object.

  A RAM (Random Access Memory) 103 is used as a work area of the CPU 101, and is also used as a temporary storage area for data transmitted and received via a communication interface 104, a digital I / O 105, and an analog I / O 106, which will be described later.

  The communication interface 104 is an interface for transmitting / receiving control data to / from another MCU 10, and is a 100BASE-TX interface in the configuration example of FIG. The digital I / O 105 is an interface that inputs and outputs data input from various sensors such as a camera, a pressure sensor, and a temperature sensor, and digital signals such as control signals output to the sensor. On the other hand, the analog I / O is an interface for inputting / outputting analog signals by performing A / D conversion processing and D / A conversion processing. Note that an interface with an external sensor may be integrated into the data communication interface 104 that exchanges data between the MCUs 10.

  Next, system programs and application programs executed by the CPU 101 will be described with reference to FIG. The system program executed by the MCU 10 of the present embodiment is a real-time OS having a multitask environment, and the application program is divided into tasks based on differences in time constraints. FIG. 3 shows a configuration of a real-time OS 20 executed by the MCU 10 and a plurality of tasks processed in parallel on a multitask environment provided by the real-time OS 20.

  Here, the real-time OS is a system program that provides a multitasking environment and performs preemptive priority-based task scheduling. Preemptive means that processing of a task in the middle of execution can be stopped and a CPU can be assigned to another task. Priority-based means that the task to be executed by the CPU is determined by the priority level given to the task. A task is a program unit that is executed in parallel in a multitasking environment provided by the real-time OS. The real-time OS may also be called a real-time kernel. As a real-time OS, the μITRON 4.0 specification defined by the TRON Association is widely used as a standard specification for a real-time OS.

  The real-time OS 20 executes task management, synchronization between tasks, interrupt management, memory management, time management, device management, and the like using hardware resources such as the CPU 101 and the RAM 103. Since these functions are functions that a conventional real-time OS is provided as standard, only an outline of each function is shown below.

  Task management creates and deletes tasks by managing task states, managing ready queues that indicate the execution order of tasks that can be started, managing priorities assigned to tasks, and saving contexts. , Providing means for starting and ending. Hereinafter, a management mechanism realized by task management will be referred to as a scheduler.

  Inter-task synchronization provides means for inter-task communication and waiting for processing between tasks using a semaphore, a mailbox based on a linked list, or the like.

  Interrupt management manages interrupt handlers that are activated in response to interrupts to the CPU. Specifically, it defines an interrupt handler and plays a role of associating interrupts with interrupt handlers.

  Time management manages system time and realizes time-dependent processing. Specifically, based on the system time, generation and deletion of so-called time event handlers such as handlers that are activated at regular intervals (called cyclic handlers), handlers that are activated at specified times (called alarm handlers), etc. Do.

  Memory management is responsible for managing a shared memory area used for inter-task communication and the like.

  Finally, the device management provides a device driver function for operating each hardware device such as input / output control of the communication interface 104, and a device driver management function. The device driver function may be realized as software independent from the kernel part such as task management, inter-task synchronization, interrupt management, memory management, and time management.

  The reception task RTA, the reception task RTB, the transmission task STC, and the task TD indicate an example of a task group that is executed in the multitask environment of the real-time OS 20 described above. For the following explanation, it is assumed that the reception task RTA and the reception task RTB are tasks for processing data received by the communication interface 104. Furthermore, it is assumed that the reception task RTA is a task with strict time constraints that require real-time communication, and the reception task RTA is given higher priority than the reception task RTB.

  The transmission task STC is a task that executes a process of transmitting data to another MCU 10 via the communication interface 105. The task TD is a task that does not perform data transmission / reception via the communication interface 104. It is assumed that the task TD has a lower priority than the reception task RTA, the reception task RTB, and the transmission task STC.

  The interrupt handler INH is a program that is activated in response to a hardware interrupt requested by a device such as the communication interface 104 connected to the CPU 101.

  Subsequently, the characteristic processing of the MCU 10 that is effective for realizing real-time communication in the communication interface 104 and the configuration of the control system 1 will be described.

<Data reception processing>
The flow of task dispatch performed when received data arrives at the communication interface 104 provided in the MCU 10 will be described with reference to FIGS. FIG. 4 is a timing chart showing the period from when the communication interface 104 receives data until the reception task RTA that has been stopped because of waiting for data reception is started.

  In FIG. 4, when data arrives at the communication interface 104, an interrupt request is made from the communication interface 104 to the CPU 101 (S11). In response to this interrupt request, the CPU 101 activates the interrupt handler INH, and interrupt processing by the interrupt handler NH is executed (S12).

  Here, details of the interrupt processing (S12) performed by the interrupt handler INH activated based on the data reception of the communication interface 104 will be described with reference to the flowchart of FIG. When the interrupt handler INH is activated, the memory area where the received data of the communication interface 104 is stored is accessed, and the priority given to the received data is scanned (step S21). Here, the priority given to the received data is added to the communication data by the MCU 10 on the data transmission side, and higher priority is given to data that is handed over to a task with severe time constraints.

  In order to give priority to communication data transferred by the communication interface 104, first, other tasks are executed in the scheduler so that a transmission task and a reception task that request real-time communication are executed with priority over other tasks. A higher priority will be given. The other tasks here include a reception task and a transmission task that do not require real-time communication. In addition, when the transmission task is executed, a priority reflecting the priority given by the scheduler to the task requesting real-time communication may be added to the transfer data.

  FIG. 6 shows the structure of a MAC frame transferred when the communication interface 104 is a 100BASE-TX interface. When performing data transfer using such a MAC frame, a VLAN tag defined by IEEE802.1p is inserted, and a priority reflecting the priority given to the task by the 3-bit user priority field in the VLAN tag It may be used as a field indicating the degree. Moreover, it is good also as inserting not in a frame header but in the predetermined position in a payload.

  Returning to FIG. 5, in step S22, the reception data with the highest priority is determined, and the reception task corresponding to the reception data is determined. For example, when both the data waiting for reception by the reception task RTA shown in FIG. 3 and the data waiting for reception by the reception task RTB have arrived at the communication interface 104, reception with high priority is performed. The data that the task RTA is waiting to receive is determined, and the reception task RTA corresponding to this is determined.

  In step S23, the reception task RTA determined in step S22 is woken up. Specifically, the address indicating the storage location of the received data is handed over to the reception task RTA, and the state of the reception task RTA is changed from a state waiting for data reception to an executable state (Ready state) to be scheduled. . Note that the state of waiting for data reception is a waiting state (waiting state) in which the context is saved and execution of the task is interrupted, or a communication state (to be referred to as a “com state” hereinafter).

  Subsequently, returning to FIG. 4, processing subsequent to the interrupt processing (S12) by the interrupt handler INH will be described. In S13 after the end of the interrupt handler INH, task scheduling by the real-time OS 20 is performed. The scheduling request may be explicitly requested by the interrupt handler INH or may be implicitly performed by the real-time OS 20 according to the end of the interrupt handler INH. By this scheduling, the reception task RTA that has been released from the data reception wait state and is in the Ready state is scheduled. At this time, by giving the highest priority to the reception task RTA that requests real-time communication, the reception task RTA is dispatched (S14), and the reception task RTA is executed in the CPU 101 (S15).

  As described above, in the MCU 10 according to the present embodiment, priority information reflecting the priority order of the corresponding task is given to the communication data between the MCUs 10, and the priority given to the communication data is referred to. A reception task to be scheduled is selected. As a result, even when the reception data for the reception task RTB having a low priority arrives at the communication interface 104 before the reception data for the reception task RTA having a high priority, the reception task RTA can be executed with priority. .

  If the start of execution of the reception task RTA that requests real-time communication is delayed because a plurality of data has arrived at the communication interface 104, the processing time from the arrival of the reception data until the reception task RTA is dispatched is predicted. Unacceptable fluctuations will occur. In contrast, the MCU 10 according to the present embodiment can execute the reception task RTA with priority even under a situation where a plurality of data arrives at the communication interface 104. For this reason, it is possible to improve the predictability of the processing time from the arrival of the received data until the reception task RTA is dispatched.

  Further, based on the priority information given to the received data, the process for determining the task to be shifted from the data reception waiting state to the Ready state is realized by the interrupt handler INH. Therefore, when implementing this function, there is an advantage that the real-time OS 20, specifically, a task management function (scheduler) for performing task scheduling is not particularly required to be improved.

  In addition, although the interrupt request from the communication interface 104 was mentioned in S11 of FIG. 4, it is normal that many devices other than the communication interface 104 are connected to the CPU 101. For this reason, various interrupt requests with different interrupt factors are made to the CPU 101. In order to arbitrate such a large number of interrupt requests, a priority is assigned to each interrupt request in advance according to the interrupt factor. As a result, when a plurality of interrupt requests having different interrupt factors are generated at the same time, an interrupt request based on an interrupt factor having a higher priority is performed by the CPU 101 or an interrupt controller (not shown) which is a device that transmits the interrupt factor to the CPU 101. Will be processed preferentially.

  For this reason, in order to perform real-time communication in the communication interface 104, it is desirable to give higher priority to interrupt requests caused by data reception of the communication interface 104 than interrupt requests made by other devices. With this configuration, an interrupt request due to data reception of the communication interface 104 is preferentially processed, and an unpredictable processing delay due to waiting for another interrupt request is generated. Can be avoided. Thereby, the predictability of the processing time of the data reception process can be improved.

<Task management>
Next, task management in the real-time OS 20 will be described. FIG. 7 shows a task state transition diagram in the real-time OS 20. Among the task states shown in FIG. 7, the Running state 301, the Ready state 302, the Waiting state 303, and the Dormant state 305 are the same as the task states defined in the conventional task management. Specifically, the Running state 301 is a state in which the CPU 101 is assigned and a task is being executed. In the Ready state 302, conditions necessary for execution of a task are in place, but a task having a higher priority than the task or a task that can be executed first with the same priority as the task is in the Running state 301. Therefore, it cannot be executed.

  When a task in the running state 301 is completed, or a task having a higher priority than the task in the running state 301 enters the ready state 302, a new task is dispatched to the execution state (S31). Note that a task preempted by a task with a higher priority makes a transition from the Running state 301 to the Ready state 302 (S32).

  The Waiting state 303 is a state in which a condition for executing a task is not satisfied and a certain condition is awaited. The task in the Running state 301 transitions to the Waiting state 303 when waiting for the establishment of some condition (S33), and transitions to the Ready state 302 if the condition is met (S34).

  The Dormant state 305 is a state in which a task that has never been started or a task that has been executed has transitioned. The task activated from the Dormant state 305 makes a transition to the Ready state (S37). The task whose execution has been completed transits from the Running state 301 or the Ready state 302 to the Dormant state 305 (S38 or S39).

  In addition to these four states, in this embodiment, the task state that is waiting for the arrival of communication data is defined as the Com state 304, and when a task that requests real-time communication waits for reception, The task is transitioned to the Com state 304 (S35). One condition for the transition from the Com state 304 to the Ready state 302 is to cancel waiting for data reception. Specifically, the change to the Ready state 302 is performed by the interrupt handler INH described above. Apart from this, another condition for transition from the Com state 304 to the Ready state 302 is a timeout. That is, when entering the Com state 304, a timeout time is specified, and if the received data does not arrive even after the timeout time has elapsed, the state transitions from the Com state 304 to the Ready state 302.

  The task that requests real-time communication is usually a task related to processing that requests hard real-time. For this reason, it is not preferable to continue waiting for data reception because it will cause a failure in processing that requires hard real-time. On the other hand, even if it is a process that requires hard real-time, when new received data cannot be obtained, it is possible to avoid the occurrence of a critical situation by executing an alternative process using past received data There is. In the MCU 10 according to the present embodiment, the above-described Com state 304 is defined, and the transition is made from the Com state 304 to the Ready state 302 when the received data does not arrive even after the timeout time elapses. Thereby, the periodic processing of the task can be continued, and the alternative processing as described above can be executed.

<Data transmission process>
A process of transmitting data from the communication interface 104 by the transmission task STC that requests real-time communication will be described. First, in order to realize real-time communication, it is necessary to control the start time of data transmission. In order to realize this, the timing for transmitting data by the task may be determined using the time management function provided in the real-time OS 20 described above. Specifically, data transmission to the communication interface 104 may be performed by a periodic handler that is activated at a constant period based on the system time.

  In order to realize real-time communication with a shorter cycle, it is desirable to perform transmission processing at high speed. Thus, in the MCU 10 according to the present embodiment, the transmission data is DMA-transferred from the transmission task to the communication interface 104 using the DMA (Direct Memory Access) function of the communication interface 104. In normal communication, the transmission data generated by the transmission task is copied from the user memory area to the system memory area and then transferred to the communication interface. In the present embodiment, transmission is performed without data copying by the CPU 101. Data transfer can be started. For this reason, a delay associated with memory copy can be avoided and transmission processing can be performed at high speed.

  In order to perform the above-described DMA transfer, it is necessary to secure an area where DMA transfer is possible as a memory area for generating transmission data. However, in general, it is difficult to predict the processing time in the process of securing the memory area. For this reason, the MCU 10 according to the present embodiment does not repeat the securing and releasing of the memory area every time transmission data is generated, but uses the memory area secured at the start of the task that requires real-time communication at the end of the task. Will be used repeatedly. As a result, memory area allocation and release need only be performed at the start and end of a task, respectively, and unpredictable delays due to memory area allocation processing can be eliminated, improving the predictability of processing time required for transmission processing. Can be made.

<Not using retransmission function>
TCP / IP is widely used as an upper layer (network layer and transport layer) of Ethernet (registered trademark). However, TCP / IP performs retransmission processing when transmission data does not arrive, and is a protocol that enables advanced transfer control such as route selection, so that the processing is complicated and the processing time of communication data is reduced. There is a problem that it is difficult to predict. Therefore, the MCU 10 of the present embodiment does not use TCP / IP. Specifically, in the network layer and the transport layer, only data that associates the communication interface 104 with the task is transferred, and data transfer between the MCUs 10 is performed by the Ethernet (registered trademark) data link layer. Only data transfer control between devices is used.

  At this time, the physical connection between the MCUs 10 is not limited to the point-to-point connection shown in FIG. 1, but two or more MCUs 10 are connected via the layer 2 switch 30 that performs switching based on the MAC address. Can be used. A configuration example of a control system by star connection using the layer 2 switch 30 is shown in FIG. Even in the case of star connection, the physical link between one layer 2 switch 30 and the MCU 10 (twisted pair cable in the case of 100BASE-TX) is occupied in full duplex. For this reason, there is no room for waiting for data transmission due to a MAC frame collision, and the data transfer time can be predicted. When the layer 2 switch 30 is used, an internal delay associated with data store processing and forwarding processing within the layer 2 switch 30 occurs, but the amount of fluctuation in the internal delay time can be predicted.

  As described above, by adopting a configuration in which communication data collision does not occur as a network configuration for connecting the MCUs 10 without retransmitting transmission data, it is possible to improve predictability of time required for data transmission processing. .

Other embodiments.
The MCU 10 according to the first embodiment of the present invention described above has characteristic configurations such as data reception processing, task management, data transmission processing, and non-use of the retransmission function. As a result, the predictability of the time required for the end-to-end transmission / reception processing required to realize real-time communication between the MCUs 10 is improved. However, it is possible to improve the predictability of the time required for the end-to-end transmission / reception processing without having all of the characteristic configurations of the MCU 10.

  For example, by referring to the priority given to communication data, even when only the data reception process for selecting the reception task to be activated preferentially is used, the predictability of the processing time of the data reception process is improved. Therefore, it is possible to contribute to improvement in predictability of time required for end-to-end transmission / reception processing. That is, the MCU according to the present invention does not have to include all of the characteristic configurations included in the MCU 10 according to the first embodiment of the invention, and may include a part of these characteristic configurations. .

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

It is a block diagram of the control system concerning Embodiment 1 of invention. It is a figure which shows the hardware constitutions of MCU concerning Embodiment 1 of invention. It is a figure which shows the software structure of MCU concerning Embodiment 1 of invention. It is a timing diagram for demonstrating the data reception process in MCU concerning Embodiment 1 of invention. It is a flowchart for demonstrating the data reception process in MCU concerning Embodiment 1 of invention. It is a figure which shows the frame format of a MAC frame. It is a state transition diagram for demonstrating the task management of MCU concerning Embodiment 1 of invention. It is a figure which shows an example of the physical connection structure of the control system concerning Embodiment 1 of invention.

Explanation of symbols

1 Control system 10, 10a, 10b Micro controller unit (MCU)
101 CPU
102 ROM
103 RAM
104 Communication interface 105 Digital I / O (DIO)
106 Analog I / O (AIO)
20 Real-time OS (RTOS)
30 Layer 2 switch RTA, RTB reception task STD transmission task INH interrupt handler

Claims (8)

A CPU that executes tasks;
A communication device capable of transmitting and receiving data;
Based on the priority information given to the received data arriving at the communication device, the wake-up order of a plurality of tasks waiting for data reception is determined, and a high priority is given by the priority information. Event processing means for preferentially executing a task waiting to receive received data;
An information processing apparatus comprising scheduling means for determining a task to be assigned to the CPU based on a priority order of a plurality of tasks in an executable state.   The information processing apparatus according to claim 1, wherein the priority of the received data indicated by the priority information is determined by reflecting a priority of a task that processes the received data.   The information processing apparatus according to claim 1, wherein the event processing unit is realized by executing an interrupt handler program started in response to an interrupt request from the communication device to the CPU. Task management means for managing the status of tasks executed by the CPU;
The task management means is executable in a first state assigned to the CPU and executed, but is not assigned to the CPU because another task is being executed in the CPU. State, a third state stopped due to waiting for reception of data arriving at the communication device, and a fourth state stopped due to waiting for establishment of other conditions other than waiting for reception of data arriving at the communication device Manage tasks in at least four states
The task waiting for reception by the task in the third state transitions to the second state if the data does not arrive at the communication device within a predetermined time. Item 4. The information processing apparatus according to Item 1. A timer that generates interrupt requests at regular intervals;
5. The information processing apparatus according to claim 1, further comprising means for causing a transmission task for executing data transmission processing from the communication device to transition to an executable state in response to an interrupt request generated by the timer. Data transmitted from the communication device is DMA-transferred from the user memory area accessible to the transmission task to the communication device by the transmission task,
The information processing apparatus according to claim 5, wherein the transmission task continuously uses the user memory area allocated according to the generation of the transmission task for the DMA transfer until the end of the transmission task. A plurality of the information processing devices according to any one of claims 1 to 6,
The communication devices included in the plurality of information processing apparatuses are Ethernet (registered trademark) devices,
The distributed processing system in which the plurality of information processing apparatuses are communicably connected via a layer 2 switch. A task management method in an information processing apparatus equipped with a real-time OS that schedules an assignment order of a plurality of tasks in an executable state to a CPU based on task priority,
The CPU activates an interrupt handler in response to an interrupt request indicating that data has arrived at a communication device included in the information processing apparatus,
The interrupt handler scans the priority information given to a plurality of received data arriving at the communication device, and selects the received data given the highest priority by the priority information, The task waiting to receive the selected received data is preferentially transitioned to the executable state,
A task management method in which the real-time OS performs scheduling of tasks that are made executable by the interrupt handler and assigns them to the CPU.