JP2007243527A - Sample timing monitor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect abnormal timing in a sampling pulse. <P>SOLUTION: A sample timing monitor system has at least one detection circuit. The detection circuit comprises: a pulse conversion circuit for converting the timelike relationship between a drive signal for driving an imaging pickup device and the sampling pulse supplied to a sampling circuit for performing correlation double sampling to an analog output signal outputted from the image pickup device to a pulse; a counter circuit for measuring the width of a pulse outputted from the pulse conversion circuit; and a comparison circuit for determining whether a value measured by the counter circuit is within a prescribed range. The detection circuit can detect the abnormal output timing of a sampling pulse based on a result determined by the comparison circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a sample timing monitor system for detecting an abnormality in timing of a signal supplied to a sampling circuit that outputs a digital video signal by performing predetermined signal processing on an analog output signal from an image sensor, and further relates to the system The present invention relates to an electronic endoscope apparatus including

  2. Description of the Related Art Conventionally, in a device including an image sensor such as a CCD, a CDS (Correlated double sampling) circuit for reducing noise of an analog output signal from the image sensor has been often used. In the CDS circuit, a sampling pulse for sampling a video signal period in an analog output signal of a CCD and a sampling pulse for sampling a field through period are used to sample a digital video signal. The CDS circuit can output a video signal from which noise has been removed by extracting the difference between the voltage value sampled during the video signal period and the voltage value sampled during the field-through period. That is, as the analog output signal of the CCD, a signal including reset noise is output in the field through period, and a signal in which the reset noise and the video signal are superimposed is output in the subsequent video signal period. Therefore, a video signal from which reset noise has been removed is output by taking the difference between outputs during those periods.

  When the sampling pulse supplied to the CDS circuit deviates from the intended timing, the CDS circuit does not perform normal sampling of the video signal, resulting in an abnormality in the image output to the monitor or the like. End up. Therefore, the sampling pulse has the intended timing, that is, the sampling pulse for sampling the video signal period is within a predetermined range during the video signal period, and the sampling pulse for sampling the field through period is the field through period. It is set to be supplied within a predetermined range.

  Patent Document 1 describes an electronic endoscope apparatus including a sampling pulse automatic adjustment device that can automatically adjust the timing of a sampling pulse for sampling a digital video signal from an analog output signal obtained by an image sensor. Has been. In this sampling pulse automatic adjustment device, the phase of the sampling pulse is adjusted by the delay time by measuring the propagation delay time from when the drive signal is output until the analog output signal of the CCD is input to the CDS circuit. It is possible. Therefore, the apparatus can easily adjust the timing of the sampling pulse even if the delay time as described above changes due to a change in the length of the insertion portion of the electronic endoscope apparatus. Yes.

JP 2002-27335 A

  In an electronic endoscope apparatus, when an abnormality is seen in an image picked up by an image pickup device and output to a monitor or the like, an inspection or the like is performed to find out the cause. In the inspection, since various circuit elements are included in the periphery including the image sensor, various items must be checked. Among them, the check of the timing of the sampling pulse used in the CDS circuit tends to be overlooked. That is, at the time of inspection, the inspection is often performed assuming that the timing of the sampling pulse is normal. However, if an abnormality in the timing of the sampling pulse is overlooked, it is difficult to specify the abnormality even if other parts are inspected, and there is a problem that the inspection time is wasted.

  On the other hand, in the sampling pulse automatic adjustment device described in Patent Document 1, it is possible to adjust the phase of the sampling pulse in accordance with the delay time that affects the length of the insertion portion of the electronic endoscope device. However, if the timing of the sampling pulse has deviated from the intended timing before automatic adjustment, it is difficult to return the timing of the sampling pulse to a normal state even with the automatic adjustment device. Therefore, the above problem cannot be solved.

  Therefore, there has been a demand for a means that can easily detect that an abnormality has occurred in the timing of the sampling pulse at the time of inspection when an abnormality is seen in the video.

  Therefore, an object of the present invention is to provide a sample timing monitor system capable of detecting an abnormality in timing of a sampling pulse and an electronic endoscope apparatus including the system.

  In order to solve the above problems, in the present invention, a drive signal for driving the image sensor, and a sampling pulse supplied to a sampling circuit that performs correlated double sampling on an analog output signal output from the image sensor, Conversion circuit capable of converting the temporal relationship between them into a pulse, a counter circuit for measuring the width of the pulse output from the pulse conversion circuit, and whether the value measured in the counter circuit is within a predetermined range A sampling circuit having at least one detection circuit that determines whether or not, and the detection circuit can detect an abnormality in the output timing of the sampling pulse based on a determination result in the comparison circuit Provide a monitor system.

  Therefore, according to the present invention, the timing between the driving signal such as the reset gate signal and the horizontal driving signal and the sampling pulse supplied to the CDS circuit for sampling the field through period and the video signal period of the analog output signal. Can be measured using a counter. An abnormality in the sample signal can be detected based on whether or not it is included in a predetermined time interval from the measured value.

  In the sample timing monitor system according to the present invention, the pulse output from the pulse conversion circuit has a pulse width corresponding to the time interval from the falling edge of the drive signal to the rising edge of the sampling pulse.

  The first detection signal has two detection circuits, one of which is a reset gate signal as a driving signal and a first sampling signal for sampling a field through period of the analog output signal as a sampling pulse. The other detection circuit is a second detection circuit in which the drive signal is a horizontal drive signal and the sampling pulse is a second sampling signal for sampling the video signal period of the analog output signal.

  The detection circuit further includes an abnormality notification means for notifying an abnormality when an abnormality in the output timing of the sampling pulse is detected.

  In addition, the abnormality notification unit notifies the abnormality when an abnormality is detected in at least one detection circuit when the system includes at least two detection circuits. For example, the abnormality notification means notifies the abnormality by light emission.

  The pulse conversion circuit is a D-type flip-flop circuit having a reset input, and a drive signal is input as a clock signal and a sampling pulse is input as a reset signal. In addition, at least the detection circuit is formed in the programmable IC.

  In addition, it further includes a drive signal detection circuit capable of comparing the timing between at least two drive signals and detecting an abnormality in output timing between the drive signals. The drive signal detection circuit can detect an abnormality by determining whether or not the rise of the reset gate signal and the rise of the horizontal drive signal are the same among the drive signals.

  The sample timing monitor system of the present invention is provided in an electronic endoscope apparatus.

  According to the present invention, with the above-described configuration, it is possible to provide a sample timing monitor system capable of detecting an abnormality in the timing of the sampling pulse and an electronic endoscope apparatus including the system.

  Hereinafter, a sample timing monitor system according to the present invention and an electronic endoscope apparatus including the system will be described with reference to the drawings. In the embodiment of the present invention, a case where the system is employed in an electronic endoscope apparatus will be described. However, the system is not limited to being implemented with an electronic endoscope apparatus. For example, the present invention can be implemented in various devices including a digital camera, a digital video camera, a mobile phone, and other imaging devices.

  FIG. 1 is a functional block diagram of the electronic endoscope apparatus 100. The electronic endoscope apparatus 100 includes a CCD 110 that is an image sensor, a CCD driver circuit 120, a CDS (Correlated Double Sampling) circuit 130, a programmable IC 140, a configuration ROM 140C, a signal processing circuit 150, A buffer 160 and an amplifier 170 are included. In addition, a processor 200 and a monitor 300 as external devices can be connected to the electronic endoscope apparatus 100. Although not shown, the electronic endoscope apparatus 100 includes an insertion portion that is a portion to be inserted into the body cavity of a patient, an operation portion for performing various operations, an image processing device, and the like. Each function is provided inside them.

  The CCD 110 is provided near the distal end of the insertion portion of the electronic endoscope apparatus 100. The CCD 110 has a light receiving surface that receives reflected light reflected from a subject when illumination light is irradiated onto the subject from a light source (not shown). A plurality of photodiodes are arranged on the light receiving surface, and each photodiode corresponds to a pixel. The charge accumulated in the photodiode according to the reflected light from the subject is read and transferred by the vertical drive signal supplied to the CCD 110, and then output as an analog output signal by the horizontal drive signal and the reset gate signal. Is done.

  A cable or the like for connecting the CCD 110, the CCD driver circuit 120, and the CDS circuit 130 is disposed in the insertion portion of the electronic endoscope apparatus 100. The analog output signal output from the CCD 110 is input to the CDS circuit 130. Various drive signals (vertical / horizontal drive signals, reset gate signals, etc.) and power to the CCD 110 are output via the CCD driver circuit 120.

  The CCD driver circuit 120 supplies the generated vertical drive signal, horizontal drive signal, reset gate signal, and the like to the CCD 110. At the same time as output to the CCD 110, a horizontal drive signal and a reset gate signal are output to the programmable IC 140.

  The CDS circuit 130 is a circuit for removing noise such as reset noise of the CCD 110. The analog output signal of the CCD 110 has a reset period, a field through period, and a video signal period (detailed in FIG. 2). The CDS circuit 130 samples the black level (voltage value during the period) during the field-through period and the video level (voltage value during the period) during the video signal period. A digital video signal is generated and output based on the difference between the black level and the video level. Note that the CDS circuit 130 includes an AGC (automatic gain control), an A-D converter (ADC), and the like, and processing by these functions is also executed in the generation of a digital video signal.

  The CDS circuit 130 is supplied with a black sample signal and a video sample signal, which are sampling pulses for defining the timing for sampling the voltage of the black level and the video level. The black sample signal and the video sample signal are generated and supplied by the signal processing circuit 150.

  The programmable IC 140 is an IC such as an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device). The programmable IC 140 has an advantage that a circuit can be created without designing and manufacturing a mask pattern, although the unit price during mass production is higher than that of an ASIC or the like. For this reason, in devices such as electronic endoscope devices where the number of units produced per model is small, and therefore the reduction of development costs is more important than the reduction of manufacturing costs, programmable ICs are used as circuits. It is preferable to use it.

  The programmable IC 140 includes a control circuit that controls the entire electronic endoscope apparatus 100. The programmable IC 140 also includes a sampling pulse timing abnormality detection circuit 400 (see FIG. 3). The abnormality detection circuit 400 has a function of detecting an abnormality in timing of each of the black sample signal and the video sample signal (details will be described later). Therefore, when incorporating the abnormality detection circuit 400 into the electronic endoscope apparatus, it is only necessary to add the circuit inside the programmable IC. That is, the abnormality detection circuit 400 can be introduced without complicating the circuit configuration inside the electronic endoscope apparatus 100.

  The configuration ROM 140C holds a program for starting up the volatile programmable IC 140 (that is, for configuring at least the above-described abnormality detection circuit 400). Note that when a CPLD is used as the nonvolatile programmable IC, for example, the above-described program may be executed only once at the time of manufacture, so the configuration ROM 140C may be omitted.

  The signal processing circuit 150 includes a DSP (Digital Signal Processor), an image memory, a DA converter, and the like. The signal processing circuit 150 has a function of performing predetermined signal processing on the digital video signal of the CCD 110 output from the CDS circuit 130 and transmitted via the programmable IC 140. For example, the signal processing circuit 150 performs predetermined processing on the digital video signal, and finally outputs an analog video signal such as an RGB signal. The signal processing circuit 150 includes a signal generator and can generate a black sample signal and a video sample signal. The black sample signal and the video sample signal generated in the signal processing circuit 150 are output to the CDS circuit 130 and also to the programmable IC 140 (abnormality detection circuit 400).

  The analog video signal output from the signal processing circuit 150 is subjected to processing such as amplification by the amplifier circuit 170 and is output to the monitor 300 as a video signal. On the monitor 300, an image captured by the CCD 110 is displayed.

  The processor 200 is, for example, a signal processing device with a built-in light source, and is a device that can be input by an inspection operator using a keyboard (not shown). In addition, various types of information regarding the electronic endoscope apparatus 100 can be displayed. The processor 200 can control the programmable IC 140, the signal processing circuit 150, and the like via the buffer 160.

  In the description of the electronic endoscope apparatus 100 described above, the CCD driver circuit 120 generates a horizontal drive signal and a reset gate signal, and the signal processing circuit 150 generates a black sample signal and a video sample signal. It was supposed to be. However, the place where these signals are generated is not particularly limited, and may be generated in any one of the CCD driver circuit 120, the programmable IC 140, and the signal processing circuit 150, for example.

  FIG. 2 shows a timing chart of the horizontal drive signal, the reset gate signal, the analog output signal of the CCD 110, the black sample signal, and the video sample signal.

2 (a) shows the output timing of the horizontal driving signal _{S H} outputted from the CCD driver circuit 120. FIG. 2B shows the output timing of the reset gate signal _SRG output from the CCD driver circuit 120. Depending on the horizontal driving signal _{S H} and the reset gate signal _{S RG,} the period of the analog output signal of CCD110 is determined. The rising edges of the horizontal drive signal _SH and the reset gate signal _SRG are adjusted to be simultaneous.

FIG. 2C shows the analog output signal S _OUT of the CCD 110. The analog output signal of CCD110 is composed of a reset period _{T R,} and the field-through period _{T F,} the image signal period _{T V.} Reset period T _R is a period corresponding to the pulse width of the reset gate signal S _RG. Field through period T _F is a period in which only the reset noise determined in the reset period T _R is output. Image signal period T _V is the period corresponding to the pulse widths of the horizontal driving signal S _H, a period in which the video signal detected at each pixel of a reset noise and CCD110 is output by superimposing. In FIG. 2C, the analog output signal _Sout is schematically shown, but in actuality, the rise or fall of the signal in each period has some temporal spread. In other words, the output of the analog output signal S _OUT changes gently near the boundary of each period.

Figure 2 (d) shows the output timing of the black sampling signal S _B outputted from the signal processing circuit 150. Figure 2 (e) shows the output timing of the image sampling signal S _V output from the signal processing circuit 150. The CDS circuit 130, the black level and the video level is sampled in a black sample signal S _B and the image sampling signal S _V, respectively rising. Incidentally, the black sample signal near the center of the pulse of the rising field-through period of S _B (i.e., had a near the center, in the period in which the analog output signal S _OUT is adjacent in the vicinity at the beginning and end of the period as included for) likely to have affected the output, the rise of the pulse of the image sampling signal S _V is to be included in the central vicinity (same as above) of the image signal period is adjusted respectively. However, in actuality, the delay time from when the drive signal (the horizontal drive signal _SH and the reset gate signal S _RG ) is output until the analog output signal S _OUT is input to the CDS circuit 130 is considered. the output timing of the black sampling signal S _B and the image sampling signal S _V is set. That is, the black sample signals S _B and image sampling signal S _V, only the delay time to be expected, is output with a delay than the drive signal. In an embodiment of the present invention, the black sample signal S _B is based on the reset gate signal S _RG, as image sampling signal S _V is based on the horizontal driving signal S _H, the respective timings are monitored. That is, if these timings deviate from the assumed timing, it is determined that there is an abnormality.

The time difference between the horizontal driving signal _{S H} and the reset gate signal _{S RG} in each rising and _{t 1.} Further, the time difference between the falling edge of the reset gate signal S _RG to the rising of the black sampling signal S _B and t _2. Further, the t ₃ the time difference to the rising of the image sampling signal S _V from the fall of the horizontal driving signal S _H.

  FIG. 3 is a diagram showing a sampling pulse timing abnormality detection circuit 400 provided in the programmable IC 140. The abnormality detection circuit 400 includes a black sample signal circuit 410, a video sample signal circuit 430, and an LED 450. The black sample signal circuit 410 includes a flip-flop 411, a counter circuit 412, and a comparison circuit 413. The video sample signal circuit 430 includes a flip-flop 431, a counter circuit 432, and a comparison circuit 433.

  The flip-flops 411 and 431 are D-type flip-flops and have a reset inverse terminal (˜CLR terminal) and a preset inverse terminal (˜PR terminal). Further, the clock terminals (CK terminals) of the flip-flops 411 and 431 are of a type in which rising is input. In this embodiment, H is always input to the D terminal and the ~ PR terminal of the flip-flops 411 and 431. FIG. 4 shows a truth table of the flip-flop 411 (same for 431).

In the black sample signal circuit 410, a signal obtained by inverting the reset gate signal _SRG is input to the CK terminal of the flip-flop 411. That is, the flip-flop 411 outputs the value D (H) to the Q terminal when the reset gate signal _SRG falls. Further, the ~CLR terminal, black sampling signal _{S B,} which is inverted is input. That is, when the black sampling signal _{S B} becomes H level, L is the input flip-flop 411 is cleared (Q terminal becomes L) in ~CLR terminal. Accordingly, the output of the Q terminal, H becomes at the falling edge of the reset gate signal S _RG, then, it becomes the black sample signal S _B is inputted as L. Thus, flip-flop 411 outputs a pulse P _B for a time interval until the rise of the black sampling signal S _B and the pulse width from the falling of the reset gate signal S _RG. Flip-flop 411, together with the input of the reset gate signal _{S RG} and black sampling signal _{S B,} sequentially outputs a pulse _{P B.}

The counter circuit 412, the pulse _{P B} output from flip-flop 411 as an input value, and counts the pulse width _{t 2} of the pulse _{P B.} The counter circuit 412 may be well-known pulse width counter (period _{T 2} of the clock used to count the pulse width _{t 2 is} T 2 << _{t 2).}

The comparison circuit 413, the value of t ₂ which is output from the counter circuit 412 as an input value is compared with a previously specified value. That is, the counter circuit 412 has a lower limit _{t 2MIN} and the upper limit value _{t 2MAX} of _{t 2} is set in advance, it is possible _{to t 2} is to determine whether it is within the scope of those _{(t 2MIN} ≦ _{t 2} ≦ Determine if t _2MAX ). The comparison circuit 413 _outputs L if t ₂ is t _{2 MIN} ≦ t ₂ ≦ t _{2 MAX,} and outputs H if t ₂ <t _{2 MIN} and t ₂ > t _{2 MAX} . The lower limit value t _2MIN and the upper limit value t _2MAX can be set using the processor 200, respectively.

In the video sample signal circuit 430, the CK terminal of the flip-flop 431, the inverted signal is input to the horizontal driving signal S _H. That is, flip-flop 431, at the fall of the horizontal driving signal _{S H,} and outputs the value of D (H) to the Q terminal. Further, the ~CLR terminal, inverted image sampling signal _{S V} is inputted. That is, when the image sampling signal _{S V} becomes H level, L is the input flip-flop 431 is cleared (Q terminal becomes L) in ~CLR terminal. Accordingly, the output of the Q terminal, H becomes at the fall of the horizontal driving signal S _V, then becomes the video sample signal S _V is inputted as L. Thus, flip-flop 431 outputs a pulse P _V to the time interval from the fall of the horizontal driving signal S _H to the rising of the image sampling signal S _V and the pulse width. Flip-flop 431, with the input of the horizontal drive signal _{S H} and the image sampling signal _{S V,} sequentially outputs a pulse _{P V.}

The counter circuit 432, the pulse _{P V} output from the flip-flop 431 as an input value, and counts the pulse width _{t 3} of the pulse _{P V.} The counter circuit 432 may be well-known pulse width counter (clock period _{T 3} which is used for counting the pulse width _{t 3 is T 3} << _t 3).

The comparison circuit 433, the value of t ₃ when output from the counter circuit 432 as an input value is compared with a previously specified value. That is, the counter circuit 432 has a lower limit _{t 3MIN} and the upper limit value _{t 3MAX} of _{t 3} is set in advance, _{t 3} can determine whether it is within the scope of those _{(t 3MIN} ≦ _{t 3} ≦ Determine if it is _t3MAX ). The comparison circuit 433 _outputs L if t ₃ is t _3MIN ≦ t ₃ ≦ t _3MAX , and H if t ₃ <t _3MIN and t ₃ > t _3MAX . The lower limit value t _3MIN and the upper limit value t _3MAX can be set using the processor 200, respectively.

The LED 450 is lit when an abnormality is detected in at least one of the black sample circuit 410 and the video sample circuit 430 (provided that Enable is H). That is, the LED 450 is turned on when either or both of the comparison circuit 413 and the comparison circuit 433 output H. The abnormality detection circuit 400 is configured to emit light when a predetermined voltage (5 V) is applied to one terminal of the LED 450 and the output of the NOT circuit is 0 V (L). The emission of the LED 450, the operator who performs the test, it is possible to notify the abnormality of the black sampling signal S _B or video sample signal S _V. For example, the LED 450 is provided on the circuit board of the electronic endoscope apparatus 100 and in the vicinity of the programmable IC 140. However, the arrangement of the LED 450 is not limited thereto. Further, it means for notifying the abnormality of the image sampling signal S _V or black sample signal S _B is without using the LED 450, for example, may be configured to display to that effect on the monitor 300.

  As above, the configuration in which the abnormality of the black sample signal or the video sample signal can be detected in the electronic endoscope apparatus 100 has been described. When the inspection is actually performed, for example, when the operator operates the processor 200, the Enable signal of the abnormality detection circuit 400 included in the programmable IC 140 is switched from L to H via the buffer 160. Alternatively, the Enable signal may be configured to output L for a predetermined time after the power source of the electronic endoscope apparatus 100 is turned on. By doing so, it is possible to avoid detecting the timing of the sample signal in an unstable state when the power is turned on. When H is output from either the comparison circuit 413 or the comparison circuit 433, the LED 450 is turned on. In addition, for example, the operator can adjust the timing of the video sample signal and the black sample signal by setting a predetermined parameter for the signal processing circuit 150 using the processor 200. In the embodiment of the present invention, two sample circuits (410, 430) are provided in the abnormality detection circuit 400. However, the configuration may be such that only one of the sample circuits is provided. That is, even if only one of them is provided, the object of the present invention of easily detecting an abnormality in the sample signal can be achieved. Moreover, you may provide LED individually in each circuit for a sample.

  Therefore, according to the present invention, it is possible to realize a function that can easily detect an abnormality in a sampling pulse by simply adding a predetermined circuit using the programmable IC 140.

Further, when performing the inspection, it is necessary to check whether there is an abnormality in the timing of the horizontal drive signal _SH and the reset gate signal _SRG . In this case, although it can be confirmed with an oscilloscope or the like, a circuit for detecting an abnormality in the timing difference t ₁ between the horizontal drive signal _SH and the reset gate signal _SRG may be provided. For example, by using the configuration of the abnormality detection circuit 400 as described above, it is possible to check for an abnormality by checking whether the rising timings of the horizontal drive signal _SH and the reset gate signal _SRG are the same (that is, t ₁ = 0). Detection is possible.

It is a functional block diagram of an electronic endoscope apparatus. It is a timing chart of a horizontal drive signal, a reset gate signal, an analog output signal, a black sample signal, and a video sample signal. It is a figure which shows an abnormality detection circuit. It is a truth table of a flip-flop.

Explanation of symbols

100 Electronic endoscope device 110 CCD
120 CCD driver circuit 130 CDS circuit 140 Programmable IC
150 Signal Processing Circuit 160 Buffer 170 Amplifier 200 Processor 300 Monitor 400 Anomaly Detection Circuit 410 Black Sample Circuit 430 Video Sample Circuit 411, 431 Flip-Flop 412, 432 Counter 413, 433 Comparison Circuit 450 LED

Claims (11)

Converts a temporal relationship between a drive signal for driving an image sensor and a sampling pulse supplied to a sampling circuit that performs correlated double sampling on an analog output signal output from the image sensor into a pulse. Possible pulse conversion circuit,
A counter circuit for measuring the width of a pulse output from the pulse conversion circuit;
A comparison circuit for determining whether or not a value measured in the counter circuit is within a predetermined range, and comprising at least one detection circuit,
The sample timing monitor system characterized in that the detection circuit can detect an abnormality in the output timing of the sampling pulse based on a determination result in the comparison circuit.   2. The sample timing monitor system according to claim 1, wherein the pulse output from the pulse conversion circuit has a pulse width corresponding to a time interval from a fall of the drive signal to a rise of the sampling pulse. Two detection circuits,
One is a first detection circuit in which the drive signal is a reset gate signal and the sampling pulse is a first sampling signal for sampling a field through period of the analog output signal;
The other is a second detection circuit in which the drive signal is a horizontal drive signal and the sampling pulse is a second sampling signal for sampling a video signal period of the analog output signal;
The sample timing monitor system according to claim 1, wherein the sample timing monitor system is a sample timing monitor system.   4. The sample timing monitoring system according to claim 1, further comprising an abnormality notifying means for notifying an abnormality when an abnormality in an output timing of the sampling pulse is detected in the detection circuit. .   5. The abnormality notification unit, when at least two detection circuits are provided in the system, notifies an abnormality when an abnormality is detected in at least one of the detection circuits. The sample timing monitor system described in 1.   6. The sample timing monitor system according to claim 4, wherein the abnormality notification means notifies abnormality by light emission. The pulse conversion circuit is a D-type flip-flop circuit having a reset input,
7. The sample timing monitor system according to claim 1, wherein the drive signal is input as a clock signal, and the sampling pulse is input as a reset signal.   8. The sample timing monitor system according to claim 1, wherein at least the detection circuit is formed in a programmable IC.   The drive signal detection circuit according to any one of claims 1 to 8, further comprising a drive signal detection circuit capable of detecting an abnormality in output timing between the drive signals by comparing timings between at least two of the drive signals. Sample timing monitor system.   The drive signal detection circuit is capable of detecting an abnormality by determining whether or not the rise timing of the reset gate signal and the rise timing of the horizontal drive signal are the same among the drive signals. 10. The sample timing monitor system according to claim 9, wherein An electronic endoscope apparatus comprising the sample timing monitor system according to claim 1.

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