JP2007243366A - Motion vector searching apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems of the conventional searching apparatus that it is difficult to obtain the same access time at all times when a block unit is adaptively changed and wasteful accesses to a frame memory are caused since read positions of pixel data used for searching a motion vector from the memory are complicated. <P>SOLUTION: A reference image cache memory 100 has a storage capacity for signals with a range of blocks wherein the number of blocks in a horizontal direction is equal to the number of blocks in the horizontal direction of image signals for one screen and the number of blocks in a vertical direction is greater than the number of blocks in the vertical direction of a searching range. Reference image signals in the searching range are read from the cache memory 100 and written in a reference image buffer 407 to be used for searching the motion vector, and the reference image signals of blocks at positions ahead by the prescribed number of blocks in a raster order from the center block of a searching range are read from a reference image frame memory 405 and written in the cache memory 100. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a motion vector search apparatus, and more particularly to a motion vector search apparatus used in an image high efficiency encoding apparatus that performs predictive encoding with reference to an image signal having a field / frame structure.

  In general, a high-efficiency image encoding method is indispensable for moving image transmission and recording. For example, MPEG-2 Video (ISO / IEC13818-2) system is adopted in digital broadcasting. Furthermore, in recent years, the H.264 / MPEG-4AVC (ITU-T Rec. H.264 | ISO / IEC14496-10 MPEG-4 Part 10: Advanced Video Coding) system has been adopted for broadcasting and storage media, and portable terminals. Attention has been paid to low-rate coding for video and high-quality coding methods that are higher than conventional methods. However, since the encoding device and the decoding device require more complicated signal processing than before, the hardware load increases, which is a problem.

  Hereinafter, a macroblock reference method based on a field / frame structure used in the inter-picture prediction encoding unit in the H.264 / MPEG-4 AVC encoding apparatus according to the present invention will be described.

  In the H.264 / MPEG-4AVC encoding system, as shown in Table 1-1 (1-1) to (1-4), a field having a picture structure / frame adaptive encoding and a field having a macroblock structure according to an input image format. 4 types of encoding combined with / frame adaptive encoding can be used.

特に、入力画像フォーマットが飛び越し走査である場合には、２つのフィールドを１つのフレームとして扱う「フレーム・ピクチャ」と、２つのフィールドを独立した２つのピクチャ（画面）として扱う「フィールド・ピクチャ」とを、ピクチャごとに切り替えて使用するピクチャＡＦＦ（Picture-AFF: Picture-Adaptive Frame-Field Coding）と呼ばれる機能がある。

In particular, when the input image format is interlaced scanning, “frame picture” that handles two fields as one frame and “field picture” that handles two fields as two independent pictures (screens) There is a function called Picture-AFF (Picture-Aaptive Frame-Field Coding) that is used by switching for each picture.

  FIG. 8A is a diagram schematically showing the screen of “frame picture”, in which the lines of two fields indicated by white lines and gray lines are alternately aligned to form a “frame picture”. Is shown. FIG. 8B is a diagram schematically showing a “field picture” screen in which two fields (first field and second field) are configured as different pictures.

  Further, when the “frame picture” is selected, two encoding units called macroblocks (16 pixels × 16 lines rectangular area) are vertically combined, and the inside is frame encoded and field encoded. There is a function called MB-AFF (Macroblock-Adaptive Frame-Field Coding) that is used by switching between and.

  FIG. 9A schematically shows a state in which the screen 200 is divided into macroblocks (rectangular areas of 16 pixels × 16 lines), and two macroblocks 201 and 202 adjacent in the vertical direction are combined. ing. The 32 lines in the two macroblocks combined vertically are subjected to interlaced scanning in which the first field lines and the second field lines are alternately arranged.

  FIG. 9B schematically shows frame encoding using the macro blocks 203 and 204 in which the first field lines indicated by white lines and the second field lines indicated by gray lines are alternately arranged. . FIG. 9C shows a field code divided into a macroblock 205 composed of 16 lines of the first field indicated by white lines and a macroblock 206 composed of the lines of the second field indicated by gray lines. This is schematically shown. These details are described in Non-Patent Document 1.

  In addition, as a unit for performing motion compensation, a macroblock created by the above-described method based on the field / frame structure is used as it is by using a method of using 16 pixels × 16 lines as shown in FIG. The method used by dividing into 8 pixels × 16 lines, and after dividing into 8 pixels × 8 lines, as shown in FIG. 10B, the 8 pixels × 8 lines are used as they are, or the inside is further 8 pixels × 4 lines. It can be divided into 4 pixels × 8 lines or 4 pixels × 4 lines. These details are described in pages 114 to 115 of Non-Patent Document 1.

  These functions greatly contribute to the improvement of coding efficiency, but the processing becomes complicated and a lot of hardware load is required. In this inter-screen predictive coding, each pixel value in the block and a region with a small error are cut out from the image to be referred to as a predicted image. A region with a small error is searched by block matching between screens, and a vector value indicating the position is encoded. For this search, it is necessary to acquire image data in various directions, and access to the frame memory connected to the outside of the encoding integrated circuit frequently occurs. As a result, problems such as an increase in processing time due to data acquisition from the outside of the integrated circuit having a low access speed and an increase in power consumption associated with external access are caused.

  Therefore, an internal buffer circuit is employed that eliminates the need to access an external memory during vector search by temporarily storing pixel data within the vector search range in the internal buffer of the encoding integrated circuit and then performing vector search. The method is commonly used.

  FIG. 11 shows a configuration example for reducing the number of accesses to the external memory. In FIG. 11, it is assumed that two frame memory controllers 402 and 406, a current image buffer 403, a reference image buffer 407, and a motion vector searcher 408 are built in an integrated circuit. The current image frame memory 401 and the reference image frame memory 405 are connected to the outside of the integrated circuit. This is because it is generally difficult to incorporate a large-scale circuit such as a frame memory in an integrated circuit.

  FIG. 12 shows a configuration in which the motion vector search circuit shown in FIG. 11 is replaced with an integrated circuit. In the figure, the same components as those in FIG. The motion vector search circuit shown in FIG. 12 includes a motion vector integrated circuit 500 and a current image frame memory 401 and a reference image frame memory 405 connected thereto. The motion vector integrated circuit 500 includes the two frame memory controllers 402 and 406 shown in FIG. 11, a current image buffer 403, a reference image buffer 407, and a motion vector searcher 408.

  Next, the circuit operation of FIG. 11 will be described. A digital signal of the encoding target screen is input from the input terminal 400 in FIG. 11 and is stored in the current image frame memory 401 for one screen. The frame memory controller 402 reads the macro block data to be encoded from the current image frame memory 401 and accumulates it in the current image buffer 403. In parallel with this, the digital signal of the reference screen displayed before or after the time is input from the input terminal 404 to the digital signal of the encoding target screen, and is stored in the reference image frame memory 405 for one screen. Is done. The frame memory controller 406 reads the reference area data from the reference image frame memory 405 and stores it in the reference image buffer 407.

  The motion vector search unit 408 searches the reference area image stored in the reference image buffer 407 for an area that matches the encoding target macroblock stored in the current image buffer 403, obtains a motion vector amount, and outputs the motion vector amount. A motion vector value is output from the terminal 409.

  When the above operation is performed for one encoding target macroblock and a vector value is output, the frame memory controllers 402 and 406 move the encoding target macroblock from the left to the right of the screen while performing each encoding. The same operation as described above is repeated for the macroblock, and when the output of the motion vector value for the rightmost encoding target macroblock is completed, the next leftmost macroblock is moved to be the encoding target ( The macroblock data is read from the frame memory so as to be in raster order. By repeating this operation, vector values for each encoding target macroblock are obtained for one screen in raster order.

  As described above, by providing the current image buffer memory 403 and the reference image buffer 407 between the external current image frame memory 401 and the reference image frame memory 405 and the motion vector search unit 408, the motion vector search unit 408 is externally connected. The amount of motion vector can be obtained without frequently accessing the current image frame memory 401 and the reference image frame memory 405.

  As an example of the above configuration, an apparatus for searching for a motion vector has been conventionally disclosed (see, for example, Patent Document 1). First, the normal operation of this apparatus will be described. A search area centered on a search from a macroblock 601 located in the same screen position as the macroblock stored in the current image buffer from the image data of the screen 600 shown in FIG. 13A stored in the reference screen frame memory. 602 is read from the reference screen frame memory and stored in the reference screen buffer.

  The motion vector searcher obtains an area where the sum of absolute values of differences for each pixel between the search area 602 and the macroblock stored in the current image buffer is minimized, and the horizontal direction from the macroblock 601 and The amount of movement in the vertical direction is calculated and output as a vector value.

  By the way, as shown in FIG. 13B, when the search center macroblock 603 reaches the right end of the screen, the partial area 605 of the search area 604 is outside the screen 600, so reading from the frame memory is not performed. . Conversely, as shown in FIG. 13C, when the search center macroblock 606 moves from the right end of the screen to the left end of the screen one macroblock below, the data in the partial area 608 of the search area 607 is stored in the frame memory at a time. Will be read from.

  In view of the above problems, the method according to Patent Document 1 aims to eliminate the nonuniformity of the read operation. That is, in the method described in Patent Document 1, as shown in FIG. 13D, when the search center macroblock 609 approaches the right end of the screen 600 and the right partial region 611 of the search region 610 protrudes from the screen 600. In this case, the data of the left end area 612 is read as the data of the partial area 611, and it is not necessary to read from the frame memory at a time when the search center moves to the left end, and access to the frame memory is concentrated in time. It is characterized by equalization without any problems. With this operation, not only the number of accesses to the frame memory is reduced, but also the time concentration of access is avoided.

Supervised by Satoshi Okubo, "H.264 / AVC textbook", Impress, Inc., 2004 (ISBN 4-8443-1983-3), pages 93-94 and pages 158-161 Japanese Patent Laid-Open No. 10-224797

  By the way, in the vector value search by block matching, the pixel data reading operation frequently occurs in order to move the block position while shifting the pixel. As a result, the waiting time when reading the pixel data of the reference image from the frame memory with a slow access time has a great influence on the number of search processing cycles, and frequent access to the outside of the coding integrated circuit consumes power. It is a problem to cause an increase in

  In general, the buffer circuit is incorporated in the encoding integrated circuit to cope with the above problem. However, as described above, in H.264 / MPEG-4AVC, signal processing is conventionally performed to improve encoding efficiency. It is several times more complicated, and there is a need for higher speed hardware and lower power consumption.

  In the conventional buffer circuit method described above, when the pixel data within the search range is accumulated, every time the position of the search center macroblock moves, only the pixel data outside the search range is discarded, and the old search region is discarded. The pixel data of the area overlapping with the new search area is stored, and only the pixel data of the partial area newly set as the search frame area is read from the frame memory.

  This will be described with reference to FIG. In FIG. 14A, the search range when the macro block 701 in the screen 700 is set as a new search center position is indicated by a thick frame 702. At this time, the gray area 703 in the pixel data stored in the buffer is discarded because it is not included in the new search range. On the other hand, the hatched area 704 newly added to the search range is read from the frame memory.

  Incidentally, the hatched area 705 shown in FIG. 14B in the hatched area 704 newly read from the frame memory in FIG. 14A is when the search center position is one position above the macroblock 701. In addition, it has been read once from the frame memory. In other words, when the search center position moves, it is necessary to read pixel data once discarded, and there is a problem that access to the frame memory is wasted. In particular, in the MB-AFF of H.264 / MPEG-4AVC described above, the vector search center macroblock position moves in a zigzag pattern rather than in raster order, resulting in further waste of access.

  Conventionally, the pixel data in the buffer is stored so as to coincide with the screen image. However, as shown in FIG. 10 described above, in H.264 / MPEG-4AVC, a macroblock of 16 pixels × 16 lines has a field / frame structure, 4 pixels × 4 lines, 8 pixels × 4 lines, or 4 pixels. There is a possibility that vector search is performed by dividing up to x8 lines. For this reason, the pixel data reading position becomes complicated in the conventional pixel data storage order, and it is difficult to always obtain the same access time when the block unit is adaptively changed. For this reason, there is a problem that the processing time required for encoding is not uniform.

  The present invention has been made in view of the above points. The number of accesses from the coding integrated circuit to the external memory is reduced more than before, and the field / frame structure and block size can be adaptively switched during vector search. An object of the present invention is to provide a motion vector search device that can flexibly cope with the motion vector.

  In order to achieve the above object, according to a first aspect of the present invention, a first memory for storing an input image signal to be encoded for one screen and a block having a predetermined number of pixels are read from the first memory. A first buffer for temporarily storing an image signal to be encoded, a second memory for storing a reference image signal displayed before or after the image signal to be encoded for one screen, and A second buffer for temporarily storing a reference image signal in a predetermined search range including a block at a position corresponding to the block, read from the memory of 2, and an image signal to be encoded from the first buffer Searching means for searching for a motion vector indicating a relative positional relationship with a block position within the search range matching the block based on the block and the reference image signal of the predetermined search range from the second buffer. A vector search device provided between a second memory and a second buffer, wherein the number of horizontal blocks is the same as the number of horizontal blocks of an image signal for one screen, and is vertical A cache memory having a storage capacity for signals in the block range in which the number of blocks in the direction is larger than the number of blocks in the vertical direction of the search range, and a predetermined number of blocks in raster order from the second block in the central block of the search range The reference image signal of the block at the specified position is read and written in the cache memory, and the reference image signal in the range corresponding to the search range in the second memory is read from the cache memory and supplied to the second buffer. Write and read control means for repeating the range and the read range while cyclically shifting the range and the read range by one block each. And features.

  In the present invention, when searching for a motion vector indicating a relative positional relationship with a block position within a search range matching a block based on a block of an image signal to be encoded and a reference image signal of a predetermined search range. The storage capacity of the signal in the block range is the same as the number of horizontal blocks in the image signal for one screen in the horizontal direction and the number of vertical blocks is larger than the number of vertical blocks in the search range. The reference image signal in the search range is read from the provided cache memory and used for the motion vector search, and the reference image signal of the block at a position preceding the center block of the search range by a predetermined number of blocks in the raster order is read from the second memory. Since it is read and written to the cache memory, the reference image signal in the search range of the second memory is repeatedly read. It can be. The reason why the number of vertical blocks is made larger than the vector search range is that the vector search center position may move not only in raster order but also zigzag.

  Here, the cache memory can be provided in the integrated circuit together with the first and second buffers and the motion vector search means. In this case, although the circuit scale in the integrated circuit increases, an external second Only one block is required per motion vector search for one memory vector access, and there is an advantage that power consumption in the entire system can be suppressed. This is because the power required for accessing the external second memory from the integrated circuit is much larger than the power consumption inside the integrated circuit. Further, the processing completed within the integrated circuit is more advantageous in that it can operate at a higher speed than the access time from the integrated circuit to the external second memory.

  In order to achieve the above object, the second invention provides a reference image signal obtained by dividing the cache memory of the first invention into a predetermined number of pixels out of a predetermined number of pixels constituting a block. Each of the plurality of bank memories stores at least a selector that distributes and stores the reference image signals from the second memory in the plurality of bank memories, and the selector reads the reference image signals simultaneously from the plurality of bank memories. In this configuration, the sorting operation is performed so that the plurality of pixels are composed of pixels constituting an image signal having a desired field / frame structure. According to the present invention, it is possible to easily read out data having a complicated block configuration from the cache memory in parallel, and it is possible to effectively function the latter buffer memory.

  According to the present invention, by providing a cache memory between the reference image signal storage memory and the buffer, it is possible to avoid duplication of reading of the reference image signal storage memory in both the horizontal direction and the vertical direction. Since the number of accesses to the reference image signal storage memory provided outside the image encoding integrated circuit when performing motion vector search can be reduced compared to the prior art, signal processing speed and power consumption can be reduced. Can be achieved effectively.

  Further, according to the present invention, the cache memory is provided with a plurality of bank memories, and the reference image signal is distributed and stored in units of predetermined pixels in the cache memory, so that complicated block configuration data is stored from the plurality of bank memories. Since it can be easily read out in parallel, it is possible to flexibly cope with the case of adaptively switching between various different size coding block units, which is a major feature of H.264 / MPEG-4AVC, and the signal processing time can be reduced. Uniformity can be achieved.

  Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a motion vector search apparatus according to the present invention. In the figure, the same circuit blocks as those in FIG. As shown in FIG. 1, in the present embodiment, the reference image cache memory 100 is inserted between the reference image frame memory 405 and the reference image buffer 407 as compared with the conventional motion vector search apparatus shown in FIG. There is a feature in the point. The reference image frame memory 405 and the reference image cache memory 100 are controlled to be written / read by the memory controller 410 as described later.

  The cache memory 100 described above is provided not on the current image frame memory 401 side but on the reference image frame memory 405 side because the motion vector has a position that matches one macro block (MB) of the current image to be encoded. Since the number of accesses is greater in the reference image frame memory 405 than in the current image frame memory 401, and the position of the current MB is known in advance (fixed). On the other hand, since the reference image does not know in advance where to access in the search range, all data must be prepared.

  Next, the operation of the reference image cache memory 100 in FIG. 1 will be described with reference to FIGS. In the following description, the search center and search range indicate the center and range of motion vector search. 2 shows a screen image stored in the reference image frame memory 405 of FIG. 1, and FIG. 3 shows that the macroblock data read from the reference image frame memory 405 is arranged in the reference image cache memory 100. The figure which showed the image typically is shown. 2 and 3 represents a macroblock of 16 pixels × 16 lines.

  As can be seen from FIG. 3, the horizontal memory size of the reference image cache memory 100 of the present embodiment is characterized by the same size as the number of macroblocks in the horizontal direction of the reference image. The vertical memory size of the reference image cache memory 100 is characterized by a larger number of blocks than the vertical vector search range. However, in the present embodiment, the reference image cache memory 100 has a memory size 1 larger than the motion vector search range. The size is large for the macroblock. The reason why the vertical memory size is made larger than the vertical motion vector search range is that the motion vector search center position may move not only in raster order but also zigzag. For example, in order to realize the structure of FIG. 9B or 9C, after the current macroblock moves in the vertical (vertical) direction as shown in FIG. This is because the motion vector search range also moves zigzag when moving up and down in a zigzag manner.

  First, the position of the search center macroblock 110a in FIG. 2A in the reference image frame memory 405 is the search center, and the range 111a is set as the search range. Further, in the reference image cache memory 100, the search center macroblock 120a of FIG. 3A is arranged corresponding to the search center macroblock 110a of FIG. 2A, and the search range of FIG. A region corresponding to 111a is a search range 121a in FIG.

  At this time, the pixel data of each macro block in the search range 121a is read by the memory controller 410 and transferred to the reference image buffer 407 of FIG. 1 connected in the subsequent stage, and used for motion vector search. Also, pixel data read from the reference image frame memory 405 by the memory controller 410 and transferred to the reference image cache memory 100 immediately before or in parallel with the reading of the pixel data of the reference image cache memory 100 It is written in the position of the macro block 122a adjacent to the lower right of the search range 121a of FIG. This writing pixel data is a macro block adjacent to the lower right of the search range 111a in FIG. 2A (that is, a fixed length in raster order that includes the search range and does not overtake the search range (here In this case, the pixel data of the macro block 112a preceding by 12 macro blocks).

  When the motion vector search by the motion vector search unit 408 in FIG. 1 is completed, the search center macroblock in the reference image frame memory 405 is moved by one macroblock in the horizontal direction in the raster order, and the search in FIG. From 110a to 110b in FIG. Along with this, the reference image cache memory 100 also moves to the search center macroblock 120b in FIG. As a result, the search range is the search range 111b in FIG. 2B and the search range 121b in FIG. 3B.

  As a result, the pixel data of each macro block in the search range 121b of the reference image cache memory 100 is read out and transferred to the reference image buffer 407 of FIG. 1 for use in motion vector search. At this time, the pixel data of the macro block 112b shown in FIG. 2B of the reference image frame memory 405 is read and written in the position of the macro block 122b of FIG. 3B of the reference image cache memory 100. This writing pixel data is the pixel data of the macro block 112b that precedes the search center macro block 110b of FIG. 2B by a fixed length (12 macro blocks) in the raster order. In addition, the position of the pixel data writing macro block in FIG. 3B in the reference image cache memory 100 is also the macro block preceding the search center macro block 120b by a fixed length (12 macro blocks) in the raster order. Position.

  Further, as shown in FIG. 2C, when the search center is moved to the search center macroblock 110c, the search range is 111c, and the pixel data read from the reference image frame memory 405 is the same as the search center macroblock 110c. The macroblock 112c preceded by a fixed length (12 macroblocks) in the raster order becomes corresponding to this, and in the reference image cache memory 100, the search center macroblock 120c in FIG. 3C and the search range in FIG. The c) 121c of c) is a macroblock 122c that precedes the search center macroblock 112c by a fixed length (12 macroblocks) in raster order. This operation explains the case where the search center macroblock approaches the right edge of the screen.

  Next, FIG. 2D shows a state where the search center macroblock reaches the right end and turns back to the left end one macroblock below. Correspondingly, in the reference image cache memory 100, the search center macroblock is 120d shown in FIG. 3D, and the write macroblock is 122d shown in FIG.

  Here, the search range in the reference image cache memory 100 is the search range 121d shown in FIG. 3D when the search center macroblock 120d is the center position of the search range, but the lower side of the range is the reference image cache memory. The pixel data protrudes from the storage area 100 and there is no pixel data, but this part of the pixel data exists at a position included in the area indicated by the search range 123d shown in FIG. Therefore, the pixel data corresponding to the search range 111d in FIG. 2D can be obtained in the reference image buffer 407 in FIG.

  Further, as shown in FIG. 2E, when the search center macroblock of the reference image frame memory 405 moves to 110e, the search range becomes 111e, and the read macroblock is relative to the search center macroblock 110e. The macro block 112e is preceded by a fixed length (12 macro blocks) in the raster order. In this case, in the reference image cache memory 100, as shown in FIG. 3E, the search center macroblock becomes 120e, and the write macroblock has a fixed length (12 macros) in the raster order with respect to the search center macroblock 120e. 122e preceding the block). However, since the read macroblock 112e in FIG. 2E is folded in the vertical direction, the write macroblock 122e is pixel data of a reference image frame that is temporally different from the read macroblock 112e.

  In FIG. 3E, a broken line 124e indicates a boundary position where the reference image frame is changed to a frame in the next processing order. Here, the search range is the search range 121e in FIG. 3E, and the lower side of the range protrudes from the storage area of the reference image cache memory 100, and there is no pixel data. The pixel data corresponding to the search range 111e in FIG. 2 (e) is read later by reading out this portion together because it exists in the region indicated by the search range 123e shown in FIG. The connected reference image buffer 407 of FIG. 1 can be obtained. This operation explains the case where the search center macroblock approaches the lower right corner of the screen.

  Further, as shown in FIG. 2 (f), when the search center macroblock of the reference image frame memory 405 moves to 110f, the search range becomes the search range 111f shown in FIG. 112f shown in FIG. In this case, as shown in FIG. 3F, the reference image cache memory 100 has a search center macroblock of 120f, a search range of 121f, and a write macroblock of 122f.

  At this time, the upper side of the search range 121f protrudes from the storage area of the reference image cache memory 100 and there is no pixel data, but this portion of the pixel data exists in the area indicated by the search range 123f obtained by folding the search range downward. Therefore, by reading out this portion together, the pixel data corresponding to the search range 111f in FIG. 2F can be obtained in the reference image buffer 407 in FIG. 1 connected in the subsequent stage. However, in FIG. 3F, the pixel data below the broken line 124f indicating the boundary position of the frame is not referred to because it is the pixel data of the frame at the next time. This operation explains the case where the search center macroblock is at the lower right corner of the screen.

  Finally, as shown in FIG. 2 (g), when the search center macroblock in the reference image frame memory 405 moves to 110g, the search range becomes the search range 111g shown in FIG. The search center macroblock 110g is 112g shown in FIG. 5G, which precedes the fixed length (12 macroblocks) in raster order. In this case, as shown in FIG. 3G, in the reference image cache memory 100, the search center macroblock is 120g, the search range is 121g, and the write macroblock is fixed in raster order with respect to the search center macroblock 120g. It becomes 122 g that precedes the long part (12 macroblocks). However, the pixel data above the broken line 124g in FIG. 3G indicating the frame boundary position is not referred to because it is the pixel data of the previous frame in the processing order. This operation explains a case where the search center macroblock moves to the upper left corner of the next frame in the processing order. Thus, the search range moves cyclically within the reference image cache memory 100.

  The above description of the operation shows only a part of the phase relationship between the reading of the reference image frame memory 405 and the writing and search range of the reference image cache memory 100 in FIG. Can also be easily imagined. In the present embodiment, the frame structure in which the search macroblock moves in the raster order has been described. However, the field structure that moves in a zigzag manner may be considered in the same manner.

  As described above, the present embodiment is characterized in that the horizontal size is the same as the horizontal block size of the reference image, and the vertical size is set larger than the number of vertical blocks in the search range. A reference image cache memory 100 is provided, and by simply writing pixel data from the reference image frame memory 405 to the reference image cache memory 100 one macroblock at regular time intervals in accordance with the motion vector search operation, Search operation is possible.

  In addition, according to the present embodiment, duplication of data reading from the reference image cache memory 100 in both the horizontal direction and the vertical direction is avoided, so that the reference image frame memory 405 that is an external memory of the image coding integrated circuit. The number of accesses to the network can be reduced, and signal processing speed and power consumption can be effectively reduced.

  Furthermore, in this embodiment, the addition of the reference image cache memory 100 increases the circuit scale inside the integrated circuit, but instead, the reference image frame memory 405 as an external memory is accessed one time. Only one macroblock is required per vector search, and there is an advantage that power consumption in the entire system can be suppressed. This is because much more power is required to access an external circuit from the integrated circuit than the power consumption inside the integrated circuit. Further, the processing completed within the integrated circuit is more advantageous in that it can operate at a higher speed than the access time from the integrated circuit to the external circuit.

  Next, the reference image cache memory will be described in more detail. FIG. 4 shows a block diagram of an embodiment of a reference image cache memory that can be used in the motion vector search apparatus according to the present invention. The reference image cache memory having the configuration shown in FIG. 4 can be used as the reference image cache memory 100 of the motion vector search apparatus according to the present invention shown in FIG.

  The pixel data from the reference image frame memory 405 in FIG. 1 is input to the input terminal 150 in FIG. 4 in units of macroblocks and supplied to the selector 151. Four bank memories 152 to 155 are connected to the output side of the selector 151, and the bank memory for storing the pixel data is selected according to the position in the macroblock of the input pixel data.

  Here, the relationship between the position in the macroblock of the pixel data and the accumulated bank memory will be described with reference to FIGS. FIG. 5 shows one macroblock of 16 pixels in the horizontal direction and 16 lines in the vertical direction, and 4 pixels in the horizontal direction are represented by one rectangle. Therefore, FIG. 5 shows pixel data of one macroblock of 16 pixels × 16 lines by four rectangles in the horizontal direction and 16 rectangles in the vertical direction.

  In FIG. 5, a three-digit symbol consisting of one alphabet and two digits written in each rectangle is an identifier of the four bank memories 152 to 155 to be written. As shown in FIG. The banks A to D are distributed by the selector 151 shown in FIG. Here, the banks A, B, C, and D correspond to the bank memories 152, 153, 154, and 155 of FIG.

  The total capacity of these four bank memories 152 to 155 (banks A to D) is the same as the number of horizontal blocks in the reference image and the vertical direction as described in the above embodiment. It is assumed that the number of blocks is set larger than the number of vertical blocks in the search range. In addition, as shown in FIG. 6, it is assumed that data of 8 pixels (32 bits) is assigned to one address, and data for 8 pixels is read from one bank memory at a time.

  Also, the pixel data is read from the four bank memories 152 to 155 in blocks of 8 pixels × 4 lines or 4 pixels × 8 lines in the field / frame structure as described above. However, it is assumed that 4 pixels × 4 lines indicated by bold lines in FIG. 5 serve as the boundary of the reading position, and the starting point of the reading block position cannot be specified in any one pixel unit.

  Here, the reason why the block size is limited to two types of 8 pixels × 4 lines and 4 pixels × 8 lines is that the reference image buffer 407 at the subsequent stage of the reference image cache memory 100 is a small block such as 4 pixels × 4 lines. This is because it can be used by cutting out from the above two types of blocks, but rather has a larger demerit that complicates read control by increasing the type of read block size.

  As an example, FIG. 7A shows the position in the bank memory when reading 4 pixels × 8 lines of frame structure starting from A00 in FIG. 5, and FIG. 7B shows the field starting from A00 in FIG. The position in the bank memory in the case of reading the structure 4 pixels × 8 lines is shown. FIG. 7C shows the position in the bank memory when the frame structure of 8 pixels × 4 lines is read starting from A00 in FIG. 5, and FIG. 7D shows the field structure starting from A00 in FIG. The position in the bank memory when reading 8 pixels × 4 lines is shown.

  7A to 7D, the pixel data shown in FIG. 6 is allocated to and stored in the four bank memories 152 to 155 (banks A to D). On the other hand, the read address is simultaneously issued (but not the same address, and differs depending on the pixel data in FIGS. 7A to 7D), and only issued once in parallel (that is, one data read is performed). The read operation is completed.

  For example, when the frame structure 4 pixels × 8 lines shown in FIG. 7A is read out, the bank memory 152 is designated with one address storing A00 and A01 shown in FIG. 1 is designated with one address storing B00 and B01 shown in FIG. 6, and the bank memory 154 is designated with one address storing C20 and C21 shown in FIG. For the memory 155, the read operation is completed by designating one address storing D20 and D21 shown in FIG. The same applies to FIGS. 7B to 7D.

  Returning to FIG. 4 again, the pixel data read out simultaneously and in parallel from the bank memories 152 to 155 are input to the rearranger 156, for example, any of FIGS. 7A to 7D. In this way, the data order is rearranged to create a block of 8 pixels × 4 lines or 4 pixels × 8 lines having a field / frame structure. The block data created by the rearranger 156 is output from the output terminal 157 and supplied to the reference image buffer 407 in FIG.

  As described above, according to this embodiment, even when adaptively switching between variously sized encoding block units described with reference to FIG. 10, which is a major feature of H.264 / MPEG-4AVC, the minimum unit is used. The pixel data of 4 pixels x 8 lines and 8 pixels x 4 lines including the size of 4 pixels x 4 lines can be acquired by one reading, and the pixel data of 8 pixels x 8 lines is acquired by reading twice. In addition, even if they have a frame structure or a field structure, they can be acquired with the same access time, and the signal processing time can be made uniform, so that a very effective vector search can be performed.

  Note that the number of macroblocks in the screen used in the present embodiment is used for convenience in order to simplify the description, and the number of macroblocks in the screen targeted by the motion vector search apparatus according to the present invention is limited. It is not a thing. In H.264 / MPEG-4AVC, a plurality of screens can be selected as reference images. In that case, a reference image frame memory, a reference image cache memory and a reference image buffer circuit according to the present invention are provided. It can be easily imagined that a plurality of reference images may be prepared according to the number of reference images to be used.

It is a block diagram of one embodiment of a motion vector search device of the present invention. It is a figure which shows typically the screen image accumulate | stored in the reference image frame memory of FIG. FIG. 2 is a diagram schematically illustrating an image in which macroblock data read from a reference image frame memory in FIG. 1 is arranged in a reference image cache memory. It is a block diagram which shows the structure of position embodiment of the reference image cache memory in FIG. It is a figure which shows an example of the bank write destination of the data in a macroblock. It is a figure explaining the data arrangement in a bank memory. It is a figure explaining the data reading from a bank memory. It is a schematic diagram explaining the picture AFF. It is a schematic diagram explaining MB-AFF. It is a schematic diagram explaining a macroblock type. It is a block diagram which shows an example of the conventional motion vector search apparatus. It is a connection diagram at the time of expressing the conventional motion vector search apparatus with an integrated circuit. It is explanatory drawing of the pixel data accumulate | stored in a buffer memory in the conventional apparatus. It is a figure explaining the problem of the pixel data storage method of the conventional apparatus.

Explanation of symbols

100 Reference image cache memory 150, 400, 404 Input terminals 110a-110g, 120a-120g Search center macroblocks 111a-111g, 121a-121g, 123d, 123e, 123f Search area 112a-112g Frame memory read macroblock 122a-122g Cache Memory write macroblock 124e, 124f, 122g Frame boundary 151 Selector 152, 153, 154, 155 Bank memory 156 Rearranger 401 Current image frame memory 402 Frame memory controller 403 Current image buffer 405 Reference image frame memory 407 Reference image buffer 408 Motion vector searcher 410 Memory controller 157, 409 Output terminal 500 Motion vector Kuttle integrated circuit

Claims (2)

A first memory for storing the input image signal to be encoded for one screen, and a first memory for temporarily storing the image signal to be encoded read from the first memory for each block of a predetermined number of pixels. 1 buffer, a second memory for storing a reference image signal that is displayed before or after the image signal to be encoded for one screen, and read from the second memory, A second buffer for temporarily storing the reference image signal in a predetermined search range including a block at a position corresponding to the block; a block of the image signal to be encoded from the first buffer; Search means for searching for a motion vector indicating a relative positional relationship with a block position in the search range that matches the block based on a reference image signal in the predetermined search range from a buffer of A motion vector search apparatus having,
Provided between the second memory and the second buffer, the number of horizontal blocks is the same as the number of horizontal blocks of the image signal for one screen, and the number of vertical blocks A cache memory having a storage capacity of a signal in a block range larger than the number of blocks in the vertical direction of the search range;
A reference image signal of a block located at a predetermined number of blocks in raster order from the central block of the search range is read from the second memory and written to the cache memory, and from the cache memory to the second memory And a writing and reading control means for repeatedly reading the reference image signal in a range corresponding to the search range and supplying the reference image signal to the second buffer while cyclically shifting the search range and the read range by one block each. A motion vector search apparatus comprising: The cache memory is
A plurality of bank memories each storing the reference image signal divided into a predetermined number of pixels among the predetermined number of pixels constituting the block;
A selector that distributes and stores the reference image signal from the second memory in the plurality of bank memories, and the selector includes a plurality of reference image signals that are simultaneously read from the plurality of bank memories. 2. The motion vector search apparatus according to claim 1, wherein the sorting operation is performed so that the pixels are pixels constituting an image signal having a desired field / frame structure.

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