JP2007242663A - Semiconductor device including magnetoresistive effect element and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device in which variation can be suppressed in resistance of magnetoresistic effect elements. <P>SOLUTION: A magnetoresistive effect element is formed on a semiconductor substrate while sandwiching a nonmagnetic layer between a pinned layer composed of a ferromagnetic material having a fixed magnetization direction and a free layer having a magnetization direction which varies depending on the external magnetic field (a). An interlayer dielectric layer is formed to cover the magnetoresistive effect element, in such an insulating material as becoming an insulator which permeate less moisture as compared with the original material through nitriding (b). Surface layer of the interlayer dielectric layer is then nitrided (c). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a magnetoresistive effect element and a manufacturing method thereof, and more particularly to a semiconductor device suitable for a memory for storing information by resistance change of the magnetoresistive effect element and a manufacturing method thereof.

  Patent Document 1 listed below discloses a magnetic random access memory (MRAM) using a magnetoresistive effect element. MRAM uses a phenomenon in which information is written in a magnetic tunnel junction (MTJ) element exhibiting a tunnel magnetoresistance (MTJ) element using magnetism, and resistance changes depending on the magnetization direction of the MTJ element. Read information.

  FIG. 8A shows a schematic cross-sectional view of a general MTJ element. An MTJ element 110 is formed on the interlayer insulating film 100. An interlayer insulating film 115 covers the MTJ element 110. The MTJ element 110 has a stacked structure in which a tunnel insulating film 104 is sandwiched between a pinned layer 103 whose magnetization direction is fixed and a free layer 105 whose magnetization direction freely changes. Electrodes 120 and 121 are formed on both sides of the laminated structure, respectively. As the magnetization direction in the free layer 105 changes, the electrical resistance of the MTJ element 110 changes. Information is read by detecting this change in electrical resistance.

  Note that a film made of a nonmagnetic conductive material may be used instead of the tunnel insulating film. Such an element is generally called a magnetoresistive element.

JP 2005-340468 A

  The MTJ element 110 includes a material that is easily oxidized, such as NiFe or CoFe. When these materials are oxidized, the element resistance changes. For example, the MTJ element 110 is oxidized in the process of forming the interlayer insulating film by decomposing the source gas with plasma.

  FIG. 8B shows the measurement results of electrical resistance of 80 MTJ elements formed on the same substrate. The MTJ element to be evaluated has a tunnel junction surface size of 0.2 μm × 0.4 μm. In the measurement, the magnetization direction of the free layer 105 and the magnetization direction of the pinned layer 103 were parallel.

It can be seen that the element resistance is varied in a range of ^{1kΩ · μm 2 ~3kΩ · μm 2} . If the element resistance varies, the determination threshold value between the “0” state and the “1” state varies for each MTJ element, and information cannot be read stably.

  The objective of this invention is providing the semiconductor device which can suppress the dispersion | variation in resistance of a magnetoresistive effect element, and its manufacturing method.

According to one aspect of the invention,
(A) forming a magnetoresistive element in which a nonmagnetic layer is sandwiched between a pinned layer made of a ferromagnetic material whose magnetization direction is fixed and a free layer whose magnetization direction is changed by an external magnetic field;
(B) forming an interlayer insulating film so as to cover the magnetoresistive element;
(C) providing a method of manufacturing a semiconductor device including a step of nitriding a surface layer portion of the interlayer insulating film.

According to another aspect of the invention,
A plurality of digit lines extending in a first direction;
A plurality of bit lines extending in a second direction intersecting the first direction;
Magnetoresistance formed by pinching a pinned layer made of a ferromagnetic material whose magnetization direction is fixed and a free layer whose magnetization direction is changed by an external magnetic field and sandwiching a nonmagnetic layer at the intersection of the digit line and the bit line An effect element;
There is provided a semiconductor device having an interlayer insulating film formed so as to cover the magnetoresistive element and having a surface layer portion nitrided, and wherein the bit line is formed on the interlayer insulating film.

  By nitriding the interlayer insulating film, a nitride layer that is difficult to transmit moisture is formed. As a result, the ferromagnetic material of the magnetoresistive effect element can be prevented from being oxidized, and the resistance variation can be reduced.

  A method of manufacturing a semiconductor device according to the embodiment will be described with reference to FIGS. 1A to 1F show one memory cell. Many memory cells are arranged in a matrix on the substrate.

  As shown in FIG. 1A, an element isolation insulating film 2 is formed on a surface layer portion of a semiconductor substrate 1 made of silicon or the like to define an active region. A MOS transistor 3 is formed in this active region. The gate electrode of the MOS transistor 3 also serves as the word line 4 and extends in a direction perpendicular to the paper surface. An interlayer insulating film 5 is formed on the semiconductor substrate 1 so as to cover the MOS transistor 3.

  Via holes are formed in the interlayer insulating film 5, and conductive plugs 6 and 7 are filled in the via holes. Conductive plugs 6 and 7 are connected to the source and drain regions of MOS transistor 3, respectively. An interlayer insulating film 8 is formed on the interlayer insulating film 5. A wiring groove is formed in the interlayer insulating film 8, and the isolated wiring 9 and the ground line 10 are filled in the wiring groove. The isolated wiring 9 is connected to the conductive plug 6, and the ground line 10 is connected to the other conductive plug 7. The ground line 10 extends in a direction perpendicular to the paper surface.

  An interlayer insulating film 13 is further formed on the interlayer insulating film 8. A via hole is formed in the interlayer insulating film 13 and a conductive plug 14 connected to the isolated wiring 9 is filled in the via hole. An interlayer insulating film 15 is further formed on the interlayer insulating film 13. A wiring trench is formed in the interlayer insulating film 15, and the isolated wiring 17 and the digit line 16 are filled in the wiring trench. The isolated wiring 17 is connected to the conductive plug 14 therebelow. The digit line 16 extends in a direction parallel to the word line 4. An interlayer insulating film 20 is further formed on the interlayer insulating film 15. A via hole is formed in the interlayer insulating film 20 and a conductive plug 21 connected to the isolated wiring 17 is filled in the via hole.

  These interlayer insulating films 5, 8, 13, 15, and 20 are formed of, for example, silicon oxide, an organic insulating material, or the like. The lowermost conductive plugs 6 and 7 are made of tungsten (W) or the like. The upper conductive plugs 14 and 21, the isolated wirings 9 and 17, the ground line 10, and the digit line 16 are formed of copper (Cu) or the like. Note that the number of wiring layers may be increased as necessary. Alternatively, the conductive plug and the wiring may be formed at the same time using a dual damascene method.

  As shown in FIG. 1B, a wiring 25 connected to the conductive plug 21 and reaching above the corresponding digit line 16 is formed on the interlayer insulating film 20. The wiring 25 has a layer structure in which, for example, a Ti film, a TiN film, an Al film, and a TiN film are stacked in this order.

  An MTJ element 30 is formed on the wiring 25. The MTJ element 30 is disposed on a region where the wiring 25 and the digit line 16 intersect.

  FIG. 2 shows a layer structure of the MTJ element 30. On the lower electrode 61 made of Ta, a NiFe layer 62, an antiferromagnetic layer 63, a pinned layer 64, a tunnel barrier layer 65, a free layer 66, and an upper electrode 67 are laminated in this order. The thickness of the NiFe layer 62 is 2 nm, for example. The antiferromagnetic layer 63 is made of an antiferromagnetic material such as PtMn or IrMn, and has a thickness of 20 nm.

The pinned layer 64 includes three layers in which a CoFe layer 64A having a thickness of 3 nm, a Ru layer 64B having a thickness of 0.9 nm, and a CoFe layer 64C having a thickness of 3 nm are stacked in this order from the bottom. The tunnel barrier layer 65 is made of aluminum oxide (AlO _x ) and has a thickness of 1 nm. The free layer 66 includes three layers in which a NiFe layer 66A having a thickness of 6 nm, a Ru layer 66B having a thickness of 0.9 nm, and a NiFe layer 66C having a thickness of 4 nm are stacked in this order from the bottom. The upper electrode 67 is made of Ta.

  Each of these layers is formed by sputtering, for example, and patterned by ion milling or the like.

  As shown in FIG. 1C, an interlayer insulating film 35 made of silicon oxide is formed on the interlayer insulating film 20 by plasma CVD. The interlayer insulating film 35 covers the wiring 25 and the MTJ element 30. The thickness of the interlayer insulating film 35 is in the range of 100 to 300 nm.

As shown in FIG. 1D, a protective film 36 made of silicon nitride is formed by nitriding the surface layer portion of the interlayer insulating film 35. This nitriding treatment can be performed, for example, by exposing the surface of the interlayer insulating film 35 to plasma of a mixed gas of NH ₃ and H _{2 under} the following conditions.

NH ₃ flow rate: 40 sccm
H ₂ flow rate: 10 sccm
Pressure: 1.0Pa
RF power: 200W
Processing time: 10 seconds Substrate temperature: Room temperature to 400 ° C
3A and 3B show the results of measuring the constituent element distribution in the depth direction of the interlayer insulating film 35 before and after the nitriding treatment by Auger electron spectroscopy, respectively. The horizontal axis represents the sputtering time in units of “minutes” and corresponds to the depth from the surface. The vertical axis shows the detection intensity of each element. It can be seen that by performing the nitriding treatment, nitrogen is introduced into the surface layer portion and silicon nitride is formed. Note that oxygen is detected on the outermost surface after the nitriding treatment, which is because the surface was naturally oxidized by exposing the measurement object to the atmosphere before the measurement.

  As shown in FIG. 1E, a via hole 37 is formed in the interlayer insulating film 35 and the protective film 36 to expose a part of the surface of the upper electrode 67 of the MTJ element 30.

  As shown in FIG. 1F, the bit line 40 is formed on the protective film 36. The bit line 40 extends in the horizontal direction of FIG. 1F and is connected to the upper electrode 67 of the MTJ element 30 through the via hole 37. The bit line 40 has the same stacked structure as the wiring 25 connected to the lower electrode 61 of the MTJ element 30. An interlayer insulating film 45 made of silicon oxide is formed on the protective film 36 so as to cover the bit line 40. Next, the surface of the interlayer insulating film 45 is planarized by chemical mechanical polishing (CMP). A wiring 50 is formed on the interlayer insulating film 45. Further, an interlayer insulating film 51 is formed on the interlayer insulating film 45 so as to cover the wiring 50.

  Next, with reference to FIGS. 4A to 4D, a method for fabricating a semiconductor device according to the second embodiment will be described.

  The process until the bit line 40 shown in FIG. 4A is formed is the same as the process until the bit line 40 shown in FIG. 1F of the first embodiment is formed. An interlayer insulating film 45 made of silicon oxide is formed on the protective film 36 so as to cover the bit line 40. As shown in FIG. 4B, the surface of the interlayer insulating film 45 is planarized by performing chemical mechanical polishing (CMP).

  As shown in FIG. 4C, the protective film 46 is formed by nitriding the surface layer portion of the interlayer insulating film 45. The nitriding treatment is the same as the method for forming the protective film 36 shown in FIG. 1D. As shown in FIG. 4D, the wiring 50 is formed on the protective film 46. Further, an interlayer insulating film 51 is formed on the protective film 46 so as to cover the wiring 50. In this way, multilayer wiring layers are formed sequentially.

FIG. 5A shows the measurement results of the resistance variation of 80 MTJ elements formed on the same substrate by the method according to the first embodiment. FIG. 5B shows measurement results of resistance variations of 80 MTJ elements formed on the same substrate by the method according to the second embodiment. FIG. 5C shows variation in resistance of MTJ elements of the semiconductor device according to the third embodiment in which the interlayer insulating film 35 of the semiconductor device according to the first embodiment shown in FIG. 1F is formed of SiOF instead of silicon oxide. . In the first embodiment, the nitriding time is 10 seconds. In the third embodiment, the nitriding time is 15 seconds. The horizontal axis represents the element number, and the vertical axis represents the resistance of the MTJ element 30 in the unit “Ω · μm ² ”.

  Comparing the conventional example shown in FIG. 8B, it can be seen that the variation in resistance is small in any of the first to third embodiments. This is presumably because the intrusion of moisture into the MTJ element 30 was prevented by the protective films 36 and 46 made of silicon nitride.

As a material of the interlayer insulating films 36 and 46, in addition to silicon oxide and SiOF, an insulating material that is less permeable to moisture than the original material by nitriding may be used. For example, it may be formed of an insulating material containing Si such as SiC or SiOC, or may be formed of an insulating material containing Al such as Al ₂ O ₃ . When the interlayer insulating films 35 and 45 are formed of SiOC, the nitriding time is set to 15 seconds, for example. Further, in the case of forming with SiC or Al ₂ O ₃ , the nitriding time is set to 20 seconds, for example.

  In general, silicon nitride and aluminum nitride have a higher dielectric constant than silicon oxide, silicon carbide, silicon oxyfluoride, and aluminum oxide. The protective films 36 and 46 formed by nitriding the surface layer portions of the interlayer insulating films 35 and 45 have a dielectric constant higher than that of the interlayer insulating films 35 and 45. For this reason, if the protective films 36 and 46 are too thick, the parasitic capacitance between the wirings increases, which causes a signal propagation delay. On the other hand, if the protective films 36 and 46 are too thin, the effect of preventing the entry of moisture will be reduced. Therefore, it is preferable that the thickness of each of the protective films 36 and 46 is in the range of 10 to 30 nm.

  FIG. 6 shows an equivalent circuit diagram of the semiconductor device according to the first to third embodiments. A plurality of word lines 4 extend in the first direction (vertical direction in FIG. 6). A digit line 16 extending in the first direction is arranged corresponding to the word line 4. The plurality of bit lines 40 extend in a second direction (lateral direction in FIG. 6) intersecting the first direction.

  An MTJ element 30 is disposed at the intersection of the bit line 40 and the digit line 16. A MOS transistor 3 is arranged at the intersection of the word line 4 and the bit line 40. One terminal of the MTJ element 30 is connected to the corresponding bit line 40, and the other terminal is connected to one terminal of the corresponding MOS transistor 3. The other terminal of the MOS transistor 3 is grounded. The gate electrode of the MOS transistor 3 is connected to the corresponding word line 4.

  FIG. 7 is a plan view of the semiconductor device according to the first to third embodiments. A plurality of word lines 4 and digit lines 16 extend in a first direction (vertical direction in FIG. 7). Both are almost overlapping in plan view. One ground line 10 is arranged between two word lines 4. A plurality of bit lines 40 extend in the second direction (lateral direction in FIG. 7). An MTJ element 30 is disposed at the intersection of the bit line 40 and the digit line 16.

  An active region 50 is arranged at the intersection of the three lines composed of the two word lines 4 and the corresponding ground line 10 and the bit line 40. A MOS transistor 3 is arranged at the intersection of the word line 4 and the bit line 40. That is, two MOS transistors 3 are arranged in one active region 50, and an impurity diffusion region connected to the ground line 10 is shared. A wiring 25 connects the impurity diffusion region of the MOS transistor 3 opposite to the ground line 10 and the MTJ element 30. A protective film 36 covers the entire surface.

  When a write current is passed through one selected digit line 16 and one bit line 40, a composite magnetic field is generated at the intersection of the two. By this synthetic magnetic field, the magnetization direction of the free layer of the MTJ element 30 changes, and writing is performed. Information is read by conducting the MOS transistor 3 and detecting the electrical resistance of the MTJ element 30.

  In the semiconductor devices according to the first to third embodiments, the resistance variation of the plurality of MTJ elements 30 is small. For this reason, it is possible to read information stably with respect to the plurality of MTJ elements 30.

  In the first to third embodiments, the MTJ element is used as the magnetoresistive effect element. In addition, an element whose magnetic resistance is changed by an external magnetic field, for example, a tunnel insulating film of the MTJ element is made of a nonmagnetic conductive material. It is also possible to use a magnetoresistive effect element replaced with a film.

  The combination of the interlayer insulating film and the protective film according to the first to third embodiments is not limited to MRAM using a magnetoresistive effect element, but also ferroelectric memory (FRAM) using a ferroelectric material, The present invention can also be applied to a resistance RAM (RRAM) using resistance change.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  The invention shown in the following supplementary notes is derived from the above embodiments.

(Appendix 1)
(A) forming a magnetoresistive element in which a nonmagnetic layer is sandwiched between a pinned layer made of a ferromagnetic material whose magnetization direction is fixed and a free layer whose magnetization direction is changed by an external magnetic field;
(B) forming an interlayer insulating film so as to cover the magnetoresistive element;
(C) a method of manufacturing a semiconductor device, including a step of nitriding a surface layer portion of the interlayer insulating film.

(Appendix 2)
The method for manufacturing a semiconductor device according to appendix 1, wherein the interlayer insulating film contains Si or Al, and silicon nitride or aluminum nitride is formed in the step c.

(Appendix 3)
The manufacturing method of a semiconductor device according to appendix 1 or 2, wherein a thickness of the surface layer portion nitrided in the step c is in a range of 10 to 30 nm.

(Appendix 4)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the step c is performed by plasma CVD.

(Appendix 5)
A plurality of digit lines extending in a first direction;
A plurality of bit lines extending in a second direction intersecting the first direction;
Magnetoresistance formed by pinching a pinned layer made of a ferromagnetic material whose magnetization direction is fixed and a free layer whose magnetization direction is changed by an external magnetic field and sandwiching a nonmagnetic layer at the intersection of the digit line and the bit line An effect element;
A semiconductor device having an interlayer insulating film formed so as to cover the magnetoresistive effect element and having a surface layer portion nitrided, and wherein the bit line is formed on the interlayer insulating film.

(Appendix 6)
further,
A second interlayer insulating film formed on the bit line, the surface layer portion of which is nitrided;
The semiconductor device according to appendix 5, further comprising: a wiring layer formed on the second interlayer insulating film.

(Appendix 7)
The semiconductor device according to appendix 5 or 6, wherein the interlayer insulating film includes Si or Al, and a surface layer portion thereof is formed of silicon nitride or aluminum nitride.

(Appendix 8)
The semiconductor device according to any one of appendices 5 to 7, wherein the thickness of the nitrided surface layer portion of the interlayer insulating film is in the range of 10 to 30 nm.

FIGS. 1A and 1B are cross-sectional views (part 1) of a device in the middle of manufacturing for explaining a method of manufacturing a semiconductor device according to a first embodiment. FIGS. (1C) and (1D) are sectional views (part 2) of the device in the middle of manufacture for explaining the method of manufacturing the semiconductor device according to the first embodiment. (1E) is a cross-sectional view of the device in the middle of manufacture for explaining the method of manufacturing the semiconductor device according to the first embodiment (No. 3), and (1F) is a cross section of the semiconductor device according to the first embodiment. FIG. It is sectional drawing of an MTJ element. (3A) is a graph showing the impurity distribution in the thickness direction of the interlayer insulating film before nitriding treatment, and (3B) is a graph showing the impurity distribution in the thickness direction of the interlayer insulating film after nitriding treatment. FIGS. 4A and 4B are cross-sectional views (part 1) of a device in the middle of manufacture for explaining a method for manufacturing a semiconductor device according to the second embodiment. FIGS. (4C) is a cross-sectional view of a device in the middle of manufacturing for explaining the method of manufacturing the semiconductor device according to the second embodiment (No. 2), and (4D) is a cross section of the semiconductor device according to the second embodiment. FIG. (5A), (5B), and (5C) are graphs showing variations in electrical resistance of the MTJ elements of the semiconductor devices according to the first, second, and third embodiments, respectively. It is an equivalent circuit diagram of the semiconductor device by the 1st-3rd Example. It is a top view of the semiconductor device by the 1st-3rd Example. (8A) is a cross-sectional view of an MTJ element portion of a conventional semiconductor device, and (8B) is a graph showing variation in resistance of the MTJ element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation insulating film 3 MOS transistor 4 Word line 5, 8, 13, 20, 35, 45, 51 Interlayer insulating film 6, 7, 14, 21 Conductive plug 9, 15 Isolated wiring 10 Ground line 16 Digit line 25 50 Wiring 30 MTJ elements 36, 46 Protective film 37 Via hole 40 Bit line 50 Active region 61 Lower electrode 62 NiFe layer 63 Antiferromagnetic layer 64 Pinned layer 65 Tunnel barrier layer 66 Free layer 67 Upper electrode

Claims (5)

(A) forming a magnetoresistive element in which a nonmagnetic layer is sandwiched between a pinned layer made of a ferromagnetic material whose magnetization direction is fixed and a free layer whose magnetization direction is changed by an external magnetic field;
(B) forming an interlayer insulating film so as to cover the magnetoresistive element;
(C) a method of manufacturing a semiconductor device, including a step of nitriding a surface layer portion of the interlayer insulating film.   The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film includes Si or Al, and silicon nitride or aluminum nitride is formed in the step c.   The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the surface layer portion nitrided in the step c is in a range of 10 to 30 nm. A plurality of digit lines extending in a first direction;
A plurality of bit lines extending in a second direction intersecting the first direction;
Magnetoresistance formed by pinching a pinned layer made of a ferromagnetic material whose magnetization direction is fixed and a free layer whose magnetization direction is changed by an external magnetic field and sandwiching a nonmagnetic layer at the intersection of the digit line and the bit line An effect element;
A semiconductor device having an interlayer insulating film formed so as to cover the magnetoresistive effect element and having a surface layer portion nitrided, and wherein the bit line is formed on the interlayer insulating film.   The semiconductor device according to claim 4, wherein the interlayer insulating film includes Si or Al, and a surface layer portion thereof is formed of silicon nitride or aluminum nitride.

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