JP2007242147A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with built-in nonvolatile memory allowing data to be electrically erased therefrom and written therein, in which information of propriety is read from a sub-storage area where the information of erasing/writing propriety is stored, through simple circuit constitution without additionally preparing an exclusive sense amplifier. <P>SOLUTION: The semiconductor integrated circuit is equipped with: a memory cell array 7 having a main storage area dividable and erasable for each sector and the sub-storage area for storing the information of erasing/writing propriety regarding the plurality of sectors of the main storage area in accordance with an address; and control circuits 2 and 5 which supply a row address of the memory cell of the sub-storage area to a row decoder when an erasing/writing command is supplied and also supply a column address formed on the basis of a sector address of a specified memory cell to a column decoder to control the sense amplifier so that the information of erasing/writing propriety is read out from the corresponding memory cell of the sub-storage area. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a built-in nonvolatile memory capable of electrically erasing and writing data and capable of divisional erasing.

  Non-volatile memories that can electrically erase and write data are EEPROMs that can erase data in units of words, and flash that can erase data in batches or blocks Memory etc. exist. Non-volatile memory can retain stored information even when the power is shut off, so it is important to store programs that control the CPU and microcomputer, and to be used in systems equipped with semiconductor integrated circuits that incorporate non-volatile memory. Used to store data.

  In such a nonvolatile memory, in order to protect programs and important data, erasure and writing of data in a part of storage areas are prohibited. For this purpose, a sub-storage area for storing erasure / write enable / disable information is provided separately from the main storage area for storing general data. Reference is made to the erasure / write enable / disable information stored in the storage area. Based on this erasure / write enable / disable information, it is determined whether the address indicated by the erase or write command is in an area where data should be protected or an area where data can be rewritten, and the address protects the data. When it is in the area to be stored, erasing and writing of data are prohibited.

  As a related technique, Patent Document 1 is provided with a flag bit (lock bit) memory cell for controlling write / erase prohibition / permission for each erase block in order to prevent the loss of important data. In a flash memory, there is a semiconductor non-volatile memory device in which the control circuit is downsized, the characteristics and reliability of the memory cell for the lock bit are the same as those of the data memory cell, and the memory cell for the lock bit can be easily formed. It is disclosed.

  This semiconductor nonvolatile memory device is a semiconductor nonvolatile memory device having a memory array in which a plurality of data storage memory cells are arranged in a matrix, and writing and erasing data in the memory array in units of blocks. A write / erase inhibit memory cell (lock bit memory) that is formed corresponding to each erase block in the memory array and into which data indicating whether write / erase to the block unit is permitted or prohibited is written. Cell) and a control means for writing write / erase inhibit data to the write / erase inhibit memory cell corresponding to the block when a write / erase inhibit command is received for the addressed block. is doing.

However, in this semiconductor nonvolatile memory device, the write / erase prohibition memory cells are provided in a line along the column direction of the data storage memory cells arranged in a two-dimensional matrix. As a result, a plurality of write / erase inhibit memory cells connected to one lock bit line are connected to a write data latch or a dedicated sense amplifier, so that data in these write / erase inhibit memory cells is Can only be written or read one bit at a time, and it takes time to write or read data. In addition, a dedicated sense amplifier is required for the write / erase inhibit memory cell.
Japanese Patent Laid-Open No. 10-188577 (page 1-2, FIG. 1)

  Accordingly, in view of the above points, the present invention is capable of erasing and writing data in a semiconductor integrated circuit incorporating a nonvolatile memory that can be electrically erased and written, and that can be divided and erased. It is an object of the present invention to read availability information with a simple circuit configuration without adding a dedicated sense amplifier from a secondary storage area in which is stored.

  In order to solve the above-mentioned problem, a semiconductor integrated circuit according to one aspect of the present invention is a semiconductor integrated circuit including a nonvolatile memory capable of electrically erasing and writing data, wherein (i) A memory cell array including a plurality of memory cells arranged in a two-dimensional array, comprising a plurality of rows of memory cells, and comprising a main memory area that can be divided and erased for each sector, and at least one row of memory cells. A memory cell array having a sub-storage area for storing erasability / write-ability information regarding a plurality of sectors in the main storage area in correspondence with addresses; and (ii) configuring memory cells in each row of the main storage area Drives multiple word lines connected to the control gates of multiple transistors based on sector and row addresses A row decoder for selecting one row of memory cells, and (iii) a plurality of bit lines respectively connected to drains of a plurality of transistors constituting memory cells of each column of the memory cell array as column addresses. (Iv) a driver for driving the sources of a plurality of transistors included in the plurality of memory cells included in the memory cell array, and (v) ) A sense amplifier that reads data from at least one memory cell selected by the row decoder and the column decoder via at least one bit line; and (vi) a sector address and a row address based on an address supplied from the outside. Address latch circuit that latches column address and (vii) supplied from outside A command decoder that decodes a command; and (viii) a row decoder that obtains the row address of the memory cell in the secondary storage area in the second period when an erase command or a write command is supplied to the command decoder in the first period. And a column address generated based on the sector address of the memory cell designated as the object of erasure or writing is supplied to the column decoder, and the erasure or write permission information on the sector of the designated memory cell is The memory cell designated in the third period when at least the sense amplifier is controlled to read from the corresponding memory cell in the storage area, and the read / write erasure / readability information indicates permission of erasure or write Control at least the driver to erase or write to a sector of ; And a control circuit.

  Here, the control circuit activates a control signal in a predetermined period and reads / write / erase control information for controlling the driver and the sense amplifier in order to read the erasure / write enable / disable information regarding the designated sector. When the control signal is activated, the supply of the row address and column address of the memory cell designated as the target of erasure or writing to the row decoder and column decoder is stopped, and the row of the memory cell in the secondary storage area is stopped. In addition to supplying an address to the row decoder, a logic circuit unit that supplies a sector address of a memory cell designated as an erase or write target to the column decoder may be included.

  Further, the control circuit may reset the erase operation or the write operation when the erasure or write enable / disable information read from the memory cell in the secondary storage area indicates prohibition of the erase or write. Alternatively, the semiconductor integrated circuit further includes an interface for outputting the erasure / write permission information read from the memory cell in the sub storage area to the outside, and the control circuit performs an erasing operation or an operation according to a signal input from the outside. The write operation may be reset.

  According to the present invention, when the erase command or the write command is supplied, the row address of the memory cell in the secondary storage area is supplied to the row decoder, and the sector address of the memory cell designated as the target of erase or write is supplied. A dedicated sense amplifier is added by supplying the column address generated on the basis of the column decoder and reading out the erasure / write enable / disable information regarding the sector of the designated memory cell from the corresponding memory cell in the secondary storage area. And a simple circuit configuration can be realized.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a nonvolatile memory built in a semiconductor integrated circuit according to the first embodiment of the present invention. This semiconductor integrated circuit has a built-in nonvolatile memory that can electrically erase and write data and can be divided and erased.

  As shown in FIG. 1, the semiconductor integrated circuit includes an address latch circuit 1, a logic circuit unit 2, an X decoder 3, a command decoder 4, a write / read / erase control unit 5, a power supply circuit 6, The memory cell array 7, Y decoder 8, sense amplifier 9, I / O interface 10, SL (source line) driver 11, and latch circuit 12 are included. Here, the logic circuit unit 2 and the write / read / erase control unit 5 constitute a control circuit.

  In the memory cell array 7, a plurality of memory cells from which data is erased, written, and read are arranged in a two-dimensional array. These memory cells are connected to a plurality of word lines WL, a plurality of bit lines BL, and a plurality of source lines SL. In the present embodiment, a main memory area 7a is constituted by a plurality of rows of memory cells, and a sub memory area 7b is constituted by at least one row of memory cells.

In the main memory area 7a, a sector is composed of a predetermined number of adjacent memory cells, and divided erasure is possible for each sector. An address (sector address) designating a sector is represented by X _S (the Nth sector is X _SN ), and an address (row address) designating a row (word line) of a memory cell included in each sector is , X _W (the Nth row is X _WN ). Further, an address (column address) that designates a column (bit line) of the memory cell is represented by Y (the Nth row is Y _N ).

The secondary storage area 7b is used to store erasure / write enable / disable information (hereinafter also referred to as “control bits”) for a plurality of sectors in the main storage area 7a. The erasure / write enable / disable information for each sector may be information on whether or not erasure and write are prohibited, and information on whether or not erasure is prohibited and whether or not write is prohibited. May be included separately. Row address of the memory cells included in the secondary storage area 7b is represented by X _WS, column address, Y (N-th row Y _N) is represented by.

  FIG. 2 is a cross-sectional view showing a partial structure of the memory cell array shown in FIG. Each memory cell 20 included in the memory cell array is constituted by a transistor including a floating gate 104 and a control gate 107. As shown in FIG. 2, in a P-type substrate 100, an N-type impurity diffusion region 102 serving as a drain and an N-type impurity diffusion region 101 serving as a source are formed. On the P-type substrate 100, a floating gate 104 is formed through an insulating film 103, and a control gate 107 is formed through insulating films 105 and 106.

FIG. 3 is a diagram showing an example of voltages at various parts of the memory cell in writing, reading and erasing.
When writing data in the memory cell, the X decoder 3 applies a first voltage (for example, 2V) to the control gate 107 of the selected memory cell via the word line, and controls the control gate of the unselected memory cell. A low level voltage (for example, 0 V) is applied to 107 via the word line. Further, the Y decoder 8 applies a low level voltage (for example, 0 V) to the drain 102 of the memory cell in which the data “0” is written via the bit line, so that the data “0” is not written (at the time of erasing). A second voltage (for example, 4V) is applied to the drain 102 of the memory cell (maintaining data “1”) via the bit line. The SL driver 11 applies a high voltage (for example, 12V) to the source 101 of the selected memory cell via the source line.

  At this time, in the memory cell in which data “0” is written, the potential of the floating gate 104 becomes about 10 V due to capacitive coupling between the floating gate 104 and the source 101. As a result, some of the electrons flowing from the drain 102 to the source 101 are injected into the floating gate 104 as channel hot electrons. As a result, in the memory cell in which data “0” is written, the floating gate 104 is negatively charged, and the threshold voltage between the control gate and the source is increased.

  When reading the data stored in the memory cell, the X decoder 3 applies a third voltage (for example, 4V) to the control gate 107 of the selected memory cell via the word line, and the unselected memory A low level voltage (for example, 0 V) is applied to the control gate 107 of the cell via the word line. The SL driver 11 applies a low level voltage (for example, 0 V) to the source 101 of the selected memory cell via the source line. At this time, when a current source is connected to the memory cell from the sense amplifier side via the bit line, the bit line becomes 2 V or 0 V, for example, depending on the data write state.

  That is, in the memory cell in which data “0” is written, electrons accumulate in the floating gate 104 and the threshold voltage between the control gate and the source is high, so that the drain current does not flow and the bit line is 2V. Become. On the other hand, in the memory cell in which data “0” is not written, since no electrons are accumulated in the floating gate 104, the threshold voltage between the control gate and the source is low, the drain current flows, and the bit line becomes 0V. In the sense amplifier 9, data can be identified by comparing the voltage of the bit line with the reference voltage.

  When erasing the data stored in the memory cell, the X decoder 3 applies a high voltage (for example, 15V) to the control gate 107 of the memory cell from which the data is erased via the word line, and the Y decoder 8 applies a low level voltage (for example, 0V) to the drain 102 of the memory cell from which data is erased via the bit line, and the SL driver 11 applies the source line to the source 101 of the memory cell from which data is erased. A low-level voltage (for example, 0 V) is applied via. As a result, a high electric field is generated between the control gate 107 and the floating gate 104, and electrons accumulated in the floating gate 104 are extracted to the control gate 107 side by the tunnel effect, thereby erasing data. The erased state corresponds to data “1”.

Referring to FIG. 1 again, when the address ADD is inputted from the outside, the address latch circuit 1 latches the sector address X _S , the row address X _W , and the column address Y based on the address, and sets the addresses. Output to the logic circuit unit 2.

X decoder 3, driven based on the plurality of word lines WL each connected to the control gates of each of the plurality of transistors constituting the memory cells of the row of the main memory area 7a in the sector address X _S and the row address X _W Thus, one row of memory cells is selected. The Y decoder 8 drives at least 1 bit line BL based on the column address Y by driving a plurality of bit lines BL respectively connected to the drains of the plurality of transistors constituting the memory cells in each column of the memory cell array 7. A memory cell in a column (for example, 8 columns corresponding to 8-bit data) is selected.

In the read mode, the sense amplifier 9 receives at least one memory cell (for example, eight memory cells corresponding to 8-bit data) selected by the X decoder 3 and the Y decoder 8 via the corresponding bit line BL. Read data. I / O interface 10, in the write mode, supplying the data D _IN input from the outside to the bit line BL, in read mode, and outputs the data D _OUT read by the sense amplifier 9 to the outside.

  The SL driver 11 applies a predetermined voltage to at least the sources of the transistors constituting the memory cells in the selected row according to the erase, write, and read operations. The latch circuit 12 latches the control bit read by the sense amplifier 9 and outputs it to the write / read / erase control unit 5.

  The command decoder 4 decodes a chip select signal, a write command, a read command, an erase command, etc. supplied from the outside. FIG. 1 shows a state in which the command decoder 4 is supplied with a chip select signal CS # (negative logic) and a write command WE # (negative logic).

  The write / read / erase control unit 5 controls the power supply circuit 6 so as to generate a power supply voltage corresponding to the write / read / erase operation, and when an erase command or a write command is supplied to the command decoder 4. The check signal (flag) FCHK is activated in a predetermined check period in order to check whether or not erasure or writing can be performed with respect to the sector of the memory cell specified by the address ADD as an object of erasing or writing. Hereinafter, a period other than the check period is referred to as a “normal operation period”.

Logic circuit portion 2 includes an AND circuit 21 for inputting the row address _{X W} and check signal FCHK, a buffer circuit 22 supplies the word line of the memory cell of the secondary storage area 7b buffers the check signal FCHK, sector address X An AND circuit 23 for inputting _S and the check signal FCHK, an AND circuit 24 for inputting the column address Y and the check signal FCHK, and a logical sum of outputs of the AND circuits 23 and 24 are obtained, and the logical sum is obtained for the Y decoder 8. OR circuit 25 for outputting as column address YY. In each of the AND circuits 21 and 24, one input terminal is an inverting input.

The AND circuit 21 outputs the row address _XW to the X decoder 3 in the normal period, and stops the selection of the memory cell in the main memory area 7a in the X decoder 3 by setting the output to the low level in the check period. . The buffer circuit 22 activates the word line of the secondary storage area 7b during the check period.

AND circuit 23 in the normal period, and outputs a low level, in the check period, and outputs the sector address X _S. The AND circuit 24 outputs the column address Y in the normal period, and sets the output to the low level in the check period. As a result, OR circuit 25, in the normal period, and outputs the column address Y, in the check period, and outputs the sector address X _S.

Further, the write / read / erase control unit 5 controls the sense amplifier 9 so as to read the control bit from the memory cell of the secondary storage area 7b corresponding to the column address YY in the check period. Thus, the memory cell of the secondary storage region 7b having a row address YY corresponding to the sector address X _S designated from the outside, the control bits are read.

  The read control bit is latched by the latch circuit 12 and supplied to the write / read / erase control unit 5. The write / read / erase control unit 5 resets the erase operation or the write operation when the control bit read from the memory cell in the secondary storage area 7b indicates prohibition of erase or write.

Next, a command sequence of the nonvolatile memory shown in FIG. 1 will be described.
FIG. 4 is a timing chart showing signal states in the command sequence of the nonvolatile memory shown in FIG. In FIG. 4 and the description thereof, the word “program” means one of a write operation and an erase operation, that is, an operation of rewriting data.

In this nonvolatile memory, an address XAD (sector) designating a sector, an address XAD (row) designating a row in each sector, an address YAD designating a column, and a chip designating a chip of the nonvolatile memory A select signal CS # (negative logic), a write command WE # (negative logic) as an example of a program command, and data _DIN are input as external signals.

Here, the first three cycles of the command sequence are command acquisition periods for confirmation prior to the write operation. In the fourth cycle of the command sequence, an address and data for actually performing the write operation are input. The Based on these external signals, the address latch circuit 1 latches the sector address X _S , the row address X _W , and the column address Y, and the logic circuit unit 2 generates the row address X _WS and the column address YY. The write / read / erase controller 5 generates a status and check signal FCHK.

In the present embodiment, the fourth cycle of the command sequence is used as a check period, and it is determined whether or not data can be erased or written to a specified memory cell. As shown in FIG. 4, in the fourth cycle of the command sequence, as a row address X _W, instead of the row address X _W3 of the specified memory cells for erasure or write, the logic circuit section 2, the secondary storage area The row address X _WS of the memory cell 7b is generated. Furthermore, as the column address YY, instead of the column address Y ₃ of the memory cells designated for erasure or write, the logic circuit section 2, a sector address X _S3 of memory cells designated for erasure or write Generate.

In the fourth cycle, which is the check period, the write / read / erase control unit 5 issues a status so as to execute a read operation instead of a program operation, and activates a check signal (flag) FCHK. Further, the write / read / erase control unit 5 controls the sense amplifier 9 so as to read the control bit from the memory cell of the secondary storage area 7b having the column address YY. Thus, the memory cell of the secondary storage region 7b having a row address YY corresponding to the sector address X _S, the control bits are read.

  In the present embodiment, the read control bit is latched by the latch circuit 12 and supplied to the write / read / erase control unit 5. The write / read / erase control unit 5 determines whether or not data can be erased or written to the designated memory cell based on the control bit.

  If the read control bit indicates erasure or write permission, the write / read / erase control unit 5 issues a status so as to execute the program operation in the fifth cycle and thereafter. On the other hand, when the read control bit indicates prohibition of erasure or writing, the write / read / erase control unit 5 resets the program operation. As a result, it is possible to prevent the loss of programs and important data indispensable in the system.

In the above description, the sub storage area 7b is configured by one row of memory cells. However, the sub storage area 7b may be configured by a plurality of rows of memory cells. In this case, the row address X _WS and the column address YY are determined based on the sector address X _S3 included in the main storage area 7a. Here, based on the sector address _XS3 of the M rows and N columns of memory cells included in the main storage area 7a, control bits are stored in the K rows of memory cells in the sub storage area 7b (M , N, and K, and M> K). For example, when X _S3 ≦ N, X _WS = 1, when N <X _S3 ≦ 2N, X _WS = 2, and when 2N <X _S3 ≦ 3N, X _WS = 3,. . Further, when X _S3 ≦ N, YY = X _S3 , when N <X _S3 ≦ 2N, YY = X _S3 −N, when 2N <X _S3 ≦ 3N, YY = X _S3 −2N,.・ ・. Correspondingly, in the fourth cycle of the command sequence, the row address X _WS is generated based on the designated sector address X _S3 .

Next, a second embodiment of the present invention will be described.
FIG. 5 is a block diagram showing a configuration of a nonvolatile memory built in a semiconductor integrated circuit according to the second embodiment of the present invention. In the second embodiment, the control bit read from the secondary storage area 7b of the memory cell array 7 is output from the I / O interface 10 to the outside as data _DOUT . Based on the control bit, it is determined whether or not data can be erased or written to the designated memory cell.

  When the read control bit indicates erasure or write permission, no signal is input to the command decoder 4 from the outside, and the write / read / erase control unit 5 performs the data after the fifth cycle in FIG. A status is issued to execute erasing or writing. On the other hand, when the read control bit indicates prohibition of erasing or writing, an ABORT signal for stopping the erasing or writing operation is input to the command decoder 4 from the outside. The write / read / erase control unit 5 resets the erase or write operation according to the ABORT signal.

The block diagram which shows the structure of the non-volatile memory in the 1st Embodiment of this invention. FIG. 2 is a cross-sectional view showing a partial structure of the memory cell array shown in FIG. 1. The figure which shows the example of the voltage of each part of the memory cell in writing, reading, and erasing. 3 is a timing chart showing signal states in the nonvolatile memory shown in FIG. 1. The block diagram which shows the structure of the non-volatile memory in the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Address latch circuit, 2 Logic circuit part, 3 X decoder, 4 Command decoder, 5 Write / read / erase control part, 6 Power supply circuit, 7 Memory cell array, 7a Main memory area, 7b Submemory area, 8 Y decoder, 9 Sense amplifier, 10 I / O interface, 11 SL (source line) driver, 12 latch circuit, 20 memory cell 200 P-type substrate, 101 source, 102 drain, 103, 105, 106 insulating film, 104 floating gate, 107 control gate

Claims (4)

A semiconductor integrated circuit including a nonvolatile memory capable of electrically erasing and writing data,
A memory cell array including a plurality of memory cells arranged in a two-dimensional array, comprising a plurality of rows of memory cells, and comprising a main memory area that can be divided and erased for each sector, and at least one row of memory cells. The memory cell array having a secondary storage area for storing erasability or writeability information relating to a plurality of sectors of the main storage area corresponding to an address;
By driving a plurality of word lines respectively connected to control gates of a plurality of transistors constituting memory cells in each row of the main storage area based on sector addresses and row addresses, one row of memory cells is A row decoder to select;
A column decoder for selecting at least one column of memory cells by driving a plurality of bit lines respectively connected to drains of a plurality of transistors constituting memory cells in each column of the memory cell array based on a column address When,
A driver for driving sources of a plurality of transistors constituting a plurality of memory cells included in the memory cell array;
A sense amplifier for reading data from at least one memory cell selected by the row decoder and the column decoder via at least one bit line;
An address latch circuit that latches a sector address, a row address, and a column address based on an externally supplied address;
A command decoder for decoding commands supplied from the outside;
In the first period, when an erase command or a write command is supplied to the command decoder, in the second period, a row address of the memory cell in the secondary storage area is supplied to the row decoder and erase or write is performed. The column address generated based on the sector address of the memory cell designated as the target of the memory cell is supplied to the column decoder, and the erasure or write enable / disable information regarding the sector of the designated memory cell corresponds to the sub storage area. When at least the sense amplifier is controlled to read from the memory cell, and the read / write erasure information indicates permission of erasure or write, the sector of the designated memory cell is set in the third period. A control circuit for controlling at least the driver to perform erasing or writing with respect to the driver;
A semiconductor integrated circuit comprising: The control circuit comprises:
A read / erase control unit that activates a control signal in a predetermined period and reads the erasure / write enable / disable information related to the designated sector, and controls the driver and the sense amplifier;
When the control signal is activated, the supply of the row address and the column address of the memory cell designated as an erase or write target to the row decoder and the column decoder is stopped, and the memory in the sub storage area A logic circuit for supplying a row address of the cell to the row decoder and supplying a sector address of a memory cell designated for erasing or writing to the column decoder;
The semiconductor integrated circuit according to claim 1, comprising:   3. The control circuit according to claim 1, wherein the control circuit resets the erasing operation or the writing operation when the erasing or writing permission information read from the memory cell in the sub storage area indicates prohibition of erasing or writing. Semiconductor integrated circuit. An interface for outputting the erasure or writeability information read from the memory cell in the secondary storage area to the outside;
The semiconductor integrated circuit according to claim 1, wherein the control circuit resets an erase operation or a write operation according to a signal input from the outside.

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