JP2007242049A - Memory module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory module which matches access time of a large capacity nonvolatile memory and a RAM and includes the large capacity nonvolatile memory. <P>SOLUTION: When a load instruction code is written in a command register, a control circuit reads data from the nonvolatile memory and transfers the read data to the RAM. When a writing instruction is input in an external command signal terminal and an address for accessing the RAM is input in the external address signal, data input via an external data terminal is written in the RAM, when the writing instruction is input in the external command signal terminal and an address for accessing the command register is input in the external address signal terminal, the load instruction code input via the external data terminal is written in the command register. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory module including a plurality of different memories, a combination thereof, a control method thereof, and a mounting structure as a multichip module.

  A list of documents referred to in this specification is as follows. [Non-Patent Document 1]: LRS1337 Stacked Chip 32M Flash Memory and 4M SRAM Data Sheet ([Search April 21, 2000], Internet <URL: http://www.sharpsma.com/index.html>), [Patent Document 1]: Japanese Patent Application Laid-Open No. 5-299616 (corresponding European Patent Publication No. 566,306, October 20, 1993), [Patent Document 2]: Japanese Patent Application Laid-Open No. 7-68820, [Patent Document 3] ]: JP 2001-5723 A.

  [Non-Patent Document 1] describes a composite semiconductor memory in which a flash memory (32 Mbit capacity) and an SRAM (4 Mbit capacity) are integrally sealed in an FBGA type package with a stack chip. The flash memory and the SRAM share an address input terminal and a data input / output terminal with respect to the input / output electrodes of the FBGA type package. However, each control terminal is independent.

  FIG. 17 of [Patent Document 1] describes a composite semiconductor memory in which a flash memory chip and a DRAM chip are integrally sealed in a lead frame type package. FIG. 1 shows a flash memory and a DRAM in which address input terminals, data input / output terminals, and control terminals are input / output in common with respect to input / output electrodes of a package.

  FIG. 1 of [Patent Document 2] describes a system including a flash memory, a cache memory, a controller, and a CPU that are handled as a main storage device.

FIG. 2 of [Patent Document 3] describes a semiconductor memory including a flash memory, a DRAM, and a transfer control circuit.
LRS1337 Stacked Chip 32M Flash Memory and 4M SRAM Data Sheet ([Search April 21, 2000], Internet <URL: http://www.sharpsma.com/index.html>) Japanese Patent Laid-Open No. 5-299616 Japanese Unexamined Patent Publication No. 7-68820 JP 2001-5723 A

  Prior to the present application, the inventors of the present application examined a mobile phone and a memory module in which a flash memory and an SRAM used in the cellular phone were mounted in one package.

  Applications, data, and work areas handled by mobile phones become larger as functions (distribution of music, games, etc.) added to mobile phones increase, and it is expected that flash memory and SRAM with larger storage capacity will be required. Furthermore, recent mobile phones are remarkably advanced in functionality, and the need for large-capacity memories is increasing.

  Currently, flash memories used in mobile phones are NOR flash memories using a memory array system called a NOR system. The NOR method is an array method in which the parasitic resistance of the memory cell array is suppressed to a low level, and the resistance is reduced by providing one metal bit line contact for every two cells connected in parallel. For this reason, the read time is about 80 ns, which can be almost equal to the read time of the large capacity medium speed SRAM. However, on the other hand, since it is necessary to provide one contact for every two cells, the proportion of the contact portion in the chip area is high, and the area per 1 bit memory cell is large, so that the capacity increase is partitioned. There is no problem.

  In addition, typical large-capacity flash memories include an AND type flash memory whose memory array uses the AND method and a NAND type flash memory which uses the NAND method. Since these flash memories are provided with one bit line contact for 16 to 128 cells, a high-density memory array can be realized. Therefore, the area per memory cell per bit can be made smaller than that of NOR-type FLASH, and the capacity can be increased. However, on the other hand, it has been found that the read time until the first data is output is as slow as about 25 to 50 μs, and it is difficult to achieve consistency with the SRAM.

  The flash memory can retain data even when the power is turned off, but the SRAM is connected to a power source for retaining data even when the power of the mobile phone is off. In order to retain data over a long period of time, it is desirable that the data retention current of the SRAM be small. However, a large-capacity SRAM has a problem that the data retention current increases as the storage capacity increases, and another problem that the data retention current increases due to an increase in the gate leakage current. This is because if a microfabrication is introduced to realize a large-capacity SRAM and the oxide insulating film of the MOS transistor is thinned, a tunnel current flows from the gate to the substrate and the data holding current increases. Thus, it has been found that reducing the data retention current becomes increasingly difficult as the capacity of the SRAM increases.

  Accordingly, one of the objects of the present invention is to realize a ROM having a large storage capacity and capable of high-speed reading and writing, and a RAM having a large storage capacity and a small data holding current.

  An example of typical means of the present invention is as follows. That is, a non-volatile memory having a first read time, a random access memory RAM having a second read time that is 100 times or more shorter than the first read time, the non-volatile memory, and the non-volatile memory A semiconductor coupled to a random access memory and including a control circuit for controlling access to the random access memory and the non-volatile memory; and a plurality of input / output terminals coupled to the circuit Configure the storage device.

  At this time, the control circuit may perform control to transfer at least a part of the data of the flash memory to the DRAM in advance from the nonvolatile memory to the DRAM. For writing into the nonvolatile memory, it is preferable to write the data in the RAM into the nonvolatile memory between the access requests from the outside of the semiconductor device after writing into the RAM once. Further, the control circuit can perform control for concealing refresh when the RAM is DRAM from outside the semiconductor device.

  By copying FLASH data to DRAM, the reading and writing speed of FLASH data can be made equivalent to SDRAM and SRAM.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor).

<Example 1>
FIG. 1 shows a first embodiment of a memory module as an example of a semiconductor integrated circuit device to which the present invention is applied. This memory module is composed of three chips. Each chip will be described below.

  First, CHIP1 (FLASH) is a nonvolatile memory. As the nonvolatile memory, ROM (read only memory), EEPROM (electrically erasable and programmable ROM), flash memory, or the like can be used. A typical example of the non-volatile memory of CHIP1 used in this embodiment is a NAND flash memory in a broad sense as will be described later, and typically has a large storage capacity of about 256 Mb and has a read time (data is output from a read request). Time is relatively slow, about 25 to 50 μs. In contrast, an SDRAM typically used as CHIP3 has a large storage capacity of about 256 Mb and a read time of about 35 ns. That is, the reading time of CHIP3 is at least 100 times shorter than that of CHIP1. This is in contrast to the NOR-type flash memory, which has a read time of about 80 ns and the same order of read time as a DRAM. The present invention provides a solution for efficient access of memories with large differences in read times. There are various types of DRAM such as EDO, SDRAM, and DDR-SDRAM due to differences in internal configuration and interface. Any DRAM can be used for this memory module, but in this embodiment, an example of an SDRAM which is a typical example of a clock synchronous DRAM will be described. CHIP2 (CTL # LOGIC) has a control circuit for controlling CHIP1 and CHIP3.

  An address (A0 to A15), a clock signal (CLK), and a command signal (CKE, / CS, / RAS, / CAS, / WE, DQMU / DQML) are input to this memory module. Power is supplied through S-VCC, S-VSS, L-VCC, L-VSS, F-VCC, F-VSS, D1-VCC, D1-VSS, and DQ0 to DQ15 are used for data input / output. This memory module is operated by a so-called SDRAM interface.

  CHIP2 supplies signals necessary for the operation of CHIP1 and CHIP3. CHIP2 is serial clock (F-SC), address and data for FLASH (I / O0 to I / O7), command (F-CE, F- / OE, F- / WE, F- / RES, CHIP2) F-CDE, F-RDY / BUSY). Furthermore, CHIP2 has a clock (D1-CLK), address (D1-A0 to D1-A14), command (D1-CKE, D1- / CS, D1- / RAS, D1- / CAS, D1- / WE, D1-DQMU / DQML) and DRAM data (D1-DQ0 to D1-DQ15) are supplied.

  Here, each command signal will be briefly described. CLK input to CHIP2 is clock signal, CKE is clock enable signal, / CS is chip select signal, / RAS is row address strobe signal, / CAS is column address strobe signal, / WE is write enable signal, DQMU / DQML is Input / output mask signal. D1-CLK input to CHIP3 is a clock signal, D1-CKE is a clock enable signal, D1- / CS is a chip select signal, D1- / RAS is a row address strobe signal, D1- / CAS is a column address strobe signal, D1 -/ WE is a write enable signal, and D1-DQMU / DQML are input / output mask signals. F- / CE input to CHIP1 is chip enable signal, F- / OE is output enable signal, F- / WE is write enable signal, F-SC is serial clock signal, F- / RES is reset signal, F -CDE is a command data enable signal, F-RDY / BUSY is a ready / busy signal, and I / O0 to I / O7 are input / output signals used for address input and data input / output.

  The CHIP2 control circuit (CTL # LOGIC) selects the command register provided in the CHIP2 control circuit (CTL # LOGIC), the CHIP3 DRAM, or the CHIP1 FLASH according to the address value input from the outside. . By setting a value in the control register provided in the control circuit (CTL # LOGIC), it is possible to distinguish whether access from the outside is access to the command register, access to DRAM, or access to FLASH. Can do. Both accesses are performed by the SDRAM interface method.

  The DRAM is divided into a work area and a FLASH data copy area. The work is used as a work memory when executing a program, and the FLASH data copy area is used as a memory for copying data from the FLASH.

  By accessing the command register in the control circuit (CTL # LOGIC) and writing the load instruction or store instruction code, the FLASH data can be copied (loaded) to the DRAM FLASH data copy area, or the DRAM FLASH data copy area Can be written back to FLASH (store).

  Write address and I / O data signal (D1--) from address signal (A0 to A15) to access command register and command signal (CKE, / CS, / RAS, / CAS, / WE, DQMU / DQML) DQ0 to D1-DQ15), the load instruction code, and then the load start address and load end address in the address range to select FLASH are input, then the load instruction code, load start address, and load end address are input to the command register. Is written. Thereafter, data between the load start address and the load end address of the FLASH is read and transferred to the FLASH data copy area of the DRAM. As a result, the FLASH data is held in the DRAM.

  When the store start code and store end address are written to the command register at the address for selecting the store instruction code and FLASH, the data in the FLASH data copy area of the DRAM is transferred from the store start address of the FLASH to the address between the store end addresses. Written.

  Which address range of FLASH corresponds to which address range of the FLASH data copy area of DRAM can be determined by setting a value in the control register provided in the control circuit (CTL # LOGIC) .

  In FLASH, rewriting is repeated to reduce reliability, and data written at the time of writing rarely becomes different data at the time of reading or data is not written at the time of rewriting.

  When the control circuit (CTL # LOGIC) reads data from FLASH, CHIP2 (CTL # LOGIC) detects and corrects an error in the read data, and transfers it to the DRAM.

  When writing data to the FLASH, CHIP2 (CTL # LOGIC) checks whether it has been written correctly. If it has not been written correctly, it writes to an address different from the current address. A so-called substitution process is performed. Address management is also performed in which the substitute processing is performed for the defective address and the defective address.

  When accessing the FLASH data copy area of DRAM, from the address signal (A0 to A15), from the address to select FLASH and the command signal (CKE, / CS, / RAS, / CAS, / WE, DQMU / DQML) When a read command is input, the control circuit of CHIP2 accesses the DRAM and reads data from the address in the FLASH data copy area of the DRAM corresponding to the FLASH address. As a result, the reading time of the data in the FLASH area held in the DRAM becomes equivalent to that of the DRAM.

  When accessing the DRAM work area, an address signal and command signals necessary for accessing the DRAM work area are input. The control circuit (CTL # LOGIC) generates an address to the DRAM work area and accesses the DRAM. In the case of read access, read data from the DRAM passes through the DRAM data I / O (D1-DQ0 to D1-DQ15) and is output to the data input / output lines (I / O0 to I / O15). In the case of write access, write data is input from the memory module's data input / output lines (I / O0 to I / O15) and then input to the DRAM through DRAM data I / O (D1-DQ0 to D1-DQ15). .

  As described above, in the memory module according to the present invention, the SDRAM interface method is followed and a part of FLASH data or an area where all data can be copied is secured in the DRAM, and the data is transferred from the FLASH to the DRAM in advance. By doing so, FLASH data can be read at the same speed as DRAM. When writing data to the FLASH, the data can be written once to the DRAM and then written back to the FLASH as needed, so the data writing speed is equivalent to that of the DRAM. In the memory module, when reading from FALSH, error detection and correction are performed, and when writing, replacement processing is performed for defective addresses that were not written correctly, so processing can be performed at high speed. And reliability can be maintained. In addition, since a large-capacity DRAM is used, in addition to the area where FLASH data can be copied, a large-capacity work area can be secured, and it is possible to cope with the higher functionality of mobile phones.

  FIG. 2 is a block diagram of CHIP2 (CTL # LOGIC). CHIP2 (CTL # LOGIC) is a control circuit that operates from an external SDRAM interface and controls CHIP3 (DRAM1) and CHIP1 (FLASH). The operation of each circuit block will be described below.

  The initialization circuit INT initializes the control register in the memory management unit MMU and the DRAM when power supply to the DRAM is started. The memory management unit MMU converts the address inputted from the outside according to the value set in the built-in control register, selects the command register REG, the DRAM work area, the FLASH data copy area, and the FLASH, and performs access. The value of the control register is initialized by the initialization circuit INT when power is supplied, and then changed when a memory management MMU change instruction is input to the command register REG. The data update address management circuit CPB holds address information when data is written in the FLASH data copy area of the DRAM. In the command register REG, instruction codes such as a load instruction, a store instruction, and a memory management unit MMU change instruction, and addresses such as a load start address, a load end address, a store start address, and a store end address are written and held.

  The data buffer R / WBUFFER temporarily holds DRAM read data and write data or FALSH read data and write data. The clock buffer CLKBUF supplies a clock signal to the DRAM and the flash control circuit FCON. The command generator COM # GEN generates commands necessary for accessing DRAM. The access controller A # CONT generates an address for overall control of CHIP2 and access to the DRAM. The power module (PM) supplies power to the DRAM and controls the power. The flash control signal generation circuit FGEN controls reading and writing of FLASH data. The error correction circuit ECC checks whether there is an error in the data read from the FLASH, and corrects if there is an error. The substitution processing circuit REP checks whether or not the writing to the FLASH has been performed correctly. If the writing has not been performed correctly, the substitution processing circuit REP writes to a new replacement address prepared in advance in the FLASH.

  Next, the operation of this memory module will be described. The initialization circuit INT initializes a control register in the memory management unit MMU and initializes the DRAM when power supply to the DRAM is started. When the command register REG is selected and a load instruction is written to the command register REG, data transfer from the FLASH to the DRAM is started. First, the flash control signal generation circuit FGEN performs a read operation on the FLASH. If there is no error in the data read from the FLASH, the data is directly transferred to the data buffer R / W BUFFER. If there is an error, the data is corrected by the error correction circuit ECC and transferred to the data buffer R / W BUFFER. Next, the write command from the command generation circuit COM # GEN, the address signal from the access controller A # CONT, and the data read from the FLASH from the data buffer R / W BUFFER are input to the DRAM and transferred to the FLASH data copy area of the DRAM Writing is performed.

  The data update management circuit CPB retains write address information when data is written in the FLASH data copy area of the DRAM. When the command register REG is selected and a store instruction is written to the command register, data transfer from the data in the FLASH data copy area of the DRAM to the FLASH is started.

  First, a read command is sent from the command generation circuit COM # GEN and an address signal is sent from the access controller A # CONT to the DRAM to read the data. Data read from the DRAM is transferred to the flash controller FCON through the data buffer R / W BUFFER, and the flash control signal generation circuit FGEN writes to the FLASH. The address substitution processing circuit REP checks whether or not the writing is successful, and if successful, ends the processing. When writing fails, writing is performed to a new alternative address prepared in advance in the FLASH. When the replacement process is performed, the address information indicating the replacement address for the defective address and the defective address is held and managed. The data update management circuit CPB clears the address information for which writing to the FLASH has been completed from the stored DRAM address information. Thus, the data update management circuit CPB can always manage the address at which the latest data is updated.

  When the DRAM work area and the FLASH data copy area are selected and a read instruction is issued, a read instruction signal from the command generation circuit COM # GEN and an address signal from the access controller A # CONT are sent to the DRAM to read data.

  When the DRAM work area and FLASH data copy area are selected and a write instruction is issued, the write instruction signal from the command generation circuit COM # GEN, the address signal from the address generation circuit A # CONT, and the data from the data buffer R / W BUFFER to the DRAM Send and data is written.

  When a DRAM power-off command is input from the signal PS, the DRAM data corresponding to the address held by the data update management circuit CPB is transferred to the FLASH.

  First, a read command is sent from the command generation circuit COM # GEN and an address signal is sent from the access controller A # CONT to the DRAM to read data. Data read from the DRAM is transferred to the flash controller FCON through the data buffer R / W BUFFER, and written in FLASH by the flash control signal generation circuit FGEN.

  The data update management circuit CPB clears the address information that has been written to the FLASH out of the DRAM address information held, and when all the data corresponding to the held address is written to the FLASH, the data update management circuit CPB All address information is cleared. After all data is transferred from DRAM to FALSH, power off the DRAM. Power can be reduced by shutting off the power supply.

  In order to operate the DRAM again after stopping the DRAM power supply, a power-on command is input from the PS signal. The power supply instruction restarts the power supply to the DRAM, and the initialization circuit INT instructs the access controller (A # CONT) the initialization procedure, and the initialization is executed.

  3 and 4 show an example of a memory map converted by the memory management unit MMU. Any of these memory maps can be selected according to the value set in the control register inside the MMU. Although not particularly limited in the present embodiment, a typical memory map will be described by taking a memory module having a nonvolatile memory storage area of 256 + 8 Mb, a DRAM storage area of 256 Mb, and a command register of 8 kb as an example.

  In FIG. 3, based on the row address (A0 to A15) and column address (A0 to A9) input through the address signals A0 to A15, the memory management unit MMU uses the command register REG (8 kb), the DRAM Work area (128 Mbit), A memory map in which addresses are converted into the FLASH copy area (128 Mbit) and FLASH (256 Mbit + 8 Mb) of DRAM is shown. Although there is no particular limitation, command registers REG, DRAM, and FLASH are mapped from the bottom of the address space of the memory map.

  The command register REG existing in CHIP2 (CTL # LOGIC) is externally loaded with instruction codes such as load instructions, store instructions, MMU register change instructions, and power-off instructions, and start and end addresses for load instructions and store instructions. Is written.

  The DRAM is divided into a Work area (128 Mbit) and a FLASH copy area (128 Mbit). The Work area is used as a work memory at the time of program execution, and the FLASH copy area is used to copy and hold a part of the data in the FLASH area. In order to copy a part of the data in the FLASH area to the FLASH copy area, the memory management unit MMU corresponds to which address in the FLASH copy area corresponds to which address data in the FLASH depending on the value set in the internal register. Decide what you are doing. In FIG. 3, the A1 area (64 Mbit) and C1 area (64 Mbit) data in the FLASH area correspond to addresses that can be copied to the A1 area (64 Mbit) and 1 area (64 Mbit) in the FLASH copy area of DRAM, respectively. An example is shown. By changing the value of the internal control register of the memory management unit MMU, the data in the B1 area (64Mbit) and D1 area (56Mbit) in the FLASH area must be changed so that they can be copied to the DRAM FLASH copy area. You can also. The value of the MMU internal register can be changed by writing the MMU register change instruction code and the register value to the command register from the outside. FLASH (256M + 8Mbit) is not particularly limited, but main data area MD-Area (A1, A2, B1, B2, C1, C2, D1, D2: 255.75Mbit) and alternative area Rep-Area (E1, E2: 8.25) Mbit). The main data area MD-Area is further divided into a data area (A1, B1, C1, D1) and a redundant area (A2, B2, C2, D2). The data area stores programs and data, and the redundant area stores ECC parity data necessary for detecting and correcting errors. Data in the FLASH data area is transferred to the FLASH copy area of the DRAM, or data in the FLASH copy area of the DRAM is transferred to the FLASH data area. In FLASH, rewriting is repeated to reduce reliability, and data written at the time of writing rarely becomes different data at the time of reading or data is not written at the time of rewriting. The replacement area is provided in order to replace the data of the defective areas (Fail Area B and Fail Area C) with new areas. The size of the alternative area is not particularly limited, but it is preferable to determine it so as to ensure the reliability guaranteed by FLASH.

  Data transfer from FLASH to DRAM will be described. In order to transfer data in the AAL area of the FALSH to the FLASH copy area A1 area of the DRAM, the load instruction, the transfer start address SAD and the transfer end address EAD of the A1 area in the FALSH area are written in the command register. Then, the control circuit (CTL # LOGIC) reads the data in the address range indicated by the transfer start address FSAD and the transfer end address FEAD in the A1 area of the FLASH, and the DRAM FLASH copy area associated with the memory management unit MMU Transfer to the address range of addresses DSAD and DEAD in the A1 area. When reading data from the FLASH, the data in the FLASH data area A1 and the ECC parity data in the redundant area A2 are read and corrected by the error correction circuit ECC if there is an error ga. Only the corrected data is transferred to DRAM.

  Data transfer from DRAM to FLASH will be described. In order to transfer the data in the FLASH copy area A1 of the DRAM to the AAL area of the FALSH, the store instruction, the transfer start address SAD and the transfer end address EAD of the AAL area of the FALSH are written to the command register. Then, the control circuit (CTL # LOGIC) reads the data in the address range ADAD and DEAD in the DRAM FLASH copy area A1 associated with the memory management unit MMU, and the transfer start address in the FLASH A1 area. Write the address range data of FSAD and transfer end address FEAD. When writing data to FLASH, the error correction circuit ECC generates ECC parity data. The data read from the DRAM by the flash control circuit FGEN is written to the FLASH data area A1, and the generated ECC parity data is written to the redundant area A2. The address substitution processing circuit REP checks whether or not the writing is successful, and if successful, ends the processing. When the writing fails, the address in the alternative area of FLASH is selected, the data read from the DRAM is written into the alternative data E1 in the alternative area, and the generated ECC parity data is written into the alternative redundant area E2.

  Next, reading of data from the FLASH copy area A1 of the DRAM will be described. When an external address FAD0 in the FLASH A1 area and a read command are input from the outside, the MMU converts the address to the address DAD0 in the FLASH copy area A1 of the DRAM corresponding to the address FAD0. As a result, the DRAM data is selected and the FLASH data copied to the DRAM can be read. In other words, FLASH data can be read at the same speed as DRAM.

  Next, reading of data in the DRAM work area will be described. When the work area address WAD0 and the read command are input from the outside, the MMU outputs the address WAD0 to the address generation circuit A # COUNT. As a result, the data of the DRAM work area address WAD0 can be read.

  Next, writing of data into the FLASH copy area A1 of the DRAM will be described. When the FLASH A area address FAD0, the write command, and the write data are input from the outside, the MMU converts the address to the address DAD0 in the DRAM FLASH copy area corresponding to the address FAD0. As a result, DRAM is selected and data is written to the FLASH copy area A1. By writing to the FLASH copy area A1 of the DRAM corresponding to the FLASH data area A1, the FLASH data can be written at the same speed as the SRAM.

  Next, reading of data in the DRAM work area will be described. When the work area address WAD0 and a read command are input from the outside, the MMU outputs the address WAD0 to the access controller A # COUNT. As a result, the data of the DRAM work area address WAD0 can be read.

  Next, data writing in the DRAM work area will be described. When the work area address WAD0, a write command, and input data are input from the outside, the access controller A # COUNT outputs the address WAD0 to the DRAM. As a result, data in the DRAM work area address WAD0 can be written.

  FIG. 4 shows a memory map when the DRAM FLASh copy area is secured as a larger area of 192 Mbits compared to FIG. Based on the row address (A0 to A15) and column address (A0 to A9) input through address signals A0 to A15, the memory management unit MMU uses the REGISTER area, the DRAM work area (64 Mbit), and the DRAM flash copy area (192 Mbit). ), Convert the address to the FLASH area (256Mbit).

  The memory map can be freely selected by the user according to the system by changing the value of the control register inside the MMU. The value of the MMU internal control register can be changed by writing the MMU register change instruction code and the register value to be changed to the command register from the outside.

  FIG. 5 shows an initialization operation performed by the control circuit (CTL # LOGIC) when the power is turned on. When the power is turned on during T1, the control circuit (CTL # LOGIC) is initialized during the reset period of T2. The value of the control register in the memory management unit MMU is initialized in the period T2. In the period T3, the initialization circuit INT performs the DRAM initialization operation and the FLASH initialization operation simultaneously. When the initialization operation is completed, the memory module is in an idle state and can accept access from the outside.

  FIG. 6 shows a flowchart of data transfer from FLASH to DRAM. When the memory module is idle and waiting for an external command (STEP1), when the load command and the address for selecting FLASH are input (STEP2), the data corresponding to the input address and ECC parity data are read from FLASH (STEP3) . Check whether there is an error in the read data (STEP 4). If there is an error, correct the error (STEP 5) and write it to the buffer (STEP 6). If there is no error, write directly to buffer R / W_BUFFER (STEP 6). When data written to buffer R / W_BUFFER is written to DRAM, it is checked whether a refresh request is generated for DRAM (STEP 7). If there is a refresh request, refresh operation is performed (STEP 8), and then Write data to DRAM (STEP 9). If there is no refresh request, the data is immediately written to DRAM (STEP 9).

  FIG. 7 shows a flowchart of data transfer from DRAM to FLASH. When the memory module is idle and waiting for an instruction from the outside (STEP 1), when a store instruction and an address for selecting FLASH are input (STEP 2), reading of data from the DRAM is started. At this time, it is checked whether or not a refresh request is generated for the DRAM (STEP 3). If there is a refresh request, a refresh operation is performed (STEP 4), and then data is read from the DRAM (STEP 5). If there is no refresh request, data is immediately read from the DRAM (STEP 5). The read data is transferred to the buffer R / W_BUFFER (STEP 6) and written to the FLASH (STEP 7). When writing to the FLASH (STEP 7), the data read from the DRAM and the ECC parity data generated by the error correction circuit ECC are written to the FLASH. It is checked whether writing to the FLASH is successful (STEP 8), and if successful, the process is finished (STEP 10). If the writing fails, another address for substitution is selected (STEP 9), writing to the FLASH (STEP 7) is performed again, a writing success check (STEP 11) is performed, and if successful, the process is terminated (STEP 10).

  FIG. 8A shows an instruction flow from the outside when data is read from the DRAM in the memory module. FIG. 8B shows the instruction flow from the outside when writing data to the DRAM in the memory module. Instructions are input to the memory module from the outside via the SDRAM interface. FIG. 8A will be described. The memory module is idle and waiting for an external command (STEP1). When an ACTIVE command and row address are input from outside (STEP2), and then a READ command and column address are input (STEP3), the data held in the DRAM memory cell selected by the row and column addresses is read. And output to the outside of the memory module through the input / output data signals (DQ0 to DQ15). When the PRICHARGE instruction is input (STEP 4), the memory module enters an idle state.

  FIG. 8B will be described. The memory module is idle and waiting for an external command (STEP1). When an ACTIVE command and a row address are input from outside (STEP2), and then a WRITE command and a column address are input (STEP3), an input / output data signal (DQ0−) is sent to the DRAM memory cell selected by the row address and column address. Data input from DQ15) is written. When the PRICHARGE instruction is input (STEP 4), the memory module enters an idle state.

  FIG. 9 shows a flow of address holding and address clearing performed by the data update management circuit CPB. When data is written to the FLASH data copy area of the DRAM by an external write command (STEP 1), a flag signal corresponding to the write address is written to the flag register in the data update management circuit CPB (STEP 2). When a store instruction and an address are input from the outside, data transfer from the FLASH data copy area of the DRAM to the FLASH is started (STEP 3). Check that the transfer is completed (STEP 4). If completed, clear the flag of the transfer completion address in the flag register.

  FIG. 10 shows an operation flow of the memory module when a DRAM power-off command is input to the memory module. When a power-off instruction is input to the command register, all data written in the FLASH copy area in the DRAM but not written back to the FLASH is transferred to the FLASH. When a power-off command is input (STEP 1), first, in order to search for the address of data that has not been written back to FLASH among the data written in the FLASH copy area in DRAM, the search address is first set as the search start address. (STEP2). If the flag written in the flag register in the data update management circuit CPB for the search address is found (STEP 3), the DRAM data for the search address is transferred to the FLASH. When the transfer is completed, this flag is cleared (STEP 5). It is determined whether or not the current search address is the final search address (STEP 6). If it is not the final search address, an address obtained by adding 1 to the current search address is set as the next search address (STEP 7), and then STEP 3 and STEP 4 Repeat STEP5 and STEP6. If the current search address is the final search address, the processing is completed and the DRAM power is shut off (STEP 8).

  FIG. 11 shows the SDRAM operation performed by the module when data is transferred from the FLASH to the DRAM when a load instruction is input to the command register. The active instruction A and the row address R are input from the outside of the memory module through the SDRAM interface, and then the load instruction code Ld is input from the write instruction W, the column address C, and the input / output signals IO0 to IO15. Subsequently, the start address Sa and the end address Ea of data to be copied to the DRAM as data in the FLASH area are input from the input / output signals IO0 to IO15. The command register is selected by the row address R and the column address C, and the load instruction code Ld, the start address Sa, and the end address Ea are written into the command register. The control circuit reads data corresponding to the range of the start address Sa and the end address Ea from the FLASH and holds it in the buffer, and then starts writing to SDRAM1. The address for writing to DRAM1 is converted by the memory management unit MMU from the data start address Sa to the DRAM row address R0 and column address C0 in the FLASH copy area. Similarly, the end address Ea is converted to the row address R0 and column address CF. Is converted to

  To write to DRAM1, an active instruction A from D1-COM and a row address R0 from D1-A0 to D1-A15 are input, and then a write instruction W from D1-COM and a column address C0 from D1-A0 to D1-A15. Input and write data from I / O signals D1-IO0 to D1-IO15. The write operation continues to the column address and data until the final address CF of the column address, and the write is terminated by the precharge command P. From the start of writing data to the DRAM until the end, the WAIT signal is output to High to notify that data is being transferred to the DRAM.

  FIG. 12 shows the SDRAM operation performed by the memory module when data is transferred from SDRAM to FLASH when a store instruction is input to the command register. The active instruction A and the row address R are input from the outside of the memory module through the SDRAM interface, and then the store instruction code St is input from the write instruction W, the column address C, and the input / output signals IO0 to IO15. Subsequently, the start address Sa and the end address Ea of the data to be copied back from the DRAM to the FLASH with the data in the FLASH area are input from the input / output signals IO0 to IO15. The command register is selected by the row address R and the column address C, and the store instruction code St, the start address Sa, and the end address Ea are written into the command register.

  The control circuit reads data corresponding to the range of the start address Sa and the end address Ea from the SDRAM and writes it to the FLASH.

  The address for reading from SDRAM1 is converted by the memory management unit MMU from the data start address Sa to the SDRAM row address R0 and column address C0 in the FLASH copy area, and similarly the end address Ea to the row address R0 and column address CF. Converted.

  For reading from SDRAM1, an active instruction A from D1-COM and a row address R0 from D1-A0 to D1-A15 are input, and then a read instruction R from D1-COM and a column address C0 from D1-A0 to D1-A15. Input and read. The read operation continues until the final address CF of the column address, and the read is terminated by the precharge command P. During the period from the start of reading data to the end of SDRAM, the WAIT signal is output to High to inform that data is being transferred from the SDRAM.

  FIG. 13 (a) shows the SDRAM operation when accessing the SDRAM work area, and FIG. 13 (b) shows the SDRAM operation when accessing the FLASH copy area of the SDRAM.

  The read operation in FIG. 13 (a) will be described. The active command A and the row address R0 are input from the outside of the memory module through the SDRAM interface, and then the read command R and the column address C0 are input. When the control circuit inputs an active instruction A and a row address R0 to SDRAM1, and then inputs a read instruction R and a column address C0, data is output from the input / output signals D1-IO0 to D1-IO15, and the input / output signals IO0 to IO0 to Output to the outside through IO15.

  The write operation of FIG. 13 (a) will be described. The active instruction A and the row address R0 are input from the outside of the memory module through the SDRAM interface, and then the data In is input from the write instruction W, the column address C0, and the input / output signals IO0 to IO15. The control circuit inputs the active instruction A and the row address R0 to the SDRAM 1, and then the data In is input from the write instruction W, the column address C0, and the input / output signals D1-IO0 to D1-IO15, and the data is written to the SDRAM.

  The read operation in FIG. 13B will be described. An active instruction A and a row address RD, and then a read instruction R and a column address CD are input from the outside of the memory module through the SDRAM interface. The memory management unit MMU converts the row address RD of the FLASH area into the row address RT of the FLASH copy area, and similarly converts the column address CD of the FLASH area into the column address CT of the FLASH copy area. The active instruction A and row address RT are input to SDRAM1, then the read instruction R and column address CT are input, data is output from the input / output signals D1-IO0 to D1-IO15, and externally through the input / output signals IO0 to IO15. Is output.

  The write operation in FIG. 13B will be described. Data In is input from the outside of the memory module through the SDRAM interface through the active instruction A and the row address RF, then the write instruction W, the column address CF, and the input / output signals IO0 to IO15. The memory management unit MMU converts the row address RF of the FLASH area into the row address RU of the FLASH copy area, and similarly converts the column address CF of the FLASH area into the column address CU of the FLASH copy area. An active instruction A and a row address RU are input to the SDRAM 1 and then a write instruction W and a column address CT are input. Data is input from the input / output signals D1-IO0 to D1-IO15 and written to the SDRAM.

  FIG. 14 shows the operation of the SDRAM when a read command is input from the outside when data is being read from the DRAM due to a store command written to the command register from the outside. When the WAIT signal becomes High by the store instruction and the data Os to be transferred to FLASH is read from the DRAM, if the active instruction A and the row address R0 are input from the outside, the control circuit Ps is issued to DRAM1, and reading of data Os for transfer from DRAM to FLASH is temporarily interrupted. Thereafter, an active instruction A and a row address R0 are issued to DRAM1. Next, when a read command R and a column address C0 are input from the outside, a read command R and a column command C0 are issued to the DRAM 1, and data O is read and output from IO0 to IO15. When the precharge command P and the bank address B0 are input from the outside, the precharge command P and the bank address B0 are issued to the DRAM 1, and the data reading is completed. After that, the control circuit resumes reading of data Os for transfer from the DRAM to the FLASH, so that the active instruction AS and the row address R4, the read instruction Rs and the column command C4, and the read instruction RS and the column command C8 are transferred to the DRAM 1. Issue.

  FIG. 15 is a configuration example of CHIP1 (FLASH) in the present embodiment. Control signal buffer C-BUF, command controller CTL, multiplexer MUX, data input buffer DI-BUF, input data controller DC, sector address buffer SA-BUF, X decoder X-DEC, memory array MA (FLASH), Y address counter Y -CT, Y decoder Y-DEC, Y gate & sense amplifier circuit YGATE / SENSE-AMP, data register DATA-REG, data output buffer DO-BUF The operation of CHIP1 is the same as that of an AND-type FLASH memory that has been generally used. The AND-type FLASH memory is sometimes classified as a NAND-type flash memory in a broad sense in the sense of a large-capacity flash memory. In the present application, the NAND-type flash memory includes an AND-type FLASH memory. This CHIP1 (FLASH) can constitute the memory module of this embodiment.

  FIG. 16 shows a data read operation from an AND-type FLASH memory that can constitute CHIP1. When the chip enable signal F- / CE is LOW, the command data enable signal F-CDE is LOW, and the write enable signal F- / WE rises, the instruction code of the read instruction from the I / O signals I / O0 to I / O7 Enter the Rcode. The sector address is input from the input / output signals I / O0 to I / O7 at the rise of the second and third write enable signals F- / WE. The 16 kbit data corresponding to the input sector address is transferred from the memory array MA to the data register DATA-REG. While data is being transferred from the memory array MA to the data register DATA-REG, FLASH is busy and F-RDY / BUSY sets the ready / busy signal to Low. When the data transfer is completed, the data in the data register DATA-REG is read out in order of 8 bits in synchronization with the rising edge of the serial clock signal F-SC and output from the input / output signals I / O0 to I / O7.

  FIG. 17 shows an example in which CHIP1 (FLASH) of this memory module is configured by another NAND flash memory. F- / CE input to CHIP1 is chip enable signal, F-CLE is command latch enable signal, F-ALE is address latch enable signal, F- / WE is write enable signal, F- / RE is read enable signal, F- / WP is a write protect signal, FR / B is a ready / busy signal, and I / O0 to I / O7 are input / output signals used for address input and data input / output. As described above, the present memory module can also be configured by a NAND flash memory.

  FIG. 18 shows a block diagram of a NAND memory used in the present memory module. Operation logic controller L-CONT, control circuit CTL, I / O control circuit I / O-CONT, status register STREG, address register ADREG, command register COMREG, ready / busy circuit RB, high voltage generation circuit VL-GEN, low address buffer ROW-BUF, row address decoder ROW-DEC, column buffer COL-BUF, column decoder COL-DEC, data register DATA-REG, sense amplifier SENSE-AMP, and memory array MA. The operation of CHIP1 is the same as that of a NAND type FLASH memory that has been generally used. This CHIP1 (FLASH) can constitute the memory module of this embodiment.

  FIG. 19 shows a data read operation from the NAND-type FLASH memory configuring CHIP1. When the chip enable signal F- / CE is LOW, the command latch enable signal F-CLE is high, and the write enable signal F- / WE rises, the instruction code of the read instruction from the I / O signals I / O0 to I / O7 Enter the Rcode. Thereafter, the address latch enable F-ALE becomes High, and the page address is input from the input / output signals I / O0 to I / O7 at the rise of the second, third and fourth write enable signals F- / WE. The 4 kbit (4224 bit) data corresponding to the input page 4 kbit (4224 bit) address is transferred from the memory array MA to the data register DATA-REG. While data is being transferred from the memory array MA to the data register DATA-REG, FLASH is busy and F-R / B sets the ready / busy signal low. When the data transfer is completed, the data in the data register DATA-REG is read in order of 8 bits and output from the input / output signals I / O0 to I / O7 in synchronization with the fall of the read enable signal F- / RE. The

  FIG. 20 shows a configuration example of the DRAM in the present embodiment. X address buffer X-ADB, refresh counter REF. COUNTER, X decoder X-DEC, memory array MA, Y address buffer Y-ADB, Y address counter Y-AD COUNTER, Y decoder Y-DEC, sense amplifier circuit & Y gate ( Column switch) SENS AMP. & I / O BUS, input data buffer circuit INPUT BUFFER, output data buffer circuit OUTPUT BUFFER, control circuit & timing generation circuit CONTROL LOGIC & TG. DRAM is a general-purpose SDRAM that has been used conventionally. That is, it includes four independently operable memory banks, and the address input terminals and data input / output terminals for them are shared and used in a time-sharing manner for each bank. The memory module according to this embodiment can be configured by this DRAM.

  As described above, the memory module according to the present invention follows the SDRAM interface method, secures a part of FLASH data or an area where all data can be copied in DRAM, and transfers data from FLASH to DRAM in advance. By doing so, FLASH data can be read out at the same speed as DRAM. When writing data to the FLASH, the data can be written once to the DRAM and then written back to the FLASH as needed, so that the data writing speed can be equivalent to that of the DRAM.

  In the memory module, when reading from FALSH, error detection and correction are performed, and when writing, replacement processing is performed for defective addresses that were not written correctly, so processing can be performed at high speed. And reliability can be maintained.

  Since a large-capacity DRAM is used, a large-capacity work area can be secured in addition to an area where FLASH data can be copied.

  The size of the work area and flash data copy area reserved in DRAM and the management unit can be programmed from the outside, and can be freely selected by the user according to the system.

<Example 2>
FIG. 21 shows another embodiment of the memory module of the present invention. This memory module is composed of three chips. Each chip will be described below. First, CHIP1 (FLASH) is a nonvolatile memory. As the nonvolatile memory, ROM (read only memory), EEPROM (electrically erasable and programmable ROM), flash memory, or the like can be used. In this embodiment, a flash memory will be described as an example. In CHIP2 (SRAM + CTL # LOGIC), a static random access memory (SRAM) and a control circuit (CTL # LOGIC) are integrated. The control circuit controls the SRAM and CHIP3 integrated in CHIP2. CHIP3 (DRAM1) is a dynamic random access memory (DRAM). There are various types of DRAM such as EDO, SDRAM, and DDR due to differences in internal configuration and interface. Although any DRAM can be used for this memory module, this embodiment will be described using SDRAM as an example.

  This memory module has external addresses (A0 to A24) and command signals (S- / CE1, S-CE2, S- / OE, S- / WE, S- / LB, S- / UB, LS-EN, F-EN) is input. Power is supplied through S-VCC, S-VSS, LF-VCC, LF-VSS, LD-VCC, and LD-VSS, and S-I / O0 to S-I / O15 are used for data input / output. This memory module operates by a so-called SRAM interface method.

  CHIP2 supplies signals necessary for the operation of CHIP1 and CHIP3. CHIP2 is a serial clock (F-SC), address and data for FLASH (I / O0 to I / O7), command (F-CE, F- / OE, F- / WE, F- / RES, CHIP2) F-CDE, F-RDY / BUSY) and power supply (F-VCC, F-VSS) are supplied. Furthermore, CHIP2 has a clock (D1-CLK), address (D1-A0 to D1-A14), command (D1-CKE, D1- / CS, D1- / RAS, D1- / CAS, D1- / WE, D1-DQMU / DQML), DRAM data (D1-DQ0 to D1-DQ15), and power supplies (D1-VCC, D1-VSS, D1-VCCQ, D1-VSSQ) are supplied.

  Here, each command signal will be briefly described. S- / CE1 and S-CE2 input to CHIP2 are chip enable signals, S- / OE is output enable signals, S- / WE is write enable signals, S- / LB is lower byte select signals, S- / UB is an upper byte selection signal.

  F- / CE input to CHIP1 is chip enable signal, F- / OE is output enable signal, F- / WE is write enable signal, F-SC is serial clock signal, F- / RES is reset signal, F -CDE is a command data enable signal, F-RDY / BUSY is a ready / busy signal, and I / O0 to I / O7 are input / output signals used for address input and data input / output.

  The CHIP2 control circuit (CTL # LOGIC) selects either the command register REG provided in the control circuit (CTL # LOGIC), SRAM in CHIP2, DRAM in CHIP3, or FLASH in CHIP1 depending on the address value. To do.

  Each region can be distinguished by setting a value in advance in a control register provided in the control circuit (CTL # LOGIC). Access to both is performed by the so-called SRAM interface method.

  The DRAM is divided into a work area and a FLASH data copy area. The work is used as a work memory when executing a program, and the FLASH data copy area is used as a memory for copying data from the FLASH.

  When accessing the SRAM, the address signal and command signals for selecting the SRAM are input to the control circuit (CTL # LOGIC) to access the SRAM inside the CHIP2. In the case of read access, data is read from the SRAM and output to the data input / output lines (I / O0 to I / O15) of the memory module. In the case of write access, write data is input from the data input / output lines (I / O0 to I / O15) of the memory module and written to the SRAM.

  By accessing the command register REG in the control circuit (CTL # LOGIC) and writing the load instruction or store instruction code, the FLASH data can be copied (loaded) to the FLASH data copy area in the DRAM, or the FLASH in the DRAM Data in the data copy area can be written back to FLASH (store).

  Address to access command register REG from address signal (A0 to A24) and command signal (S- / CE1, S-CE2, S- / OE, S- / WE, S-LB, S- / UB) When a load start code and a load end address are input from the I / O data signal (I / O0 to I / O15) to the load instruction code, followed by the address in the FLASH area, the load instruction is sent to the command register. Code, load start address and load end address are written. As a result, data between the load start address and the load end address of the FLASH is read and transferred to the FLASH data copy area in the DRAM. As a result, the FLASH data is held in the DRAM.

  When the store start code and store end address are written to the command register at the address for selecting the store instruction code and FLASH, the data in the FLASH data copy area in the DRAM is transferred to the address between the store start address and the store end address of the FLASH. Written back.

  Which address range of FLASH corresponds to which address range of the FLASH data copy area of DRAM can be determined by setting a value in the control register provided in the control circuit (CTL # LOGIC) .

  In FLASH, rewriting is repeated to reduce reliability, and data written at the time of writing rarely becomes different data at the time of reading or data is not written at the time of rewriting.

  When reading data from FLASH, CHIP2 (CTL # LOGIC) detects and corrects errors in the read data and transfers them to DRAM. When writing data to the FLASH, CHIP2 (CTL # LOGIC) checks whether it has been written correctly, and if not written correctly, writes to an address different from the current address. A so-called substitution process is performed. Address management is also performed in which the substitute processing is performed for the defective address and the defective address.

  To access the DRAM FLASH data copy area, the address signal (A0 to A24), the address of the FLASH area, and the command signal (S- / CE1, S-CE2, S- / OE, S- / WE, S -/ LB, S- / UB). When the command signal is a read command, the control circuit of CHIP2 accesses the DRAM and reads data from the address in the FLASH data copy area of the DRAM corresponding to the address in the FLASH area. In the case of a write instruction, the write data is input from the data input / output lines (I / O0 to I / O15) of the memory module, and then input to the DRAM through the DRAM data I / O (D1-DQ0 to D1-DQ15). . As a result, FLASH data read and write times are equivalent to SRAM.

  When accessing the DRAM work area, an address signal and a command signal necessary for accessing the DRAM work area are input. The control circuit (CTL # LOGIC) generates an address to the work area in the DRAM and accesses the DRAM. In the case of read access, read data from the DRAM passes through the DRAM data I / O (D1-DQ0 to D1-DQ15) and is output to the data input / output lines (I / O0 to I / O15). In the case of write access, write data is input from the memory module's data input / output lines (I / O0 to I / O15) and then input to the DRAM through DRAM data I / O (D1-DQ0 to D1-DQ15). .

  Power to CHIP3 (DRAM) is supplied from LD-VCC and LD-VSS, and connected to D1-VCC, D1-VSS, D1-VCCQ, D1-VSSQ through the control circuit (CTL # LOGIC) and power to FLASH Is supplied from LF-VCC and LF-VSS and connected to F-VCC and F-VSS through the control circuit (CTL # LOGIC). The power supply to the DRAM and FLASH is controlled by the command signal PS and can be cut off as necessary.

  When the DRAM power is shut off, the control circuit (CTL # LOGIC) automatically writes back only the data that needs to be written back from the DRAM to the FLASH, and shuts off the DRAM power after the data write-back is completed.

  It is necessary to initialize the DRAM when powering off the disconnected DRAM. The control circuit (CTL # LOGIC) performs signal generation and timing control necessary for initialization of DRAM and FLASH.

  Further, when refreshing the DRAM, the control circuit (CTL # LOGIC) can periodically perform a bank active command. In general, the refresh characteristics of DRAM deteriorate at high temperatures, but DRAM can be used in a wider temperature range by providing a thermometer in the control circuit (CTL # LOGIC) to narrow the interval between bank active commands at high temperatures.

  According to the embodiment described above, it is possible to realize a memory module having a large capacity and an access speed equivalent to that of SRAM using inexpensive general-purpose SDRAM and FLASH while following the SRAM interface method.

  In the memory module according to the present invention, a part of FLASH data or an area where all data can be copied is secured in DRAM, and data is transferred from FLASH to DRAM in advance. Data can be read out. When writing data to the FLASH, the data can be written once to the DRAM and then written back to the FLASH as needed, so that the data writing speed can be equivalent to that of the SRAM.

  By using large-capacity SDRAM, a large work area can be secured in addition to the area where FLASH data can be copied to SDRAM.

  When reading from FALSH, error detection and correction are performed, and when writing, replacement processing is performed for defective addresses that were not written correctly, so processing can be performed at high speed and reliability can be maintained. it can.

  Since a large-capacity SDRAM is used, a large work area can be secured in addition to the area where FLASH data can be copied to SDRAM.

  By changing the interval of the refresh executed inside the module according to the temperature, it becomes possible to extend the operating temperature range of the DRAM, and a large capacity memory module with a wide operating temperature range can be realized.

  Another object of the present invention is to realize a memory module with a small data holding current. For this purpose, the data holding current can be reduced by extending the refresh interval executed inside the module, particularly at low temperatures.

  In order to further reduce the data holding current, it is only necessary to cut off the power supplied to the DRAM and hold only the data stored in the SRAM. As a result, only necessary data can be held with a minimum data holding current.

  FIG. 22 shows CHIP2 (SRAM + CTL # LOGIC). CHIP2 (SRAM + CTL # LOGIC) is composed of an SRAM and a control circuit (CTL # LOGIC), and the integrated SRAM is an asynchronous SRAM that is generally used conventionally. The control circuit (CTL # LOGIC) is a part other than the SRAM of CHIP2, and is shown as an area surrounded by a broken line in FIG. 18, and AS, MMU, ATD, DTD, R / W BUFFER, CPB, A # CONT, Consists of REG, INT, TMP, RC, PM, CLK # GEN, and COM # GEN. The operation of each circuit block will be described below.

  The initialization circuit INT initializes the control register and the DRAM in the memory management unit MMU at the start of power supply.

  The memory management unit MMU converts the address input from the outside according to the value set in the built-in control register, and converts the command register REG in the REGISTER area, the work area in the DRAM, the FLASH data copy area, and the FLASH area in the DRAM. Select and access. The value of the control register is initialized by the initialization circuit INT when power is supplied. If you want to change the value of the control register, if an SRAM that inputs a memory management MMU change instruction is selected in the command register REG, an address signal and a command signal are sent to the SRAM by the access switch (AS), and to the SRAM. Is accessed.

  The address transition detector circuit (ATD) detects a change in the address signal and the command signal and outputs a pulse. The command transition detector circuit (CTD) detects a change in the command signal and outputs a pulse. When these detection circuits detect a change in signal, access to the memory is started.

  The data update address management circuit CPB holds address information when data is written in the FLASH data copy area of the DRAM.

  In the command register REG, instruction codes such as load instruction, store instruction, memory management unit MMU change instruction, power shutdown instruction, and addresses such as load start address, load end address, store start address, store end address are written and held Is done.

  The data buffer R / WBUFFER temporarily holds DRAM read data and write data or FALSH read data and write data.

  The command generator COM # GEN generates commands necessary for accessing DRAM. The access controller A # CONT generates an address for overall control of CHIP2 and access to the DRAM.

  The flash control signal generation circuit FGEN controls reading and writing of FLASH data.

  The error correction circuit ECC checks whether there is an error in the data read from the FLASH, and corrects if there is an error. The substitution processing circuit REP checks whether or not the writing to the FLASH has been performed correctly. If the writing has not been performed correctly, the substitution processing circuit REP writes to a new replacement address prepared in advance in the FLASH.

  The temperature measurement module (TMP) measures the temperature and outputs a signal corresponding to the measured temperature to RC and A # CONT. RC is a refresh counter that generates an address to be refreshed in accordance with the DRAM refresh interval. Also, the refresh interval is changed according to the temperature by the output signal of the temperature measurement module (TMP).

  The power module (PM) supplies power to the CHIP2 control circuit (CTL # LOGIC) and DRAM and controls power. The clock generator (CLK # GEN) generates a clock and supplies it to the DRAM and the control circuit (CTL # LOGIC). The command generator (COM # GEN) generates commands necessary for accessing DRAM. The access controller (A # CONT) controls the overall operation of CHIP2 (SRAM + CTL # LOGIC) and generates an address for accessing the DRAM.

  The flash control signal generation circuit FGEN controls reading and writing of FLASH data.

  The error correction circuit ECC checks whether there is an error in the data read from the FLASH, and corrects if there is an error. The substitution processing circuit REP checks whether or not the writing to the FLASH has been performed correctly. If the writing has not been performed correctly, the substitution processing circuit REP writes to a new replacement address prepared in advance in the FLASH.

  Next, the operation of this memory module will be described.

  To perform memory access to CHIP2 (SRAM + CTL # LOGIC), the asynchronous SRAM method that has been generally used is used.

  When the address signal (A0 to A24) or command signal (S- / LB, S- / UB, S- / WE, S- / CE1, S-CE2, S- / OE) changes, ATD detects this. Then, access to the command register REG, SRAM, DRAM or FLASH is started.

  The value of the address signal (A0 to A24) input from the outside is first converted by the memory management unit MMU. Whether the access destination is the command register REG, SRAM, DRAM, or FLASH is determined by the converted address.

  The address conversion pattern is determined by the value of the control register in the memory management unit MMU.

  When the command register REG is selected and the load instruction code is written into the command register REG, data transfer from the FLASH to the DRAM is started. First, the flash control signal generation circuit FGEN in the flash controller FCON performs a read operation on the FLASH. If there is no error in the data read from the FLASH, the data is directly transferred to the data buffer R / W BUFFER. If there is an error, the data is corrected by the error correction circuit ECC and transferred to the data buffer R / W BUFFER. Next, the write command from the command generation circuit COM # GEN, the address signal from the access controller A # CONT, and the data read from the FLASH from the data buffer R / W BUFFER are input to the DRAM and transferred to the FLASH data copy area of the DRAM Writing is performed.

  The data update management circuit CPB retains write address information when data is written in the FLASH data copy area of the DRAM.

When the command register REG is selected and a store instruction is written to the command register, data transfer from the data in the FLASH data copy area of the DRAM to the FLASH is started.

  First, a read command is sent from the command generation circuit COM # GEN and an address signal is sent from the access controller A # CONT to the DRAM to read the data. Data read from the DRAM is transferred to the flash controller FCON through the data buffer R / W BUFFER, and the flash control signal generation circuit FGEN writes to the FLASH. The address substitution processing circuit REP checks whether or not the writing is successful, and if successful, ends the processing. When writing fails, writing is performed to a new alternative address prepared in advance in the FLASH. When the replacement process is performed, the address information indicating the replacement address for the defective address and the defective address is held and managed. The data update management circuit CPB clears the address information for which writing to the FLASH has been completed from the stored DRAM address information. Thus, the data update management circuit CPB can always manage the address at which the latest data is updated.

  When the DRAM work area and FLASH data copy area are selected and a read instruction is issued, a read instruction signal from the command generation circuit COM # GEN and an address signal from the access controller A # CONT are sent to the DRAM to read data.

  When the DRAM work area and FLASH data copy area are selected and a write instruction is issued, the write instruction signal from the command generation circuit COM # GEN, the address signal from the address generation circuit A # CONT, and the data from the data buffer R / W BUFFER to the DRAM Send and data is written.

  When the command register REG is selected and a power shutdown command is written to the command register, the DRAM data corresponding to the address held by the data update management circuit CPB is transferred to the FLASH. First, a read command is sent from the command generation circuit COM # GEN and an address signal is sent from the access controller A # CONT to the DRAM to read data. Data read from the DRAM is transferred to the flash controller FCON through the data buffer R / W BUFFER, and written in FLASH by the flash control signal generation circuit FGEN.

  The data update management circuit CPB clears the address information that has been written to the FLASH out of the DRAM address information held, and when all the data corresponding to the held address is written to the FLASH, the data update management circuit CPB All address information is cleared.

  When the memory module is used at a high temperature, the refresh interval of the DRAM may be shortened and frequently refreshed. Therefore, in this memory module, the temperature measurement module (TMP) measures the temperature and notifies the refresh counter and the access controller. When the temperature becomes high, the refresh counter changes the refresh interval short and outputs a refresh address. Conversely, if the refresh interval of the DRAM is changed to be longer at low temperatures, the data holding current can be reduced. Even in such a case, the temperature measurement module (TMP) measures the temperature and notifies the refresh counter and the access controller. When the temperature becomes low, the refresh counter changes the refresh interval longer and outputs a refresh address.

  In some cases, a device in which a memory module is mounted may want to reduce current consumption according to the operating state. Therefore, a method for reducing the power consumption by changing the operation state of the memory using the power module will be described.

  First, the simplest one is that the power module stops the refresh performed by the refresh counter in accordance with the command signal PS. As a result, the data stored in the DRAM is destroyed, but the power required for the refresh can be reduced.

  To further reduce power consumption, the power supplied to the DRAM is cut off inside the memory module. In this case, the power module stops power supply to D1-VCC supplied to the DRAM according to the command signal PS output from the device.

  In addition, if it is desired to further reduce power consumption, the power module may stop supplying power to the portion of CHIP2 (SRAM + CTL # LOGIC) involved in memory access to the DRAM according to the command signal PS. In this state, for example, in CHIP2 (SRAM + CTL # LOGIC), in addition to the SRAM, it is possible to connect the power supply only to the MMU and AS to be in the operating state, and to set the mode in which only the SRAM is accessed.

  Further, it is possible to set the operation state in which only the SRAM data is held by the command PS. In this case, access to the memory is prohibited by disconnecting power other than the power supply (S-VCC, S-VSS) connected to the SRAM. In this state, the memory module holds the data stored in the SRAM.

  In order to operate the DRAM again after stopping the power supply to the DRAM and stopping the operation, it is necessary to initialize the DRAM in addition to restarting the power supply. Although the initialization method is general, in this memory module, the initial circuit (INT) instructs the access controller (A # CONT) the initialization procedure and the initialization is executed.

  Note that even if DRAM refresh is stopped, DRAM initialization is required to operate the DRAM again, but the initial circuit (INT) still instructs the access controller (A # CONT) the initialization procedure. Then initialization is executed.

  23, 24, 25, and 26 show an example of a memory map converted by the memory management unit MMU. Any of these memory maps can be selected according to the value set in the control register inside the MMU. Although not particularly limited in the present embodiment, a typical memory map will be described taking a memory module having a FLASH storage capacity of 256 + 8 Mb, a data holding SRAM of 2 Mb, and a DRAM of 256 Mb as an example.

  In FIG. 23, the memory management unit MMU uses the command register REG (16kbit), SRAM data holding area (2Mbit), DRAM work area (128Mbit), DRAM FLASH copy area based on the addresses input through address signals A0 to A24. (128Mbit), a memory map in which addresses are converted to FLASH (256 + 8 Mbit).

  Although there is no particular limitation, command registers REG, SRAM, DRAM, and FLASH are mapped from the lower part of the address space of the memory map.

  The command register REG is externally written with instruction codes such as load instructions, store instructions, and MMU register change instructions, and start and end addresses for load instructions and store instructions.

  The DRAM is divided into a Work area (128 Mbit) and a FLASH copy area (128 Mbit). The Work area is used as a work memory at the time of program execution, and the FLASH copy area is used to copy and hold a part of the data in the FLASH area.

  The 2Mbit data holding area by SRAM is set in the lower part of the address space. This area overlaps with the DRAM and is mapped in the memory space, but the DRAM is not accessed and only the SRAM is accessed.

  When the memory module power supply is controlled and only SRAM data is retained and used, the SRAM area can be centrally managed.

  The unaccessible DRAM area (SHADOW) can be used to relieve DRAM memory cells. The memory module has been devised to extend the refresh interval at low temperatures to reduce power consumption, but in that case, memory cells (Fail bit) that are difficult to hold data also occur. Therefore, the fail bit can be substituted by using the DRAM which becomes SHADOW. In FIG. 23, there are Fail bit A and Fail bit B in the DRAM, and these addresses are registered in advance. When access is made to Fail bit, each SHADOW is accessed instead. By replacing SHADOW, the fail bit is relieved, and a memory module with low power consumption can be realized by extending the refresh interval at low temperatures.

  In order to copy a part of the data in the FLASH area to the FLASH copy area, the memory management unit MMU determines which address data in the FLASH area is assigned to which address in the FLASH copy area according to the value set in the internal register. Decide if it is compatible. In FIG. 23, the data in the A1 area (64 Mbit) and the C1 area (64 Mbit) in the FLASH area correspond to addresses that can be copied to the A1 area (64 Mbit) and 1 area (64 Mbit) in the DRAM FLASH copy area, respectively. An example is shown. By changing the value of the internal control register of the memory management unit MMU, the data in the B1 area (64Mbit) and D1 area (56Mbit) in the FLASH area must be changed so that they can be copied to the DRAM FLASH copy area. You can also.

  FLASH (256M + 8Mbit) is not particularly limited, but main data area MD-Area (A1, A2, B1, B2, C1, C2, D1, D2: 255.75 Mbit) and alternative area Rep-Area (E1, E2: 8.25) Mbit). The main data area is further divided into a data area (A1, B1, C1, D1) and a redundant area (A2, B2, C2, D2). The data area stores programs and data, and the redundancy area stores ECC parity data for detecting and correcting errors. Data in the FLASH data area is transferred to the FLASH copy area of the DRAM, or data in the FLASH copy area of the DRAM is transferred to the FLASH data area. In FLASH, rewriting is repeated to reduce reliability, and data written at the time of writing rarely becomes different data at the time of reading or data is not written at the time of rewriting. The replacement area is provided in order to replace the data of the areas (Fail Area C and Fail Area D) that have become defective in this way with new areas. The size of the alternative area is not particularly limited, but it is preferable to determine it so as to ensure the reliability guaranteed by FLASH.

  Data transfer from FLASH to DRAM will be described. In order to transfer data in the AAL area of the FALSH to the FLASH copy area A1 area of the DRAM, the load instruction, the transfer start address SAD and the transfer end address EAD of the A1 area in the FALSH area are written in the command register. Then, the control circuit (CTL # LOGIC) reads the data in the address range indicated by the transfer start address FSAD and the transfer end address FEAD in the A1 area of the FLASH, and the DRAM FLASH copy area associated with the memory management unit MMU Transfer to the address range of addresses DSAD and DEAD in the A1 area. When reading data from FLASH, data in FLASH data area A1 and ECC parity data in redundant area A2 are read in the data management unit (8 kbit in this case) and corrected if there is an error by error correction circuit ECC . Only the corrected data is transferred to DRAM.

  Data transfer from DRAM to FLASH will be described. In order to transfer the data in the FLASH copy area A1 of the DRAM to the AAL area of the FALSH, the store instruction, the transfer start address SAD and the transfer end address EAD of the AAL area of the FALSH are written to the command register. Then, the control circuit (CTL # LOGIC) reads the data in the address range ADAD and DEAD in the DRAM FLASH copy area A1 associated with the memory management unit MMU, and the transfer start address in the FLASH A1 area. Write the address range data of FSAD and transfer end address FEAD. When writing data to FLASH, the error correction circuit ECC generates ECC parity data in a data management unit (here, 8 kbit). The data read from the DRAM by the flash control circuit FGEN is written to the FLASH data area A1, and the generated ECC parity data is written to the redundant area A2. The address substitution processing circuit REP checks whether or not the writing is successful, and if successful, ends the processing. When the writing fails, the address in the alternative area of FLASH is selected, the data read from the DRAM is written into the alternative data E1 in the alternative area, and the generated ECC parity data is written into the alternative redundant area E2.

  Next, reading of data from the FLASH copy area A1 of the DRAM will be described. When an external address FAD0 in the FLASH A1 area and a read command are input from the outside, the MMU converts the address to the address DAD0 in the FLASH copy area A1 of the DRAM corresponding to the address FAD0. As a result, the DRAM data is selected and the FLASH data copied to the DRAM can be read. In other words, FLASH data can be read at the same speed as DRAM.

  Next, reading of data in the DRAM work area will be described. When the work area address WAD0 and the read command are input from the outside, the MMU outputs the address WAD0 to the address generation circuit A # COUNT. As a result, the data of the DRAM work area address WAD0 can be read.

  Next, writing of data into the FLASH copy area A1 of the DRAM will be described. When the FLASH A1 area address FAD0, the write command, and the write data are input from the outside, the MMU converts the address to the address DAD0 in the DRAM FLASH copy area corresponding to the address FAD0. As a result, DRAM is selected and data is written to the FLASH copy area A1. By writing to the FLASH copy area A1 of the DRAM corresponding to the FLASH data area A1, the FLASH data can be written at the same speed as the SRAM.

  Next, reading of data in the DRAM work area will be described. When the work area address WAD0 and a read command are input from the outside, the MMU outputs the address WAD0 to the access controller A # COUNT. As a result, the data of the DRAM work area address WAD0 can be read.

  Next, data writing in the DRAM work area will be described. When a work area address WAD0, a write command, and input data are input from the outside, the address generation circuit A # COUNT outputs the address WAD0 to the DRAM. As a result, data in the DRAM work area address WAD0 can be written.

  In the example of the memory map shown in FIG. 24, SRAM areas are set in a plurality of address spaces. Again, the SRAM address space overlaps the DRAM address space, and access to the overlapped address space is made to the SRAM. Multiple SHADOWs are used to save multiple Fail bits. In this example, the SRAM area is set in units of 2 Kbytes, but this is aligned with the FLASH memory write / erase unit, and the memory space is handled by the OS and programs by aligning the address space management unit with the FLASH memory. It is a device for simplifying.

  In addition, when the memory module power source is controlled to use only the SRAM data, the SRAM area can be distributed and arranged in the memory space.

  In the example of the memory map shown in FIG. 25, SRAM and DRAM are mapped to different address spaces, and there is no SHADOW caused by duplication. Therefore, the address space is 258Mb, which is the sum of 256Mb of DRAM and 2Mb of SRAM, and a wider address space can be obtained.

  The memory map shown in FIG. 26 is an example in which the SRAM area of FIG. As in the example shown in FIG. 25, a wider address space can be provided. Similarly to the example shown in FIG. 22, when the memory module power supply is controlled and only the SRAM data is retained and used, the SRAM area can be distributed in the memory space. .

  In this way, the MMU can allocate the SRAM area and DRAM area to the specified address space. The assignment method can be easily changed by changing the register value set in the MMU.

  Further, in particular, when it is desired to reduce the data holding current, an address space for storing data to be held may be allocated to the SRAM area, and power supply to the DRAM may be stopped. By this method, a memory module with a small data holding current can be realized.

  FIG. 27A shows the priorities of access to the DRAM at the time of external access, refresh access, load instruction and store instruction. The refresh access has the first priority, the external access has the second priority, and the access in the load or store instruction has the third priority.

  FIG. 27B shows the operation when a read access (READ) and a refresh access (REF) are generated from the outside to the DRAM.

  FIG. 27C shows the operation when a write access (WRITE) and a refresh access (REF) occur in the DRAM.

  When the refresh access (REF) does not occur and the external access (READ, WRITE) occurs, the external access is directly performed on the DRAM, and data is read or written.

  When a refresh access (REF) and an external access occur, a refresh operation is first performed by a refresh access having a high priority, and then an operation by the external access is executed. During the refresh operation, the WAIT signal goes high, indicating that the DRAM operation has already been performed.

  FIG. 28A shows the operation to the DRAM when data is transferred from the FLASH to the DRAM when the load instruction is written to the command register. Reads data from FLASH, temporarily stores it in the data buffer R / W BUFFER, and then accesses the DRAM and writes the data. During the period from the start of the write access to the DRAM until the end of the write, the WAIT signal is set to High to indicate that the DRAM has already been accessed.

  FIG. 28B shows the operation to the DRAM when data is transferred from the DRAM to the FLASH when a store instruction is written to the command register. Reads data from DRAM and temporarily stores it in the data buffer, then accesses FLASH and writes data. From the start of read access to DRAM until the end of write, the WAIT signal is set to High to indicate that access to DRAM has already been performed.

  FIG. 29A shows the operation of the DRAM when a read access occurs from the outside during the write access to the DRAM at the time of the load instruction. The type of external access is not particularly limited, but here, read access is taken as an example. When an external access occurs, the DRAM write access at the time of the load instruction is temporarily stopped and the external access is preferentially processed. When the external access processing is completed, the DRAM write access at the time of the load instruction is resumed.

  FIG. 29B shows the operation of the DRAM when an external write / read access occurs during a read access to the DRAM at the time of a store instruction. The type of external access is not particularly limited, but here, write access is taken as an example. When an external access occurs, the DRAM read access at the time of the store instruction is temporarily stopped, and the external access is preferentially processed. When the external access processing is completed, the DRAM read access at the time of the store instruction is resumed.

  FIG. 30 shows an example of operation waveforms of the memory module according to the present invention. A0 to A20, S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE are signals that are input to the memory module, and are so-called asynchronous SRAM interface signals. . The data input / output signals I / O0 to I / O15 are represented as DIN and DOUT by dividing the data input and output, respectively. MMU, ATD, and CTD represent output signals of the MMU circuit, ATD circuit, and CTD circuit, respectively. D1-CLK is a clock supplied to DRAM, D1-COM is a generic name for command signals supplied to DRAM, D1-A0 to D1-A15 are DRAM address lines, D1-DQ0 to D1-DQ15 are DRAM I / O O line.

  First, read access that is performed first will be described. When the addresses A0 to A24 are input, the MMU circuit outputs the converted address. The ATD circuit detects changes in addresses A0 to A24 and commands (S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE). When confirmed, a pulse is output. In response to this pulse, the bank active command A and the row address Ra, and then the read command R and the column address Co are issued to the DRAM 1. Data read from the DRAM 1 is output to D-DQ0 to D-DQ15, and is output to I / O0 to I / O15 once through the R / W BUFFER. In the next cycle, an example of write access is shown. In the case of write access, the bank active command A and the row address Ra are issued in response to the fall of the ATD signal, as in the case of read access. After that, the CTD circuit detects changes in commands (S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE) and confirms that it is a write operation. Recognize and output a pulse. As a result of this pulse, a write command W and a column command Co are issued and a write is executed.

  FIG. 31 shows an example of operation waveforms of the memory module according to the present invention, and shows operation waveforms when a read access is generated from the outside during the refresh operation.

  In order to perform refresh, a bank active command A and a row address Ra are issued to the DRAM 1, and then a precharge command P and a bank address Ba are issued. During this refresh operation, the refresh counter outputs a signal RC indicating that RC is in the refresh period. An external read access that occurs during the refresh period will be described. When the addresses A0 to A24 are input, the MMU circuit outputs the converted address. The ATD circuit detects changes in addresses A0 to A24 and commands (S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE). When confirmed, a pulse is output. This pulse latches the address and command. In response to the end of the refresh period, the bank active command A and the row address Ra, and then the read command R and the column address Co are issued to the DRAM 1. Data read from the DRAM 1 is output to D-DQ0 to D-DQ15, and is output to I / O0 to I / O15 once through the R / W BUFFER.

  FIG. 32 shows a configuration example of the SRAM in this embodiment. It consists of X decoder X-DEC, memory array MA (SRAM), Y gate Y-GATE, Y decoder Y-DEC, input data control circuit D # CTL, control circuit CONTROL LOGIC and input / output buffers for each signal line . This SRAM is a general so-called asynchronous SRAM. The memory module according to this embodiment can be configured by this SRAM.

  According to the embodiment described above, a large-capacity memory module using an inexpensive general-purpose DRAM can be realized while following the SRAM interface method. In the memory module according to the present invention, a part of FLASH data or an area where all data can be copied is secured in the DRAM, and the data is transferred from the FLASH to the DRAM in advance, so that the FLASH can be processed at the same speed as the SRAM. Can be read. When writing data to the FLASH, the data can be written once to the DRAM and then written back to the FLASH as needed, so the data writing speed is equivalent to that of the SRAM. When reading from FALSH, error detection and correction are performed, and when writing, replacement processing is performed for defective addresses that were not written correctly, so processing can be performed at high speed and reliability can be maintained. it can.

  Since the memory management unit MMU can freely set the data holding area by SRAM, the FLASH copy area of DRAM, and the work area, it can be used widely corresponding to various devices.

  In the control circuit (CTL # LOGIC) according to the present invention, DRAM is used, but refresh required for DRAM is executed by the control circuit (CTL # LOGIC), so it can be used without considering refresh as in SRAM. I can do it. Furthermore, by reducing the DRAM refresh interval, the DRAM can be operated even at high temperatures, and a memory module with a wide operating temperature range can be realized. On the other hand, by increasing the DRAM refresh interval at low temperatures, the power required for data retention can be reduced, and a memory module with low data retention power can be realized. Depending on the function of the power module PM, the power supply for part or all of the DRAM can be stopped to limit the storage area and reduce the power required for data retention. Furthermore, the power supply of the control circuit is also stopped, and a memory module with less data holding power can be realized.

<Example 3>
FIG. 33 shows a third embodiment of the memory module according to the present invention. FIG. 33A shows a top view and FIG. 33B shows a cross-sectional view. This memory module is mounted on the board by a ball grid array (BGA) (for example, a printed circuit board PCB made of a glass epoxy board) CHIP1 (FLASH), CHIP2 (CTL # LOGIC), CHIP3 shown in the first embodiment. (DRAM) is mounted, or CHIP1 (FLASH), CHIP2 (SRAM + CTL # LOGIC), and CHIP3 (DRAM) described in the second embodiment are mounted. Although not limited in particular, CHIP1 uses a general-purpose DRAM bare chip in which one row of signal and power pad rows is arranged at one end of the chip, and CHIP3 has one row of signal and power pad rows in the center of the so-called chip. Lined general-purpose DRAM bare chips are used. CHIP1 and the bonding pad on the substrate are connected by a bonding wire (PATH2), and CHIP2 and the bonding pad on the substrate are connected by a bonding wire (PATH3). Connected to CHIP3 and CHIP2 with bonding wire (PATH1). Connected to CHIP1 and CHIP2 with bonding wire (PATH4). Resin molding is performed on the upper surface of the substrate on which the chip is mounted to protect each chip and connection wiring. Further, a metal, ceramic, or resin cover (COVER) may be used from above.

  In the embodiment according to the present invention, since the bare chip is directly mounted on the printed circuit board PCB, a memory module having a small mounting area can be configured. Further, since the chips can be arranged close to each other, the interchip wiring length can be shortened. By unifying the wiring between chips and the wiring between each chip and the substrate by a bonding wire system, a memory module can be manufactured with a small number of processes. Further, by directly connecting the chips with bonding wires, the number of bonding pads and bonding wires on the substrate can be reduced, and the memory module can be manufactured with a small number of processes. Since a general-purpose DRAM bare chip mass-produced in large quantities can be used, a memory module can be stably supplied at low cost. When a resin cover is used, a stronger memory module can be configured. When a ceramic or metal cover is used, a memory module excellent in heat dissipation and shielding effect can be configured in addition to strength.

  FIG. 34 is a modification of the memory module of FIG. 34 according to the present invention. FIG. 34 (A) shows a cross-sectional view of the top view 34 (B). In this example, a ball grid array (BGA) is used for mounting and wiring of CHIP3 (DRAM) and CHIP2 (CTL # LOGIC or SRAM + CTL # LOGIC). CHIP1 and the bonding pad on the substrate are connected by a bonding wire (PATH2). This assembly method eliminates the need for bonding between CHIP2 (CTL # LOGIC or SRAM + CTL # LOGIC), CHIP3 (DRAM), and CHIP2 (CTL # LOGIC) and the board, reducing the number of bonding wires. Man-hours can be reduced, and a more reliable memory module can be realized.

<Example 4>
FIG. 35 shows another embodiment of the memory module of the present invention. This memory module is composed of four chips. Each chip will be described below. First, CHIP1 (FLASH) is a nonvolatile memory. As the nonvolatile memory, ROM (read only memory), EEPROM (electrically erasable and programmable ROM), flash memory, or the like can be used. In this embodiment, a flash memory will be described as an example. In CHIP2 (SRAM + CTL # LOGIC), a static random access memory (SRAM) and a control circuit (CTL # LOGIC) are integrated. The control circuit controls the SRAM, CHIP3 and CHIP4 integrated in CHIP2. CHIP3 (DRAM1) and CHIP4 (DRAM2) are dynamic random access memories (DRAM). There are various types of DRAM such as EDO, SDRAM, and DDR due to differences in internal configuration and interface. Although any DRAM can be used for this memory module, this embodiment will be described using SDRAM as an example.

  This memory module has external addresses (A0 to A24) and command signals (S- / CE1, S-CE2, S- / OE, S- / WE, S- / LB, S- / UB, LS-EN, F-EN) is input. Power is supplied through S-VCC, S-VSS, F-VCC, F-VSS, L-VCC, and L-VSS, and S-I / O0 to S-I / O15 are used for data input / output. This memory module is operated by a so-called SRAM interface.

  CHIP2 supplies signals necessary for the operation of CHIP1, CHIP3, and CHIP4. CHIP2 is a serial clock (F-SC), address and data for FLASH (I / O0 to I / O7), command (F-CE, F- / OE, F- / WE, F- / RES, F-CDE, F-RDY / BUSY) and DRAM data (D1-DQ0 to D1-DQ15, D2-DQ0 to D2-DQ15) are supplied. Furthermore, CHIP2 is locked to CHIP3 and CHIP4 (D1-CLK, D2-CLK), address (D1-A0 to D1-A14, D2-A0 to D2-A14), command (D1-CKE, D2-CKE, D1- / CS, D2- / CS, D1- / RAS, D2- / RAS, D1- / CAS, D2- / CAS, D1- / WE, D2- / WE, D1-DQMU / DQML, D2-DQMU / DQML), DRAM data (D1-DQ0 to D1-DQ15, D2-DQ0 to D2-DQ15), power supply (D1-VCC, D2-VCC, D1-VSS, D2-VSS, D1-VCCQ, D2-VCCQ, D1-VSSQ, D2-VSSQ).

  Here, each command signal will be briefly described. S- / CE1 and S-CE2 input to CHIP2 are chip enable signals, S- / OE is output enable signals, S- / WE is write enable signals, S- / LB is lower byte selection signals, S- / UB is an upper byte selection signal.

  F- / CE input to CHIP1 is chip enable signal, F- / OE is output enable signal, F- / WE is write enable signal, F-SC is serial clock signal, F- / RES is reset signal, F -CDE is a command data enable signal, F-RDY / BUSY is a ready / busy signal, and I / O0 to I / O7 are data input / output signals used to control the flash memory.

  Depending on the address value input from the outside, the CHIP2 control circuit (CTL # LOGIC) is either a command register provided in the CHIP2 control circuit (CTL # LOGIC), the SRAM inside CHIP2, or the DRAM of CHIP3 and CHIP4. , Select CHIP1 FLASH.

  Each value can be distinguished by previously setting a value in a control register provided in the control circuit (CTL # LOGIC). Access to both is performed by the so-called SRAM interface method.

  When accessing the SRAM area, input the address signal and command signals in the SRAM area to the control circuit (CTL # LOGIC) to access the SRAM inside CHIP2. In the case of read access, data is read from the SRAM and output to the data input / output lines (S-I / O0 to S-I / O15) of the memory module. In the case of write access, write data is input from the data input / output lines (S-I / O0 to S-I / O15) of the memory module and written to the SRAM.

  By accessing the command register in the control circuit (CTL # LOGIC) and writing the load instruction or store instruction code, the data in the FLASH area can be copied (loaded) to the FLASH data copy area in the DRAM, or the FLASH in the DRAM Data in the data copy area can be written back (stored) in the FLASH area.

  From the address for accessing the command register from the address signal (A0 to A24) and the command signal (S- / CE1, S-CE2, S- / OE, S- / WE, S-LB, S- / UB) When a load instruction code is input from a write instruction or input / output data signal (I / O0 to I / O15), followed by a load start address and load end address at an address in the FLASH area, the load instruction code is input to the command register. And load start address and load end address are written. Then, the data between the load start address and the load end address in the FLASH area is read and transferred to the FLASH data copy areas of DRAM1 and DRAM2. As a result, the FLASH data is held in the DRAM.

  When the store start code and the store end address are written to the command register using the store instruction code and the address in the FLASH area, the FLASH data copy area in DRAM1 or DRAM2 from the store start address to the store end address in the FLASH area Will be written back.

  Which address range in the FLASH area corresponds to which address range in the FLASH data copy area of DRAM1 and DRAM2 can be determined by setting a value in the control register provided in the control circuit (CTL # LOGIC) it can.

  In FLASH, rewriting is repeated to reduce reliability, and data written at the time of writing rarely becomes different data at the time of reading or data is not written at the time of rewriting.

  When reading data from FLASH, CHIP2 (CTL # LOGIC) detects and corrects the error in the read data and transfers it to DRAM1 and DRAM2. When writing data to the FLASH, CHIP2 (CTL # LOGIC) checks whether it has been written correctly, and if not written correctly, writes to an address different from the current address. A so-called substitution process is performed. Address management is also performed in which the substitute processing is performed for the defective address and the defective address.

  When accessing the FLASH data copy area to DRAM, the address signal (A0 to A24), the address of the FLASH area and the command signal (S- / CE1, S-CE2, S- / OE, S- / WE, S- / LB, S- / UB). When the command signal is a read command, the CHIP2 control circuit accesses the DRAM, and the DRAM data I / O (D1-DQ0 to D1-DQ15) from the address in the FLASH data copy area of the DRAM corresponding to the address in the FLASH area. Or data is read through D2-DQ0 to D2-DQ15). In the case of a write instruction, write data is input from the data input / output lines (SI / O0 to SI / O15) of the memory module, and then the DRAM data I / O (D1-DQ0 to D1-DQ15 and D2-DQ0 to D2- It is input to DRAM through DQ15). As a result, the data read / write time in the FLASH area is equivalent to that of the SRAM.

  When accessing the DRAM work area, an address signal and a command signal necessary for accessing the DRAM work area are input. The control circuit (CTL # LOGIC) generates an address to the work area in the DRAM and accesses the DRAM. In the case of read access, the read data from the DRAM passes through the DRAM data I / O (D1-DQ0 to D1-DQ15 or D2-DQ0 to D2-DQ15) and the data input / output lines (SI / O0 to SI / O15). ). In the case of write access, the write data is input from the data input / output lines (SI / O0 to SI / O15) of the memory module, and then the DRAM data I / O (D1-DQ0 to D1-DQ15 and D2-DQ0 to D2- DQ15) is input to DRAM.

  Power to DRAM1 is supplied from LD-VCC and LD-VSS, and connected to D1-VCC, D1-VSS, D1-VCCQ and D1-VSSQ through a control circuit (CTL # LOGIC). The power supply to the DRAM is controlled by the command signal PS and can be cut off as necessary.

  When the DRAM power is shut off, the control circuit (CTL # LOGIC) automatically writes back only the data that needs to be written back from the DRAM to the FLASH, and shuts off the DRAM power after the data write-back is completed.

  When powering off the disconnected DRAM, it is necessary to initialize the DRAM and FLASH. The control circuit (CTL # LOGIC) performs signal generation and timing control necessary for DRAM initialization.

  Further, when refreshing the DRAM, the control circuit (CTL # LOGIC) can periodically perform a bank active command. In general, the refresh characteristics of DRAM deteriorate at high temperatures, but DRAM can be used in a wider temperature range by providing a thermometer in the control circuit (CTL # LOGIC) to narrow the interval between bank active commands at high temperatures.

  In addition, the work area and the FLASH area are duplicated by two DRAMs, and one data is held in two DRAMs, and the refresh timing is adjusted to adjust the refresh timing from the outside of the memory module. Conceal the refresh so that there are no restrictions on

  According to the embodiment described above, it is possible to realize a memory module having a large capacity and an access speed equivalent to that of SRAM using inexpensive general-purpose SDRAM and FLASH while following the SRAM interface method. In the memory module according to the present invention, a part of FLASH data or an area where all data can be copied is secured in DRAM, and data is transferred from FLASH to DRAM in advance. Data can be read out. When writing data to the FLASH, the data can be written once to the DRAM and then written back to the FLASH as needed, so the data writing speed can be equivalent to that of the SRAM.

  By using large-capacity SDRAM, a large work area can be secured in addition to the area where FLASH data can be copied to SDRAM.

  When reading from FALSH, error detection and correction are performed, and when writing, replacement processing is performed for defective addresses that were not written correctly, so processing can be performed at high speed and reliability can be maintained. it can. Since a large-capacity SDRAM is used, a large work area can be secured in addition to the area where FLASH data can be copied to SDRAM.

  Although the DRAM is used in the memory module according to the present invention, the refresh necessary for the DRAM is executed inside the module, so that it can be used without considering the refresh like the SRAM. Also, by changing the refresh interval executed inside the module depending on the temperature, it is possible to extend the operating temperature range of the DRAM, and a large-capacity memory module with a wide operating temperature range can be realized.

  In addition, the DRAM refresh can be hidden from the outside of the memory module by adjusting the data retention duplex and refresh timing in the DRAM. Therefore, when accessing this memory module, adjust the timing in consideration of the refresh. There is no need. Therefore, since it can be used in the same manner as a memory module using only a conventional SRAM, a large-capacity memory module can be used without changing the conventional system. Another object of the present invention is to realize a memory module with a small data holding current. For this purpose, the data holding current can be reduced by extending the refresh interval executed inside the module, particularly at low temperatures. In order to further reduce the data holding current, it is only necessary to cut off the power supplied to the DRAM and hold only the data stored in the SRAM. By storing only the data to be retained in the SRAM and stopping the power supply to the memory where the data that does not need to be retained is stored, it is possible to retain only the necessary data with the minimum data retention current. is there.

  FIG. 36 shows a circuit block diagram of CHIP2 (SRAM + CTL # LOGIC). CHIP2 (SRAM + CTL # LOGIC) is composed of an SRAM and a control circuit (CTL # LOGIC), and the integrated SRAM is an asynchronous SRAM that is generally used conventionally. The control circuit (CTL # LOGIC) is the part other than CHIP2 SRAM, and is shown as an area surrounded by a broken line in Fig. 36. AS, MMU, ATD, CTD, FIFO, R / W BUFFER, CACHE, A # Consists of CONT, INT, TMP, RC, PM, CLK # GEN, and COM # GEN.

  The operation of each circuit block will be described below. The initialization circuit INT initializes the control register in the memory management unit MMU and the DRAM when power is supplied. The command register REG holds instructions such as a load instruction, a store instruction, and an MMU change instruction input from the outside.

  The memory management unit MMU converts the address input from the outside according to the value set in the built-in control register, and selects the command register REG, SRAM, work area in DRAM, FLASH data copy area, FLASH in DRAM Access. The value of the control register is initialized by the initialization circuit INT when power is supplied. The value of the control register is changed when an MMU change instruction is input to the command register REG.

  When SRAM is selected, an address signal and a command signal are sent to the SRAM by the access switch (AS), and the SRAM is accessed.

  The address transition detector circuit (ATD) detects a change in the address signal and the command signal and outputs a pulse. The command transition detector circuit (CTD) detects a change in the command signal and outputs a pulse. When these detection circuits detect a change in signal, access to the memory is started.

  R / W BUFFER temporarily holds data for DRAM read / write. The first-in first-out memory (FIFO) is a first-in first-out buffer circuit that temporarily holds data to be written to the DRAM and its address. The CACHE temporarily stores the write data to the DRAM and the read data from the DRAM when the DRAM to be refreshed is switched or accessed once for a long period of time. Furthermore, CACHE also temporarily stores data written to DRAM by load instructions.

  The data update management circuit CPB holds information on the address or address range in which data has been updated, that is, the address or address range in which data has been written, in the address in the FLASH data copy area allocated to the DRAM.

  In the command register REG, instruction codes such as load instruction, store instruction, memory management unit MMU change instruction, power shutdown instruction, and addresses such as load start address, load end address, store start address, store end address are written and held Is done.

  The command generator COM # GEN generates commands necessary for accessing DRAM. The access controller A # CONT generates an address for overall control of CHIP2 and access to the DRAM.

  The flash control signal generation circuit FGEN controls reading and writing of FLASH data.

  The error correction circuit ECC checks whether there is an error in the data read from the FLASH, and corrects if there is an error. The substitution processing circuit REP checks whether or not the writing to the FLASH has been performed correctly. If the writing has not been performed correctly, the substitution processing circuit REP writes to a new replacement address prepared in advance in the FLASH.

  The temperature measurement module (TMP) measures the temperature and outputs a signal corresponding to the measured temperature to RC and A # CONT. RC is a refresh counter that generates an address to be refreshed in accordance with the DRAM refresh interval. Also, the refresh interval is changed according to the temperature by the output signal of the temperature measurement module (TMP).

  The power module (PM) supplies power to the CHIP2 control circuit (CTL # LOGIC) and DRAM and controls power. The clock generator (CLK # GEN) generates a clock and supplies it to the DRAM and the control circuit (CTL # LOGIC). The command generator (COM # GEN) generates commands necessary for accessing DRAM. The access controller (A # CONT) controls the overall operation of CHIP2 (SRAM + CTL # LOGIC) and generates an address for accessing the DRAM.

  Next, the operation of this memory module will be described.

  In order to perform memory access to CHIP2 (SRAM + CTL # LOGIC), an interface is used with the asynchronous SRAM method that has been generally used.

  When the address signal (A0 to A24) or command signal (S- / LB, S- / UB, S- / WE, S- / CE1, S-CE2, S- / OE) changes, ATD detects this. Access to the command registers REG, SRAM, DRAM is started.

  The value of the address signal (A0 to A24) input from the outside is first converted by the MMU. The conversion pattern is determined by the value previously input to the register in the MMU. Whether the access destination is the command register REG, SRAM, or DRAM is determined by the converted address.

  When accessing the SRAM, the MMU sends the converted address to the SRAM and at the same time instructs the access switch (AS) to transfer the command. The access switch (AS) transfers the command to the SRAM, and access to the SRAM is started. In subsequent operations, access to a so-called asynchronous SRAM is performed.

  When performing read access to DRAM, an address input from the outside and converted by the MMU and a command detected by ATD are sent to A # CONT. A # CONT determines that access is executed to the DRAM from the address and command sent, and instructs COM # GEN to issue a command to the DRAM. A # CONT converts the address received from the MMU into a DRAM row address and a column address, and outputs them to the DRAM in charge of access of the two DRAMs. COM # GEN issues a command to the DRAM in charge of access in the same way as the address in synchronization with the clock generated by CLK # GEN. The DRAM receiving the command and address outputs data, and the output data is transferred to I / O0 to I / O15 via the R / W BUFFER, and the read access is completed. When performing write access to the DRAM, an address input from the outside and converted by the MMU, a command detected by the ATD, and a command and data detected by the DTD are sent to the A # CONT. A # CONT determines that access is to be executed to DRAM from the address and command sent, and instructs COM # GEN to issue a command to DRAM. A # CONT converts the address received from the MMU for DRAM, and outputs it to the DRAM in charge of access of the two DRAMs. COM # GEN issues a command to the DRAM in charge of access in the same way as the address in synchronization with the clock generated by CLK # GEN. The data to be written is input from I / O0 to I / O15, temporarily held in the R / W BUFFER, and then sent to the DRAM in charge of access for writing. The data to be written and its address are once held in the FIFO, and are written in the other DRAM after the refresh is completed. When the memory module is used at a high temperature, the refresh interval of the DRAM may be shortened and frequently refreshed. Therefore, in this memory module, the temperature measurement module (TMP) measures the temperature and notifies the refresh counter and the access controller. When the temperature becomes high, the refresh counter changes the refresh interval short and outputs a refresh address. Conversely, if the refresh interval of the DRAM is changed to be longer at low temperatures, the data holding current can be reduced. Even in such a case, the temperature measurement module (TMP) measures the temperature and notifies the refresh counter and the access controller. When the temperature becomes low, the refresh counter changes the refresh interval longer and outputs a refresh address.

In some cases, a device in which a memory module is mounted may want to reduce current consumption according to the operating state. Therefore, description of power supply control for explaining a method of reducing power consumption by changing an operation state of a memory by a power module.

  First, the simplest one is that the power module stops the refresh performed by the refresh counter in accordance with the command signal PS. As a result, the data stored in the DRAM is destroyed, but the power required for the refresh can be reduced.

  To further reduce power consumption, the power supplied to the DRAM is cut off inside the memory module. In this case, the power module stops supplying power to D1-VCC and D2-VCC supplied to the DRAM according to the command signal PS output from the device. The power may be turned off for two DRAMs, or only one DRAM may be turned off.

  In addition, if it is desired to further reduce power consumption, the power module may stop supplying power to the portion of CHIP2 (SRAM + CTL # LOGIC) involved in memory access to the DRAM according to the command signal PS. In this state, for example, in CHIP2 (SRAM + CTL # LOGIC), in addition to the SRAM, it is possible to connect the power supply only to the MMU and AS to be in the operating state, and to set the mode in which only the SRAM is accessed.

  Further, it is possible to set the operation state in which only the SRAM data is held by the command PS. In this case, access to the memory is prohibited by disconnecting power other than the power supply (S-VCC, S-VSS) connected to the SRAM. In this state, the memory module holds the data stored in the SRAM.

  In order to operate the DRAM again after stopping the power supply to the DRAM and stopping the operation, it is necessary to initialize the DRAM in addition to restarting the power supply. Although the initialization method is general, in this memory module, the initial circuit (INT) instructs the access controller (A # CONT) the initialization procedure and the initialization is executed.

  Note that even if DRAM refresh is stopped, DRAM initialization is required to operate the DRAM again, but the initial circuit (INT) still instructs the access controller (A # CONT) the initialization procedure. Then initialization is executed.

  FIG. 37 shows an example of a memory map converted by the MMU. Any of these memory maps can be selected according to the values set in the registers in the MMU. Although not particularly limited in the present embodiment, a typical memory map will be described by taking as an example a memory module having a FLASH storage area of 256 + 8 Mb, an SRAM data holding area of 2 Mb, and a DRAM storage area of 256 Mb.

  FIG. 37 shows a memory map in which the memory management unit MMU converts the addresses into command registers REG, SRAM, Work area in DRAM, FLASH copy area in DRAM, and FLASH based on addresses A0 to A24 input from the outside. Each is selected and accessed by address.

  The command register REG in the control circuit (CTL # LOGIC) is externally supplied with an instruction code such as a load instruction, store instruction, MMU register change instruction, and power-off instruction, and a start address and an end address at the time of a load instruction or store instruction Is written.

  When a load instruction is written in the command register REG, the control circuit performs data transfer from FLASH to DRAM. In other words, writing is performed on the DRAM. When the store instruction is written, the control circuit transfers data from DRAM to FLASH. That is, the DRAM is read.

  Two DRAMs (CHIP3 and CHIP4) are mapped to the same address space and hold the same data. Each DRAM alternately repeats the period in which access is performed (WORK period) and the period in which refresh is prioritized (REF. Period). Memory access from the outside is executed for DRAM during the WORK period.

  In this example, the 2Mb SRAM area is set concentrated in the lower part of the address space. This area overlaps with the DRAM and is mapped in the memory space, but the DRAM is not accessed and only the SRAM is accessed.

  When the memory module power supply is controlled and only SRAM data is retained and used, the SRAM area can be centrally managed.

  The unaccessible DRAM area (SHADOW) can be used to relieve DRAM memory cells. The memory module has been devised to extend the refresh interval at low temperatures to reduce power consumption, but in that case, memory cells (Fail bit) that are difficult to hold data also occur. Therefore, the fail bit can be substituted by using the DRAM which becomes SHADOW. In Figure 37, the DRAM during the WORK period has Fail bit A and the DRAM during the REF. Period has Fail bit B, but these addresses are registered in advance, and if access is made to the Fail bit, Instead, each SHADOW is accessed instead. By replacing SHADOW, the fail bit is relieved, and a memory module with low power consumption can be realized by extending the refresh interval at low temperatures.

  FIG. 38 shows the principle of an access control method for concealing DRAM refresh. The operation of the DRAM according to the present invention can be explained by the concept that the access to the bank during the REF period is executed with priority.

  FIG. 35 (A) schematically shows access priorities. This figure shows that DRAM1 is in the WORK period and DRAM2 is in the REF. Period. In addition, CACHE that takes over access temporarily, FIFO that temporarily stores write data, refresh requests generated from RC, and DRAM access during load and store instructions are shown.

  DRAM1 is only accessed from outside during the WORK period. On the other hand, in the DRAM 2 during the REF period, refresh is first performed with the highest priority. Next, the data held in the FIFO is written. Next, the write data is written back to the DRAM by the load instruction held in the CACHE, and finally the DRAM access by the load instruction or the store instruction is executed. These operations are executed with the priority determined by the access control circuit (A # CONT).

  As for external access, one access is executed in 80 ns, but refresh and write back from FIFO, write access from CACHE, load, and store are executed in 70 ns. This memory module uses this time difference to conceal refresh from the outside.

  FIG. 38B shows a state in which read access is executed. The case where read access is continuously performed for DRAM1 during the WORK period is shown. In DRAM1, only external access is executed in 80 ns, data is read and access is completed. On the other hand, in DRAM2, the refresh is only executed in 70ns.

  The case where write access is performed is shown in FIG. Write access from the outside is first executed in DRAM1 during the WORK period. At the same time, the write data is once held in the FIFO. In the DRAM 2 during the REF period, refresh is first performed with the highest priority. Next, the data stored in the FIFO is written back.

  Here, the DRAM 1 during the WORK period requires 80 ns for one operation, whereas the DRAM 2 during the REF period completes one operation in 70 ns. Therefore, even if the DRAM 2 performs the refresh operation, the write operation is performed at a speed higher than that of the DRAM 1, so that all the data writing in the FIFO can be finished and catch up with the DRAM 1.

  FIG. 39 shows the concealment operation of the write and read access to the DRAM by the load and store instructions.

  FIG. 39 (A) shows the state of access to the DRAM when read access and write access are generated from the outside when read access to the DRAM by the store instruction is executed. An example is shown in which DRAM1 is in the WORK period and DRAM2 is in the REFRESH period. In DRAM1, only read access from the outside is executed in 80 ns. On the other hand, in DRAM2, read access to the DRAM by the store instruction is only executed in 70ns.

FIG. 39B shows a state of access to the DRAM when a write access is generated from the outside when the write access to the DRAM by the load instruction is being executed. In DRAM1, external write access is executed in 80 ns, and at the same time, write data is temporarily held in the FIFO. In the DRAM 2 during the REF period, write access to the DRAM by the load instruction is performed, and at the same time, the write data is held in the CACHE. Next, the data held in the FIFO is written. The data held in CACHE is written back to DRAM1 when DRAM1 enters the REFRESH period. Here, the DRAM 1 during the WORK period requires 80 ns for one operation, whereas the DRAM 2 during the REF period completes one operation in 70 ns. Therefore, even if the DRAM 2 performs the write operation by the load instruction, the write operation is performed at a speed higher than that of the DRAM 1, so that all the data writing in the FIFO can be finished and catch up with the DRAM 1.

  Figure 39 (C) shows the access to DRAM when write access from outside occurs when CACHE performs write access to DRAM when DRAM1 is changed during the REFRESH period and DRAM2 is changed during the WORK period. It shows the state of. In DRAM2, write access from the outside is executed in 80 ns, and at the same time, write data is temporarily held in the FIFO. In DRAM1 during the REF period, the write access from the CACHE to the DRAM is executed, and then the data held in the FIFO is written. Here, the DRAM 2 during the WORK period requires 80 ns for one operation, while the DRAM 1 during the REF period completes one operation in 70 ns. Therefore, even if the DRAM 1 performs a write operation from CACHE, the write operation is performed at a higher speed than the DRAM 2, so that all the data writing in the FIFO can be completed and catch up with the DRAM 2. In this way, internal access to the DRAM by load instructions and store instructions can be concealed and access can be executed from the outside.

  FIG. 40 shows how two DRAMs are operated in a time-sharing manner in order to conceal internal access to DRAMs by DRAM refresh, load instructions, and store instructions. FIG. 40 (A) shows an example of DRAM operation at 75 ° C. or lower, which is the normal operating temperature range. Two DRAMs (DRAM1 and DRAM2) alternately repeat the WORK period and the REF. Period. DRAM during the WORK period labeled WORK operates for external access. The first DRAM1 is in the WORK period and supports external access. On the other hand, the DRAM during the REF. Period gives priority to the refresh operation, and when external access is writing, data is written after refreshing is completed.

  DRAM memory cells usually need to be refreshed within 64 ms, but in the example shown, the WORK period and REF. Period are switched 8 times within this time, and DRAM 1 and DRAM 2 alternate with the WORK period and REF. The period is repeated 4 times.

  Here, T1 is the time required for refresh during one REF. Period of 8 ms, and T2 is the time required to write back the data accumulated in the FIFO as a result of the write access performed during that time. Next, it will be described that refresh, load-time write access, and write-back can be performed during the REF. Period as the time T3 during which the write access at the time of the load instruction is possible.

  Taking 256Mbit SDRAM as an example, the memory configuration is 8192 rows x 512 columns x 16 bits x 4 banks, and refreshing 32768 times (for 8192 rows x 4 banks) in 64 ms is sufficient. Therefore, in the example of Fig. 40 (A), there are 4 REF. Periods in 64 ms for one DRAM, so 8192 refreshes are performed in one REF. Period (8 ms). Become.

  Since the time required for one refresh is 70 ns, T1 = 70 ns × 8192 times = 0.574 ms. On the other hand, when the maximum value of the write access performed from the outside during 8 ms is obtained, it is 100,000 times (8 ms / 80 ns) assuming that every access is a write. The time T1 required to write this back to the DRAM during the REF. Period is 7 ms (70 ns x 100000 times). If write access is performed 4096 times during loading, the time required for write access during loading is T3 = 70 ns × 4096 times = 0.287 ms.

  Therefore, T1 + T2 + T3 = 7.861ms <8ms, and it can be seen that the write access and writeback by the refresh and load instructions can be sufficiently executed during the REF. Period. The refresh can also be executed simultaneously in a plurality of banks in the DRAM during the REF period. In this case, since the number of refreshes executed during the T1 period can be reduced, the T1 period can be shortened. If the T1 period is shortened, the memory capacity of the FIFO can be reduced, and a high-speed memory can be realized by shortening the interval of external access.

  FIG. 40B shows the case where the DRAM refresh interval is changed. In general, DRAM refresh characteristics deteriorate at high temperatures. Therefore, for example, when the refresh interval is shortened at a high temperature of 75 ° C. or higher, data can be retained, and operation can be performed in a wider temperature range. In this example, the refresh interval is shortened to 48 ms at high temperatures. T1 does not change, but if T2 is 5.25ms and T3 is 0.144ms, then T1 + T2 + T3 = 5.97ms <6ms, and refresh access and load write access and write back can be performed sufficiently during REF. Recognize.

  On the other hand, at low temperatures, the refresh interval can be shortened to reduce the data retention current. In the illustrated example, the refresh interval is doubled to 128 ms at low temperatures. In this case, the REF period is 16 ms. T1 does not change, but T2 is 14ms, T3 is 1.15ms, T1 + T2 + T3 = 15.8ms <16ms, and refresh and load write access and write back can be performed sufficiently during REF. Recognize.

  In this embodiment, the operation unit of the DRAM has been described for each chip. However, for example, a bank may be used as the operation unit according to the performance of the memory module and the configuration of the memory chip. In addition, the refresh interval of 64 ms is divided into 8 periods to be the WORK period and the REF period. However, if the data is further divided, the storage capacity of the FIFO holding data and addresses can be reduced. On the other hand, since the number of switching between the WORK period and the REF period can be reduced if it is divided largely, the control circuit accompanying the switching can be simplified.

  FIG. 41 is a diagram for explaining the function of CACHE. FIG. 41 (A) shows a case where a write access is performed from the outside immediately before switching between the WORK period and the REF. Period. Here, external access A is performed just before the end of the WORK period of DRAM1. In such a case, the WORK period of DRAM1 is extended by dT until the end of the write access. On the other hand, DRAM2 enters the WORK period as scheduled, and waits for the end of write access without writing write data. Data that has not been written to DRAM2 is temporarily held in CACHE. If access to the same address held in CACHE occurs during the WORK period, read / write is performed on CACHE instead of DRAM2. If the access is a write, the DRAM 1 during the REF. Period is written via the FIFO as usual. The data held in CACHE is written back in the next REF. Period after the DRAM2 WORK period ends. When this write back is completed, the contents of CACHE are cleared. If the access is a read, the WORK period of DRAM1 is only extended by dT until the end of the access.

  FIG. 41 (B) shows a case where one access is performed longer than the WORK period and the REF. Period, or when the extension period dT cannot cover it. External access B started when DRAM1 is started during the WORK period exceeds the extension time dT and continues to be accessed during the next REF. Period. In this case, access is handed over to CACHE, and DRAM 1 enters the REF. Period. DRAM2 enters the WORK period as planned and enters a standby state. In the case of read access, data is transferred from DRAM1 to CACHE. In the case of write access, when the continued access is completed, the data written in CACHE is written back to DRAM1 and DRAM2. Write back is performed when each DRAM enters the REF. Period. The contents of CACHE are cleared when both writebacks are completed. In this way, CACHE can be used to handle an access that extends over the WORK period and the REF. Period, or an access that exceeds one or more WORK periods.

  FIG. 42 shows an example of operation waveforms of the memory module according to the present invention. A0 to A20, S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE are signals that are input to the memory module, and are so-called asynchronous SRAM interface signals. . The data input / output signals I / O0 to I / O15 are represented as DIN and DOUT by dividing the data input and output, respectively. MMU, ATD, and DTD represent the output signals of the MMU circuit, ATD circuit, and CTD circuit, respectively. D1-CLK is a clock supplied to DRAM1, D1-COM is a generic name for command signals supplied to DRAM1, D1-A0 to D1-A15 are address signals supplied to DRAM1 of DRAM, D1-DQ0 to D1-DQ15 The DRAM I / O lines are the input / output data signals of DRAM1. D2-CLK is a clock supplied to DRAM2, D2-COM is a generic name for command signals supplied to DRAM2, D2-A0 to D2-A15 are address signals supplied to DRAM2 of DRAM, D2-DQ0 to D2-DQ15 The DRAM I / O line is the DRAM 2 input / output data signal.

  First, read access that is performed first will be described. When the addresses A0 to A24 are input, the MMU circuit outputs the converted address. The ATD circuit detects changes in addresses A0 to A24 and commands (S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE). When confirmed, a pulse is output. In response to this pulse, the bank active command A and the row address Ra, and then the read command R and the column address Co are issued to the DRAM 1 during the WORK period. Data read from the DRAM 1 is output to D-DQ0 to D-DQ15, and is output to I / O0 to I / O15 once through the R / W BUFFER. Further, the DRAM 2 during the REF. Period is refreshed by the bank active command A and the precharge command P. In the next cycle, an example of write access is shown. In the case of write access, the bank active command A and the row address Ra are issued to DRAM1 and DRAM2 in response to the fall of the ATD signal, as in read access. Since no refresh operation is performed during write access, the command and address are issued to both DRAM1 and DRAM2. After that, the CTD circuit detects changes in commands (S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE) and recognizes that it is a write operation. , Output a pulse. In response to this pulse, a write command W and a column command Co are issued to both DRAM1 and DRAM2 to execute writing.

  According to the embodiment described above, a large-capacity memory module using an inexpensive general-purpose DRAM can be realized while following the SRAM interface method. In the control circuit (CTL # LOGIC) according to the present invention, DRAM is used, but refresh required for DRAM is executed by the control circuit (CTL # LOGIC), so it can be used without considering refresh as in SRAM. I can do it. In addition, DRAM refresh and internal access can be hidden from the outside of the memory module by adjusting the timing of data retention and refresh in DRAM and the internal access to DRAM by load and store instructions, so this memory module There is no need to adjust the timing in consideration of refresh or internal access of DRAM when accessing. Therefore, since it can be used in the same manner as a memory module using only a conventional SRAM, a large-capacity memory module can be used without changing the conventional system. In addition, by reducing the refresh interval of the DRAM, the DRAM can be operated even at high temperatures, and a memory module with a wide operating temperature range can be realized. On the other hand, by increasing the DRAM refresh interval at low temperatures, the power required for data retention can be reduced, and a memory module with low data retention power can be realized. Depending on the function of the power module PM, the power supply for part or all of the DRAM can be stopped to limit the storage area and reduce the power required for data retention. Furthermore, the power supply of the control circuit is also stopped, and a memory module with less data holding power can be realized. In such a case, since the storage area for holding data can be freely set by the MMU, it can be used widely corresponding to various devices.

<Example 5>
FIG. 43 shows a fourth embodiment of the memory module according to the present invention. FIG. 43A shows a top view and FIG. 43B shows a cross-sectional view. This memory module is mounted on a board (e.g., printed circuit board PCB made of glass epoxy board) by ball grid array (BGA), CHIP1 (FLASH), CHIP2 (SRAM + CTL # LOGIC), CHIP3 (DRAM1) and CHIP4 (DRAM2) is installed. Although not limited in particular, CHIP3 and CHIP4 use a general-purpose DRAM bare chip in which signal and power supply pad rows are arranged in a row at the center of a so-called chip. Further, although not particularly limited, the CHIP1 uses a so-called FLASH general-purpose bare chip in which one row of signal and power supply pads is arranged at one end of the chip.

  CHIP1 and the bonding pad on the substrate are connected by a bonding wire (PATH2), and CHIP2 and the bonding pad on the substrate are connected by a bonding wire (PATH3). CHIP3 and CHIP4 are connected to CHIP2 by a bonding wire (PATH1). Connected to CHIP1 and CHIP2 with bonding wire (PATH4). Resin molding is performed on the upper surface of the substrate on which the chip is mounted to protect each chip and connection wiring. Further, a metal, ceramic, or resin cover (COVER) may be used from above.

  In the embodiment according to the present invention, since the bare chip is directly mounted on the printed circuit board PCB, a memory module having a small mounting area can be configured. Further, since the chips can be arranged close to each other, the interchip wiring length can be shortened. By unifying the wiring between chips and the wiring between each chip and the substrate by a bonding wire system, a memory module can be manufactured with a small number of processes. Further, by directly connecting the chips with bonding wires, the number of bonding pads and bonding wires on the substrate can be reduced, and the memory module can be manufactured with a small number of processes. Since a general-purpose DRAM bare chip mass-produced in large quantities can be used, a memory module can be stably supplied at low cost. When a resin cover is used, a stronger memory module can be configured. When a ceramic or metal cover is used, a memory module excellent in heat dissipation and shielding effect can be configured in addition to strength.

  FIG. 44 shows a modification of the memory module in FIG. 43 according to the present invention. FIG. 44A shows a top view and FIG. 44B shows a cross-sectional view. In this example, CHIP2 (SRAM + CTL # LOGIC) is mounted on CHIP3 and CHIP4. PATH5 is used for wiring to CHIP2 and CHIP3 or CHIP4. CHIP1 and the bonding pad on the substrate are connected by a bonding wire (PATH2), and CHIP2 and the bonding pad on the substrate are connected by a bonding wire (PATH3). Connected to CHIP1 and CHIP2 with bonding wire (PATH4).

  This mounting method can reduce the area of the printed circuit board PCB. In addition, since the wiring length can be shortened by the wiring PATH1 between the stacked chips, the reliability of the wiring can be improved and noise radiation to the outside can be reduced.

<Example 6>
FIG. 45 shows an embodiment of a cellular phone using a memory module according to the present invention. The mobile phone includes an antenna ANT, a radio block RF, a baseband block BB, an audio codec block SP, a speaker SK, a microphone MK, a processor CPU, a liquid crystal display LCD, a keyboard KEY, and the memory module MEM of the present invention.

  The operation during a call will be described. The sound received through the antenna ANT is amplified by the radio block and input to the baseband block BB. The baseband block BB converts an audio analog signal into a digital signal, performs error correction and decoding processing, and outputs it to the audio codec block SP. When the audio codec block converts the digital signal into an analog signal and outputs it to the speaker SK, the other party's voice can be heard from the speaker.

  An operation when a series of operations of accessing a homepage on the Internet from a mobile phone, downloading music data, listening to it, and storing the music data downloaded last will be described. The memory module MEM stores basic programs and application programs (email, web browser, music playback, game, etc.). When the activation of the Web browser is instructed from the keyboard, the Web browser program stored in the FLASH in the memory module MEM is transferred to the DRAM in the same memory module. When the transfer to the DRAM ends, the processor CPU executes the Web browser program in the DRAM, and the Web browser is displayed on the liquid crystal display LCD. When the user accesses a desired home page and instructs the user to download his / her favorite music data from the keyboard, the music data is received through the antenna ANT, amplified by the radio block, and input to the baseband block BB. The baseband block BB converts music data that is an analog signal into a digital signal, and performs error correction and decoding processing. Finally, the digital music data is temporarily stored in the DRAM of the memory module MEM and transferred to the FLASH. Next, when the keyboard KEY instructs to start the music playback program, the music playback program stored in the FLASH in the memory module MEM is transferred to the DRAM in the same memory module. When the transfer to the DRAM is completed, the processor CPU executes the sound reproduction program in the DRAM, and the music reproduction program is displayed on the liquid crystal display LCD. When an instruction to listen to music data downloaded to the DRAM is given from the keyboard, the processor CPU executes the music playback program, processes the music data stored in the DRAM, and finally hears music from the speaker SK. . At this time, since the memory module of the present invention uses a large-capacity DRAM, the Web browser and the music playback program are held in the DRAM, and both programs are simultaneously executed by the CPU. Furthermore, an e-mail program can be started, and the e-mail program and mail can be sent and received simultaneously. Even if the Web browser is stopped, it is retained in the DRAM in the memory module, so it can be started immediately upon restart. When a power-off instruction is input from the keyboard, the memory module operates only the SRAM, holds the minimum amount of data, and can significantly reduce power consumption.

  As described above, by using the memory module of the present invention, a large amount of mail, music playback, application programs, music data, still image data, moving image data, and the like can be stored, and a plurality of programs can be executed simultaneously.

  As described above, the effects obtained by the preferred embodiments of the present invention are as follows. By copying FLASH data to DRAM, the reading and writing speed of FLASH data can be made equivalent to SDRAM and SRAM.

It is a block diagram of the memory module to which this invention is applied. FIG. 2 is a block diagram showing an example of CHIP2 in FIG. It is explanatory drawing which shows an example of the address map of the memory module to which this invention is applied. It is explanatory drawing which shows an example of the address map of the memory module to which this invention is applied. It is a figure which shows an example of the operation | movement at the time of power activation of the memory module to which this invention is applied. It is a flowchart which shows the flow of the data transfer operation | movement from FLASH in the memory module of this invention to DRAM. It is a flowchart which shows the flow of the data transfer operation | movement from DRAM in the memory module of this invention to FLASH. 3 is a flowchart showing a flow of a read operation and a write operation to a DRAM in the memory module of the present invention. FIG. 3 is a diagram illustrating an example of an operation of a data update management circuit CPB illustrated in FIG. 2. 3 is a flowchart showing a flow of operation when power is shut down in the memory module of the present invention. FIG. 5 is a diagram illustrating an example of a DRAM operation according to a load instruction from the outside of a memory module. FIG. 5 is a diagram illustrating an example of a DRAM operation by a store instruction from the outside of a memory module. It is a figure which shows an example of the read-out operation | movement and write-in operation | movement to DRAM in the memory module of this invention. It is a figure which shows an example of the read-out operation from DRAM when the read-out operation to DRAM is generated from the outside, while the read-out operation to DRAM by the store instruction is performed. It is a block diagram which shows the example of 1 structure of FLASH shown by FIG. 16 is an example of a timing chart for reading data from the FLAH shown in FIG. It is the figure which showed one structural example of the memory module to which this invention is applied. FIG. 18 is a block diagram showing a configuration example of FLASH shown in FIG. FIG. 19 is an example of a timing chart for reading data from the FLAH shown in FIG. It is a block diagram which shows one structural example of DRAM. It is a block diagram of the memory module to which this invention is applied. FIG. 23 is a block diagram showing an example of CHIP2 in FIG. It is explanatory drawing which shows an example of the address map of the memory module to which this invention is applied. It is explanatory drawing which shows an example of the address map of the memory module to which this invention is applied. It is a figure which shows an example of the operation | movement at the time of power activation of the memory module to which this invention is applied. It is a figure which shows an example of the operation | movement at the time of power activation of the memory module to which this invention is applied. It is the figure which showed an example of the priority and operation | movement of access to the memory module of this invention. It is a figure showing an example of operation of DRAM by a load instruction and a store instruction from the outside of a memory module. It is a figure which shows an example of operation | movement of DRAM when access to DRAM arises from the outside, while access to DRAM by the load instruction and the store instruction is performed. It is an example of the timing chart of the memory module to which this invention is applied. It is an example of the timing chart of the memory module to which this invention is applied. It is a block diagram which shows one structural example of SRAM. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is a block diagram of the memory module to which this invention is applied. FIG. 36 is a block diagram showing an example of CHIP2 in FIG. It is explanatory drawing which shows an example of the address map of the memory module to which this invention is applied. It is a figure explaining a mode that it performs both access and refresh of DRAM from the outside. It is a figure explaining a mode that DRAM access from the outside and internal DRAM access are performed at the same time. It is a figure which shows an example of the refresh system of DRAM. It is a figure explaining a mode that access is taken over at the time of switching of a WORK period and a REF. Period. It is an example of the timing chart of the memory module to which this invention is applied. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is a figure which shows the structural example of the mobile telephone using the memory module by this invention.

Explanation of symbols

CHIP1… Non-volatile memory,
CHIP2 ... Semiconductor chip with integrated control circuit (CTL # LOGIC) or static random access memory (SRAM) and control circuit (CTL # LOGIC)
CHIP3… Dynamic random access memory (DRAM) or dynamic random access memory (DRAM1), CHIP4… Dynamic random access memory (DRAM2),
S-VCC ... CHIP2 power supply, S-VSS ... CHIP2 ground, PS ... Power control signal, L-VCC ... CHIP2 power supply,
L-VSS ... CHIP2 ground, CLK ... CHIP2 clock signal, CKE ... CHIP2 clock enable signal, /CS...CHIP2 chip select signal, /RAS...CHIP2 row address strobe signal, /CAS...CHIP2 column address strobe signal , /WE...CHIP2 write enable signal, DQMU / DQML ... CHIP2 input / output mask signal, WAIT ... CHIP wait signal, A0 to A15 ... CHIP2 address signal, D1-CLK ... CHIP3 clock signal, D1-CKE ... CHIP3 clock enable signal,
D1- / CS ... CHIP3 chip select signal,
D1- / RAS ... CHIP3 row address strobe signal,
D1- / CAS ... CHIP3 column address strobe signal,
D1- / WE ... CHIP3 write enable signal, D1-A0 to D1-A15 ... CHIP3 address signal, D1-DQMU / DQML ... CHIP3 input / output mask signal,
D1-DQ0 to D2-DQ15 ... CHIP3 data input / output,
D1-VCC ... CHIP3 power supply, D1-VSS ... CHIP3 ground,
D1-VCCQ ... CHIP3 I / O power supply,
D1-VSSQ ... CHIP3 I / O ground, F- / CE ... CHIP1 chip enable signal,
F- / OE… CHIP1 output enable signal, F- / WE… CHIP1 write enable signal,
F-SC ... CHIP1 serial clock signal, F- / RES ... CHIP1 reset signal, F-CDE ... CHIP1 command data enable signal, F-RDY / BUSY ... CHIP1 ready / busy signal, I / O0 to I / O7 ... CHIP1 input / output signal, COM # GEN ... command generator, INT ... initialization circuit, MMU ... memory management unit, CPB ... data update address management circuit, REG ... command register, A # CONT access controller,
PM ... Power management module,
R / W BUFFER ... Read / write buffer, CLKBUF ... Clock buffer, FGEN ... Flash control signal generation circuit, ECC ... Error correction circuit, REP ... Alternative processing circuit, FLASH Copy Area ... Flash data copy area, Work Area ... Work area, MD-Area ... Main data area, REP-Area ... Alternative area, Fail Area B ... Defective area B, Fail Area C ... Defective area C, A, As ... Active instruction, R, Rs ... Read instruction, W ... Write instruction, RR, R0, R1, RD, RT, RU ... Row address, RC, C0, C1, CD, CF, CT, CU, CR ... Column address, Ld ... Load instruction code, Sa ... Start address, Ea ... End address, P, Ps ... Precharge command, In ... Input data, O, Os ... Output data, St ... Store command code, B, BOs ... Bank address, C-BUF ... Control signal buffer, CTL ... Command controller, MUX ... Multiplexer, DI-BUF: Data input buffer Input data controller IDC ... Input data controller, SA-BUF ... Sector address buffer, X-DEC ... X decoder, MA ... Memory array, Y-CT ... Y address counter, Y-DEC ... Y decoder, YGATE / SENSE- AMP ... Y gate & sense amplifier circuit, DATA-REG ... data register, DO-BUF ... data output buffer, Rcode ... read instruction code, AD1, AD2, AD3 ... address, F- / CE ... chip enable signal, F- CLE ... Command latch enable signal, F-ALE ... Address latch enable signal, F- / WE ... Write enable signal, F- / RE ... Read enable signal, F- / WP ... Write protect signal, FR / B ... Ready / busy Signals, I / O0 to I / O7: Input / output signals are used for address input and data input / output. L-CONT ... Operation logic controller, CTL ... Control circuit, I / O-CONT ... Input / output control circuit, STREG ... Status register, ADREG ... Address register, COMREG ... Command register, RB ... Ready / busy circuit, VL-GEN ... High voltage generation circuit, ROW-BUF ... Row address buffer, ROW-DEC ... Row address decoder, COL-BUF ... Column buffer, COL-DEC ... Column decoder, DATA-REG ... Data register, SENSE-AMP ... Sense amplifier, MA ... Memory array, X-ADB ... X address buffer, REF.COUNTER ... Refresh counter, X-DEC ... X decoder, MA ... Memory array, Y-ADB ... Y address buffer, Y-AD COUNTER ... Y address counter, Y -DEC ... Y decoder, SENS AMP. & I / O BUS ... Sense amplifier circuit & Y gate, INPUT BUFFER ... Input data buffer circuit, OUTPUT BUFFER ... Output data buffer circuit, CONTROL LOGIC & TG ... Control circuit & timing Generator, S- / CE1, S-CE2 ... chip enable signal, S- / OE ... output enable signal, S- / WE ... write enable signal, S- / LB ... lower byte select signal, S- / UB ... Upper byte selection signal, AS ... Access switch circuit, SRAM ... Static random access memory,
ATD ... Ad Restaurant Detector,
CTD ... Command transition detector, TMP ... Temperature measurement module,
RC ... Refresh counter, X-DEC ... X decoder, MA (SRAM) ... Memory array, Y-GATE ... Y gate, Y-DEC ... Y decoder, D # CTL ... Input data control circuit, CONTROL LOGIC ... Control circuit, PCB ... printed circuit board, COVER ... module sealing cover,
PATH1… bonding wiring connecting CHIP1 and CHIP3 or CHIP4,
PATH2: Bonding wiring connecting PCB and CHIP1,
PATH3: Bonding wiring that connects PCB and CHIP2.
PATH4: Bonding wiring connecting CHIP1 and CHIP2,
PATH5 ... CHIP3 or CHIP4 and bonding wiring that connects CHIP3 and CHIP2 mounted on CHIP4,
FIFO ... First in first out (memory),
CACHE ... cache memory, SHADOW ... shadow area, WORK ... work period,
REF ... Refresh period, ANT ... Antenna, RF ... Wireless block, BB ... Baseband block, SP ... Audio codec block, SK ... Speaker, MK ... Microphone, CPU ... Processor, LCD ... Liquid crystal display, KEY ... Keyboard, MEM ... Memory module of the present invention

Claims (10)

Non-volatile memory;
Random access memory,
A control circuit for controlling the nonvolatile memory and the random access memory;
A command register in which the instruction code is written;
Multiple external command signal terminals;
A plurality of external address signal terminals;
A plurality of external data terminals,
When a load instruction code is written to the command register, the control circuit reads data from the nonvolatile memory, transfers the read data to the random access memory,
When a write command is input to the plurality of external command signal terminals, and an address for accessing the random access memory is input to the plurality of external address signals, the plurality of random access memories include the plurality of random access memories. Data input via the external data terminal is written,
When the write command is input to the plurality of external command signal terminals and an address for accessing the command register is input to the plurality of external address signal terminals, the plurality of external data terminals are connected to the command register. A memory module, wherein the load instruction code inputted via the memory module is written. In claim 1,
The memory module, wherein the command register is further written with a start address for starting transfer from the non-volatile memory via the plurality of external data terminals. In claim 2,
The memory module, wherein the command register is further written with an end address for terminating transfer from the nonvolatile memory via the plurality of external data terminals. In claim 1,
When an external access to the random access memory occurs while transferring data from the random access memory to the nonvolatile memory, the memory module has completed the data transfer. A memory module that outputs data from the random access memory according to the external access even if there is not. In claim 1,
When an external access to the random access memory occurs while transferring data from the random access memory to the non-volatile memory, the memory module stores data to the non-volatile memory. A memory module, wherein transfer is interrupted and data is read from the random access memory according to the external access. In claim 1,
Data read from the non-volatile memory is transferred to the random access memory via an ECC circuit. In claim 1,
The memory module, wherein the random access memory is a dynamic random access memory, and a capacity of the dynamic random access memory is larger than a capacity of the nonvolatile memory. In claim 1,
The memory module uses an SRAM interface. In claim 1,
When a store instruction code is written to the command register via the plurality of external data terminals, the control circuit reads data from the random access memory, and reads the read data to the nonvolatile memory A memory module, wherein the memory module is transferred to a memory. In claim 9,
A memory module, wherein when data is written to the nonvolatile memory from outside the memory module, the data is written to the nonvolatile memory via the random access memory.