JP2007241601A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up data transfer between respective cache memories corresponding to a plurality of processor cores in a multiprocessor system while suppressing increase in a hardware mounting cost as much as possible. <P>SOLUTION: The multiprocessor system comprises: the plurality of cache memories corresponding to the plurality of processor cores, respectively; and a direct memory access control means for directly controlling data transfer between the plurality of cache memories. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer method between caches in a multiprocessor system, and more specifically, data updated by one of processor cores constituting the multiprocessor system is transferred to another processor without going through a lower memory hierarchy. The present invention relates to a multiprocessor system that can directly transfer data to a core cache and reduce the latency of data movement and cache access.

A multiprocessor system that divides processing by a plurality of processors and executes the processing in parallel is widely used to realize high-speed processing. FIG. 18 is a block diagram showing a conventional example of such a multiprocessor system. In the figure, a plurality of processors 101 _a to 101 _d are provided on a chip 100, and each processor is connected to a main memory 105 by a bus 106. For 101 _d from the processor 101 _a, is provided with a 102 _d from the cache memory 102 _a, respectively.

  In the multiprocessor system as shown in FIG. 18, in order to improve the average performance of memory access, a distributed cache system in which a cache memory is provided for each processor is used. In such a distributed cache system, it is necessary to maintain data consistency so that inconsistency of data for the same address does not occur between each cache memory and the lower memory hierarchy.

FIG. 19 is an explanatory diagram of a first prior art of data transfer for maintaining data consistency in each memory in such a multiprocessor system. In the figure, data updated by a processor (core) on 101 _a, together with written into the cache memory 102 _a, generally written in lower memory hierarchy 105 by instructions of the program back. At the same time another processor (core), invalidation is instructed to the corresponding address of the data, for example, the cache memory 102 _b on 101 _b, data in the cache memory 102 _b is discarded. If it becomes necessary data processor 101 _b, by leading the latest update data from the lower memory hierarchy 105, consistency of data is ensured.

FIG. 20 is an example of a data transfer sequence in the first prior art. In FIG. 19, for example, after update data on the transfer source cache, that is, the cache memory 102 _a is transferred from the processor 101 _{a in} FIG. 19, that is, the data transfer source execution unit, to the lower memory hierarchy 105 as the lower memory hierarchy, The processing sequence will be described on the assumption that data transfer is performed to the transfer destination cache 102 _b provided corresponding to the processor 101 _b as the transfer destination execution unit.

First the source cache from the source execution unit, ie an instruction of updating the data transfer is issued to the cache memory 102 _a, is performed updating data transfer from the cache memory 102 _a to the lower memory hierarchy 105 as lower memory hierarchy. The source cache, i.e. also in the cache memory 102 _a, in response to the deactivation instruction data given to subsequently maintain the integrity of data in the memory system, disabling data. The transfer destination execution unit from the processor 101 _a as a former execution unit, i.e. the processor 101 _b, notification that the update data is stored in the lower memory hierarchy 105 is sent, transfer that requires that data The pre-execution unit, that is, the processor 101 _b makes a data request to the cache memory 102 _b as the transfer destination cache. At this time, the update data is not yet stored in the cache memory 102 _b , and the transfer destination cache the cache memory 102 _b perform move-in request for data to the lower memory hierarchy, receives the data sent back in response to the request, by further returns the data to the destination execution unit, use the update data There processing in the processor 101 _b has become possible.

However, in the first prior art, data updated in a certain processor core and stored in the corresponding cache memory is once written back to the lower memory hierarchy, and then the necessary processor core transfers the data from the lower memory hierarchy. It is necessary to read through the cache memory,
There is a problem that it takes a long time until the transfer destination execution unit that requires the update data actually acquires the data after the transfer source execution unit instructs the transfer of the update data.

FIG. 21 is an explanatory diagram of a second conventional example of a data transfer method for maintaining data consistency in a distributed cache system. When the data processor (core) on 101 _a cache memory 102 _a located in the drawing is updated, updated data written in the cache memory 102 _a is broadcast to all other processors, the data of the same address The stored data on the cache memory is updated. Such a cache control method is called a snoop cache.

FIG. 22 is an example of a transfer sequence of update data in the second prior art, that is, the snoop cache method. When the source cache, for example, data in the cache memory 102 _a is written in the figure, the cache memory, i.e. the transfer from the original cache, transfer destination cache by snooping process, that is, the data of the same address of all the other cache memory Is written to the cache memory in which the data is stored, and the processor corresponding to the transfer destination cache serving as the transfer destination execution unit is notified that the data has been written, and the transfer destination execution unit Data is requested from the transfer destination cache, and processing is performed using the returned data.

  However, the second prior art has a problem that the hardware mounting cost for broadcasting the update data is increased. In other words, since data is broadcast to the cache memory in which the data at the corresponding address is not stored, the memory access traffic increases, a wide bus is required, and each processor has a cache memory. In order to perform other processing while updating the above data, it is necessary to provide a random access memory having two ports, for example, which increases the cost of hardware.

In Patent Document 1, which discloses a technique for managing a cache with a software program in order to reduce the memory access waiting time in DMA transfer in such a multiprocessor system, data in the system memory is transferred to each processor. A method for providing a cache management command that enables software program management of a DMA cache provided to speed up the process is disclosed.
However, the prior art disclosed in Japanese Patent Laid-Open No. 2005-276199 is a technique for speeding up the transfer of data on the system memory to each processor, and the cache memory in the distributed cache memory system to which the present invention is directed. There is a problem that it cannot be applied to data transfer between each other.

  In view of the above-described problems, an object of the present invention is to speed up data transfer between cache memories respectively corresponding to a plurality of processor cores in a multiprocessor system while suppressing an increase in hardware implementation cost as much as possible. It is.

FIG. 1 is a block diagram showing the principle configuration of a multiprocessor system according to the present invention. In the figure, the multiprocessor system includes a plurality of processor cores 1 _a to 1 _d and direct memory access control means 3.

For 1 _d from each processor core 1 _a, provided with 2 _d from the corresponding cache memory 2 _a, the direct data transfer control unit 3 directly between each other 2 _d from the plurality of cache memories 2 _a It controls data transfer.

  The direct memory access control means 3 in FIG. 1 is, for example, a bus master, and the bus master transfers from the source processor core to the source processor core number, the destination processor core number, the storage start address of the transfer data in the cache memory, and the data In response to the transfer condition indicating the transfer amount and the transfer start instruction, read access is performed to the transfer source cache memory, transfer data, a flag, etc. are read in response to the cache hit response, and the transfer destination cache memory Write access is performed, and the transfer data and flags are written to the transfer destination cache memory.

  According to the present invention, in a multiprocessor system, it is possible to directly transfer data between cache memories corresponding to respective processor cores, the data transfer between cache memories is accelerated, and the entire multiprocessor system is This greatly contributes to improving data processing efficiency.

FIG. 2 is a block diagram showing the basic configuration of the multiprocessor system according to the present invention. In this figure, the system is composed of the same chip 10 and main memory 15 as in the conventional example of FIG. 18, and a plurality of processors (cores) 11 _a to 11 _d are mounted on the chip 10. Each processor is provided with cache memories _12a to _12d . In the present invention, without passing through the main memory 15 among these components added 12 from the cache memory 12 _a to _d, DMAC (direct memory access controller) 14 in order to transfer the data The processors 11 _a to 11 _d , the main memory 15, and the DMAC 14 are connected by a bus 16.

In the present invention, read and write data from the cache memory 12 _a for 12 _d respectively corresponding to 11 _d from the respective processor (core) 11 _a as shown in FIG. 2, that is, DMAC14 for controlling the transfer is established, data updated by a processor (core), for example, a cache memory on 12 _a by computation by 11 _a, the another processor under the control of the DMAC 14 (core), are transferred directly to the example 11 _b, the cache memory 12 _b Corresponding data is updated. In this case, the should any transfer to the processor is performed from any processor, for example, since should the operation result by the processor 11 _a is used in the computation by the processor 11 _b, it is designated by the overall processing of the program for the multiprocessor system The

FIG. 3 is an explanatory diagram of a method for reflecting the data update to the main memory in the basic configuration system of FIG. In a cache control method in a general multiprocessor system other than the snoop cache method described in FIG. 21, after the data update result is reflected in the main memory as described in FIG. 19, a plurality of cache memories, here Of 12 _a to 12 _d , control is performed so that only one cache memory holds valid data for an address corresponding to data in which data update is reflected on the main memory.

That is, in FIG. 3, updated data written to the cache memory 12 _a corresponding to the processor 11 _a in FIG. 2 is transferred to the processor 11 _b is written into the cache memory 12 _b, the update of the data is performed, The final update of the data in the main memory 15 is performed by transferring the data from the processor 11 _b to the main memory 15. At this time, if the update data in the cache memory 12 _a to the original data transfer source processor 11 _a is in the subsequent unusable is disabled, or the dirty bit is cleared as the update flag corresponding to the data by being, even if the processor 11 is _a the available such as other processors, the transfer to example 11 _c are unusable.

FIG. 4 is an explanatory diagram of direct data transfer by DMAC to a plurality of processor cores in the basic configuration system of FIG. In the figure, the write data that has been updated in the cache memory 12 _a is, for example, transferred by all the control of DMAC14 of the other three processors ₁₁ b, 11 _c, and 11 _d, 12 _d from the cache memory 12 _b The data at the corresponding address above can be updated. However, except for the above-described snoop cache system, only one of a plurality of transfer destination processors has the right to actually write data to the cache as valid data. Although the control is ensured by software, the control itself is not directly related to the present invention, and thus detailed description thereof is omitted.

FIG. 5 is a block diagram showing the configuration of the first embodiment of the multiprocessor system according to the present invention. System In this figure, the chip 20 and the lower memory hierarchy is constituted by, for example, a main memory 25, chip 20 21 _d from a plurality of processor cores 21 _a is on, provided with a bus master 24, 21 _d from the processor core 21 _a The bus master 24 and the lower memory hierarchy 25 are connected by a bus 26. And each processor core, for example, the processor core 21 _a is provided with an execution unit 22 _a and the cache memory 23 _a. The bus master 24 corresponds to, for example, the DMAC 14 in FIG.

5, for example, as a cache memory 23 _a is the source cache memory on the processor core 21 _a, the cache memory 23 _b as the transfer destination cache memory on the processor core 21 _b, charge transfer cache memory between the data directly Details of processing when data is transferred under the control of the bus master 24 will be described with reference to the flowcharts of FIGS.

FIG. 6 is a process flowchart of the bus master 24. The processing of the bus master 24 in figure is started for example in response to a data transfer request sent from the execution unit 22 _a on the processor core 21 _a. When the process is started, the transfer source core number at step S1, wherein the processor core 21 _a number of the regions in the cache memory 23 to be transferred _a, i.e. address and transfer data size, and the transfer destination of the core number , for example, the processor core 21 _b number Configuration result of, the source core, i.e. received from the processor core 21 _a, also start instruction transferred from the processor core 21 _a is received in step S2, corresponding to the read operation to The hour action is started.

The operation during the read operation, first, the source core in step S3, where the request for the read operation is issued to the execution unit 22 _a of the processor core 21 _a, the source core in response to the request in step S4 It is determined whether the cache response received from is a hit. In general, the cache response corresponding to the transfer request of the transfer source core is often a hit, and in this case, in step S5, the data and flags on the cache from the transfer source core, for example, the dirty flag as the above-mentioned updated flag are stored. The bit is read, and in step S6, the transfer source core is requested to invalidate the transfer data or to clear the dirty bit, and then the operation during the write operation is performed. Here, data indicating whether invalidation processing or dirty bit clear processing should be requested to the transfer source core is stored in a register (not shown) in the bus master, and the bus master performs any processing corresponding to the data. It shall be requested to the transfer source core.

The operation at the time of the write operation, first, the destination core in step S8, the processor core 21 _b in this case, a request for a write operation to the cache memory 23 _b of the data is issued, to the destination core in step S9 The write data and the flag are transferred, and it is determined in step S10 whether or not all the transfer of the data to be transferred has been completed. In general, when a large amount of data is transferred, the transferred data is divided into small data amount units, and data is read and transferred for each unit. If the transfer of all data has not been completed, the processes after step S3 are repeated.

If the transfer of all data has been completed, the source core in step S11, where the notification is completed data transfer to 21 _a, also the destination core in step S12, i.e., data transfer to 21 _b Is notified, and the process ends. As will be described later, this data transfer completion notification is not sent from the bus master 24 but from, for example, the execution unit 22 _b of the processor core 21 _b as the data transfer destination execution unit, for example, to the transfer source core 21 _a . In this case, the process in step S11 is omitted. Here, the fact that the processing of steps S11 and S12 can be omitted is indicated by adding parentheses to the whole. Whether or not the bus master should notify the completion of data transfer is specified by data stored in a register (not shown) in the bus master as described above.

If the cache response of the transfer source core is not a hit in step S4 in the operation during the read operation, the processing from step S14 is performed. While the foregoing is a cache response corresponding to receiving the data transfer request from the transfer source core as it should be hit basically the address where the data to be transferred in the cache memory 23 _a is stored data, the processing subsequent processor core 21 _a, it is determined that the reference locality is low, since it may also occur that they've been written back to the lower memory hierarchy, such as a main memory, the hit cache response It is also possible to make a mistake.

  When the cache response is a miss as described above, it is determined in step S14 whether or not data to be transferred is to be acquired from the lower memory hierarchy, for example, the main memory. Whether or not data should be acquired is specified in the setting by the transfer source core in step S1, for example. When data is to be acquired from the main memory, a read operation is performed on the lower memory hierarchy in step S15, read data is received in step S16, and the processing after step S8 as an operation at the time of the write operation is continued. The

If it is determined that it should not get the data from the lower memory hierarchy in the case of a cache miss in the step S14, the data transfer is interrupted at step S17, an error is notified transfer source core step S18, that is, the processor core 21 _a To finish the process. Note that the processing in step S18 can also be omitted.

FIG. 7 is a flowchart of processing on the transfer source cache side, here, on the cache memory _23a side. This process execution unit 22 _a processor core 21 _a is a flowchart of a process performed as the source execution unit. When the process is started in the figure, a data read operation request is received from the bus master 24 in step S21. This corresponds to the process of step S3 in FIG. In step S22, it is checked whether the accepted address exists in the cache. In step S23, it is determined whether the access address has a cache hit.

  If there is a cache hit, a hit response is returned to the bus master 24 in step S24, the data and flag at the corresponding address are returned to the bus master 24 in step S25, and the cache line is invalidated or dirty in step S26. The bit is cleared and the process ends. For example, in the case of snoop cache control, the process of step S26 is omitted. If it is determined in step S23 that there is no cache hit, a cache miss response is sent to the bus master 24 in step S27, and the process is terminated.

8, the transfer destination cache side, where a flow chart of the processing in the cache memory 23 _b side of the processor core 21 _b. When the processing is started in the figure, first, a write operation request from the bus master 24 is accepted in step S31. This corresponds to the process of step S8 in FIG. In step S32, it is checked whether the received address exists in the cache. In step S33, it is determined whether the access address has a cache hit.

  If there is a hit, the data and flag sent from the bus master 24 in step S34 are written in the cache, and the process is terminated. If it is not a cache hit, it is determined in step S35 whether or not there is an empty entry in the cache. If there is an empty entry, data and a flag are written in the empty entry in step S34, and the process is terminated. If there is no empty entry, copy back processing is performed in the main memory in step S36 to create an empty entry, data and a flag are written in the empty entry in step S34, and the process is terminated. Note that the processes in steps S35 and S36 are processes not directly related to the present invention.

The data transfer process in the first embodiment is basically performed in accordance with the flowcharts of FIGS. 6 to 8, but an example of the data transfer sequence in the first embodiment will be described with reference to FIGS. explain. The source execution unit 9, for example, to the bus master 24 from the processor core 21 _a of the execution unit 22 _a, is given an instruction instructing the start Transfer Conditions. This operation corresponds to the processing of steps S1 and S2 in FIG. The bus master 24 performs _a data read operation on the transfer source cache, here, the cache memory 23a, receives a cache hit response from the transfer source cache side, and receives read data and a flag. The bus master 24 is the destination cache, for example, as a data write operation to the cache memory 23 _b, and transfers the write data, and a flag. On the other hand, in the transfer source cache, that is, the cache memory _23a , for example, the transferred data is invalidated.

  FIG. 10 is an operation sequence in the case of a cache miss at the transfer source. As in FIG. 9, a transfer condition instruction and a transfer start instruction are given from the transfer source execution unit to the bus master 24, and a data read operation is performed from the bus master 24 to the transfer source cache side, but a cache miss response is returned. Therefore, the data transfer is interrupted. These operations correspond to the processing of steps S14 and S17 in FIG. 6 and correspond to the case where data is not acquired from the lower memory hierarchy.

  FIG. 11 shows an operation sequence when data is read from the lower memory hierarchy, for example, the main memory, when a cache miss response is returned to the bus master 24. As in FIG. 10, when the bus master 24 receives a cache miss response from the transfer source cache, corresponding to steps S15 and S16 in FIG. 6, performs a data read operation on the lower memory hierarchy and receives read data. Writes data and flags as a write operation to the transfer destination cache. For example, the transfer destination cache notifies the transfer source execution unit of the completion of data transfer. As described above, this data transfer completion notification can be sent from the bus master to the transfer source execution unit. However, when the bus master performs the notification, the data transfer is not actually completed at that time. It is also possible to perform a more reliable operation by notifying the completion of transfer from the transfer destination cache to which the data and flag are actually transferred.

FIG. 12 is a sequence of data transfer operations for a plurality of cache memories. As in FIG. 9, when the read data and the flag is provided to the bus master 24 from the source cache, transfer destination cache 1 from the bus master 24, and the transfer destination cache 2, for example, writes to the cache memory 23 _b and 23 _c Data and flags are written as operations. For example, data is invalidated on the transfer source cache, that is, the cache memory _23a side.

  FIG. 13 is a block diagram showing the configuration of the second embodiment of the multiprocessor system. Comparing this figure with the first embodiment of FIG. 5, in place of the bus 26 in FIG. 5, a dedicated bus 27 for direct data transfer between the cache memories by the bus master 24, and each cache memory and lower memory hierarchy 25 For example, the only difference is that the bus 28 for connecting the main memory is separated.

  The second embodiment of FIG. 13 differs from the first embodiment in that a dedicated bus 27 for data transfer by the bus master 24 between the cache memories is provided unlike the first embodiment as described above. However, the processing on the bus master 24 and each cache memory side is the same as in the first embodiment, and the description thereof is omitted.

  14 and 15 show examples of data transfer sequences in the second embodiment. In FIG. 14, as in FIG. 9, for example, data and flags are written from the bus master 24 to the transfer destination cache as a write operation, and unnecessary lines are discharged from the transfer destination cache to the lower memory hierarchy 25. In addition, the transfer source execution unit is notified of the completion of data transfer. Of these, unnecessary line discharge corresponds to, for example, that there is no empty entry in the cache in step S35 of FIG. 8, and that in step S36 the data of unnecessary lines is exported to the main memory as the lower memory hierarchy 25 as copy back processing. To do. This unnecessary line discharge is performed using a bus 28 that connects each cache memory and the lower memory hierarchy 25. The data transfer completion notification from the transfer destination cache to the transfer source execution unit is the same as in FIG.

  FIG. 15 shows an operation sequence when a data transfer completion notification is sent from the transfer destination cache to the transfer destination execution unit. Unlike FIG. 14, a data transfer completion notification is sent from the transfer destination cache to the transfer destination execution unit. The transfer destination execution unit can surely know that the data transfer by the bus master 24 has been completed by notification from the transfer destination cache. If necessary, the transfer destination execution unit stores data necessary for the subsequent processing in the transfer destination cache. The processing is executed using the requested and returned data.

  FIG. 16 is an explanatory diagram for comparing the prior art described in FIG. 19 and FIG. 21 with the present invention. In the figure, the performance is basically determined by the cache access latency and the latency for data movement.

  FIG. 17 is an explanatory diagram of cache access latency and latency for data movement. This figure corresponds to the operation sequence of FIG. 15, and only the point that a data transfer completion notification is also sent from the transfer destination cache to the transfer source execution unit is added. The latency associated with data movement refers to the fact that transfer data is actually written to the transfer destination cache after the transfer instruction from the transfer source execution unit is given to the bus master 24, that is, the transfer condition instruction and the transfer start instruction. This is the time until the transfer completion notification is sent from the cache to the transfer destination execution unit and the transfer source execution unit. The cache access latency is, for example, after the data transfer is completed, This corresponds to the time from requesting data to receiving transfer data.

  In FIG. 16, the first prior art does not include a DMAC as in the present invention, and the hardware implementation cost can be reduced. However, when the transfer destination execution unit needs data after the data transfer, the data is transferred. In order to make a request to the lower memory hierarchy, that is, the main memory and receive the transfer data, the cache access latency is increased, and as a result, the performance is decreased.

  On the other hand, in the second prior art, by using the snoop cache, the latency for data movement is reduced and the performance is increased, but the hardware implementation cost for broadcasting is increased.

  On the other hand, in the present invention, there is a demerit that the hardware mounting cost is slightly increased because the DMAC has to be added, but the latency for data movement and the cache access latency are reduced, and the performance is improved.

  Particularly in the second embodiment, the bus for direct data transfer between the cache memories is provided independently of the bus connecting the main memory and the cache memory. For example, even if the number of processor cores increases, the memory bus Traffic can be kept small, and a large performance can be obtained.

  That is, in the present invention, the data transfer between the cache memories does not go through the main memory as compared with the prior art, so the bus bandwidth with the main memory is not consumed, and compared with the snoop cache, For example, since data transfer is performed only between cache memories specified by a program, bus traffic is minimized, and a practical operation can be maintained even if the number of processor cores increases. Furthermore, since the transfer destination processor core accesses the cache when data is needed and does not need to access the main memory, it can receive the necessary data with a small cache access latency.

1 is a block diagram showing the principle configuration of a multiprocessor system according to the present invention. It is a basic composition block diagram of the multiprocessor system of the present invention. It is explanatory drawing of reflection to the main memory of the data update result in FIG. It is explanatory drawing of the data direct transfer to the some cache memory in FIG. 1 is a configuration block diagram of a first embodiment of a multiprocessor system. FIG. It is a detailed flowchart of the process by a bus master. It is a detailed flowchart of the process in the transfer source cache side. It is a detailed flowchart of the process in the transfer destination cache side. It is an example (the 1) of the data transfer sequence in a 1st Example. It is an example (the 2) of the data transfer sequence in a 1st Example. It is an example (the 3) of the data transfer sequence in a 1st Example. It is an example (the 4) of the data transfer sequence in a 1st Example. It is a block diagram of the configuration of the second embodiment of the multiprocessor system. It is an example (the 1) of the data transfer sequence in a 2nd Example. It is an example (the 2) of the data transfer sequence in a 2nd Example. It is explanatory drawing of the comparison with this invention and a prior art. It is explanatory drawing of the latency concerning data movement as a data transfer performance, and cache access latency. It is a configuration block diagram of a conventional example of a multiprocessor system. It is explanatory drawing of the 1st prior art of data transfer. It is explanatory drawing of the data transfer sequence by 1st prior art. It is explanatory drawing of the 2nd prior art of data transfer. It is explanatory drawing of the data transfer sequence in a 2nd prior art.

Explanation of symbols

1, 21 Processor core 2, 12, 23 Cache memory 3 Direct memory access control means 10, 20 Chip 11 Processor 14 Direct memory access controller (DMAC)
15 Main memory 16, 26 Bus 22 Execution unit 24 Bus master 25 Lower memory hierarchy 27 Direct data transfer bus between cache memories 28 Bus between cache memory and lower memory hierarchy

Claims (5)

A multiprocessor system comprising a plurality of processor cores,
A plurality of cache memories respectively corresponding to the plurality of processor cores;
And a direct memory access control means for controlling direct data transfer among the plurality of cache memories. The direct memory access control means should invalidate the output data on the data transfer source cache memory after the transfer data is output from the data transfer source cache memory, or clear the updated flag for the data A register for storing data indicating whether or not
The memory access control means requests the data transfer source cache to invalidate the output data or clear the updated flag for the data corresponding to the stored contents of the register. Item 4. The multiprocessor system according to Item 1. Whether the direct memory access control means should notify the data transfer source processor core or the transfer destination processor core of completion of data transfer from the data transfer source cache memory to the data transfer destination cache memory A register for storing data indicating
Corresponding to the stored contents of the register, the direct memory access control means notifies the transfer source processor core or the transfer destination processor core of the completion of data transfer when the data write access to the transfer destination cache memory is completed. The multiprocessor system according to claim 1, wherein:   2. The direct memory access control means suspends all data transfer processing when receiving a cache miss response from the transfer source cache memory during data read access to the data transfer source cache memory. The described multiprocessor system.   When the direct memory access control means receives a cache miss response from the transfer source cache memory at the time of data read access to the data transfer source cache memory, the direct memory access control means reads the data to be transferred from the lower memory hierarchy, The multiprocessor system according to claim 1, wherein the read data is transferred to the computer.

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