JP2007240390A - Inspection method and device for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the increase of the area of the semiconductor integrated circuit at a minimum by largely simplifying a comparator when using BIST technology at inspection, and to eliminate change operation in an inspection facility outside the semiconductor integrated circuit, with the changes in an objective circuit to be inspected. <P>SOLUTION: Even when an additional bit string 321 is incorporated into an inspection response bit string 312 outputted by the objective circuit 310 and a first inspection response bit string 310 is changed with changes in the circuit 310, properly selecting the additional bit string 321 enables keeping the expected value 341 of a compression signature at a fixed value. Thus, the configuration of an acceptance determination section 340 including the expected value comparison circuit can be simplified, to suppress the increase of the area. When the expected value comparison is performed at the outside of the semiconductor integrated circuit, changes in an inspection program becomes unnecessary, since the expected value is invariable. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit inspection method and a semiconductor integrated circuit inspection apparatus using BIST technology.

  Conventionally, a semiconductor integrated circuit is generally inspected using a dedicated inspection facility such as an LSI tester. That is, the inspection bit string stored in the storage device in the inspection facility is supplied to the semiconductor integrated circuit, and the inspection response bit string output from the semiconductor integrated circuit in response to the inspection bit string and the expected value stored in the storage device in the inspection facility In comparison, pass / fail judgment is performed. In addition, for a read-only storage device mounted on a semiconductor integrated circuit, a read address is supplied as a check bit string, storage data is output as a check response bit string, and all data is compared with an expected value to read-only storage device The pass / fail judgment is performed.

  In recent years, with the progress of miniaturization of semiconductor manufacturing processes, the degree of semiconductor circuit integration has been improved year by year. In a large-scale semiconductor integrated circuit, the expected value of the inspection bit string and inspection response bit string necessary for the inspection becomes long, and the capacity required for the storage device of the inspection facility for storing this is greatly increased. Increases the cost of equipment. At the same time, the time required for the inspection has been greatly increased, and the inspection cost has occupied a large proportion of the total cost of the semiconductor integrated circuit.

One technique for improving the above situation is a built-in self-test (BIST) technique.
In BIST, since the expected values of the inspection bit string and the inspection response bit string are mounted on the semiconductor integrated circuit, it is not necessary to increase the capacity of the storage device in the inspection facility.

  Further, the exchange of signals between the inspection facility and the semiconductor integrated circuit is limited to a very small number such as the start of the self-inspection operation and the confirmation of the inspection result. Accordingly, a plurality of semiconductor integrated circuits can be measured simultaneously even in an inspection facility that does not handle many signal lines, leading to a reduction in inspection facility costs and a substantial reduction in inspection time.

  Regarding BIST technology for read-only storage devices, it is generally difficult to generate the expected value of all data read from the read-only storage device with a simple circuit. A compression signature or the like for the data is calculated, and a pass / fail judgment is performed by comparing only the same remaining signature with an expected value (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

Hereinafter, the BIST technique of the conventional read-only storage device will be described with reference to FIGS.
FIG. 12 is a diagram illustrating a configuration example of a BIST in a conventional read-only storage device, and FIG. 13 is a diagram illustrating a process of calculating an expected value of a compression signature for a conventional test response bit string.

In FIG. 12, a test bit string supply unit 1200, a test target circuit 1210, a compression signature calculation unit 1230, and a pass / fail judgment unit 1240 are included.
The inspection bit string supply unit 1200 generates a read address signal 1201 as the inspection bit string 1201 and supplies the read address signal 1201 to the inspection target circuit 1210.

The inspection target circuit 1210 has 4-bit width data “0100”, “1011”, “1001”, “0010”.
Is stored in the ROM module, and the stored data is output in accordance with the read address signal. Here, the read address signal assumes that all addresses of the circuit under test 1210 transition in ascending order, and the stored data is read according to this order. Thus, the read data 1211 is arranged in the same order as “0100 1011 1001 0010”.
The test response bit string 1212 is configured.

The compression signature calculation unit 1230 calculates a compression signature for the inspection response bit string 1212. Hereinafter, the compression signature will be briefly described.
The inspection response bit string 1212 is expressed as a polynomial of x. If this is F (x), the result is as follows.

F (x) = x ¹⁴ + x ¹¹ + x ⁹ + x ⁸ + x ⁷ + x ⁴ + x
Here, the multiplier ^k of xk represents the number of bits in the inspection response bit string 1212. Here, the inspection response bit string 1212 is 16 bits, so k is 0-15. coefficient of x ^k is the value of each bit of the test response bit sequence 1212.

Next, a polynomial representing the characteristics of the compressed signature calculation unit 1230 is P (x), where P (x) = x ⁴ + x + 1
Shall be used.

When R (x) is a polynomial representation of the compression signature, R (x) is F (x) = Q (x) P (x) + R (x)
It is obtained as a part corresponding to the remainder in the division format. Here, Q (x) is a polynomial of x.

  R (x) is obtained by performing writing as shown in FIG. However, the operation used here is based on modulo 2, and addition, subtraction, and multiplication are defined as follows.

Addition: 0 + 0 = 0
0 + 1 = 1 + 0 = 1
1 + 1 = 0
Subtraction: 0-0 = 0
0-1 = 1-0 = 1
1-1 = 0
Multiplication: 0 · 0 = 0
0 · 1 = 1 · 0 = 0
1 ・ 1 = 1
The result of the calculation is x ¹⁴ + x ¹¹ + x ⁹ + x ⁸ + x ⁷ + x ⁴ + x
= (X ¹⁰ + x ⁶ + x ⁵ + x ⁴ ) (x ⁴ + x + 1) + x
And R (x) is as follows.

R (x) = 0x ³ + 0x ² + 1x + 0
The bit string “0010” obtained by this calculation is separately stored as the expected value 1241 of the compressed signature.

  The compression signature calculation unit 1230 realizes the above division by circuit operation. The circuit configuration is called a linear feedback shift register (LFSR). As shown in FIG. 12, two exclusive ORs (XOR) are included in the shift register configuration by four flip-flops FF3 to FF0. : EXclusive OR) circuit is inserted. As the circuit operation, the operation starts from a state in which all flip-flops are 0 as an initial state, and the state changes as the test response bit string 1212 is input bit by bit from the head. The state after the last bit of the test response bit string 1212 is input, that is, the value stored in the four flip-flops FF3 to FF0 is the compression signature 1231.

  The pass / fail judgment unit 1240 compares the compressed signature 1231 output from the compressed signature calculation unit 1230 and the expected value 1241 of the compressed signature for each bit, and outputs “pass” as the pass / fail judgment result 1242 when all bits match. . If there is a mismatch, “fail” is output as the pass / fail judgment result 1242.

In some cases, the pass / fail judgment unit 1240 and the expected value 1241 of the compression signature are not mounted on the semiconductor integrated circuit, and the compression signature 1231 of the compression signature calculation unit 1230 is output from an external terminal of the semiconductor integrated circuit. In this case, the expected value 1241 of the compressed signature is stored in the storage device of the inspection facility outside the semiconductor integrated circuit, and the inspection facility also plays the role of the pass / fail judgment unit 1240.
JP 2000-322329 A JP 2001-222444 A JP 2004-304192 A

  However, in the BIST configuration of the conventional read-only storage device shown in FIG. 12, since the expected value 1241 of the compressed signature depends on the contents of the test response bit string 1212, the contents of the expected value 1241 of the compressed signature are changed by changing the test target circuit 1210. There will also be changes.

  When the inspection target circuit 1210 is a read-only storage device, the expected value 1241 also needs to be changed by changing the stored data. For this reason, normally, the pass / fail judgment unit 1240 has a large circuit configuration in order to enable comparison between arbitrary values, and there is a problem that the area of the semiconductor integrated circuit is increased.

  On the other hand, when the pass / fail judgment unit 1240 is not mounted on the semiconductor integrated circuit but is shared with the inspection facility outside the semiconductor integrated circuit together with the expected value 1241 of the compression signature, The expected value 1241 of the compressed signature stored in the storage device in the facility must be changed.

  When the inspection target circuit 1210 is a read-only storage device, the stored data changes relatively frequently, so that the operation of changing the expected value 1241 of the compressed signature on the inspection facility side becomes complicated. There was a problem.

  An object of the present invention is to solve the above-described problems, and in the inspection using the BIST technique, the comparator is greatly simplified to minimize the increase in the area of the semiconductor integrated circuit. It is an object of the present invention to provide a semiconductor integrated circuit inspection method and a semiconductor integrated circuit inspection apparatus which are limited to the above and do not require a change operation in an inspection facility outside the semiconductor integrated circuit due to the change of the inspection target circuit.

In order to achieve the above object, a method for inspecting a semiconductor integrated circuit according to claim 1 is a method for inspecting a semiconductor integrated circuit in which an inspection apparatus is used to inspect a circuit to be inspected on the semiconductor integrated circuit by self-inspection. A step of supplying a predetermined inspection bit string to the circuit to be inspected and outputting a first inspection response bit string; and a second inspection response by incorporating an additional bit string immediately after the first inspection response bit string A step of generating a bit string; a step of calculating a compression signature from the second inspection response bit string; and confirming a match between the value of the compression signature and an expected value of the compression signature, thereby determining whether the circuit to be inspected is good / not good A non-defective product determination step, and when the circuit to be inspected is a non-defective product, the additional value is set so that the expected value of the compression signature always remains a specific value. Characterized by selected according to Tsu preparative column to the value of the first test response bits.
According to a second aspect of the present invention, there is provided a method for inspecting a semiconductor integrated circuit according to the first aspect, wherein the circuit to be inspected is a read-only memory device.

  5. The semiconductor integrated circuit inspection method according to claim 3, wherein the inspection target circuit on the semiconductor integrated circuit is inspected by self-inspection using an inspection apparatus, and the semiconductor integrated circuit inspection method includes a plurality of the inspection target circuits. Connecting a series of output values obtained by supplying a predetermined test bit string to the output of the first test response bit string, and a plurality of serially connected locations including immediately after the first test response bit string A step of generating a second check response bit string by incorporating a corresponding additional bit string, and a compression signature for each unit by dividing the second check response bit string into units to be an additional bit string in which the last bit is embedded And calculating a match between each compression signature value and an expected value of the corresponding compression signature, And determining each of the additional bit strings so that an expected value of each compression signature always remains a specific value when each circuit to be inspected is a non-defective product. The selection is made according to the value of one inspection response bit string.

According to a fourth aspect of the present invention, there is provided a method for inspecting a semiconductor integrated circuit according to the third aspect, wherein the circuit to be inspected is a plurality of read-only storage devices.
The semiconductor integrated circuit inspection apparatus according to claim 5 is a semiconductor integrated circuit inspection apparatus that performs inspection of a circuit to be inspected on the semiconductor integrated circuit by self-inspection using the inspection apparatus, and generates an inspection bit string. A test bit string supply unit for outputting to the test target circuit; and a second test response bit string obtained by incorporating the additional bit string immediately after the first test response bit string generated by the test target circuit by inputting the test bit string. An additional bit string embedding unit that outputs, a compression signature calculation unit that calculates and outputs a compressed signature from the second check response bit string, and confirms a match between the value of the compressed signature and the expected value of the compressed signature A non-defective / non-defective determining unit for determining whether the circuit to be inspected is non-defective or defective. As expected value of Necha remains always a specific value, characterized in that it selected in accordance with the additional bit stream of the value of the first test response bits.

According to a sixth aspect of the present invention, there is provided the semiconductor integrated circuit inspection apparatus according to the fifth aspect, wherein the circuit to be inspected is a read-only storage device.
The semiconductor integrated circuit inspection apparatus according to claim 7 is a semiconductor integrated circuit inspection apparatus that performs inspection of a circuit to be inspected on the semiconductor integrated circuit by self-inspection using the inspection apparatus, and generates an inspection bit string. A test bit string supply unit that outputs to a plurality of the test target circuits; and immediately after a first test response bit string that is generated by connecting in series the output values of the test target circuits that are input and output the test bit strings. An additional bit string incorporation section for outputting a second inspection response bit string obtained by incorporating additional bit strings corresponding to a plurality of serially connected locations, and the second inspection divided into units such that the final bit becomes the additional bit string A compression signature calculation unit that calculates and outputs a compression signature for each unit with respect to the response bit string, and values of the respective compression signatures A non-defective / non-defective determining unit for determining whether the circuit to be inspected is good or not by confirming a match with an expected value of a corresponding compression signature. The additional bit string is selected according to the value of the first check response bit string so that the expected value of the compression signature always remains a specific value.

The semiconductor integrated circuit inspection apparatus according to claim 8 is the semiconductor integrated circuit inspection apparatus according to claim 7, wherein the circuit to be inspected is a plurality of read-only storage devices.
A semiconductor integrated circuit inspection device according to claim 9 is the semiconductor integrated circuit inspection device according to claim 6 or 8, wherein a via used for distinguishing data stored in the read-only storage device is provided. The layer is formed of the same layer as the via used for distinguishing the stored data of the additional bit string of the additional bit string embedding unit.

  The semiconductor integrated circuit inspection device according to claim 10 is the semiconductor integrated circuit inspection device according to claim 5, claim 6, claim 7, claim 8, or claim 9. It is stored in an arbitrary circuit of the circuit to be inspected.

  The semiconductor integrated circuit inspection device according to claim 11 is the semiconductor integrated circuit inspection device according to any one of claim 6, claim 8, or claim 9, wherein the additional bit string is stored in the read-only storage device. It is characterized by that.

  As described above, in the inspection of the semiconductor integrated circuit by the BIST technology, the comparator is greatly simplified to minimize the increase in the area of the semiconductor integrated circuit, and the inspection facility outside the semiconductor integrated circuit accompanying the change of the inspection target circuit It is possible to provide a semiconductor integrated circuit inspection method and a semiconductor integrated circuit inspection apparatus that do not require any change work.

  As described above, when the semiconductor device is inspected using the BIST technology, an additional bit string is added to the data to be inspected, a compressed signature is calculated, and compared with the expected value of the compressed signature, thereby determining pass / fail. Even if there is a change in the circuit to be inspected, the additional bit string can be selected to inspect the compression signature so that the expected value does not change. Is no longer necessary. In addition, since it is not necessary to change the expected value of the compressed signature, the comparator can be greatly simplified to minimize the increase in the area of the semiconductor integrated circuit.

  The present invention relates to a semiconductor integrated circuit inspection method and a semiconductor in which an inspection target circuit such as a read-only storage device configured in a semiconductor integrated circuit is inspected by a built-in self-inspection technique such as a BIST technique using an inspection apparatus such as an LSI tester This is an integrated circuit testing device. First, an additional bit string is incorporated into a test response bit string output by a circuit to be tested by inputting a test bit string such as address data. Next, a compression signature is calculated from a test response bit string incorporating the additional bit string in a predetermined manner, and a pass / fail judgment is made by comparing with an expected value of the compression signature.

  At this time, even when the circuit to be inspected is changed, by selecting the additional bit string so as not to change the expected value of the compressed signature, the circuit for determining pass / fail compares with the expected value of one compressed signature. The circuit configuration can be simplified and the increase in the area of the entire semiconductor integrated circuit can be suppressed. In addition, since it is not necessary to change the expected value of the compressed signature, there is no need to change the expected value stored in the external inspection facility, and the change work in the inspection facility outside the semiconductor integrated circuit in accordance with the change of the inspection target circuit Can be unnecessary.

Hereinafter, a semiconductor integrated circuit inspection method and a semiconductor integrated circuit inspection apparatus in each embodiment will be described by taking as an example the case where the inspection target circuit is a read-only storage device.
First, a first embodiment of the present invention will be described based on FIG. 1, FIG. 8, and FIG.

  FIG. 1 is an explanatory diagram relating to a method for inspecting a semiconductor integrated circuit according to the first embodiment, FIG. 8 is a diagram illustrating a process for calculating an expected value of a compressed signature according to the first embodiment, and FIG. 9 is a diagram illustrating the first embodiment. FIG. 9 is a diagram illustrating a process of calculating an expected value of a compressed signature in FIG. 8 and a diagram illustrating a case where a first check response bit string is different from that in FIG. 8.

In FIG. 1, step 100 is a test bit string supply process, in which a test bit string is generated and supplied to a test target circuit on a semiconductor integrated circuit.
Step 110 is a test target circuit operation process, and the test target circuit on the semiconductor integrated circuit outputs a first test response bit string 111 as a result of the circuit operation when the test bit string is input. In the present embodiment, the same 16-bit bit string as in FIG. 12 is used as the first inspection response bit string 111.

Step 120 is an additional bit string incorporation process, in which an additional bit string 121 is incorporated after the first check response bit string 111 and output as a second check response bit string 122.
Step 130 is a compression signature calculation process, and a compression signature 131 is calculated and output for the second test response bit string 122 as in the conventional technique. In the present embodiment, the same circuit configuration as that shown in FIG. 12 is used as a circuit configuration for calculating a compression signature.

Reference numeral 140 denotes a pass / fail judgment process. When the compression signature 131 matches the expected value 141 of the compression signature, the circuit to be inspected is determined as a non-defective product, and when it does not match, it is determined as a defective product.
Hereinafter, it is shown that the expected value of the compression signature 131 can be kept at a specific value by appropriately selecting the additional bit string 121 according to the value of the first test response bit string 111.

FIG. 8 shows the value of the first test response bit string 111 as “0100 1011 1001 0010”.
In this case, “d ₃ d ₂ d ₁ d ₀ ” is added as the additional bit string 121.
The second test response bit string 122 obtained by incorporating
"0100 1011 1001 0010 d ₃ d ₂ d ₁ d ₀ "
Shows a process of calculating a compression signature.

  Since the procedure for dividing the polynomial by writing is the same as that in FIG. 13, the modulo 2 operation including the variable d will be described here. Since addition and subtraction are equivalent in the modulo 2 operation, the operation symbol is represented by the addition only here.

Addition / subtraction: When d = 0, d + 0 = 0 + d = 0 + 0 = 0
d + 1 = 0 + 1 = 1 1 + d = 1 + 0 = 1
When d = 1, d + 0 = 1 + 0 = 1 0 + d = 0 + 1 = 1
d + 1 = 1 + d = 1 + 1 = 0
Multiplication: When d = 0, d · 0 = 0 · d = 0 · 0 = 0
d · 1 = 0 · 1 = 0 1 · d = 1 · 0 = 0
When d = 1, d · 0 = 1 · 0 = 0 0 · d = 0 · 1 = 0
d · 1 = 1 · d = 1 · 1 = 1
So
Addition / subtraction: d + 0 = 0 + d = d d + 1 = 1 + d = / d
Multiplication: d · 0 = 0 · d = 0 d · 1 = 1 · d = / d
Holds. Here, / d means inversion of d. For inversion operations,
/ (/ D) = d
Holds.

Applying the above, the expected value of the compression signature is “d ₃ / d ₂ / d ₁ d ₀ ”
Is obtained. Since each bit value of the additional bit string 121 is independently included in each bit position of the expected value of the compressed signature, the expected value of the compressed signature is set to an arbitrary value by appropriately selecting the value of the additional bit string. I understand that I can do it. As an example, if d ₃ = 1, d ₂ = 0, d ₁ = 0, d ₀ = 1, the expected value of the compressed signature is “1111”.
It becomes.

Next, FIG. 9 shows the value of the first test response bit string 111 as “1001 0101 1100 0011”.
In this case, “d ₃ d ₂ d ₁ d ₀ ” is added as the additional bit string 121.
The second test response bit string 122 obtained by incorporating
"1001 0101 1100 0011 d ₃ d ₂ d ₁ d ₀ "
Shows a process of calculating a compression signature.

Since the procedure for dividing the polynomial by writing is the same as in FIG. 13, a detailed description of the division operation is omitted.
As a result of the division, the expected value of the compression signature is “/ d ₃ d ₂ / d ₁ / d ₀ ”
Is obtained. As in the case of FIG. 8, since each bit value of the additional bit string 121 is independently included in each bit position of the expected value of the compressed signature, the expected value of the compressed signature can be obtained by appropriately selecting the value of the additional bit string. It can be seen that the value can be set to any value.

In order to make the same value as the expected value of the compression signature set earlier, it is only necessary to set each bit value of the additional bit string 121 to d ₃ = 0, d ₂ = 1, d ₁ = 0, and d ₀ = 0. I understand.
As described above, an expected value of the compressed signature can be set to an arbitrary value by including a process of incorporating an additional bit string appropriately selected according to the value of the first test response bit string. Therefore, even if the circuit to be inspected is changed, if the value of the additional bit string is appropriately selected according to the value of the first inspection response bit string after the change, the expected value of the compression signature is deferred to the previously set value. be able to. Therefore, the comparison operation with the expected value of the compressed signature in the process of determining pass / fail of the circuit to be inspected is greatly simplified. Further, when the same process is arranged outside the semiconductor integrated circuit, there is no need to change the expected value stored in the external inspection facility even if the inspection target circuit is changed.

Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 2 is an explanatory diagram relating to a semiconductor integrated circuit inspection method according to the second embodiment, and FIG. 10 is a diagram illustrating a process for calculating an expected value of a compressed signature according to the second embodiment.

In FIG. 2, step 200 is a test bit string supply process, in which a test bit string is generated and supplied to a test target circuit on a semiconductor integrated circuit.
Step 210 is a test target circuit operation process, and the test target circuit on the semiconductor integrated circuit outputs the first test response bit string 211 as a result of the circuit operation when the test bit string is input. In this embodiment, it is assumed that the circuit to be inspected consists of two read-only storage devices (4 bits × 4 words), a read address signal is supplied as a test bit string from the test bit string supply process step 200, and all stored data is stored. Output sequentially. That is, as the first inspection response bit string 211, a 32-bit bit string obtained by arranging two 16-bit bit strings used in the first embodiment is used.

  Step 220 is an additional bit string incorporation process, in which the additional bit string is incorporated into the first check response bit string 211 and is output as the second check response bit string 222. In the present embodiment, it is assumed that an additional bit string is incorporated every time reading of all stored data from each read-only storage device is completed, and a second check response bit string 222 is generated. That is, the additional bit string 2211 is incorporated in the middle of the first check response bit string (in this case, immediately after all stored data from the first read-only storage device), and finally the additional bit string 2212 is incorporated to form the second check response bit string. .

  Step 230 is a compression signature calculation process. The second check response bit string 222 is divided into units such that the second check response bit string 222 is an additional bit string in which the last bit is incorporated. The compression signatures 2311 and 2312 are calculated and output. The same circuit configuration as that shown in FIG. 12 is used as a circuit configuration for calculating the compression signature.

  Step 240 is a pass / fail determination process. When the calculated values of the compression signatures 2311 and 2312 match the corresponding expected values 2411 and 2412, the circuit to be inspected is determined as a non-defective product, and when they do not match, it is determined as a defective product. To do.

  Hereinafter, when incorporating the additional bit strings 2211 and 2212 in the middle and after the first check response bit string 211, the compression signature expected values 2411 and 2412 are specified for each additional bit string by appropriately selecting the value of each additional bit string. Indicates that the value can remain.

FIG. 10 shows the value “0100 1011 1001 0010” of the first inspection response bit string 211.
1001 0101 1100 0011 "
On the other hand, “d ₁₃ d ₁₂ d ₁₁ d ₁₀ ” as additional bit strings 2211 and 2122
_"D 23 _d 22 _d 21 _{d 20"}
The second test response bit string 222 obtained by incorporating
“0100 1011 1001 0010 d ₁₃ d ₁₂ d ₁₁ d ₁₀
1001 0101 1100 0011 d ₂₃ d ₂₂ d ₂₁ d ₂₀ "
Shows a process of calculating a compression signature.

Since the division of the polynomial by writing is the same as in FIG. 13, a detailed description of the division operation is omitted.
As a result of the division, “d ₁₃ / d ₁₂ / d ₁₁ d ₁₀ ” is used as the expected value 2411 of the compression signature for the second check response bit string 222 including up to the additional bit string 2211.
Is obtained. Since each bit value of the additional bit string 2211 is independently included in each bit position of the expected value of the compression signature, it can be seen that the expected value can be set to an arbitrary value by appropriately selecting the value of the additional bit string. . As an example, if the additional bit string 2211 is d ₁₃ = 1, d ₁₂ = 0, d ₁₁ = 0, and d ₁₀ = 1, the expected value 2411 of the compressed signature is “1111”.
It becomes.

Next, when the division further proceeds with respect to the second check response bit string 222 obtained by fixing the additional bit string 2211 to the above value, the compression signature of the second check response bit string 222 including the additional bit string 2212 is included. Expected value 2412 is “/ d ₂₃ / d ₂₂ / d ₂₁ / d ₂₀ ”
Is obtained. As in the previous case, since each bit value of the additional bit string 2212 is independently included in each bit position of the expected value of the compressed signature, the expected value of the compressed signature can be obtained by appropriately selecting the value of the additional bit string. It can be seen that can be set to any value.

In order to make the same value as the expected value (here, “1111”) of the compression signature set earlier, the additional bit string 2212 should be d ₂₃ = 0, d ₂₂ = 0, d ₂₁ = 0, d ₂₀ = 0. I know it ’s good.

  From the above, it has been shown that the expected values 2411 and 2412 of the compression signature can remain at specific values for each additional bit string. Since the pass / fail judgment section only needs to always compare the compression signatures 2311 and 2312 output from the compression signature calculation section with the expected value of the same compression signature, the circuit configuration is greatly simplified.

  In the present embodiment, the case where the corresponding additional bit strings are incorporated immediately after the read data from each read-only storage device when the read data from the two read-only storage devices is inspected has been described. Even when two or more additional bit strings are incorporated in the middle of the original test response bit string, the value of the additional bit string can be selected by the same procedure so that the expected value of the compression signature remains at a specific value.

  As described above, by including a process of incorporating each appropriately selected additional bit string according to the value of each partial bit string including the first bit of the first check response bit string to the last bit of each additional bit string, The expected value of each compression signature can be set to the same arbitrary value. Therefore, even when the circuit to be inspected is changed, the value of the corresponding additional bit string is changed according to the value of each partial bit string including the first bit to the last bit of each additional bit string for the changed first inspection response bit string If each is appropriately selected, all of the expected values of each compression signature can be deferred to the previously set values. Therefore, the comparison operation with the expected value of the compressed signature in the process of determining pass / fail of the circuit to be inspected is greatly simplified. Further, when the same process is arranged outside the semiconductor integrated circuit, it is not necessary to change the expected value stored in the external inspection facility even if the inspection target circuit is changed.

  Further, an additional bit string is incorporated in the middle of the first check response bit string, and a compression signature is calculated for a partial bit string including the first bit of the first check response bit string to the last bit of the additional bit string to determine pass / fail. By selecting a place where the additional bit string is incorporated, it is possible to limit a defective place in the pass / fail judgment.

Next, a third embodiment of the present invention will be described with reference to FIG.
FIG. 3 is a block diagram showing a semiconductor integrated circuit inspection apparatus according to the third embodiment.
3, the semiconductor integrated circuit inspection apparatus according to the present embodiment includes a test bit string supply unit 300, a test target circuit 310, an additional bit string incorporation unit 320, a compression signature calculation unit 330, and a pass / fail determination unit 340.

The inspection bit string supply unit 300 generates a read address signal as the inspection bit string 301 and supplies the read address signal to the inspection target circuit 310.
The inspection target circuit 310 has 4-bit width data “0100”, “1011”, “1001”, “0010”.
As a read-only storage device, for example, a single ROM module outputs stored data in accordance with a read address signal 301. Here, the read address signal 301 assumes that all the addresses of the circuit under test 310 transition in ascending order, and the stored data is read according to this order. Thus, the read data 311 is arranged in the same order as “0100 1011 1001 0010”.
The first test response bit string 312 is configured.

Reference numeral 320 denotes an additional bit string incorporation unit, and an additional bit string 321 after the first check response bit string 312.
_"D 3 _d 2 _d 1 _{d 0"}
Embedded
"0100 1011 1001 0010 d ₃ d ₂ d ₁ d ₀ "
Is output as a second inspection response bit string 322.

  Reference numeral 330 denotes a compression signature calculation unit that calculates and outputs a compression signature 331 for the second inspection response bit string 322. In the present embodiment, the same circuit configuration as that of FIG. 12 is used as a circuit configuration for calculating the compression signature 331.

  Reference numeral 340 denotes a pass / fail judgment unit. When the value of the compression signature 331 matches the expected value 341 of the compression signature, the inspection target circuit 310 is judged to be a non-defective product. Output.

According to this configuration, “d ₃ / d ₂ / d ₁ d ₀ ” is obtained as the expected value 341 of the compression signature based on the division result of FIG.
Is obtained. Since each bit value of the additional bit string 321 is independently included in each bit position of the expected value, it can be seen that the expected value 341 can be set to an arbitrary value by appropriately selecting the value of the additional bit string. As an example, assuming that each bit of the additional bit string 321 is d ₃ = 1, d ₂ = 0, d ₁ = 0, d ₀ = 1, the expected value 341 of the compressed signature is “1111”.
It becomes.

  Even if a change occurs in the first inspection response bit string 312 due to the change in the inspection target circuit 310, the expected value 341 of the compressed signature remains at a specific value by appropriately selecting the additional bit string 321. As described in the first embodiment, the same effect can be achieved.

Next, a fourth embodiment of the present invention will be described with reference to FIGS.
FIG. 4 is a block diagram showing a semiconductor integrated circuit inspection apparatus in the fourth embodiment, and FIG. 11 is a diagram for explaining the operation of the MISR in the fourth embodiment.

  4, the semiconductor integrated circuit inspection apparatus according to the present embodiment includes an inspection bit string supply unit 400, inspection target circuits 4101 and 4102, an additional bit string incorporation unit 420, a compression signature calculation unit 430, and a pass / fail determination unit 440.

The inspection bit string supply unit 400 generates a read address signal and a module selection signal as the inspection bit string 401 and supplies them to the inspection target circuits 4101 and 4102.
Both the inspection target circuits 4101 and 4102 are ROM modules for storing, for example, four pieces of 4-bit width data. 4101: “0100”, “1011”, “1001”, “0010”, respectively.
4102: “1001”, “0101”, “1100”, “0011”
And the stored data is output in accordance with the module selection signal and the read address signal in the test bit string 401. Here, in the test bit string 401, ROM modules are selected in the order of the test target circuits 4101 and 4102, and all addresses are shifted in ascending order in each ROM module, and the stored data is read according to this order. In this way, the read data 4111 and 4112 from the ROM modules are arranged in the same order as “0100”.
1011
1001
0010
1001
0101
1100
0011 ''
The first test response bit string 412 having a 4-bit width is configured.

Reference numeral 420 denotes an additional bit string incorporation unit, and additional bit strings 4211 and 4212 corresponding immediately after the inspection target circuits 4101 and 4102 of the first inspection response bit string 412.
_"D 13 _d 12 _d 11 _{d 10"
"D} 23 _d 22 _d 21 _{d 20"}
Embedded
“0100
1011
1001
0010
d ₁₃ d ₁₂ d ₁₁ d ₁₀
1001
0101
1100
0011
d ₂₃ d ₂₂ d ₂₁ d ₂₀ "
Is output as a second inspection response bit string 422.

  A compression signature calculation unit 430 calculates a compression signature 431 for the second test response bit string 422 and outputs it. In the present embodiment, a multi-input signature register (MISR) that is expanded to a multi-bit input based on the LFSR used in FIG. 12 is adopted as a circuit configuration for calculating a compression signature.

  Reference numeral 440 denotes a pass / fail judgment unit. When the value of the compression signature 431 matches the expected values 4411 and 4412 of the compression signature, the circuit to be inspected 410 is judged to be a non-defective product. It outputs as 442.

Here, the operation of the MISR of FIG. 4 will be described with reference to FIG.
FIG. 11 shows the inputs and states of the flip-flops FF3 to FF0 of the MISR at each time. One line corresponds to one time, and moves to a lower line with the time.

First, in the initial state, all flip-flops of the MISR are all zero. At the next time, the state of each flip-flop is determined as follows.
State of FF3:
XOR between the input “0” of FF3 at the previous time and the state “0” of FF2 → “0”
State of FF2:
XOR between input “1” of FF2 at the previous time and state “0” of FF1 → “1”
State of FF1:
XOR of input “0” of FF1 at the previous time, state “0” of FF0 and state “0” of FF3 → “0”
State of FF0:
XOR of FF0 input “0” and FF3 state “0” at previous time → “0”
The above operation is repeated, and the state of each flip-flop at the next time when the additional bit string 4211 is input is “/ d ₁₃ / d ₁₂ d ₁₁ / d ₁₀ ”.
Is obtained. This is the compression signature expected value 4411 for the second test response bit string 422 including up to the additional bit string 4211. Since each bit value of the additional bit string 4211 is independently included in each bit position of the expected value 4411 of the compressed signature, the expected value 4411 of the compressed signature is set to an arbitrary value by appropriately selecting the value of the additional bit string. It can be seen that can be set. As an example, when each bit of the additional bit string 4111 is d ₁₃ = 0, d ₁₂ = 0, d ₁₁ = 1, and d ₁₀ = 0, the expected value 4411 of the compressed signature is “1111”.
It becomes.

Next, when the circuit operation further proceeds with respect to the second check response bit string 422 obtained by determining the additional bit string 4211 to the above value, the compressed signature for the second check response bit string 422 including the additional bit string 4212 is obtained. As an expected value 4412 of “d ₂₃ d ₂₂ d ₂₁ / d ₂₀ ”
Is obtained. As in the previous case, since each bit value of the additional bit string 4212 is independently included in each bit position of the expected value 4412 of the compressed signature, the expected value of the compressed signature can be obtained by appropriately selecting the value of the additional bit string. It can be seen that the value 4412 can be set to any value.

In order to make the same value as the expected value 4411 (here, “1111”) of the compression signature set previously, each bit of the additional bit string 4111 is set to d ₂₃ = 1, d ₂₂ = 1, d ₂₁ = 1, d ₂₀ = It can be seen that 0 is sufficient.

  From the above, it has been shown that the expected values 4411 and 4412 of the compression signature can remain at specific values for each additional bit string. Since the pass / fail judgment unit 440 only needs to always compare the compression signature output from the compression signature calculation unit 430 with the expected value of the same compression signature, the circuit configuration is greatly simplified.

  As described above, it is provided with an additional bit string incorporation unit that incorporates an appropriately selected additional bit string according to the value of each partial bit string including the first bit of the first check response bit string to the last bit of each additional bit string. Thus, the expected values of the respective compression signatures can all be set to the same arbitrary value. Therefore, even when the circuit to be inspected is changed, the value of the corresponding additional bit string is changed according to the value of each partial bit string including the first bit to the last bit of each additional bit string for the changed first inspection response bit string If each is appropriately selected, all of the expected values of each compression signature can be deferred to the previously set values. Therefore, the circuit configuration for comparison with the expected value of the compressed signature in the pass / fail judgment unit of the circuit to be inspected is greatly simplified. Further, when the pass / fail judgment unit is arranged outside the semiconductor integrated circuit, even if the circuit to be inspected is changed, there is no need to change the expected value stored in the external inspection facility.

  In the present embodiment, the case where the corresponding additional bit strings are incorporated immediately after the read data from each read-only storage device when the read data from the two read-only storage devices is inspected has been described. Even when two or more additional bit strings are incorporated in the middle of the original inspection response bit string, it is possible to select the value of the additional bit string so that the expected value of the compression signature remains at a specific value.

  Further, an additional bit string is incorporated in the middle of the first check response bit string, and a compression signature is calculated for a partial bit string including the first bit of the first check response bit string to the last bit of the additional bit string to determine pass / fail. By selecting a place where the additional bit string is incorporated, it is possible to limit a defective place in the pass / fail judgment.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
FIG. 5 is a block diagram showing a semiconductor integrated circuit inspection apparatus according to the fifth embodiment. The data representation structure in the inspection target circuit 310, 4101 or 4102 in FIG. 3 or FIG. The structure of the additional bit generation is described.

  In the semiconductor integrated circuit inspection apparatus in this embodiment shown in FIG. 5, 510 is a circuit to be inspected, and is composed of a read-only storage device. In the data storage area, the word line 516 is arranged orthogonal to the bit line 515 of the wiring layer, and the N-channel MOS transistor 517 is arranged at the intersection of the two.

The source side of the transistor 517 is grounded and the drain side is opposed to the bit line 515, and may be connected to the bit line 515 through the via 518 or may not have a via.
The bit line 515 is set to a potential on the power supply potential side before reading stored data. When the word line 516 is activated by a read operation, the transistor 517 is turned on. In the case where the via 518 is present, the potential of the bit line 515 decreases because the charge of the bit line 515 flows to the ground side through the transistor 517. When there is no via, the potential of the bit line 515 is maintained. Thus, the stored data “0” or “1” is distinguished.

Reference numeral 520 denotes an additional bit string incorporation unit, and particularly shows a configuration for generating the additional bit string 521. Here, it is assumed that the additional bit string 521 has a value of “0100”.
Each bit signal of the additional bit string 521 reflects the potential of the wiring patterns 5231 to 5234, respectively. The wiring patterns 5231 to 5234 face the wiring patterns 5241 to 5244 connected to the power supply potential side, respectively, and simultaneously face the wiring patterns 5251 to 5254 connected to the ground potential side.

  The wiring patterns 5231 and 5251, 5232 and 5242, 5233 and 5253, and 5234 and 5254 are connected between the wiring patterns via vias 5261 to 5264 that are the same layer as the via 518 of the circuit to be inspected 510. The value of the additional bit string 521 is generated.

  With this configuration, in addition to the effects obtained in the third and fourth embodiments, the read-only storage device uses a specific mask layer to represent the stored data, and the additional bit sequence in the additional bit sequence embedding unit is Since this is realized by using the same mask layer, an economic effect is obtained in that the mask change cost required when changing the additional bit string 521 in accordance with the change of the inspection target circuit 510 can be minimized. .

Next, a sixth embodiment will be described with reference to FIG.
FIG. 6 is a block diagram showing a semiconductor integrated circuit inspection apparatus according to the sixth embodiment.
6, the semiconductor integrated circuit inspection apparatus according to the present embodiment includes a test bit string supply unit 600, a test target circuit 610, an additional bit string incorporation unit 620, a compression signature calculation unit 630, and a pass / fail determination unit 640.

The inspection bit string supply unit 600 generates a read address signal as the inspection bit string 601 and supplies the read address signal to the inspection target circuit 610.
The inspection target circuit 610 has 4-bit width data “0100”, “1011”, “1001”, “0010”.
As a read-only storage device, for example, one ROM module outputs data stored in accordance with a check bit string 601 that is a read address signal. Here, the read address signal assumes that all the addresses of the circuit under test 610 are shifted in ascending order, and the stored data is read according to this order. In this way, the read data 611 is arranged in the same order as “0100 1011 1001 0010”.
The first inspection response bit string 612 is configured.

Reference numeral 620 denotes an additional bit string incorporation unit, which is an additional bit string 621 immediately after the first check response bit string 612.
_"D 3 _d 2 _d 1 _{d 0"}
Embedded
"0100 1011 1001 0010 d ₃ d ₂ d ₁ d ₀ "
Is output as a second test response bit string 622.

  Here, the additional bit string 621 is realized as the fifth storage data of the inspection target circuit 610, and the additional bit string which is the fifth storage data is read following the reading operation of the first to fourth storage data. Thus, the second test response bit string 622 is generated.

  A compression signature calculation unit 630 calculates a compression signature 631 for the second test response bit string 622 and outputs it. In the present embodiment, the same circuit configuration as that shown in FIG. 12 is used for calculating the compression signature 631.

  Reference numeral 640 denotes a pass / fail judgment unit. When the value of the compressed signature 631 matches the expected value 641 of the compressed signature, the circuit to be inspected 610 is judged as a non-defective product. Output.

  Since the calculation of the compression signature 631 and the quality determination operation in the semiconductor integrated circuit device according to this configuration are exactly the same as those in the third embodiment, the details are omitted. In addition to the effect obtained in the third embodiment, since the constituent elements of the additional bit incorporation unit 620 are absorbed and merged into the circuit under test 610, the circuit area can be reduced.

Next, a seventh embodiment of the present invention will be described with reference to FIG.
FIG. 7 is a block diagram showing a semiconductor integrated circuit inspection apparatus according to the seventh embodiment.
7, the semiconductor integrated circuit inspection apparatus according to the present embodiment includes a test bit string supply unit 700, a test target circuit 710, an additional bit string incorporation unit 720, a compression signature calculation unit 730, and a pass / fail determination unit 740.

The inspection bit string supply unit 700 generates a read address signal as the inspection bit string 701 and supplies the read address signal to the inspection target circuit 710.
The inspection target circuit 710 has 4-bit width data “0100”, “1011”, “1001”, “0010”.
And outputs data stored in accordance with a check bit string 701 that is a read address signal. Here, the read address signal assumes that all the addresses of the circuit under test 710 are shifted in ascending order, and the stored data is read according to this order. Thus, the read data 711 is arranged in the same order as “0100 1011 1001 0010”.
The first inspection response bit string 712 is configured.

Reference numeral 720 denotes an additional bit string incorporation unit, and an additional bit string 721 after the first check response bit string 712.
_"D 3 _d 2 _d 1 _{d 0"}
Embedded
"0100 1011 1001 0010 d ₃ d ₂ d ₁ d ₀ "
Is output as a second inspection response bit string 722.

  Here, the additional bit string 721 is realized as data separately stored in a place other than the stored data in the inspection target circuit 710, and can be read in an operation mode different from the normal operation mode for reading stored data. . When the second test response bit string 722 is generated, first, the first to fourth stored data are read, and then the operation mode is switched to read the additional bit string.

  A compression signature calculation unit 730 calculates a compression signature 731 for the second inspection response bit string 722 and outputs it. In the present embodiment, the same circuit configuration as that shown in FIG. 12 is used for calculating the compression signature 731.

  Reference numeral 740 denotes a pass / fail judgment unit. When the value of the compressed signature 731 matches the expected value 741 of the compressed signature, the inspection target circuit 710 is judged to be a non-defective product. Output.

  The operation of compression signature calculation and pass / fail judgment in the semiconductor integrated circuit device according to the present configuration is exactly the same as that of the third embodiment, and the details are omitted. In addition to the effects obtained in the third embodiment, the components of the additional bit incorporation unit 720 are absorbed and merged into the circuit under test 610, so that the circuit area can be reduced. Further, this is also effective when the circuit to be inspected has used up all the data storage area and no data storage area for the additional bit string is left.

  In the above description, the read-only storage device has been described as an example of the circuit to be inspected. However, even when other general logic circuits are used as the circuit to be inspected, the same effect can be obtained by performing the inspection with the same configuration. it can.

  The present invention greatly simplifies the comparator to minimize the increase in the area of the semiconductor integrated circuit, and eliminates the need to change the inspection equipment outside the semiconductor integrated circuit in accordance with the change of the circuit to be inspected. It is useful for a semiconductor integrated circuit inspection method using semiconductor and a semiconductor integrated circuit inspection circuit.

Explanatory drawing about the inspection method of the semiconductor integrated circuit in 1st Embodiment Explanatory drawing regarding the inspection method of the semiconductor integrated circuit in 2nd Embodiment The block diagram which shows the test | inspection apparatus of the semiconductor integrated circuit in 3rd Embodiment The block diagram which shows the test | inspection apparatus of the semiconductor integrated circuit in 4th Embodiment The block diagram which shows the test | inspection apparatus of the semiconductor integrated circuit in 5th Embodiment The block diagram which shows the test | inspection apparatus of the semiconductor integrated circuit in 6th Embodiment The block diagram which shows the test | inspection apparatus of the semiconductor integrated circuit in 7th Embodiment The figure which shows the expected value calculation process of the compression signature in 1st Embodiment The figure which shows the expected value calculation process of the compression signature in 1st Embodiment The figure which shows the expected value calculation process of the compression signature in 2nd Embodiment The figure explaining operation | movement of MISR in 4th Embodiment The figure which shows the structural example of BIST in the conventional read-only memory | storage device. The figure which shows the process in which the expected value of a compression signature is calculated with respect to the conventional test response bit string

Explanation of symbols

121, 2121, 2122 Additional bit string 122, 222 Second test response bit string 131, 231, 2312 212 Compressed signature 141, 2411, 2412 Expected value of compressed signature 300, 400, 600, 700, 1200 Test bit string supply unit 301, 401, 601, 701, 1201 Inspection bit string 310, 4101, 4102, 510, 610, 710, 1210 Inspection target circuit 311, 4111, 4112, 611, 711, 1211 Read data 312, 412, 612, 712 First inspection response bit string 1212 Inspection response bit string 320, 420, 520, 620, 720 Additional bit string incorporation unit 321, 4211, 4212, 521, 621, 721 Additional bit string 322, 422, 622, 722 Second inspection response Answer bit string 330, 430, 630, 730, 1230 Compression signature calculation unit 331, 431, 631, 731, 1231 Compression signature 340, 440, 640, 740, 1240 Pass / fail judgment unit 341, 4411, 4412, 641, 741, 1241 Compression Expected value of signature 342, 442, 642, 742, 1242 Pass / fail judgment results FF0, FF1, FF2, FF3 Flip-flop XOR0, XOR1, XOR2, XOR3 Exclusive OR (eXclusive OR) circuit 515 Bit line 516 Word line 517 Transistor 518 Vias 5231, 5232, 5233, 5234 Wiring patterns 5241, 5242, 5243, 5244 Wiring patterns 5251, 5252, 5253, 5254 Wiring patterns 5261, 5262, 5263, 5264 Via

Claims (11)

A method for inspecting a semiconductor integrated circuit in which inspection of a circuit to be inspected on a semiconductor integrated circuit is performed by self-inspection using an inspection apparatus,
Supplying a predetermined inspection bit string to the circuit to be inspected and outputting a first inspection response bit string;
Incorporating an additional bit string immediately after the first test response bit string to generate a second test response bit string;
Calculating a compressed signature from the second test response bit string;
Determining whether the circuit to be inspected is non-defective / defective by confirming a match between the value of the compression signature and the expected value of the compression signature, and when the circuit to be inspected is non-defective, the compression A test method for a semiconductor integrated circuit, wherein the additional bit string is selected according to a value of the first test response bit string so that an expected value of a signature always remains a specific value.   2. The semiconductor integrated circuit inspection method according to claim 1, wherein the circuit to be inspected is a read-only storage device. A method for inspecting a semiconductor integrated circuit in which inspection of a circuit to be inspected on a semiconductor integrated circuit is performed by self-inspection using an inspection apparatus,
Connecting a series of output values obtained by supplying a predetermined inspection bit string to the plurality of inspection target circuits and outputting a first inspection response bit string;
Incorporating the additional bit string corresponding to a plurality of serial connection locations including immediately after the first test response bit string to generate a second test response bit string;
Dividing the second test response bit string into units such that the final bit is an additional bit string and calculating a compression signature for each unit;
Determining whether each circuit to be inspected is non-defective / defective by confirming a match between the value of each compressed signature and the expected value of the corresponding compressed signature, and each circuit to be inspected is non-defective In the case of the semiconductor integrated circuit, the additional bit string is selected according to the value of the first test response bit string so that the expected value of each compression signature always remains a specific value. Inspection method.   4. The semiconductor integrated circuit inspection method according to claim 3, wherein the circuit to be inspected is a plurality of read-only storage devices. A semiconductor integrated circuit inspection apparatus that performs inspection of a circuit to be inspected on a semiconductor integrated circuit using an inspection apparatus and performs self-inspection.
An inspection bit string supply unit that generates an inspection bit string and outputs the inspection bit string to the circuit to be inspected;
An additional bit string incorporation unit that inputs the inspection bit string and outputs a second inspection response bit string obtained by incorporating the additional bit string immediately after the first inspection response bit string generated by the circuit to be inspected;
A compression signature calculation unit that calculates and outputs a compression signature from the second test response bit string;
A non-defective / non-defective determination unit for determining whether the circuit to be inspected is good or not by confirming a match between the value of the compression signature and the expected value of the compression signature, and when the circuit to be inspected is non-defective, An inspection apparatus for a semiconductor integrated circuit, wherein the additional bit string is selected according to a value of the first inspection response bit string so that an expected value of the compression signature always remains a specific value.   6. The semiconductor integrated circuit testing device according to claim 5, wherein the circuit to be tested is a read-only storage device. A semiconductor integrated circuit inspection apparatus that performs inspection of a circuit to be inspected on a semiconductor integrated circuit using an inspection apparatus and performs self-inspection.
A test bit string supply unit that generates a test bit string and outputs the test bit string to the plurality of circuits to be tested;
It is obtained by incorporating additional bit strings corresponding to a plurality of serially connected locations including immediately after the first test response bit string generated by connecting the output values of each circuit to be inspected that are input and output the test bit string in series. An additional bit string incorporation section for outputting a second test response bit string;
A compression signature calculation unit that calculates and outputs a compression signature for each unit with respect to the second test response bit string divided into units such that a final bit becomes the additional bit string;
A pass / fail judgment unit for judging whether the circuit to be inspected is non-defective / defective by confirming a match between the value of each of the compressed signatures and an expected value of the corresponding compressed signature. In the case of a non-defective product, the additional bit string is selected according to the value of the first inspection response bit string so that the expected value of each compression signature always remains a specific value. Inspection device.   8. The semiconductor integrated circuit testing device according to claim 7, wherein the circuit to be tested is a plurality of read-only storage devices.   The via layer used for distinguishing the storage data of the read-only storage device is formed in the same layer as the via used for distinguishing the storage data of the additional bit string of the additional bit string embedding unit. The inspection apparatus for a semiconductor integrated circuit according to claim 6 or 8.   10. The semiconductor integrated circuit according to claim 5, wherein the additional bit string is stored in an arbitrary circuit of the circuit to be inspected. 11. Inspection equipment.   10. The inspection apparatus for a semiconductor integrated circuit according to claim 6, wherein the additional bit string is stored in the read-only storage device.

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