JP2007235678A - Image code decoding apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image code decoding apparatus capable of achieving acceleration without adding any large circuit or considerable correction to a conventional device and also without requiring a large memory size even if processing a large-sized image. <P>SOLUTION: This code decoding apparatus includes: a header decode circuit for inputting code data compressing image data and for decoding required data from a header included in a code; a color space data distribution circuit for distributing image data into data at each color space; an image decoding circuit for inputting data at each single color space and decoding the code; a color space data composing circuit for composing the data decoded at each single color space into all the color spaces; and a memory circuit for storing data, wherein a plurality of the image decoding circuits are provided in a plurality of kinds of color spaces and one memory circuit is provided at least at each image decoding circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a conventional code decoding apparatus that performs continuous image processing.

  FIG. 4 is a block diagram of a conventional code decoding circuit that performs continuous image processing. Hereinafter, JPEG2000 will be described as an example of continuous image processing.

  The configuration of the JPEG 2000 code stream is shown in FIG. Main header starting from SOC (Start Of Codestream) required as the first marker, tile part header starting from SOT (Start Of Tile-part) required at the beginning of each tile part header, tile part bitstream, and end marker It consists of EOC (End Of Codestream) which is essential.

  The tile part bitstream has a structure in which a plurality of packets each composed of a packet header and packet data are arranged in the order specified by the main header (progression order). JPEG2000 supports the five different progress orders shown in Table 1 below.

  For example, in the progress order of CPRL (Component-Position-Resolution level-Layer), the bit stream is configured as shown in FIG.

  The JPEG2000 decoding flow having the above code stream will be described next. FIG. 7 is a schematic block diagram of a conventional JPEG2000 code decoding circuit 104 '. The JPEG2000 code 120 'is input to the header decoding circuit 106', and is divided into a main header, a tile part header, a packet header part, and an MQ code. Information for decoding the MQ code from the header (subband and in-code block information) is decoded, and the MQ codes separated based on the information are stored in the memory 112 'in the order of the code blocks. Since processing is performed in units of code blocks in the MQ decoding circuit 130 ', all MQ codes are stored in the memory 112' in code block order (see FIG. 8).

  The MQ codes stored in the memory 112 'are input to the MQ decoding circuit 130' in code block order, and as a result, wavelet coefficients are output to the memory 112 '(see FIG. 9). At this time, the output wavelet coefficients are stored in the memory 112 'in units of code blocks, and are output in units of lines to the WT decoding circuit 132' (see FIG. 9).

  The wavelet coefficients input in line units are decoded into image data (YcbCr) by the WT decoding circuit 132 'and stored in the memory 112' in line units (see FIG. 10). In the reverse color conversion circuit 110 ′, the input image data is subjected to reverse reversible component conversion (Inverse-RCT) or reverse irreversible component conversion (Inverse-ICT) using an expression as shown in Table 2 below (FIG. 2). 10). After reverse color conversion, image data (RGB) is output from the reverse color conversion circuit 110 '.

  In order to reduce the circuit scale, the conventional code decoding circuit 104 'employs a system in which all components are sequentially decoded by one circuit without having a circuit for each component. Therefore, in order to perform reverse color conversion that is finally performed when decoding into an image without wasting time as much as possible, information on all components is required. That is, the image data of all components shown in FIGS. 8, 9, and 10 must be stored in the memory space.

  In the future, the necessity for decoding large images such as high-definition images will increase. However, when a large-size image is code-decoded using a conventional code-decoding circuit, the processing speed becomes slow due to an increase in data size, and there is a possibility that continuous image processing as expected cannot be realized.

  As shown in FIG. 11, it is conceivable to increase the continuous image processing speed by arranging a plurality of sets (three sets in FIG. 11) of the conventional code decoding circuit 4 'in parallel. Indeed, if it is made like FIG. 11, a several frame is decoded in parallel and the continuous image processing speed can be raised as the whole code decoding apparatus. However, the amount of memory required for the code decoding apparatus increases as the code decoding circuits 4 'are arranged in parallel, and the memory cost greatly increases. That is, if three sets are arranged in parallel as shown in FIG. 11, the memory cost increases three times. That is, it can be seen that when continuous image decoding of a large image is performed using the conventional code decoding circuit 4 ', the continuous image processing speed and the memory cost are in a trade-off relationship.

Note that Patent Document 1 includes a decoding unit that decodes encoded image data, a simplified unit that switches the subsequent decoding to a simplified process when decoding of the encoded image data is not completed within a specified time, and An image decoding apparatus including the above is disclosed. Patent Document 2 discloses a frequency conversion unit that frequency-converts image data, a bit-plane encoding unit that performs bit-plane encoding on the frequency-converted coefficient, and a code amount after the bit-plane encoding has a predetermined code amount. An image coding apparatus that compresses and encodes image data, wherein the code discarding unit performs the discarding in a predetermined first code unit. And an image encoding apparatus comprising: second means for performing the discarding as necessary in a second code unit smaller than the first code unit after the discarding by the first code unit. Is disclosed.
JP 2004-229314 A JP 2005-39793 A

  Even when processing a large image such as a high-definition image, the present invention does not require a large circuit and significant modification to a conventional code decoding device, and does not require a large memory size. An object of the present invention is to provide an apparatus capable of realizing high-speed processing.

The present invention has been made to achieve the above object. According to the first aspect of the present invention, an encoding / decoding device includes:
A header decoding circuit that decodes necessary data from the header included in the code, using the code data obtained by compressing the image data, and
A color space data distribution circuit that distributes image data into data for each color space;
An image decoding circuit for encoding / decoding data for each single color space as an input;
A color space data synthesis circuit that synthesizes the decoded data for each single color space into the entire color space;
Including a memory circuit for storing data;
A plurality of image decoding circuits are provided for a plurality of types of color spaces, and at least one memory circuit is provided for each image decoding circuit.

The encoding / decoding device according to claim 2 according to the present invention includes:
A header decoding circuit that receives JPEG2000 code as input and decodes information in the subband and code block from the header included in the code;
A component data distribution circuit that distributes the MQ codes in the bitstream into component units and distributes the MQ codes of each component into code block units;
An MQ decoding circuit for decoding MQ codes into wavelet coefficients in units of code blocks for each component;
A WT decoding circuit that inversely transforms wavelet coefficients,
Component data synthesis circuit that synthesizes the wavelet coefficients of all components,
A reverse color conversion circuit that performs reverse color conversion using wavelet coefficients of all components;
Including a memory circuit for storing data;
A plurality of image decoding circuits including the MQ decoding circuit and the WT decoding circuit are provided for a plurality of types of components, and at least one memory circuit is provided for each image decoding circuit. .

  By using the present invention, even when processing a large image such as a high-definition image, a large circuit and a large correction are not added to a conventional apparatus, and a large memory size is not required. It is possible to provide a code decoding apparatus capable of realizing high speed.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram of a code decoding apparatus 2 that performs continuous image processing according to the first embodiment of the present invention. FIG. 2 is a block diagram of a set of a code decoding circuit 4 in which a selector 7 is added to the conventional code decoding circuit 4 ′ shown in FIG. Two sets shown in FIG. 2 are installed, and further, a color space data distribution circuit 14, a color space data synthesis circuit 16, and an inverse color conversion circuit 18 are installed, and the code decoding device 2 shown in FIG. 1 is configured. ing.

  The reason why the three sets shown in FIG. 2 are provided in the code decoding apparatus 2 shown in FIG. 1 is that three color spaces are assumed. Therefore, the number of sets need not be three. The memories (12a, 12b, 12c) are provided for each set of color spaces.

  In the circuit shown in FIG. 2, the selector 7 is inserted between the header decoding circuit 6 and the image decoding circuit 8. The selector 7 is configured to select from the outside whether the image data input from “IN_A” is the image data cut by the header decoding circuit 6 or the image data input from “IN_B”. Therefore, if “IN_A” is selected, it can be used in the same manner as the conventional code decoding circuit 4 ′ (see FIG. 4).

  The image code input to the code decoding device 2 shown in FIG. 1 is first input to the header decoding circuit 11 where code information is decoded from the header portion. Image data is separated from the information and input to the color space data distribution circuit 14.

  The image data input to the color space data distribution circuit 14 is distributed to image codes for each color space. The assigned codes are input to a set of image decoding circuits (8a, 8b, 8c) for each color space via selectors (7a, 7b, 7c).

  For example, each of the image code data (image code 0, image code 1, and image code 2) in FIG. 1 is composed of three color space data (here, R, G, and B). Then, the color space R data is sorted into the top set in FIG. 1, the color space G data is sorted into the middle set in FIG. 1, and the color space B data is sorted into the bottom set in FIG. Will be entered. At this time, the amount of memory required for each set is one-third compared to the case where the image code data is stored in one set without being distributed.

  The codes decoded by the sets of the respective image decoding circuits (8a, 8b, 8c) are synthesized by the color space data synthesis circuit 16 and input to the inverse color conversion circuit 18, and as a result, the decoded image is output. .

  In the code decoding apparatus 2 according to the first embodiment, a set of code decoding circuits and a memory circuit are provided for each color space, whereby data for one image is distributed. This reduces the data that each set of code decoding circuits must store at one time (approximately one third). By doing in this way, it is possible to realize code decoding with a memory amount substantially equivalent to the memory amount (memory cost) required for code decoding using one set of the conventional code decoding circuit 4 ′ (see FIG. 4). .

  Furthermore, the coding / decoding device 2 according to the first embodiment and the one that performs coding / decoding using three sets of the conventional coding / decoding circuit 4 ′ (see FIG. 11) are first compared with emphasis on the amount of memory. View. In the case where the conventional code decoding circuit 4 ′ performs code decoding using three sets, each image decoding circuit 8 ′ must decode all color space data and input the data to the inverse color conversion circuit 10 ′. . For this reason, a memory 12 'for storing color space data for one image is required for each code decoding circuit.

  On the other hand, in the encoding / decoding device 2 according to the first embodiment, since only one color space data is processed in a set of one encoding / decoding circuit (4a, 4b, 4c), the memory (12a, 12b, 12c) May have a memory capacity for storing single color space data. As a result, it is possible to realize code decoding with a memory amount (memory cost) of about 1/3 as compared with the case of using three sets of conventional code decoding circuits.

  Next, the coding / decoding apparatus 2 according to the first embodiment is compared with the coding / decoding apparatus using three sets of the conventional coding / decoding circuit 4 ′ (see FIG. 11) with an emphasis on the continuous image processing speed. Try it. Considering the case where the input image is processed in succession of three images, the device that performs coding decoding using three sets of the conventional code decoding circuit 4 ′ and the coding / decoding device 2 according to the first embodiment have three consecutive images. The time to process the minutes is equal. Accordingly, it can be said that the continuous image processing speed is substantially the same.

  Therefore, in the continuous image processing using the coding / decoding device 2 according to the first embodiment, the memory cost required for coding / decoding using three sets of the conventional coding / decoding circuit 4 ′ is reduced to 1/3. A continuous image speed equivalent to that obtained by code decoding using three sets of the code decoding circuit 4 ′ can be realized.

  As described above, even when processing a large image such as a high-definition image, the conventional coding / decoding circuit 4 ′ is not significantly modified and the memory size is not increased. The apparatus which implement | achieves can be provided.

[Second Embodiment]
FIG. 3 is a block diagram of the code decoding apparatus 102 that performs continuous image processing according to the second embodiment of the present invention. The apparatus shown in FIG. 3 is set to perform JPEG2000 code decoding in the code decoding apparatus 2 according to the first embodiment.

  The input J2K code 120 is first input to the header decoding circuit 111, where code information is decoded from the header portion. Image data is separated from the information and input to the component data distribution circuit 114.

  The image data input to the component data distribution circuit 114 is distributed to image codes for each component. Since the JPEG2000 bit stream has a configuration as shown in FIG. 6, the MQ code cut out by the header decoding circuit 111 can be easily assigned from the header information.

  The distributed codes are input to the image decoding circuits (108a, 108b, 108c) for the respective components via the selectors (107a, 107b, 107c). The codes decoded by the respective image decoding circuits are combined by the component data combining circuit 116, input to the inverse color conversion circuit 118, and the decoded image is output.

  Also in the coding / decoding device according to the second embodiment, when processing a large image such as a high-definition image, the memory size is increased without significant modification to the conventional coding / decoding circuit. Therefore, it is possible to provide a device capable of realizing high speed.

1 is a block diagram of a code decoding apparatus that performs continuous image processing according to a first embodiment of the present invention. FIG. FIG. 5 is a block diagram of a set of a code decoding circuit obtained by adding a selector to the conventional code decoding circuit shown in FIG. It is a block diagram of the encoding / decoding apparatus which performs the continuous image process which concerns on the 2nd Embodiment of this invention. It is a block diagram of the conventional code decoding circuit which performs a continuous image process. This is a configuration of a JPEG2000 code stream. This is a bit stream structure in the progress order of CPRL (Component-Position-Resolution level-Layer). It is a schematic block diagram of a conventional JPEG2000 code decoding circuit. It is a block diagram which shows the relationship between the header decoding circuit, MQ decoding circuit, and memory in the conventional JPEG2000 code decoding circuit. It is a block diagram which shows the relationship between MQ decoding circuit, WT decoding circuit, and memory in the conventional JPEG2000 code decoding circuit. It is a block diagram which shows the relationship between the WT decoding circuit, reverse color conversion circuit, and memory in the conventional JPEG2000 code decoding circuit. It is a block diagram of the code decoding apparatus formed in parallel with 3 sets of conventional code decoding circuits.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2 ... Code decoding apparatus, 4 ... Code decoding circuit, 6 ... Header decoding circuit, 7 selector, 8 ... Image decoding circuit, 10 ... Reverse color conversion circuit, 12 ... Memory, 14 ... color space data distribution circuit, 16 ... color space data synthesis circuit, 18 ... reverse color conversion circuit, 20 ... image code, 22 ... image.

Claims (2)

A header decoding circuit that decodes necessary data from the header included in the code, using the code data obtained by compressing the image data, and
A color space data distribution circuit that distributes image data into data for each color space;
An image decoding circuit for encoding / decoding data for each single color space as an input;
A color space data synthesis circuit that synthesizes the decoded data for each single color space into the entire color space;
Including a memory circuit for storing data;
A code decoding apparatus, wherein a plurality of image decoding circuits are provided for a plurality of types of color spaces, and at least one memory circuit is provided for each image decoding circuit. A header decoding circuit that receives JPEG2000 code as input and decodes information in the subband and code block from the header included in the code;
A component data distribution circuit that distributes the MQ codes in the bitstream into component units and distributes the MQ codes of the respective components into code block units;
An MQ decoding circuit for decoding MQ codes into wavelet coefficients in units of code blocks for each component;
A WT decoding circuit that inversely transforms wavelet coefficients,
Component data synthesis circuit that synthesizes the wavelet coefficients of all components,
A reverse color conversion circuit that performs reverse color conversion using wavelet coefficients of all components;
Including a memory circuit for storing data;
A plurality of image decoding circuits including the MQ decoding circuit and the WT decoding circuit are provided for a plurality of types of components, and at least one memory circuit is provided for each image decoding circuit. Code decoding apparatus.

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