JP2007234608A - Liquid crystal display unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter circuit for a discharge tube with improved power efficiency of a transformer, and hardly influenced by a high-order resonance frequency. <P>SOLUTION: The inverter circuit for the discharge tube comprises the transformer 1 in which a resonance circuit is formed of a parasitic capacitance 3 of the discharge tube 9, and an H-bridge circuit 17 which drives a primary side of the transformer 1 at a frequency that is lower than a resonance frequency of the resonance circuit and where a phase difference θ between a voltage and a current at the primary side of the transformer 1 is within a predetermined range from its minimum point. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display unit including a discharge tube inverter circuit, and more particularly to a liquid crystal display unit including a discharge tube inverter circuit that draws out high power efficiency.

  In a conventional discharge tube inverter circuit, a resonance circuit is formed by the leakage inductance on the secondary side of the transformer and the parasitic capacitance of the discharge tube connected as a load, and the primary side of the transformer is driven at the resonance frequency of the resonance circuit. There are some (see, for example, Patent Document 1).

US Pat. No. 6,114,814

  Driving at a resonance frequency as described in Patent Document 1 involves a phase difference between the voltage and current on the primary side of the transformer, and the power efficiency of the transformer is not necessarily good.

  In addition, there is a high-order resonance frequency on the secondary side of the transformer, and there may be a phenomenon that operates at the resonance frequency or an operation that is easily affected by the high-order resonance frequency. There is a problem that it is difficult to design.

  The present invention has been made in view of the above points, paying attention to the fact that the range in which the phase difference between the voltage and current on the primary side of the transformer is small is good in power efficiency, and driving the transformer in the frequency range. An object of the present invention is to provide an inverter circuit for a discharge tube that improves the power efficiency of a transformer and is less susceptible to the effects of higher-order resonance frequencies.

  In order to achieve the above object, the present invention is provided with a discharge tube as a backlight of a liquid crystal display device, and an electromagnetic circuit in which a resonance circuit is formed on the secondary side by a parasitic capacitance generated in the discharge tube connected to the secondary side. A frequency that is less than the resonance frequency of the transformer and the resonance circuit and that has a phase difference between the voltage and current on the primary side of the electromagnetic transformer within a predetermined range from the minimum point is generated by the oscillation circuit, And a separately-excited inverter circuit for the discharge tube having an H-bridge circuit composed of four switches for driving the primary side of the electromagnetic transformer. The H-bridge circuit has a series circuit of switches composed of PMOS and NMOS connected in parallel. The gate signal waveforms for operating the PMOS switches are the same in ON time, and the NMOS switch is operated. Each ON time of the gate signal waveform is equal to or the same.

  Further, according to the present invention, the predetermined range is less than a resonance frequency of a resonance circuit formed on the secondary side, and a phase difference between the voltage and current on the primary side of the transformer is −30 ° from the minimum point. The frequency range is the phase of the range.

  Further, the present invention is characterized in that the PMOS gate signal is inputted through a delay circuit.

  Further, according to the present invention, the rise of the gate signal of the two PMOS switches is alternately performed for each apex on the upper limit side of the predetermined triangular wave, and the rise of the gate signal of the two NMOS switches is predetermined. It is characterized in that it is performed alternately for each apex on the lower limit side of the triangular wave.

  According to the present invention, the fall of the gate signal of the two NMOS switches is performed at a cross point between a predetermined triangular wave and the output voltage of the error amplifier, and the fall of the gate signal of the two PMOS switches Is delayed from the fall of the gate signal of the NMOS switch.

  The present invention also includes an electromagnetic transformer including a discharge tube as a backlight of a liquid crystal display device, wherein a resonance circuit is formed on the secondary side by a parasitic capacitance generated in the discharge tube connected to the secondary side, and the resonance circuit A frequency that is less than a resonance frequency of the electromagnetic transformer and a phase difference between a voltage and a current on the primary side of the electromagnetic transformer is within a predetermined range from a minimum point is generated by an oscillation circuit, and the primary side of the electromagnetic transformer at the frequency And an H-bridge circuit having four switches for driving the discharge tube, and the H-bridge circuit is configured by connecting a series circuit of switches composed of PMOS and NMOS connected in parallel. The driving timing of the bridge circuit is provided with a timing at which only one switch is turned on.

  The inverter circuit for a discharge tube according to the present invention has a minimum phase difference between a transformer in which a resonance circuit is formed by the parasitic capacitance of the discharge tube and a resonance frequency of the resonance circuit and a primary side voltage and current of the transformer. Since the configuration includes an H bridge circuit that drives the primary side of the transformer at a frequency within a predetermined range from the point, it is possible to improve the power efficiency of the transformer and to be affected by high-order frequencies. This makes it difficult to design a transformer.

  In addition, since the predetermined range is less than the resonance frequency on the secondary side and within a range of −30 ° from the minimum point, the power efficiency of the transformer can be reliably improved.

  Further, since a burst circuit for outputting a predetermined burst signal is further provided and the primary side of the transformer is intermittently driven by the burst signal, a wide range of light control can be easily performed.

  The burst circuit outputs a pulse signal input by setting a resistance value for determining an oscillation frequency as a high impedance as a burst signal, and a triangular wave oscillated with a predetermined DC signal by setting the resistance value as a low impedance. Since more burst signals are output, a plurality of burst signals can be easily output.

  In addition, when the burst signal becomes H level, the inverting input of the error amplifier that feedback-controls the current of the discharge tube is pulled up and the primary side of the transformer is deactivated. Can be reliably and easily performed.

  In the H bridge circuit, a series circuit of PMOS and NMOS is configured in parallel, and a delay circuit is connected to the gate circuit of the PMOS, so that the PMOS and NMOS of the series circuit are simultaneously turned on. To avoid malfunction and circuit protection.

  Further, the H bridge circuit includes a series circuit of PMOS and NMOS arranged in parallel, and rising of the gates of the two PMOSs is performed alternately for each vertex on the upper limit side of a predetermined triangular wave, Since the rise of the NMOS gate is alternately performed for each vertex on the lower limit side of the triangular wave, an appropriate gate signal that does not turn on the PMOS and NMOS of the H-bridge circuit at the same time can be easily and simply created.

  In the H bridge circuit, a series circuit of PMOS and NMOS is configured in parallel, and the fall of the gates of the two NMOSs is a cross point between a predetermined triangular wave and the output voltage of the error amplifier, Since the fall of the two PMOS gates is delayed from the fall of the NMOS gate, the PMOS and NMOS can be reliably prevented from being turned on simultaneously.

  In addition, since a voltage feedback error amplifier that feedback-controls the voltage applied to the discharge tube is provided, the open-circuit voltage can always be kept constant when the discharge tube is not connected or when the connection is poor. it can.

  In addition, a protection circuit is provided to stop the operation to the H bridge circuit when the output voltage of the error amplifier or the error amplifier for voltage feedback exceeds a predetermined value. Overvoltage to the transformer can be prevented.

  In addition, since the protection circuit is provided to stop the operation to the H bridge circuit when the output voltage of the transformer exceeds a predetermined value, the transformer and each circuit are reliably prevented from being damaged. Can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of a discharge tube inverter circuit according to a first embodiment of the present invention.

  FIG. 2 is a block diagram of the burst circuit 22 used in the discharge tube inverter circuit according to the first embodiment of the present invention.

  FIG. 3 shows the frequency characteristics of the admittance | Y | on the transformer primary side and the voltage and current levels when the resonant circuit is formed on the secondary side in the discharge tube inverter circuit according to the first embodiment of the present invention. This is a frequency characteristic of the phase difference θ.

  FIG. 4 is an operation timing chart of the discharge tube inverter circuit according to the first embodiment of the present invention.

  As shown in FIG. 1, in the inverter circuit for a discharge tube according to the first embodiment of the present invention, a resonance circuit is formed by the parasitic capacitance 3 generated between the discharge tube on the secondary side of the transformer 1 and the reflector. As shown in FIG. 3, the minimum point A0 where the phase difference θ between the primary side voltage and current is the minimum peak position is the most power efficient of the transformer 1, and the range of −30 ° from the minimum point A0 is the examination of the measurement data. As a result, the frequency range A is the minimum power with no significant difference. A point B is a resonance frequency on the secondary side, which is a driving position of the transformer 1 performed in the prior art. The resonant circuit formed on the secondary side of the transformer 1 may be formed by installing a choke coil (not shown) in series with the transformer 1 and the parasitic capacitance 3, or a part of the transformer 1 (for example, leakage) It can also be formed of a parasitic coupling 3 and a loose coupling portion of a magnetic flux type transformer.

  In order to set the frequency within the minimum power range A, the values of the resistor 5 and the capacitor 6 of the oscillation circuit 4 shown in FIG.

  Next, the operation of the discharge tube inverter circuit according to the first embodiment of the present invention will be described with reference to FIGS.

  First, in order to make the explanation easy to understand, the case where the predetermined voltage Va of the terminal 28a is not input to the inverting input unit 11a of the error amplifier 11 and the light control is not performed will be described.

  As shown in FIG. 1, the output of the triangular wave 7 (see FIG. 4A) of the oscillation circuit 4 is input to the PWM circuit 8. The liquid crystal display unit (LCD unit) 2 on the secondary side of the transformer 1 is provided with a discharge tube 9 for a liquid crystal backlight, and the voltage is converted by a current-voltage conversion circuit 10 that converts the current flowing through the discharge tube 9 into a voltage. 9 a is input to the inverting input section 11 a of the error amplifier 11.

  The error amplifier 11 outputs an output voltage 12 corresponding to the current of the discharge tube 9 to the PWM circuit 8, and the PWM circuit 8 compares the triangular wave 7 with the output voltage 12 of the error amplifier 11 and inputs the pulse signal 13 to the counter circuit 14. .

  The output pulse signal 16 of the oscillation circuit 4 is input to the counter circuits 14 and 15 and the logic circuit 29. Based on the output pulse signal 16 of the oscillation circuit 4 and the output pulse signals of the counter circuits 14 and 15, the logic circuit 29 generates gate signals 18, 19, 20 and 21 to be input to the H bridge circuit 17.

  The H bridge circuit 17 is configured by connecting a series circuit of PMOS (A1) and NMOS (B2) and a series circuit of PMOS (A2) and NMOS (B1) in parallel. The H bridge circuit 17 is operated by the gate signals 18, 19, 20, and 21, an alternating current in the range of the frequency A flows on the primary side of the transformer 1, and drives the discharge tube 9 in the LCD unit 2 with high power efficiency.

  Therefore, when the burst circuit 22 does not operate and the predetermined voltage Va from the terminal 28a is not input to the inverting input portion 11a of the error amplifier 11, no dimming is performed and the current in the discharge tube 9 is inverted in the error amplifier 11. Input to the input unit 11a, the discharge tube 9 is feedback-controlled, and constant current control is performed in a range where power efficiency is good.

  Next, the operation when the discharge tube 9 is dimmed by the burst circuit 22 will be described.

  As shown in FIG. 2, the burst circuit 22 includes a CR oscillator 40, a triangular wave voltage generation circuit 41, and a comparator 42, and a predetermined pulse input to the DUTY terminal 24a by setting the resistance 23 to a predetermined value or more. A mode in which the signal 24 is output from the burst circuit 22 as the first burst signal 25b (see FIG. 4D), and a triangular wave voltage determined by the resistor 23 and the capacitor 26 by making the resistor 23 less than a predetermined value. 27 (see FIG. 4B) and the DC voltage 36 (see FIG. 4B) input to the DUTY terminal 24a are compared, and the second burst signal 25a of the pulse wave (see FIG. 4C) is output. Can be set to either mode.

  When the burst signal 25 b from the burst circuit 22 is “H”, the transistor 28 is turned on, and the error amplifier 11 outputs the output voltage 12 corresponding to the current of the discharge tube 9 to the PWM circuit 8. The discharge tube 9 is activated by the pulse wave shown in FIG.

  When the first burst signal 25b of the burst circuit 22 is "L", the transistor 28 is turned off and the inverting terminal 11a of the error amplifier 11 is pulled up to a predetermined voltage Va applied to the terminal 28a. The operation of the H-bridge circuit 17 is stopped and the discharge tube 9 is deactivated. As described above, the discharge tube 9 is intermittently operated by the first burst signal 25b, and light control is performed. Even when the second burst signal 25a is used, the discharge tube 9 is dimmed in the same manner, and any one of the burst signals can be selectively used.

  A signal 33 obtained by dividing the voltage on the output side of the transformer 1 by the capacitors 31 and 32 is input to the protect circuit 30. The protect circuit 30 stops the operation of the logic circuit 29 when the voltage of the signal 33 exceeds a preset threshold value, and prevents an overcurrent to the discharge tube 9. When the falling edges of the gate signals 18, 19, 20, and 21 are the same timing, the PMOS (A1) and NMOS (B2) connected in series with the H bridge circuit 17 or the PMOS (A2) and NMOS (B1) are simultaneously connected. There is a possibility that the delay circuit 35 is inserted.

  FIG. 5 is a timing chart of gate signals in the discharge tube inverter circuit according to the first embodiment of the present invention.

  The rise of the gate signal 18 shown in FIG. 5B and the gate signal 19 shown in FIG. 5C is caused by the counter circuits 14 and 15 and the logic circuit 29 shown in FIG. 1 as shown in FIG. In addition, it is alternately performed at each of the vertices 18u and 19u on the upper limit side of the triangular wave 7, and the fall of the gate signal 18 and the gate signal 19 occurs at cross points 18d and 19d between the triangular wave 7 and the output voltage 12 of the error amplifier 11. Done. The gate signal 18 and the gate signal 19 cause the gates of the PMOS (A1) and the PMOS (A2) to rise and fall, respectively.

  5D and the gate signal 21 shown in FIG. 5E are alternately raised at the lowermost vertices 20u and 21u of the triangular wave 7, and the gate signal 20 and the gate The signal 21 falls at the cross points 20d and 21d between the triangular wave 7 and the output voltage 12 of the error amplifier 11. The gate signal 20 and the gate signal 21 cause the gates of the NMOS (B1) and NMOS (B2) to rise and fall, respectively.

  Further, as shown in FIG. 5B to FIG. 5D, the rising edge of the gate signals 20 and 21 is delayed with respect to the rising edge of the gate signals 18 and 19, and as shown in FIG. As described above, the fall of the gate signals 18 and 19 is delayed by the delay circuit 35 by a predetermined time t 1 with respect to the fall of the gate signals 20 and 21. Therefore, PMOS (A1), (A2) and NMOS (B1), NMOS (B2) can be prevented from being turned on simultaneously.

  Therefore, the triangular wave 7 and the output voltage 12 can easily and easily form appropriate gate signals 18, 19, 20, and 21 in which the PMOS (A1), (A2), the NMOS (B1), and the NMOS (B2) are not turned on at the same time. be able to.

  As described above, the discharge tube inverter circuit according to the first embodiment of the present invention can improve the power efficiency of the transformer and set the frequency lower than the resonance frequency. The transformer design can be made easier.

  FIG. 6 is a block diagram of a discharge tube inverter circuit according to a second embodiment of the present invention.

  As shown in FIG. 6, the discharge tube inverter circuit according to the second embodiment of the present invention is provided with a voltage feedback error amplifier 51. The voltage feedback error amplifier 51 is input to the inverting input unit 51a. The applied voltage signal 55 of the discharge tube 9 is compared with a predetermined set value Vc, and an output voltage 52 corresponding to the applied voltage to the discharge tube 9 is output to the PWM circuit 8. Further, the protect circuit 50 has a comparator circuit therein, and is connected to an output voltage 52 from the voltage feedback error amplifier 51 and a resistor 57 provided in series with the output side of the transformer 1 to output a transformer output current signal. 53 is entered. The applied voltage signal 55 is a voltage obtained by dividing the voltage at the connection portion between the capacitors 31 and 32 provided in series on the output side of the transformer 1 by the resistors 58 and 59.

  The configuration and operation other than the voltage feedback error amplifier 51 and the protection circuit 50 in the discharge tube inverter circuit of the second embodiment related to the present invention are the same as those of the discharge tube inverter circuit of the first embodiment related to the present invention. Therefore, explanation is omitted.

  Next, operations of the voltage feedback error amplifier 51 and the protection circuit 50 in the discharge tube inverter circuit according to the second embodiment of the present invention will be described.

  As shown in FIG. 6, when the applied voltage signal 55 of the discharge tube 9 is input to the inverting input section 51a, the voltage feedback error amplifier 51 compares the applied voltage signal 55 with a predetermined set value Vc to output voltage. 52 is output to the PWM circuit 8 and feedback control of the voltage applied to the discharge tube 9 is performed. Therefore, for example, when the discharge tube 9 is not connected or when there is a connection failure, the open circuit voltage can be set to a set value.

  For example, when the discharge tube 9 is not connected or when the connection is poor, the secondary output voltage of the transformer 1 may become an abnormal value. In this case, the protect circuit 50 outputs the voltage feedback error amplifier 51 output. When the voltage 52 or the transformer output current signal 53 is compared with the reference voltage of the comparator circuit in the protect circuit 50 and exceeds the reference voltage, the operation of the logic circuit 29 is stopped, the overcurrent to the discharge tube 9 and the transformer Overvoltage to 1 can be prevented. The protect circuit 50 can also receive the output voltage 12 of the error amplifier 11 and prevent overcurrent to the discharge tube 9 and overvoltage to the transformer 1.

  On the other hand, the slow start circuit 34 outputs a start signal 56 having a relatively gentle start to the PWM circuit 8 to prevent an instantaneous overvoltage from occurring at the start. In order to cope with the occurrence of an instantaneous overvoltage due to some cause, the protect circuit 50 causes the logic circuit 29 when the output voltage 52 or the output voltage 12 exceeds a predetermined value after a predetermined time set by a built-in timer. The operation is stopped so that the operation of the logic circuit 29 is not erroneously stopped.

  The protect circuit 50 stops the operation of the logic circuit 29 when the transformer output current signal 53 to be input exceeds the reference voltage of the built-in comparator circuit and becomes abnormal, and the transformer 1 and each circuit are damaged. To prevent.

  As described above, the discharge tube inverter circuit according to the second embodiment related to the present invention has the effects of the overcurrent to the discharge tube 9 in addition to the effects of the discharge tube inverter circuit according to the first embodiment related to the present invention. It is possible to easily prevent overvoltage to the transformer 1 and prevent damage to the transformer 1 and each circuit.

It is a block diagram of the inverter circuit for discharge tubes of 1st Embodiment in connection with this invention. It is a block diagram of the burst circuit used for the inverter circuit for discharge tubes concerning this invention. In the inverter circuit for a discharge tube according to the embodiment of the present invention, the frequency characteristic of the admittance | Y | on the primary side of the transformer and the frequency characteristic of the phase difference θ between the voltage and current when the resonant circuit is formed on the secondary side. . It is an operation | movement timing chart figure of the inverter circuit for discharge tubes of embodiment concerning this invention. It is a timing chart figure of the gate signal in the inverter circuit for discharge tubes of the embodiment concerning the present invention. It is a block diagram of the inverter circuit for discharge tubes of 2nd Embodiment in connection with this invention.

Explanation of symbols

1 transformer 2LCD unit (liquid crystal display unit)
DESCRIPTION OF SYMBOLS 3 Parasitic capacitance 4 Oscillation circuit 8 PWM circuit 11 Error amplifier 14, 15 Counter circuit 17 H bridge circuit 22 Burst circuit 29 Logic circuit 30, 50 Protection circuit 51 Error amplifier for voltage feedback

Claims (6)

An electromagnetic transformer comprising a discharge tube as a backlight of a liquid crystal display device, a resonance circuit formed on the secondary side by a parasitic capacitance generated in the discharge tube connected to the secondary side;
A frequency that is less than a resonance frequency of the resonance circuit and in which a phase difference between a voltage and a current on a primary side of the electromagnetic transformer is within a predetermined range from a minimum point is generated by an oscillation circuit, and the electromagnetic transformer is generated at the frequency. A separately-excited inverter circuit for the discharge tube having an H-bridge circuit composed of four switches for driving the primary side of
The H bridge circuit is configured by connecting a series circuit of switches composed of PMOS and NMOS in parallel, and the ON times of the gate signal waveforms for operating the PMOS switches are the same. A liquid crystal display unit characterized in that the ON times of the gate signal waveforms to be operated are the same.   The predetermined range is less than the resonance frequency of the resonance circuit formed on the secondary side, and the phase difference between the voltage and current on the primary side of the transformer is in the range of −30 ° from the minimum point. The liquid crystal display unit according to claim 1, wherein the liquid crystal display unit is in a frequency range.   2. The liquid crystal display unit according to claim 1, wherein the PMOS gate signal is inputted through a delay circuit.   The rise of the gate signal of the switch composed of the two PMOSs is alternately performed for each apex on the upper limit side of the predetermined triangular wave, and the rise of the gate signal of the switch composed of the two NMOSs is performed on the lower limit side of the predetermined triangular wave The liquid crystal display unit according to claim 1, wherein the liquid crystal display unit is alternately performed at each vertex.   The fall of the gate signal of the two NMOS switches is performed at a cross point between a predetermined triangular wave and the output voltage of the error amplifier, and the fall of the gate signal of the two PMOS switches is caused by the NMOS. 2. The liquid crystal display unit according to claim 1, wherein the liquid crystal display unit is delayed from a fall of a gate signal of the switch. An electromagnetic transformer comprising a discharge tube as a backlight of a liquid crystal display device, a resonance circuit formed on the secondary side by a parasitic capacitance generated in the discharge tube connected to the secondary side;
A frequency that is less than a resonance frequency of the resonance circuit and in which a phase difference between a voltage and a current on a primary side of the electromagnetic transformer is within a predetermined range from a minimum point is generated by an oscillation circuit, and the electromagnetic transformer is generated at the frequency. A separately-excited inverter circuit for the discharge tube having an H-bridge circuit composed of four switches for driving the primary side of
The H-bridge circuit is configured by connecting a series circuit of switches composed of PMOS and NMOS in parallel, and a driving timing of the H-bridge circuit is provided with a timing at which only one switch is turned on. unit.

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