JP2007234226A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which entry of noise superimposed on an external clock signal supplied from the outside can be prevented and cross talk noise between a DQ signal output to the outside and an external clock signal can be suppressed. <P>SOLUTION: The semiconductor device is provided with an external clock terminal 55-1, an output terminal 52-1, and a reversed output terminal 52-2. An external clock signal is input to the external clock terminal 55-1 from the outside. The output terminal 52-1 is arranged at the vicinity of the external clock terminal 55-1 and output a data signal DQ1 indicating data to the outside. The reversed output terminal 52-2 is arranged at the vicinity of the output terminal 52-1 and the external clock terminal 55-1 and outputs a reversed data signal DQ1B to which the data signal DQ1 is reversed to the outside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a clock terminal, such as a DRAM, for inputting and outputting data.

A clock signal in a DRAM will be described as an example of a conventional semiconductor device having a clock terminal and inputting / outputting data.
FIG. 9 is a block diagram showing a configuration of a conventional DRAM. FIG. 9 shows a configuration related to a clock signal. The DRAM 101 includes a clock input buffer 103, a DRAM core 104, a DQ output unit 105, and a DLL (Delayed Locked Loop) 106.

The clock input buffer 103 receives an external clock signal transmitted from the outside of the DRAM 101. The external clock signal is output as it is (or amplified) to the DRAM core 104 and DLL 106 as an internal clock signal.
The DRAM core 104 performs operations such as data reading, writing, and erasing based on the internal clock signal. In particular, when a read operation is performed, an output signal (read data) is output to the DQ output unit 105 as a DQ signal.
The DLL 106 delays the internal clock signal by a predetermined delay time based on the internal clock signal, and outputs it again to the DQ output unit 105 as an internal clock signal.
The DQ output unit 105 outputs the DQ signal to the outside of the DRAM 101 at the timing of the internal clock signal output from the DLL 106.

  A DQ terminal that is an output terminal for outputting a DQ signal from the DRAM 101 is located close to a CLK terminal that is an input terminal for inputting an external clock signal to the DRAM 101. Therefore, when data is read from the DRAM 101, crosstalk may occur between the DQ terminal (or its vicinity) and the CLK terminal (or its vicinity). In that case, the timing noise of the external clock signal input to the DRAM 101 increases due to the in-phase component crosstalk noise of the DQ signal at the time of data reading.

In a semiconductor device having a clock terminal such as a DRAM and inputting / outputting data, there is a demand for a technique for preventing the influence of noise on a clock signal supplied from the outside.
In a semiconductor device having an external clock terminal such as a DRAM and inputting / outputting data, a technique for suppressing the influence of crosstalk between a data output signal output to the outside and a clock signal supplied from the outside is desired. It is rare.

JP-A-11-249642

Accordingly, an object of the present invention is to provide a semiconductor device that is not affected by noise on a clock signal supplied from the outside.
Another object of the present invention is to provide a semiconductor device capable of suppressing the influence of crosstalk between a data output signal output to the outside and a clock signal supplied from the outside.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the embodiments of the present invention. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Embodiments of the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

Therefore, in order to solve the above problems, the semiconductor device of the present invention includes an internal clock generation unit (2) and a data management unit (4).
The internal clock generator (2) outputs an internal clock signal (CLK) controlled in synchronization with the external clock signal (CLK0) based on the external clock signal (CLK0). The data management unit (4) performs data processing using the internal clock signal (CLK).
The data management unit (4) controls the synchronization control in the internal clock generation unit (2) based on the operation.
The data processing includes data reading, writing, and erasing.

  In the semiconductor device of the present invention, when the operation is data reading, the data management unit (4) controls the internal clock generation unit (2) so as to interrupt or suppress the synchronization control.

In addition, the semiconductor device of the present invention includes an internal clock generation unit (2) and a data management unit (4).
The internal clock generator (2) outputs an internal clock signal (CLK) controlled in synchronization with the external clock signal (CLK0) based on the external clock signal (CLK0). The data management unit (4) performs data processing using the internal clock signal (CLK).
The internal clock generator (2) self-oscillates the internal clock signal (CLK) when the operation is data reading.

  In the semiconductor device of the present invention, the data management unit (4) outputs a control signal (CTS) for controlling the internal clock generation unit (2) based on the operation. Then, the internal clock generator (2) performs the synchronization control based on the control signal (CTS).

  In the semiconductor device of the present invention, the internal clock generator (2) includes a phase-locked loop circuit (PLL).

Furthermore, in the semiconductor device of the present invention, the internal clock generation unit (2) includes a synchronization determination unit (11), an oscillation control unit (12), and a control oscillation unit (13).
The synchronization determination unit (11) is based on the internal clock signal (CLK) and the external clock signal (CLK0), and indicates a synchronization determination signal (PD1) indicating a synchronization state between the internal clock signal (CLK) and the external clock signal (CLK0). , PD2). The oscillation control unit (12) outputs an oscillation control signal (CT) for controlling the characteristics of the internal clock signal (CLK) based on the synchronization determination signals (PD1, PD2) and the control signal (CTS). The control oscillation unit (13) outputs a new internal clock signal (CLK) based on the oscillation control signal (CT).
Then, the control oscillation unit (13) outputs a new internal clock signal (CLK) to the synchronization determination unit (11).

Furthermore, the semiconductor device of the present invention includes an external clock terminal (55-1), an output terminal (52-1 / 53-1 / 54-1), and an inverted output terminal (52-2 / 53-2 / 54-). 2).
The external clock terminal (55-1) receives an external clock signal (CLK0) from the outside. The output terminal (52-1 / 53-1 / 54-1) is disposed in the vicinity of the external clock terminal (55-1), and outputs a data signal (DQ1 / DQ2 / DQ3) indicating data to the outside. The inverting output terminal (52-2 / 53-2 / 54-2) is arranged in the vicinity of the output terminal (52-1 / 53-1 / 54-1) and the external clock terminal (55-1), and data An inverted data signal (DQ1B / DQ2B / DQ3B) obtained by inverting the signal (DQ1 / DQ2 / DQ3) is output to the outside.

  Furthermore, the semiconductor device of the present invention has a distance between the output terminal (52-1 / 53-1 / 54-1) and the external clock terminal (55-1), and an inverted output terminal (52-2 / 53-2). / 54-2) and the external clock terminal (55-1) are equal in distance within a preset range.

Further, the semiconductor device of the present invention is disposed in the vicinity of the external clock terminal (55-1), and is an inverted external clock terminal that receives an inverted external clock signal (CLK0B) obtained by inverting the external clock signal (CLK0) from the outside. (55-2).
The distance between the output terminal (52-1 / 53-1 / 54-1) and the set of the external clock terminal (55-1) and the inverted external clock terminal (55-2), and the inverted output terminal (52- The distance between 2 / 53-2 / 54-2) and the pair is equal within a preset range of difference.

  Furthermore, the semiconductor device of the present invention transfers the inverted data signal (DQ1B / DQ2B / DQ3B) to the inverted output terminal (52-2 / 53-2 / 54-2) based on the data signal (DQ1 / DQ2 / DQ3). An inverted data signal output unit (62) for outputting is further provided.

  Furthermore, in the semiconductor device of the present invention, the inverting output terminal (52-2 / 53-2 / 54-2) is terminated (67) in the vicinity of the inverting output terminal (52-2 / 53-2 / 54-2). Has been.

  According to the present invention, it is possible to prevent intrusion of noise on an external clock signal supplied from the outside, and to suppress crosstalk noise between the DQ signal output to the outside and the external clock signal.

  Embodiments of a semiconductor device according to the present invention will be described below with reference to the accompanying drawings.

First, the configuration of an embodiment of a DRAM to which a semiconductor device according to the present invention is applied will be described.
FIG. 1 is a block diagram showing the configuration of an embodiment of a DRAM to which a semiconductor device according to the present invention is applied. FIG. 1 shows a configuration related to a clock signal.

A DRAM to which a semiconductor device according to the present invention is applied includes an internal clock signal generation circuit (PLL) in the DRAM. Then, the external clock signal and the internal clock signal are isolated from each other, and the operation is performed using the internal clock signal whose oscillation is controlled so as to be synchronized with the external clock. In addition, the oscillation control of the internal clock generation circuit is stopped (or suppressed) at the time of reading (data reading), and the internal clock signal is protected from the clock noise of the external clock signal generated at the time of reading.
In addition, a DQB terminal (and a DQB output unit for generating a DQB signal) that outputs a DQB signal that is an inverted signal thereof is provided in the vicinity of the DQ terminal for the DQ signal provided around the terminal for the external clock signal. Since the crosstalk noise to the external clock signal due to the DQ signal cancels the crosstalk noise due to the DQB signal, the crosstalk noise in the external clock signal can be reduced.

Each configuration of FIG. 1 will be described.
The DRAM 1 includes a PLL (Phase Locked Loop) 2, a clock input buffer 3, a DRAM core 4, a DQ output unit 5, and a DLL (Delayed Locked Loop) 6.
Based on the external clock signal CLK0 input from the outside of the DRAM 1, the clock input buffer 3 outputs an external clock buffer signal CLK_INBUF as it is (or amplified) to the PLL 2 as it is (or amplified).
The PLL 2 outputs an internal clock signal CLK to the DRAM core 4 and the DLL 6 based on an external clock buffer signal CLK_INBUF and an oscillation control fixed signal CTS (described later).
The DRAM core 4 uses the internal clock signal CLK and performs operations such as data reading, writing, and erasing based on a control signal (not shown). At that time, the oscillation control fixed signal CTS is output to the PLL2. When data is read, a data output signal DQ_DATA as read data is output to the DQ output unit 5.
The DLL 6 outputs a delayed internal clock signal CLK_DOUT obtained by delaying the internal clock signal CLK by a predetermined delay time to the DQ output unit 5 based on the internal clock signal CLK.
Based on the data output signal DQ_DATA and the delayed internal clock signal CLK_DOUT, the DQ output unit 5 outputs the data output signal DQ_DATA to the outside of the DRAM 1 as DQ_OUT at the timing of the delayed internal clock signal CLK_DOUT.

  PLL2 is a clock generation circuit. In DRAM 1, an internal clock signal CLK synchronized with an external clock buffer signal CLK_INBUF that is synchronized with an external clock signal CLK0 is generated. The PLL 2 includes a synchronization determination unit 11, an oscillation control unit 12, and a control oscillation unit 13.

FIG. 2 is a circuit diagram illustrating a configuration of the synchronization determination unit 11.
The synchronization determination unit 11 outputs a synchronization determination signal PD1 and a synchronization determination signal PD2 based on the internal clock signal CLK and the external clock buffer signal CLK_INBUF. The synchronization determination unit 11 includes delay circuits A21-1 to 21-2, delay circuits B22-1 to 22-2, and D flip-flops 23-1 to 23-2.

  The delay circuit A 21-1 and the delay circuit A 21-2 receive the internal clock signal CLK and the external clock buffer signal CLK_INBUF, respectively, and delay the signals. Then, delayed signals are output to the D flip-flop 23-1 and the D flip-flop 23-2, respectively. The delay circuit A21-1 and the delay circuit A21-2 have the same configuration and have the same delay time.

  The delay circuit B22-1 and the delay circuit B22-2 are inputted with the external clock buffer signal CLK_INBUF and the internal clock signal CLK, respectively, and delay the signals. Then, delayed signals are output to the D flip-flop 23-2 and the D flip-flop 23-1, respectively. The delay circuit B22-1 and the delay circuit B22-2 have the same configuration as the delay circuit A21-1 and the delay circuit A21-2, but have different circuit constants. That is, the delay time is designed to be more delayed (large delay time).

  The outputs of the delay circuit A21-1 and the delay circuit B22-2 are input to the D terminals of the D flip-flop 23-1 and the D flip-flop 23-2, respectively. Further, the delay circuit B22-1 and the delay circuit A21-2 are input to the Clk terminals, respectively. Based on the inputs of the D terminal and the Clk terminal, the D flip-flop 23-1 and the D flip-flop 23-2 output the synchronization determination signal PD1 and the synchronization determination signal PD2 from the Q terminal, respectively.

  The internal clock signal CLK is judged to be “fast” in the D flip-flop 23-1 by the difference in delay time in the delay circuit in the preceding stage of the D flip-flop, and the internal clock signal CLK is “slow” in the D flip-flop 23-2. Judged by trend. In other words, when the rising timing of the internal clock signal CLK and the external clock buffer signal CLK_INBUF is “just”, the D flip-flop 1 is “fast” and the D flip-flop 2 is “slow”. Determined.

FIG. 3 is a circuit diagram showing a configuration of the oscillation control unit 12.
The oscillation control unit 12 outputs an oscillation control signal CT (analog) based on the synchronization determination signal PD1 and the synchronization determination signal PD2 output from the synchronization determination unit 11 and the oscillation control fixed signal CTS. The oscillation control unit 12 includes a control circuit 25, a charge pump 26, and a buffer 27.

  The control circuit 25 outputs a pump control signal PCS1 and a pump control signal PCS2 for controlling the charge pump based on the inputs of the synchronization determination signal PD1, the synchronization determination signal PD2, and the oscillation control fixed signal CTS. The control circuit 25 includes a NOR gate 30-2, a NOR gate 30-3, and an inverter 30-1. The NOR gate 30-2 outputs a pump control signal PCS1 based on the synchronization determination signal PD1 and the oscillation control fixed signal CTS. The NOR gate 30-3 outputs the pump control signal PCS2 based on the output of the inverter 30-1 to which the synchronization determination signal PD2 is input and the oscillation control fixed signal CTS.

  The charge pump 26 outputs an output voltage Vs based on the input of the pump control signal PCS1 and the pump control signal PCS2. The charge pump 26 includes a current source 31-1, a current source 31-2, and a charge pump capacitor 37. The current source 31-1 charges the charge pump capacitor 37 (push current) based on the pump control signal PCS 1. The current source 31-2 discharges the charge pump capacitor 37 (draws current) based on the pump control signal PCS2. The charge pump capacitor 37 generates a potential based on the charge capacity to be charged / discharged at the connection point b. The potential is the output voltage Vs.

The current source 31-1 includes an inverter 32-1, a MOS transfer gate 33-1, a P-type MOS transistor 34-1, a P-type MOS transistor 35-1, and an N-type MOS transistor 36-1.
The inverter 32-1 has an input side connected to the output side (pump control signal PCS1 side) of the control circuit 25 and an output side connected to the gate of the P-type MOS transistor of the MOS transfer gate.
The MOS transfer gate 33-1 has the output side of the control circuit 25 (pump control signal PCS1 side) as the gate of the N-type MOS transistor, the output side of the inverter 32-1 as the gate of the P-type MOS transistor, and the P-type as the source. The drain of the MOS transistor 34-1 is connected to the connection point a to the drain.
In the P-type MOS transistor 34-1, the power supply Vcc is connected to the source, the gate of the P-type MOS transistor 35-1 is connected to the gate, and the source of the MOS transfer gate 33-1 is connected to the drain.
In the P-type MOS transistor 35-1, the power source Vcc is connected to the source, the gate of the P-type MOS transistor 34-1 is connected to the gate, and the gate of the P-type MOS transistor 35-1 is connected to the source of the N-type MOS transistor 36-1. .
The N-type MOS transistor 36-1 has a source connected to the drain of the P-type MOS transistor 35-1, a gate connected to its own source, and a drain connected to ground.

The current source 31-2 includes an inverter 32-2, a MOS transfer gate 33-2, an N-type MOS transistor 34-2, a P-type MOS transistor 35-2, and an N-type MOS transistor 36-2.
The inverter 32-2 has an input side connected to the output side (pump control signal PCS2 side) of the control circuit 25 and an output side connected to the gate of the P-type MOS transistor of the MOS transfer gate.
The MOS transfer gate 33-2 is connected to the output side of the control circuit 25 (pump control signal PCS2 side) at the gate of the N-type MOS transistor, the output side of the inverter 32-2 at the gate of the P-type MOS transistor, and the connection point to the source. The source of the N-type MOS transistor 34-2 is connected to the drain a.
In the N-type MOS transistor 34-2, the source is connected to the drain of the MOS transfer gate 33-2, the gate is connected to the gate of the N-type MOS transistor 36-2, and the drain is connected to the ground.
In the P-type MOS transistor 35-2, the power supply Vcc is connected to the source, the drain of the P-type MOS transistor 35-2 is connected to the gate, and the source of the N-type MOS transistor 36-2 is connected to the drain.
The N-type MOS transistor 36-2 has a source connected to the drain of the P-type MOS transistor 35-2, a gate connected to its own source and the gate of the N-type MOS transistor 34-2, and a drain connected to the ground.

  In the charge pump capacitor 37, one is connected to the connection point b on the wiring connecting the connection point a of the charge pump 26 and the buffer 27, and the other is connected to the ground.

The buffer 27 outputs an oscillation control signal CT based on the output voltage Vs. The buffer 27 includes an N-type MOS transistor 41, an N-type MOS transistor 42, a P-type MOS transistor 43, and a P-type MOS transistor 44.
In the N-type MOS transistor 41, the drain of the P-type MOS transistor 43 is connected to the source, the connection point b is connected to the gate, and the ground is connected to the drain.
The P-type MOS transistor 43 has a source connected to the power supply Vcc, a gate connected to the gate of the P-type MOS transistor 44 and its own drain, and a drain connected to the source of the N-type MOS transistor 41.
In the N-type MOS transistor 42, the drain of the P-type MOS transistor 44 and its gate are connected to the source, the output terminal (connected to the control oscillation unit 13) is connected to the gate, and the ground is connected to the drain.
In the P-type MOS transistor 44, the power source Vcc is connected to the source, the gate of the P-type MOS transistor 43 is connected to the gate, and the source of the N-type MOS transistor 42 is connected to the drain.

FIG. 4 is a circuit diagram showing a configuration of the control oscillation unit 13.
The control oscillator 13 generates an internal clock signal CLK whose frequency and phase are controlled and its inverted signal CLKB based on the oscillation control signal CT. Then, they are output to the synchronization determination unit 11, the DRAM core 4 and the DLL 6. The control oscillation unit 13 includes a variable delay circuit 46 and buffers 50-1 to 50-2. The variable delay circuit 46 includes a plurality of unit circuits 46-i (i = 1 to n, n is an odd number, the same applies hereinafter).

  FIG. 5 is a circuit diagram showing the configuration of the unit circuit 46-i of the variable delay circuit 46. The unit circuit 46-i has two input terminals CIN and its input terminals CIIN to which the input signal CIN and its inverted signal CINB are input, and a bias input terminal CBIAS to which the signal CBIAS for controlling the unit circuit 46-i is input. , Two output terminals COUTB and COUTB for outputting the output signal COUTB and its inverted signal COUT, respectively. P-type MOS transistors 47-1 and 47-2 and N-type MOS transistors 48-1, 48-2 and 49 are provided.

In the P-type MOS transistor 47-1, the power supply Vcc is connected to the source, the output terminal COUT is connected to the gate, and the output terminal COUTB is connected to the drain.
In the N-type MOS transistor 48-1, the output terminal COUTB is connected to the source, the input terminal CIN is connected to the gate, and the source of the N-type MOS transistor 49 is connected to the drain.
In the P-type MOS transistor 47-2, the power supply Vcc is connected to the source, the output terminal COUTB is connected to the gate, and the output terminal COUT is connected to the drain.
In the N-type MOS transistor 48-2, the output terminal COUT is connected to the source, the input terminal CINB is connected to the gate, and the source of the N-type MOS transistor 49 is connected to the drain.
The N-type MOS transistor 49 has a source connected to the drains of the N-type MOS transistors 48-1 and 48-2, a gate connected to the bias input terminal, and a drain connected to the ground.

  The variable delay circuit 46 connects the input terminal CIN and the input terminal CINB of the unit circuit 46-i to the output terminal COUTB and the output signal COUT of the variable delay circuit 46-i + 1, respectively. Then, an odd-stage connection configuration using unit circuits 46-i as shown in FIG.

  The buffers 50-1 to 50-2 output the internal clock signal CLK and its inverted signal CLKB to the synchronization determination unit 11, the DRAM core 4, and the DLL 6, respectively.

The DRAM core 4 performs operations such as data writing, reading, and erasing based on external control. At this time, the internal clock signal CLK generated by the PLL 2 is input in the same manner as the conventional internal clock signal, and the operation is performed in the same manner as the conventional one based on the internal clock signal CLK.
The DRAM core 4 has an oscillation control fixed signal output unit (not shown) inside.
The oscillation control fixed signal output unit outputs an oscillation control fixed signal CTS to the PLL 2 according to the type of operation required for the DRAM core 4. That is, when a signal indicating an operation command is input to the DRAM core 4, the signal is also input to the oscillation control fixed signal output unit. When the operation command is a command for reading data in the DRAM 1, the oscillation control fixed signal output unit outputs the oscillation control fixed signal CTS to the PLL 2 at “H”. In other cases, the oscillation control fixed signal CTS is output at “L”.

The DLL 6 outputs to the DQ output unit 5 as a delayed internal clock signal CLK_DOUT obtained by delaying the internal clock signal CLK by a predetermined delay time based on the internal clock signal CLK.
Based on the data output signal DQ_DATA and the delayed internal clock signal CLK_DOUT, the DQ output unit 5 outputs the data output signal DQ_DATA to the outside as DQ_OUT at the timing of the delayed internal clock signal CLK_DOUT.

FIG. 6 is a block diagram showing a configuration around the DQ output unit 5. The DQ output unit 5 includes a DQ output unit 61, a DQB output unit 62, a buffer 63, a DQ1 terminal 52-1, a DQ1B terminal 52-2, a wiring 65-1, a wiring 65-2, and a termination 67.
Based on the data output signal DQ_DATA and the delayed internal clock signal CLK_DOUT, the DQ output unit 61 outputs the data output signal DQ_DATA as DQ_OUT at the timing of the delayed internal clock signal CLK_DOUT.
The DQ1 terminal 52-1 outputs the data output signal DQ_OUT output from the DQ output unit 61 to the wiring 65-1 outside the DRAM 1.
The wiring 65-1 transmits the data output signal DQ_OUT to a predetermined circuit element.
Based on DQB_DATA that is an inverted signal of the data output signal DQ_DATA output from the buffer 63 and the delayed internal clock signal CLK_DOUT, the DQB output unit 62 converts the inverted signal DQB_DATA of the data output signal to DQB_OUT at the timing of the delayed internal clock signal CLK_DOUT. Output.
The DQ1B terminal 52-2 outputs DQB_OUT output from the DQB output unit 62 to the wiring 65-2 outside the DRAM 1.
The wiring 65-2 transmits DQB_OUT to the termination 67, which is a termination circuit. The wiring 65-2 is short and a termination 67 is provided in the vicinity of the DRAM 1. Circuit constants are set for the wiring 65-2 and the termination 67 so that impedance is matched and reflection does not occur.

FIG. 7 is a diagram illustrating an example of the terminal arrangement of the DQ terminal and the CLK terminal.
7 includes three DQ terminals (DQ1 terminal 52-1, DQ2 terminal 53-1, DQ1 terminal 54-1) and three DQB terminals (DQ1B terminal 52-2, DQ2B terminal 53-2, DQ1B terminal 54). -2), CLK terminal 55-1, CLKB terminal 55-2, lead 55 and pad 56.
The CLK terminal 55-1 is used when inputting the external clock signal CLK to the DRAM 1. The CLKB terminal 55-2 is used when an inverted signal CLK0B of the external clock signal CLK0 is input to the DRAM 1. The crosstalk noise of the external clock signal CLK0 is reduced by inputting the inverted signals at the same time.
Each of the three DQ terminals (DQ1 terminal 52-1, DQ2 terminal 53-1, DQ3 terminal 54-1) outputs an output signal (DQ1_OUT, DQ2_OUT, DQ3_OUT) from the DQ output unit 61 to the outside. Use. Each of the three DQB terminals (DQ1B terminal 52-2, DQ2B terminal 53-2, DQ1B terminal 54-2) is used when outputting inverted signals (DQ1B_OUT, DQ2B_OUT, DQ3B_OUT) of output signals to the outside. The three DQB terminals are connected to a termination circuit (termination 67) outside the chip (DRAM1).
By simultaneously outputting the inversion signals, crosstalk noise in each output signal (DQ1_OUT, DQ2_OUT, DQ3_OUT) is canceled. That is, crosstalk noise can be reduced. At the same time, crosstalk noise generated between the CLK terminal (and the CLKB terminal) and the DQ terminals existing in the vicinity of each DQ terminal is canceled out. That is, crosstalk noise can be reduced.

  In FIG. 7A, in order to enhance the above effect, the DQ1 terminal 52-1 and the DQ1B terminal 52-2 are set in advance for the set of (CLK terminal 55-1 and CLKB terminal 55-2). They are arranged to be equidistant within the range of differences. The same applies to the DQ2 terminal 53-1, the DQ2B terminal 53-2, the DQ3 terminal 54-1, and the DQ1B terminal 54-2.

  In FIG. 7B, in order to enhance the above effect, the DQ1 terminal 52-1 and the DQ1B terminal 52-2 are adjacent to each other, and a set of (CLK terminal 55-1 and CLKB terminal 55-2). On the other hand, the DQ1 terminal 52-1 and the DQ1B terminal 52-2 are arranged so as to be equidistant within a preset range of difference. The same applies to the DQ2 terminal 53-1, the DQ2B terminal 53-2, the DQ3 terminal 54-1, and the DQ1B terminal 54-2.

In this case, the preset range of difference is the distance between adjacent output terminals.
For example, the distance s1 between the set of (CLK terminal 55-1 and CLKB terminal 55-2) and the DQ1 terminal 52-1, and the set of (CLK terminal 55-1 and CLKB terminal 55-2) and the DQ1B terminal 52- 2 is considered, s1-s2 ≦ DQ1 terminal 52-1-DQ1B terminal 52-2 distance.

  As for the DQ terminal in FIG. 7, an output terminal (DQB terminal) for an inverted signal is provided for the three DQ terminals, but the present invention is not limited to three cases.

  Next, the operation of the embodiment of the DRAM to which the semiconductor device according to the present invention is applied will be described with reference to FIGS.

  Referring to FIG. 1, external clock signal CLK0 is input to DRAM1. Then, based on the external clock signal CLK0, the clock input buffer 3 transmits the external clock buffer signal CLK_INBUF to the synchronization determination unit 11 of the PLL2.

Next, the operation of the synchronization determination unit 11 will be described with reference to FIG.
The synchronization determination unit 11 compares the rising timings of the external clock buffer signal CLK_INBUF and the internal clock signal CLK (generated by the control oscillation unit 13) after the external clock signal CLK0 has passed through the clock input buffer 3.

  In the synchronization determination unit 11, first, the internal clock signal CLK passes through the delay circuit A21-1 and enters the D terminal of the D flip-flop 23-1. On the other hand, the external clock buffer signal CLK_INBUF passes through the delay circuit B22-1 and enters the Clk terminal of the D flip-flop 23-1. Here, if the rising timing of the external clock buffer signal CLK_INBUF is faster than the rising timing of the internal clock (fast), the synchronization determination signal PD1 output from the Q terminal of the D flip-flop 23-1 becomes “H”. If the rising timing of the external clock buffer signal CLK_INBUF is sufficiently slower than the rising timing of the internal clock (slow), the synchronization determination signal PD1 output from the Q terminal of the D flip-flop 23-1 becomes “L”.

The internal clock signal CLK passes through the delay circuit B22-2 and enters the D terminal of the D flip-flop 23-2. On the other hand, the external clock buffer signal CLK_INBUF passes through the delay circuit A 21-2 and enters the Clk terminal of the D flip-flop 23-2. Here, if the rising timing of the external clock buffer signal CLK_INBUF is sufficiently faster than the internal clock rising timing (fast), the synchronization determination signal PD2 output from the Q terminal of the D flip-flop 23-2 becomes “H”. If the rising timing of the external clock buffer signal CLK_INBUF is slower than the rising timing of the internal clock (slow), the synchronization determination signal PD2 output from the Q terminal of the D flip-flop 2 becomes “L”.
The synchronization determination signal PD1 and the synchronization determination signal PD2 are output to the oscillation control unit 12.

Next, the operation of the oscillation control unit 12 will be described with reference to FIG.
(1) When the oscillation control fixed signal CTS is “L” in the oscillation control unit 12, when (PD1, PD2) = (H, H), the outputs (PCS1, PCS2) of the control circuit 25 are (H, L ) For this reason, the push-side switch (MOS transfer gate 33-1) of the charge pump 26 is turned ON, and the extraction side switch (MOS transfer gate 33-2) is turned OFF. Accordingly, the charge pump capacitor 37 is charged, and the output voltage Vs of the charge pump 26 increases. As the output voltage Vs increases, the signal voltage of the oscillation control signal CT increases via the buffer 27.
When (PD1, PD2) = (L, L), the outputs (PCS1, PCS2) of the control circuit 25 are (L, H). Therefore, the pushing side switch of the charge pump 26 is turned OFF and the drawing side switch is turned ON. Accordingly, the charge pump capacitor 37 is discharged, and the output voltage Vs of the charge pump 26 decreases. As the output voltage Vs decreases, the oscillation control signal CT decreases via the buffer 27.
When (PD1, PD2) = (H, L), the outputs (PCS1, PCS2) of the control circuit 25 are (L, L). Therefore, both the pushing side and the drawing side switches of the charge pump 26 are turned off. Accordingly, the charge pump capacitor 37 is held and the output voltage Vs of the charge pump is fixed. Thereby, the signal voltage of the oscillation control signal CT is also fixed via the buffer 27.

(2) When the oscillation control fixed signal CTS is “H” in the oscillation control unit 12 In any case, the outputs (PCS1, PCS2) of the control circuit 25 are (L, L). Therefore, both the pushing side and the drawing side switches of the charge pump 26 are turned off. Accordingly, the charge pump capacity 37 is held, and the output voltage Vs of the charge pump 26 is fixed at a constant level. Thereby, the signal voltage of the oscillation control signal CT is also fixed via the buffer 27.
The oscillation control signal CT (analog) is output to the control oscillation unit 13 by (1) or (2).

Next, the operation of the control oscillation unit 13 will be described with reference to FIG. 4 and FIG.
The unit circuit 46-i in FIG. 5 is an oscillation circuit. Based on CIN, CINB and a signal (analog, CBIAS) for controlling oscillation, the signal oscillates at a frequency corresponding to CBIAS, and outputs an output signal COUTB and an output signal COUT. The unit circuit 46-i is a differential pair. The delay time becomes shorter when CBIAS which is the bias voltage of the N-type MOS transistor 49 is higher, and becomes longer when CBIAS is lower. After the input of CIN and CINB, the output signal COUTB and the output signal COUT are output after the delay time.

In the control oscillator 13, the signal for controlling the oscillation is the oscillation control signal CT.
Therefore, the oscillation control signal CT is input to each unit circuit 46-i. When the voltage of the oscillation control signal CT increases, the oscillation frequency increases. That is, the variable delay circuit 46 generates the internal clock signal CLK having a higher frequency than before and the inverted signal CLKB. Further, when the voltage of the oscillation control signal CT is lowered, the oscillation frequency is lowered. That is, the variable delay circuit 46 generates an internal clock signal CLK having a lower frequency than before and an inverted signal CLKB thereof.
When the voltage of the oscillation control signal CT is constant, the oscillation frequency does not vary. That is, the variable delay circuit 46 self-oscillates the internal clock signal CLK having a constant frequency and its inverted signal CLKB.
Then, the control oscillation unit 13 feeds back the internal clock signal CLK and its inverted signal CLKB to the input terminal of the variable delay circuit 46, and also through the buffers 47-1 to 47-2, the synchronization determination unit 11 and the DRAM core 4 And output to DLL6.

  Due to the synchronization determination unit 11, the oscillation control unit 12, and the control oscillation unit 13, the PLL built in the DRAM 1 of FIG. 1 of the present invention is the case where the oscillation control fixed signal CTS is “L”, and the internal clock signal CLK When the timing is later than the timing of the external clock buffer signal CLK_INBUF, the oscillation frequency of the control oscillation unit 13 is increased. Further, when the timing of the internal clock signal CLK is earlier than the timing of the external clock buffer signal CLK_INBUF, the oscillation frequency of the control oscillation unit 13 is delayed. When the timing of the internal clock signal CLK and the timing of the external clock buffer signal CLK_INBUF are the same, the oscillation frequency of the control oscillation unit 13 is not changed. When the oscillation control fixed signal CTS is “H”, the oscillation frequency of the control oscillation unit is not changed. The DRAM 1 sets the oscillation control fixed signal CTS to “H” in the Read mode (data reading) and maintains a constant value without changing the oscillation frequency of the control oscillation unit.

Therefore, the internal clock signal CLK synchronized with the external clock signal CLK0 can be generated inside the DRAM 1. Accordingly, the DRAM 1 can use the internal clock signal CLK that is not affected by the noise of the external clock signal CLK0.
In particular, when the oscillation control fixed signal CTS is set to “H” so that the DRAM 1 maintains a constant value without changing the oscillation frequency of the control oscillation unit 13 at the time of data reading, the internal clock signal CLK is used as the external clock signal at the time of data reading. It becomes possible not to be affected at all by the noise of CLK0.

The DRAM core 4 uses the internal clock signal CLK to perform operations such as data writing, reading, and erasing based on external control. At this time, the internal clock signal CLK generated by the PLL 2 is used in the same manner as the conventional internal clock, and the operation is performed as in the conventional case. However, normally, “L” is output as the oscillation control fixed signal CTS, and “H” is output to the PLL 2 when an instruction to read data in the DRAM 1 is received. The data output signal DQ_DATA is output to the DQ output unit 5.
The DLL 6 outputs a delayed internal clock signal CLK_DOUT obtained by delaying the internal clock signal CLK by a predetermined delay time to the DQ output unit 5 based on the internal clock signal CLK.

Next, the operation of the DQ output unit 5 will be described with reference to FIG.
The data output signal DQ_DATA is output from the DQ output unit 61 at the timing of the delayed internal clock signal CLK_DOUT, and is transmitted to the outside (wiring 65-1) via the DQ1 terminal 52-1. Similarly, the inverted signal DQB_DATA of the data output signal DQ_DATA is output from the DQB output unit 62 at the timing of the delayed internal clock signal CLK_DOUT and transmitted to the outside (wiring 65-2) via the DQ1B terminal 52-2. At that time, the data output signals DQ_DATA and DQB_DATA are output from the respective circuits at the same timing.

  Since signals of opposite phases are output from the wiring 65-1 (DQ1 terminal 52-1) and the wiring 65-2 (DQ1B terminal 52-2), respectively, they are arranged near the DQ1 terminal 52-1 and DQ1B terminal 52-2. The influence on the provided CLK terminal for the external clock signal CLK0 (see FIG. 7) and its peripheral wiring can be suppressed. That is, it is possible to cancel out the crosstalk noise included in the external clock signal CLK0.

  Since the DRAM of the present invention has a terminal for outputting a DQ output signal and an output signal of the opposite phase around the clock terminal, in particular, a DQ signal (data output signal) that affects the clock signal at the time of data reading (Read). DQ_DATA) can be canceled out, and noise on the external clock signal can be reduced.

In the above embodiment, when data is read from the DRAM core 4, the oscillation control fixing signal CTS is set to “H” from the DRAM core 4 to fix the oscillation control of the PLL2.
However, by suppressing the oscillation control without fixing the PLL2 oscillation control, it is possible to reduce the influence of the internal clock signal CLK from the noise of the external clock signal CLK0 when reading data. FIG. 8 shows an oscillation control unit having this function.

  FIG. 8 is a circuit diagram showing a configuration of the oscillation control unit 12 ′ that can suppress the oscillation control of the PLL 2. In this circuit, an auxiliary current source 28 is added to the oscillation control unit 12 of FIG. The auxiliary power supply 28 includes a current source 31-3 and a current source 31-4. The current source 31-3 and the current source 31-4 are the same as the current source 31-1 and the current source 31-2 except that the inputs are PD1 ′ and the synchronization determination signal PD2, which are inverted signals of the synchronization determination signal PD1, respectively. Therefore, the description thereof is omitted.

The auxiliary current source 28 is not affected by the oscillation control fixed signal CTS. Even when the oscillation control fixed signal CTS becomes “H”, the charge pump capacitor 37 can be charged / discharged based on the synchronization determination signals (PD1 ′ and PD2 ′).
In this case, since the charge pump capacitor 37 is charged / discharged with a current smaller than that when the control fixed signal CTS is “L”, the fluctuation amount of the oscillation control signal CT is suppressed. Therefore, the influence of the noise of the external clock signal CLK0 on the internal clock signal CLK can be reduced.

  In this embodiment, an example of a DRAM is described. However, the present invention is not limited to the DRAM, and a semiconductor device (LSI that has external clock terminals such as various memory LSIs (RAM exemplified by SRAM, ROM exemplified by flash memory) and inputs / outputs data. ) Can be applied.

It is a block diagram which shows the structure in embodiment of DRAM which applied the semiconductor device which is this invention. It is a circuit diagram which shows the structure of a synchronous determination part. It is a circuit diagram which shows the structure of an oscillation control part. It is a circuit diagram which shows the structure of a control oscillation part. It is a circuit diagram which shows the structure of the unit circuit of a variable delay circuit. It is a block diagram which shows the structure around a DQ output part. (A) (b) It is a figure which shows the example of terminal arrangement | positioning with a DQ terminal and a CLK terminal. It is a circuit diagram which shows the structure of an oscillation control part. It is a block diagram which shows the structure regarding the clock signal of the conventional DRAM.

Explanation of symbols

1 DRAM
2 PLL
3 Clock input buffer 4 DRAM core 5 DQ output section 6 DLL
DESCRIPTION OF SYMBOLS 11 Synchronization determination part 12 Oscillation control part 13 Control oscillation part 21-1 Delay circuit A
21-2 Delay circuit A
22-1 Delay circuit B
22-2 Delay circuit B
23-1 D flip-flop 23-2 D flip-flop 25 Control circuit 26 Charge pump 27 Buffer 30-1 Inverter 30-2, 30-3 NOR gate 31-1, 31-2, 31-3, 31-4 Current source 32-1, 32-2, 32-3, 32-4 Inverters 33-1, 33-2, 33-3, 33-4 MOS transfer gates 34-1, 34-3, 35-1, 35-2, 35-3, 35-4, 43, 44, 47-1, 47-2 P-type MOS transistors 34-2, 34-4, 35-3, 36-1, 36-3, 36-4, 41, 42 48-1, 48-2, 49 N-type MOS transistor 37 Charge pump capacitance 46 Variable delay circuit 46-i (i = 1 to n) Unit circuit 50-1, 50-2 Buffer 52-1 DQ1 terminal 52- 2 DQ1B terminal 53-1 DQ2 terminal 53-2 DQ2B terminal 54-1 DQ3 terminal 54-2 DQ3B terminal 55-1 CLK terminal 55-2 CLKB terminal 56 Lead 57 Pad 61 DQ output part 62 DQB output part 63 Buffer 65-1 Wiring 65-2 Wiring 67 Termination 101 DRAM
103 clock input buffer 104 DRAM core 105 DQ output unit 106 DLL

Claims (5)

An external clock terminal for inputting an external clock signal from the outside;
An output terminal disposed in the vicinity of the external clock terminal and outputting a data signal indicating data to the outside;
A semiconductor device comprising: an inverted output terminal that is disposed in the vicinity of the output terminal and the external clock terminal and outputs an inverted data signal obtained by inverting the data signal to the outside. The semiconductor device according to claim 1, wherein a distance between the output terminal and the external clock terminal and a distance between the inverted output terminal and the external clock terminal are equal within a preset difference range. Further comprising an inverted external clock terminal disposed in the vicinity of the external clock terminal and receiving an inverted external clock signal obtained by inverting the external clock signal from the outside,
The distance between the output terminal and the set of the external clock terminal and the inverted external clock terminal and the distance between the inverted output terminal and the set are equal within a preset range of difference. Semiconductor device. 4. The semiconductor device according to claim 1, further comprising an inverted data signal output unit that outputs the inverted data signal to the inverted output terminal based on the data signal. 5. The semiconductor device according to claim 1, wherein the inverting output terminal is terminated in the vicinity of the inverting output terminal.

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