JP2007234135A - Magnetic head driving circuit and magnetic recording and reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to control an overshoot amount to a desired value. <P>SOLUTION: A recording head driving circuit 16 drives a recording head 12 for recording information on a magnetic recording medium. A switching circuit 20 is an H bridge circuit including a plurality of transistors, and the switching circuit 20 switches the direction of a write current Iw flowing to the recording head 12 corresponding to the conducting state of each transistor. A write current control part 40 controls the write current Iw flowing to the recording head 12. An overshoot control circuit 30 adds an overshoot current Ios proportional to the write current Iw to the write current Iw flowing to the recording head 12 in a prescribed overshoot period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a magnetic recording / reproducing apparatus for recording and reproducing data on a magnetic recording medium, and more particularly to a technique for controlling an overshoot current to be added to a write current at the time of recording.

  2. Description of the Related Art A magnetic recording / reproducing apparatus represented by a hard disk is often used as a recording medium used in an electronic device in recent years. In such a magnetic recording / reproducing apparatus, in order to record magnetically recorded data, a current (hereinafter also referred to as a write current) flowing through a coil of a write magnetic head (recording head) is controlled. In order to drive the magnetic head, a magnetic head driving circuit including a switching circuit such as an H bridge circuit is used.

  The magnetic head drive circuit controls the direction of the write current flowing in the coil of the magnetic head and the amplitude thereof. For example, Patent Document 1 discloses such a magnetic head driving circuit.

  As described in Patent Document 1, in a magnetic head drive circuit, when the direction of the write current flowing through the recording head changes, the write current is generally overshot to improve the write performance. Is.

JP-A-6-176558

  Here, the writing capability tends to improve as the overshoot amount increases. However, if the overshooting amount is too large, a problem of side erasure that erases information on the surrounding tracks occurs. Therefore, in the magnetic recording / reproducing apparatus, the control of the write current, that is, the control of the overshoot amount is a very important technique for improving the write performance.

  The present invention has been made in view of such problems, and an object thereof is to provide a magnetic head driving circuit capable of controlling the overshoot amount to a desired value.

  One embodiment of the present invention relates to a magnetic head drive circuit that drives a magnetic head that records information on a magnetic recording medium. This magnetic head drive circuit includes a plurality of transistors, a switching circuit that switches the direction of the write current flowing through the magnetic head in accordance with the conduction state of each transistor, and a document that controls the current value of the write current flowing through the magnetic head. And an overshoot control circuit that adds an overshoot current corresponding to the write current to the write current flowing through the magnetic head during a predetermined overshoot period. The overshoot control circuit may add an overshoot current proportional to the write current.

  According to this aspect, the amount of overshoot can be accurately controlled by changing the overshoot current according to the write current.

  The switching circuit includes a first high-side switching transistor provided on a path for supplying current to one end of the magnetic head, and a first write current control transistor provided in series on a path for drawing current from one end of the magnetic head. And a first low-side switching transistor, a second high-side switching transistor provided on a path for supplying current to the other end of the magnetic head, and a first provided on a path for drawing current from the other end of the magnetic head. 2 low-side switching transistors and a second write current control transistor. The overshoot control circuit includes a first overshoot current control transistor and a first overshoot switching transistor provided on a path parallel to a path in which the first write current control transistor and the first low-side switching transistor are provided. A second overshoot current control transistor and a second overshoot switching transistor provided on a path parallel to a path where the two write current control transistor and the second low-side switching transistor are provided may be included. The switching circuit may switch the direction of the write current in accordance with on / off of the first and second high-side switching transistors and the first and second low-side switching transistors. The control terminals of the first and second write current control transistors and the first and second overshoot current control transistors are connected in common, and the write current control unit controls the potential of the control terminal connected in common, The overshoot control circuit may turn on one of the first and second overshoot switching transistors for a predetermined overshoot period.

  According to this configuration, the first write current control transistor, the first low side switching transistor, the second write current control transistor, the second low side switching transistor, and the first overshoot current among the transistors configuring the H-bridge circuit. Since the transistor pair of each of the control transistor, the first overshoot switching transistor, the second overshoot current control transistor, and the second overshoot switching transistor has the same circuit configuration, the drain-source voltage of each transistor or the collector emitter The inter-voltage becomes uniform, and an overshoot current proportional to the write current can be generated accurately.

  The switching circuit further includes a first diode and a first resistor provided on a path from the first high-side switching transistor to one end of the magnetic head, and a path from the second high-side switching transistor to the other end of the magnetic head. A second diode and a second resistor provided may be included.

  By providing the first and second diodes, the potential at both ends of the magnetic head can be prevented from rising excessively, and circuit protection can be realized. In general, the magnetic head and the switching circuit are connected by a wiring formed on a flexible substrate. By providing the first and second resistors, the impedance desired for the magnetic head from the switching circuit can be obtained. Can be adjusted and impedance matching can be achieved.

  The first and second high-side switching transistors, the first and second write current control transistors, and the first and second overshoot current control transistors are bipolar transistors, and the first and second low-side switching transistors and first, The second overshoot switching transistor may be a field effect transistor.

  A magnetic head drive circuit according to another aspect of the present invention includes a plurality of transistors, a switching circuit that switches a direction of a write current flowing through the magnetic head in accordance with a conduction state of each transistor, and a write current flowing through the magnetic head. A write current control unit for controlling a current value; an overshoot control circuit for adding an overshoot current corresponding to the write current to a write current flowing through the magnetic head during a predetermined overshoot period; and both ends of the magnetic head Is clamped so as not to fall below a predetermined clamp voltage.

  When the write current is set large, the voltage across the magnetic head greatly fluctuates due to the back electromotive force. The amount by which the voltage across the magnetic head swings to the ground (or negative power supply voltage) side is limited by the clamp circuit. According to this aspect, the overshoot current can be set to an appropriate value by adjusting the clamp voltage.

  The clamp circuit may change a predetermined clamp voltage according to the write current. The clamp circuit may set the predetermined clamp voltage low as the write current increases.

  The clamp circuit may include a bipolar transistor having an emitter connected to one end of a magnetic head to be clamped, and the clamp voltage may be adjusted by controlling a voltage applied to the base of the bipolar transistor.

  The above magnetic head drive circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the magnetic head drive circuit as one LSI, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

  Another aspect of the present invention is a magnetic recording / reproducing apparatus. This apparatus includes the above-described magnetic head driving circuit. According to this aspect, since the overshoot amount of the write current can be set appropriately, the write performance can be improved.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the head drive circuit and the magnetic recording / reproducing apparatus of the present invention, the overshoot amount of the write current can be controlled to a desired value.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a magnetic recording / reproducing apparatus 100 according to the first embodiment. The magnetic recording / reproducing apparatus 100 is a hard disk apparatus that writes or reads information on a magnetic disk (not shown), and includes a reproducing head 10, a recording head 12, and a magnetic head drive circuit 200.

  In this magnetic recording / reproducing apparatus 100, a coil is mounted on the recording head 12, and is arranged close to a magnetic disk that rotates at high speed. When a signal current corresponding to information to be recorded is passed through the coil of the recording head 12, an induction magnetic field is generated, and the magnetic disk is magnetized by the magnetic flux leaking from the magnetic gap, and information is written.

  The reproducing head 10 includes an MR element whose resistance value changes according to the magnetic flux, and its resistance value changes due to the magnetic flux generated from the magnetic disk magnetized in accordance with the written information. It can be converted into an electrical signal and read out.

  The magnetic head driving circuit 200 is a circuit for controlling the driving of the magnetic head, that is, the reproducing head 10 and the recording head 12, and the reproducing head driving circuit 14 and the recording head driving circuit 16 are integrated. The magnetic head driving circuit 200 is switched in a time division manner to a read mode during a reproducing operation and to a write mode during a recording operation.

  The first terminal 102 and the second terminal 104 of the recording head drive circuit 16 are connected to the recording head 12 via write wirings Wx and Wy. The recording head drive circuit 16 becomes active during the write mode, and controls the magnitude and direction of the write current Iw that flows through the recording head 12 in accordance with the information written to the magnetic disk.

  The reproducing head drive circuit 14 is connected to the reproducing head 10 via reading wirings Rx and Ry. The reproducing head drive circuit 14 is active in the read mode and supplies a constant bias current Ibias to the reproducing head 10. The resistance value of the MR element of the reproducing head changes depending on the magnetic flux of the magnetic disk. If the resistance value is written as Rmr, the voltage drop Vmr across the reproducing head 10 is given by Vmr = Rmr × Ibias. Normally, the resistance value of the MR element is about several tens of Ω, and a voltage drop of about 0.1 V to 1 V can be obtained by applying a bias current of several mA. The reproducing head drive circuit 14 extracts information written on the magnetic disk as an electric signal by differentially amplifying the voltage drop of the reproducing head 10.

  The read wirings Rx, Ry and the write wirings Wx, Wy are laid in parallel on the FPC (Flexible Printed Circuit) from the magnetic head driving circuit 200 to the reproducing head 10 and the recording head 12. Therefore, there is a parasitic capacitance (not shown) between the wirings, and there is a wiring resistance.

  The embodiment described below relates to the recording head drive circuit 16 of the magnetic recording / reproducing apparatus 100, and more particularly to a technique for improving the writing characteristics.

  FIG. 2 is a circuit diagram showing a configuration of the recording head drive circuit 16 according to the first embodiment. The recording head drive circuit 16 includes a switching circuit 20, an overshoot control circuit 30, and a write current control unit 40, and is integrated as a functional IC on a single semiconductor substrate.

  The switching circuit 20 includes a plurality of transistors, and switches the direction of the current flowing through the recording head 12 according to the conduction state of each transistor. In the present embodiment, the switching circuit 20 is configured as an H-bridge circuit.

  In the present embodiment, the switching circuit 20 includes a first high side switching transistor SWH1, a second high side switching transistor SWH2, a first write current control transistor 22, a second write current control transistor 24, and a first low side switching transistor. SWL1 and second low-side switching transistor SWL2 are included.

  The first high-side switching transistor SWH1 is provided on a path for supplying a current from the power supply terminal 110 to which the power supply voltage Vdd is applied to the one end 102 of the recording head 12. The first write current control transistor 22 and the first low-side switching transistor SWL1 are provided in series on a path for drawing current from the one end 102 of the recording head 12.

  Similarly, the second high-side switching transistor SWH2 is provided on a path for supplying current from the power supply terminal 110 to the other end 104 of the recording head 12. The second write current control transistor 24 and the second low-side switching transistor SWL2 are provided in series on a path for drawing current from the other end of the recording head 12.

  In the present embodiment, the first high-side switching transistor SWH1, the second high-side switching transistor SWH2, the first write current control transistor 22, and the second write current control transistor 24 are composed of NPN bipolar transistors. The first low side switching transistor SWL1 and the second low side switching transistor SWL2 are configured as N-channel MOSFETs. However, it is a matter of design whether to use bipolar transistors or FETs for these transistors, and whether to use NPN type, PNP type, N channel, or P channel may be changed as appropriate.

  The switching circuit 20 switches the direction of the write current Iw according to on / off of the first high-side switching transistor SWH1, the second high-side switching transistor SWH2, the first low-side switching transistor SWL1, and the second low-side switching transistor SWL2. That is, when the first high-side switching transistor SWH1 and the second low-side switching transistor SWL2 are turned on, the write current Iw flows through the recording head 12 from the terminal 102 to the terminal 104. Conversely, when the second high-side switching transistor SWH2 and the first low-side switching transistor SWL1 are turned on, the write current Iw flows from the terminal 104 to the terminal 102 in the recording head 12.

  The write current control unit 40 controls the current value of the write current Iw that flows through the recording head 12. The write current control unit 40 includes a constant current source 42, a first transistor 44, a second transistor 46, and a switch control unit 50.

  The switch control unit 50 controls on / off of a switching transistor (transistor starting with SW in the drawing) configured to be controllable on / off, and controls the direction of the write current Iw. Further, in the overshoot period, the switch control unit 50 turns on the switching transistors (SWOS1, SWOS2), and activates the first overshoot control circuit 30a and the second overshoot control circuit 30b. The switch control unit 50 and the control terminal (base or gate) of each switching transistor are connected by a signal line (not shown).

  The constant current source 42 generates a bias current Ibias that is proportional to the desired write current Iw. This bias current Ibias is adjusted in a timely manner so that good write characteristics can be obtained using ambient temperature as a parameter. The first transistor 44 and the second transistor 46 are provided in series on the path of the bias current Ibias, that is, between the constant current source 42 and the ground (or negative power supply voltage). The first transistor 44 is a transistor of the same type as the first write current control transistor 22 and the second write current control transistor 24, that is, an NPN bipolar transistor, and the second transistor 46 is a first low-side switching transistor SWL1. The second low-side switching transistor SWL2 is the same type of transistor, that is, an N-channel MOSFET.

  The bases that are the control terminals of the first write current control transistor 22, the second write current control transistor 24, and the first transistor 44 are connected in common to form a current mirror circuit. The base voltage Vbias of the first write current control transistor 22 and the second write current control transistor 24 is controlled by the write current control unit 40, and the first write current control transistor 22 and the second write current control transistor 24 are controlled. Current flows in proportion to the bias current Ibias in accordance with the size ratio. That is, the first write current control transistor 22 and the second write current control transistor 24 are provided to adjust the amount of write current Iw.

  The second transistor 46 is always turned on during the writing operation by fixing the gate voltage.

  The overshoot control circuit 30 includes a first overshoot control circuit 30a and a second overshoot control circuit 30b. The overshoot control circuit 30 adds an overshoot current Ios corresponding to the write current Iw to the write current Iw flowing through the recording head 12 during a predetermined overshoot period. In the present embodiment, the overshoot control circuit 30 adds an overshoot current Ios proportional to the write current Iw.

  The first overshoot control circuit 30a includes a first overshoot current control transistor 31 and a first overshoot switching transistor SWOS1. The first overshoot current control transistor 31 and the first overshoot switching transistor SWOS1 are provided in series on a path parallel to the path where the first write current control transistor 22 and the first low-side switching transistor SWL1 are provided. Similarly, the second overshoot control circuit 30b includes a second overshoot current control transistor 32 and a second overshoot switching transistor SWOS2. The second overshoot current control transistor 32 and the second overshoot switching transistor SWOS2 are provided in series on a path parallel to the path where the second write current control transistor 24 and the second low-side switching transistor SWL2 are provided.

  The first overshoot current control transistor 31 and the second overshoot current control transistor 32 are all transistors of the same type as the first write current control transistor 22, the second write current control transistor 24, and the first transistor 44, that is, An NPN bipolar transistor is used.

  The control terminals of the first overshoot current control transistor 31 and the second overshoot current control transistor 32, that is, the base are connected in common with the bases of the first write current control transistor 22 and the second write current control transistor 24, A first mirror 44 and a current mirror circuit are formed. Therefore, an overshoot current Ios proportional to the bias current Ibias generated by the constant current source 42 flows through the first overshoot current control transistor 31 and the second overshoot current control transistor 32.

  The first overshoot switching transistor SWOS1 and the second overshoot switching transistor SWOS2 are composed of transistors of the same type as the first low-side switching transistor SWL1, the second low-side switching transistor SWL2, and the second transistor 46, that is, N-channel MOSFETs. When the first overshoot switching transistor SWOS1 is turned on, the first overshoot control circuit 30a is activated, and the overshoot current Ios is added to the write current Iw that flows leftward through the recording head 12. Conversely, when the second overshoot switching transistor SWOS2 is turned on, the second overshoot control circuit 30b is activated, and the overshoot current Ios is added to the write current Iw that flows rightward through the recording head 12. The overshoot control circuit 30 turns on one of the first overshoot switching transistor SWOS1 and the second overshoot switching transistor SWOS2 during a predetermined overshoot period.

  The operation of the recording head drive circuit 16 configured as described above will be described. 3 and 4 are operation waveform diagrams of the recording head drive circuit 16 of FIG. In FIG. 3, FIG. 4 and the subsequent figures, the vertical axis and the horizontal axis are appropriately enlarged or reduced for easy understanding, and each waveform shown is also simplified for easy understanding. It shows.

  FIG. 3 is an operation waveform diagram when overshoot control is not performed. At this time, the first overshoot switching transistor SWOS1 and the second overshoot switching transistor SWOS2 are both turned off.

  In the waveform (SWH1, SWH2, SWL1, SWL2) of the switching transistor, the high level indicates an on state and the low level indicates an off state. The first voltage Vx indicates the voltage at one end 102 of the recording head 12, and the second voltage Vy indicates the voltage at the other end 104 of the recording head 12. The lowermost Iw indicates a write current, and a rightward current is indicated as a positive current.

  In the period φ1, the first high-side switching transistor SWH1 and the second low-side switching transistor SWL2 are turned on. During this time, the write current Iw is positive and flows through the recording head 12 to the right. In the period φ1, the first high-side switching transistor SWH1 is turned on, so that the first voltage Vx is fixed to a potential lower than the power supply voltage Vdd by the drain-source voltage Vds1 of the first high-side switching transistor SWH1. . On the other hand, since the second low-side switching transistor SWL2 and the second write current control transistor 24 are turned on, the second voltage Vy is drained from the second low-side switching transistor SWL2 and the second write current control transistor 24 rather than the ground voltage. It is fixed at a potential close to the sum of the source-to-source voltages.

  In the period φ2, the second high-side switching transistor SWH2 and the first low-side switching transistor SWL1 are on, the write current Iw becomes negative, and flows through the recording head 12 to the left. During this period, the first voltage Vx and the second voltage Vy are opposite to the period φ1.

  When the switching transistor is turned on / off and the direction of the write current Iw is changed, a back electromotive force is generated in the coil of the recording head 12, so that the voltage Vx or the voltage Vy overshoots, and the write current Iw is also Rise slightly.

  In the recording head drive circuit 16 according to the present embodiment, the H bridge circuit of the switching circuit 20 includes transistors (22, 24) for controlling the current value and transistors (SWH1, SWH2) for controlling the direction of the current. , SWL1, SWL2) are provided separately. As a result, it is possible to control the write current with higher accuracy than in the case where an H-bridge circuit is configured with only four transistors and switching and current control are performed.

  FIG. 4 is an operation waveform diagram at the time of overshoot in which the write current Iw is forcibly increased when the direction of the write current Iw flowing through the recording head 12 is reversed. In FIG. 3, the waveform of the high-side switching transistor is omitted for simplification.

  The first overshoot switching transistor SWOS1 is turned on for a predetermined overshoot period Tos1 when the write current Iw is inverted from left to right. Since the first overshoot switching transistor SWOS1 is provided in parallel with the first low-side switching transistor SWL1, the write current Iw is set by the first write current control transistor 22 when the two transistors are simultaneously turned on. It is a current obtained by adding the overshoot current Ios set by the first overshoot current control transistor 31 to the normal current. As a result, the write current Iw during the overshoot period can be swung largely as shown by the broken line in FIG.

  The same applies to the second overshoot switching transistor SWOS2. When the write current Iw is reversed from right to left, it is turned on for a predetermined overshoot period Tos2 to overshoot the write current Iw. be able to.

  Here, the current value of the overshoot current Ios is controlled by the first overshoot current control transistor 31 and the second overshoot current control transistor 32 as described above. These transistors are current-mirror connected to the first transistor 44, and have a current proportional to the bias current Ibias. That is, according to the magnetic recording / reproducing apparatus 100 according to the present embodiment, the overshoot current Ios can be controlled in accordance with the magnitude of the write current Iw.

  Furthermore, in the present embodiment, the first write current control transistor 22 and the first low side switching transistor SWL1, the second write current control transistor 24 and the second low side switching transistor SWL2, the first overshoot current control transistor 31 and the first Each pair of the 1 overshoot switching transistor SWOS1, the second overshoot current control transistor 32, and the second overshoot switching transistor SWOS2 has a similar circuit configuration. As a result, the drain-source voltage or collector-emitter voltage of each transistor becomes uniform, and an overshoot current Ios proportional to the write current Iw can be generated accurately.

  FIG. 5 is a circuit diagram showing a modification of the switching circuit 20 of the recording head drive circuit 16 of FIG. In the subsequent drawings, the same or equivalent components as those already described are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The switching circuit 20 in FIG. 5 includes a first diode D1 and a first resistor R1 provided in series on a path from the emitter of the first high-side switching transistor SWH1 to one end 102 of the recording head 12. In addition, a second diode D2 and a second resistor R2 provided in series are included on a path from the emitter of the second high-side switching transistor SWH2 to the other end 104 of the recording head 12.

According to the modification of FIG. 5, in addition to the effects obtained by the recording head drive circuit 16 of FIG. 2, the following effects can be obtained.
First, by providing the first diode D1 and the second diode D2, the potentials at both ends 102 and 104 of the recording head 12 are higher than the emitter voltages of the first high-side switching transistor SWH1 and the second high-side switching transistor SWH2, respectively. The voltage is lower by the forward voltage Vf of the diode. As a result, it is possible to prevent the voltage at both ends of the recording head 12 from rising more than necessary, and circuit protection can be achieved.

  In addition, impedance matching can be achieved by providing the first resistor R1 and the second resistor R2. That is, as described above, the terminals 102 and 104 and the recording head 12 are connected via the wiring on the flexible substrate. This wiring has parasitic capacitance and wiring resistance, but the length of the flexible substrate may be different depending on each set. Therefore, by providing the first resistor R1 and the second resistor R2 and adjusting their resistance values, impedance mismatch can be improved, signal reflection can be reduced, and writing performance can be improved.

(Second Embodiment)
In general, since the overshoot period Tos is usually very short such as several hundred ps, the current flowing through each of the transistors 22, 24, 31, 32, 44 deviates from the current value determined by the mirror ratio of the current mirror circuit. As a result, under certain circumstances, it may be assumed that the overshoot amount of the write current Iw cannot be sufficiently controlled by the circuit according to the first embodiment. The second embodiment described below relates to a technique for accurately controlling the overshoot of the write current Iw by using the technique described in the first embodiment in combination or independently.

  FIG. 6 is a circuit diagram showing a part of the configuration of the recording head drive circuit 16a according to the second embodiment. The recording head drive circuit 16a according to the second embodiment includes a clamp circuit 60.

  The clamp circuit 60 clamps the voltages at both ends 102 and 104 of the recording head 12, that is, the first voltage Vx and the second voltage Vy so as not to fall below a predetermined clamp voltage VCL.

  FIG. 7 is a circuit diagram illustrating a configuration example of the clamp circuit 60. The clamp circuit 60 includes a first clamp transistor 62, a second clamp transistor 64, and a clamp level control unit 66. The first clamp transistor 62 and the second clamp transistor 64 are both NPN bipolar transistors, and a control voltage Vcnt generated by the clamp level control unit 66 is applied to the base.

  The clamp voltage VCL set by the clamp circuit 60 of FIG. 7 is given by VCL = Vcnt−Vbe. Here, Vbe is the base-emitter voltage of the first clamp transistor 62 and the second clamp transistor 64, and is typically about 0.7V.

  The clamp circuit 60 in FIG. 7 clamps the voltages Vx and Vy across the recording head 12 so as not to be lower than the clamp voltage VCL. Furthermore, the clamp circuit 60 desirably changes the clamp voltage VCL according to the write current Iw. More preferably, the clamp circuit 60 desirably sets the clamp voltage VCL low as the write current Iw increases. Therefore, the clamp level control unit 66 operates in conjunction with the write current control unit 40 and changes the control voltage Vcnt according to the bias current Ibias.

  The operation of the recording head drive circuit 16 according to the second embodiment configured as described above will be described. FIG. 8 is an operation waveform diagram of the recording head drive circuit 16 of FIG. In FIG. 8, for comparison, a waveform when clamping is not performed is indicated by a broken line.

  Under a situation where the overshoot period is short, the smaller the write current Iw, the larger the overshoot amount can be secured. As the write current Iw increases, it becomes difficult to secure the necessary overshoot amount. Therefore, when the circuit design is performed so that a sufficient overshoot amount is obtained when the write current Iw is large, the overshoot amount when the write current Iw is small may be too large.

  As shown in FIG. 6, when the first voltage Vx and the second voltage Vy are clamped, the overshoot amount of the write current Iw becomes smaller than that in the case of not clamping, and the overshoot amount is prevented from becoming too large. be able to. In other words, the overshoot amount of the write current Iw can be adjusted to a desired value by appropriately setting the clamp voltage VCL.

  Furthermore, by changing the clamp voltage VCL according to the write current Iw, the overshoot amount can be set to an optimum value according to the write current Iw. The clamp circuit 60 is not limited to the configuration shown in FIG. 7 and may have any configuration as long as the first voltage Vx and the second voltage Vy can be clamped.

(Third embodiment)
In the second embodiment, the technique for controlling the amount of overshoot has been described by paying attention to the behavior when the voltages Vx and Vy across the recording head 12 swing in the ground (or negative power supply voltage) direction. . In contrast, in the third embodiment described below, the overshoot amount is controlled by paying attention to the behavior when the voltages Vx and Vy across the recording head 12 swing in the direction of the power supply voltage Vdd. It is.

  FIG. 9 is a circuit diagram showing a configuration of a recording head drive circuit 16b according to the third embodiment. The pull-up circuit 70 independently pulls up the voltages Vx and Vy across the recording head 12 to a predetermined pull-up level during the overshoot period Tos. Hereinafter, the direction in which the write current Iw flowing in the recording head 12 flows from the first terminal 102 to the second terminal 104 is defined as a first direction, and the direction in which the write current Iw flows from the second terminal 104 to the first terminal 102 is defined as a second direction. The pull-up circuit 70 pulls up the voltage Vx of the first terminal 102 when the write current Iw switches from the first direction to the second direction, and pulls up the voltage Vx of the second terminal 104 when the write current Iw switches from the second direction to the first direction. Pull up the voltage Vy.

  The pull-up circuit 70 desirably changes the pull-up level in a stepwise manner in accordance with the overshoot amount of the write current Iw.

  FIG. 10 is a circuit diagram illustrating a configuration example of the pull-up circuit 70. The pull-up circuit 70 includes a first pull-up circuit 72 and a second pull-up circuit 74. The first pull-up circuit 72 and the second pull-up circuit 74 have the same configuration.

  The first pull-up circuit 72 includes first resistance components Rp1a to Rp1c and a first switch SWP1 provided in series on a path from the power supply terminal 110 to the first terminal 102 of the recording head 12. Similarly, the second pull-up circuit 74 includes second resistance components Rp2a to Rp2c and a second switch SWP2. The resistance values of the resistance components Rp1a to Rp1c and Rp2a to Rp2c are set to different values.

  The pull-up circuit 70 turns on either the first switch SWP1 of the first pull-up circuit 72 or the second switch SWP2 of the second pull-up circuit 74 as necessary during the overshoot period.

  When the first pull-up circuit 72 pulls up the first voltage Vx of the first terminal 102 of the recording head 12, the first terminal 102 is connected to one of the resistors Rp1a to Rp1c via the first switch SWP1, and the power supply Pulled up to voltage Vdd. Since the resistance values of the resistors Rp1a to Rp1c are different, the first voltage Vx is pulled up to different pullup levels.

  The voltage drop in the first resistance component Rp1 and the first switch SWP1 is caused by the fact that the transistor SWH1 provided on the path for supplying current to the first terminal 102 of the recording head 12 among the plurality of transistors constituting the switching circuit 20 is completely It is desirable to set a value that does not turn off. Since the second pull-up circuit 74 is the same as the first pull-up circuit 72, description thereof is omitted.

FIG. 11 is a circuit diagram showing another configuration example of the first pull-up circuit 72 (or the second pull-up circuit 74). The first pull-up circuit 72 in FIG. 11 includes a control transistor M1 that is a MOSFET and a plurality of adjustment transistors M2 to M4.
The control transistor M1 corresponds to the first switch SWP1 in FIG. 10, and functions as a switch that is turned on as necessary only during the overshoot period. The plurality of adjustment transistors M2 to M4 are connected in series with the control transistor M1 and are connected in parallel. The plurality of adjustment transistors M2 to M4 correspond to the first resistance component Rp1 in FIG. 10, and change the pull-up level depending on which one is turned on.

  The operation of the recording head drive circuit 16 according to the third embodiment configured as described above will be described. FIG. 12 is an operation waveform diagram of the recording head drive circuit 16b of FIG. As described above, as the write current Iw increases, it may be difficult to secure a necessary overshoot amount. Therefore, in the recording head drive circuit 16b according to the present embodiment, the pull-up circuit 70 causes the voltages Vx and Vy of the first terminal 102 and the second terminal 104 to be pulled up to a predetermined level during the overshoot period Tos. Pull up to level VPU. By pulling up the voltages Vx and Vy at both ends of the recording head 12, a desired overshoot can be added to the write current Iw. Furthermore, the amount of overshoot can be changed to a desired value by changing the pull-up level VPU stepwise.

(Fourth embodiment)
The fourth embodiment is a combination of the second and third embodiments. FIG. 13 is a circuit diagram showing a configuration of a recording head drive circuit 16c according to the fourth embodiment. According to the recording head drive circuit 16c according to the fourth embodiment, both the effects obtained in the second and third embodiments can be obtained. Therefore, when the overshoot amount is too large, the clamp circuit 60 Can suppress the overshoot amount, and if it is insufficient, the pull-up circuit 70 can increase the overshoot amount, and in either case, a desired overshoot current can be set.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the magnetic recording / reproducing apparatus 100 using a magnetic disk has been described. However, the technology according to the present invention is not limited to this, and as other magnetic recording media, a disk-type flexible disk storage device, a helical disk, The present invention can also be applied to a scan type image recording device (VTR) or a card type magnetic card.

1 is a circuit diagram showing a configuration of a magnetic recording / reproducing apparatus according to a first embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a recording head driving circuit according to the first embodiment. FIG. 3 is an operation waveform diagram of the recording head drive circuit of FIG. 2 when overshoot control is not performed. FIG. 3 is an operation waveform diagram of the recording head drive circuit of FIG. 2 when overshoot control is performed. FIG. 6 is a circuit diagram showing a modification of the switching circuit of the recording head drive circuit in FIG. 2. FIG. 6 is a circuit diagram illustrating a part of a configuration of a recording head driving circuit according to a second embodiment. It is a circuit diagram which shows the structural example of a clamp circuit. FIG. 7 is an operation waveform diagram of the recording head drive circuit of FIG. 6. FIG. 9 is a circuit diagram illustrating a configuration of a recording head driving circuit according to a third embodiment. It is a circuit diagram which shows the structural example of a pull-up circuit. It is a circuit diagram which shows another structural example of a 1st pull-up circuit (or 2nd pull-up circuit). FIG. 10 is an operation waveform diagram of the recording head drive circuit of FIG. 9. FIG. 10 is a circuit diagram illustrating a configuration of a recording head driving circuit according to a fourth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 reproducing head, 12 recording head, 14 reproducing head drive circuit, 16 recording head drive circuit, 20 switching circuit, 22 1st write current control transistor, 24 2nd write current control transistor, 30 overshoot control circuit, 30a 1st 1 overshoot control circuit, 30b second overshoot control circuit, 31 first overshoot current control transistor, 32 second overshoot current control transistor, 40 write current control unit, 42 constant current source, 44 first transistor, 46 Second transistor, 50 switch control unit, 60 clamp circuit, 62 first clamp transistor, 64 second clamp transistor, 66 clamp level control unit, 70 pull-up circuit, 72 first pull-up circuit 74 second pull-up circuit, 100 magnetic recording / reproducing apparatus, 200 magnetic head drive circuit, SWH1 first high-side switching transistor, SWH2 second high-side switching transistor, SWL1 first low-side switching transistor, SWL2 second low-side switching transistor, SWOS1 first overshoot switching transistor, SWOS2 second overshoot switching transistor, D1 first diode, D2 second diode, R1 first resistor, R2 second resistor.

Claims (11)

A magnetic head driving circuit for driving a magnetic head for recording information on a magnetic recording medium,
A switching circuit that includes a plurality of transistors, and switches a direction of a write current flowing through the magnetic head according to a conduction state of each transistor;
A write current control unit for controlling a current value of a write current flowing through the magnetic head;
An overshoot control circuit for adding an overshoot current corresponding to the write current to a write current flowing through the magnetic head during a predetermined overshoot period;
A magnetic head drive circuit comprising:   2. The magnetic head drive circuit according to claim 1, wherein the overshoot control circuit adds an overshoot current proportional to the write current. The switching circuit is
A first high-side switching transistor provided on a path for supplying a current to one end of the magnetic head;
A first write current control transistor and a first low-side switching transistor provided in series on a path for drawing current from the one end of the magnetic head;
A second high-side switching transistor provided on a path for supplying a current to the other end of the magnetic head;
A second write current control transistor and a second low side switching transistor provided in series on a path for drawing current from the other end of the magnetic head;
Including
The overshoot control circuit includes:
A first overshoot current control transistor and a first overshoot switching transistor provided on a path parallel to a path provided with the first write current control transistor and the first low-side switching transistor;
A second overshoot current control transistor and a second overshoot switching transistor provided on a path parallel to a path where the second write current control transistor and the second low-side switching transistor are provided;
Including
The switching circuit switches a direction of the write current according to on / off of the first and second high-side switching transistors and the first and second low-side switching transistors,
The control terminals of the first and second write current control transistors and the first and second overshoot current control transistors are connected in common, and the write current control unit determines the potential of the control terminals connected in common. Control
3. The magnetic head drive circuit according to claim 2, wherein the overshoot control circuit turns on one of the first and second overshoot switching transistors during the predetermined overshoot period. The switching circuit further includes:
A first diode and a first resistor provided on a path from the first high-side switching transistor to one end of the magnetic head;
A second diode and a second resistor provided on a path from the second high-side switching transistor to the other end of the magnetic head;
The magnetic head drive circuit according to claim 3, comprising:   The first and second high-side switching transistors, the first and second write current control transistors, and the first and second overshoot current control transistors are bipolar transistors, and the first and second low-side switching transistors 4. The magnetic head drive circuit according to claim 3, wherein the first and second overshoot switching transistors are field effect transistors.   6. The magnetic head drive circuit according to claim 1, further comprising a clamp circuit that clamps a voltage across the magnetic head so as not to fall below a predetermined clamp voltage.   The magnetic head drive circuit according to claim 6, wherein the clamp circuit changes the predetermined clamp voltage in accordance with the write current.   The magnetic head drive circuit according to claim 7, wherein the clamp circuit sets the predetermined clamp voltage to be lower as the write current increases. The clamp circuit is
7. The clamp voltage is adjusted by controlling a voltage applied to a base of the bipolar transistor, the emitter including a bipolar transistor connected to one end of the magnetic head to be clamped. The magnetic head drive circuit according to 1.   10. The magnetic head drive circuit according to claim 1, wherein the magnetic head drive circuit is integrated on a single semiconductor substrate.   A magnetic recording / reproducing apparatus comprising the magnetic head drive circuit according to claim 1.

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