JP2007232404A - Method for measuring active matrix tft array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-speed measuring method for performing charge characteristics tests on holding capacitors of TFT arrays and holding characteristics tests. <P>SOLUTION: Electric charge of a holding capacitor of a first pixel circuit is measured when a prescribed holding time has elapsed since charged, and a charge characteristics test is performed on a third pixel circuit which has not been yet charged in a TFT array provided with a plurality of pixel circuits each having a holding capacitor; a switching transistor for connecting a data line; and a gate line for controlling the operation of the transistor. Then a second pixel circuit is charged; its electric charge of a holding capacitor is measured when a prescribed holding time has elapsed, and a charge characteristics test is performed on a holding capacitor of a fourth pixel circuit which has not been yet charged. Then a third pixel circuit is charged; its electric charge of a holding capacitor is measured when a prescribed holding time has elapsed, and electric charge of a holding capacitor of the fourth pixel circuit is measured when a prescribed holding time has elapsed in this method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for measuring charge characteristics and retention characteristics of a TFT (thin film transistor) array of an active matrix display panel.

  In a test of an active matrix display panel using liquid crystal or electroluminescence (hereinafter referred to as EL, for example, an EL element of organic EL or inorganic EL), a TFT array in which each pixel circuit is formed on the panel in a matrix form. A circuit test for each pixel called an array test is performed. In this specification, the TFT array used for this array test may be in a state before forming a light emitting material such as liquid crystal or EL, or in a state after the light emitting material is formed. Shall also be included. In general, it is desirable to remove defective products before forming expensive pixels in order to reduce manufacturing costs.

  Each pixel circuit of the TFT array of these display panels is generally composed of a pixel selection transistor for selecting a pixel, a storage capacitor for storing a voltage to be supplied to the pixel, and a pixel driving unit for driving the pixel in accordance with the supply voltage. Composed.

  One of the array test tests is a test for examining the holding characteristics of the holding capacitor (hereinafter referred to as “holding characteristic test” or “holding characteristic measurement”). This is a test in which a predetermined charge is written in a storage capacitor, and the remaining charge is read and evaluated after a predetermined storage time (generally, 16.7 ms in many cases). 13 and 14 of Patent Document 1 and paragraphs 49 to 55 show an algorithm for shortening the measurement time in the holding characteristic test for the TFT array of the active matrix liquid crystal display panel.

  On the other hand, as described in Non-Patent Document 1, some recent active matrix liquid crystal display panels include a shift register corresponding to a bidirectional shift direction in a horizontal or vertical shift register of a TFT array.

  Further, as described in Patent Document 2, a test is known in which a charge is written into a storage capacitor and the charge of the storage capacitor is read immediately or after waiting for a time shorter than the retention time (in this specification, the test is performed). This is called “charge characteristic test” or “charge characteristic measurement”).

JP-A-7-5408, FIG. 13, FIG. 14, paragraphs 49-55 JP-A-5-5866 Sony, LCX028BMT (4.6cm (1.8-inch) Black-and-White LCD Panel) Data Sheet

Based on the test method disclosed in FIG. 13 of Patent Document 1, the measurement of the storage capacitance estimated by the present inventor for a TFT array of an active matrix display panel having a control line to a pixel selection shift register The method is as follows.
Here, as in Patent Document 1, it is considered that both the write time Tw to the storage capacitor and the read time Tr are equal to τ.

  As shown in FIG. 13 as a block diagram of a general test apparatus 1300 estimated by the present inventor, the TFT array 1302 has an H shift register (horizontal shift register) 1340 for selecting a data line and a V for selecting a gate line. Shift registers (vertical shift registers) 1342 are provided to select and test pixels (typically shown as 1356, 1358, 1360). Both shift registers are provided with a clock terminal (CLK_H 1328, CLK_V 1348) and a pulse input terminal (Start_H 1330, Start_V 1346), which perform a shift operation. An enable terminal (ENB_V) is connected to the V shift register. In the H shift register, a charge meter Q 1310 and a variable voltage source 1322 are connected in series to a power supply terminal 1324.

  By the way, as can be easily understood by those skilled in the art, in the measurement method according to FIG. 13 of Patent Document 1, it is necessary to make the holding time Th for the pixels to be written and read collectively equal for all the pixels. Tw and Tr need to be equal. However, when actually considering the write time Tw to the storage capacitor and the read time Tr, these are not necessarily equal. In general, Tr takes twice or more of Tw, and considering that Tw <Tr. This algorithm is inefficient as follows.

A measurement algorithm conceivable from the test apparatus shown in FIG. 13 will be described using the timing chart of FIG. In this test method, all pixels are divided into a plurality of pixel groups, and the test is performed for each pixel group. Here, a description will be given focusing on the j-th pixel group. The storage capacitor of _{the first} pixel P _{j, 1} is written or charged over time T ₀ to writing time W (ie, Tw in FIG. 13 of Patent Document 1), and then held time H (ie, Patent Document 1). In FIG. 13, the charge is read out, that is, measured over the readout time R from time t ₃ after the passage of Th). Regarding the measurement of the next pixel P _{j, 2} , even if the start of reading is time t ₄ immediately after the end of reading of P _{j, 1} , in order to ensure the holding time H of each pixel, from the write end time t ₁ to the pixel P _{j, 1,} latency a ₁ is generated between the write start time t ₂ to the pixels P _{j, 2.}

  In the method shown in FIG. 14, the number N of pixels in each pixel group is N = H / R at the maximum from the relationship between the holding time H and the reading time R. The number of pixel groups is M in total.

In the following description, the i-th pixel of the j-th pixel group is represented as P _{j, i} in the present specification. The pixel group refers to pixels that are measured or tested, that is, inspected as a group of pixels.

In FIG. 14, A ₂ is a waiting time that is a fraction due to the relationship between the holding time H and the reading time R.

The total of the waiting time A _{1 in} the entire display panel is, for example, the difference between the writing time and the reading time, that is, the waiting time, for example, for the number of pixels 1280 × 1024 = 1,310,720 of the display panel of Non-Patent Document 1. Even if it is estimated to be 20 μs, it reaches 26 seconds.

By the way, when the charge characteristic test is performed, in the TFT array 1302 shown in FIG. 13, the pixel selection transistor of the pixel to be tested, the data line connected to the pixel, the H shift register 1340, and the pixel are connected. The operation of the gate line, V shift register 1342 is verified.
Conventionally, the holding characteristic test has been a long test. Therefore, the charge characteristic test is first performed to determine the quality of the TFT array, and then the holding characteristic test is performed. It was. However, when the test is performed as a separate test in this manner, each pixel of the non-defective TFT array results in additional test time because two tests are set up.

  Therefore, the problem to be solved by the present invention is to provide a high-speed test method when both the charge characteristic test and the retention characteristic test of the retention capacity of the TFT array are performed.

  Furthermore, another problem to be solved by the present invention is to provide a high-speed and high-accuracy test method when performing both the charge characteristic test and the retention characteristic test of the retention capacitor.

  The above object of the present invention can be achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  According to the first aspect of the method of measuring an active matrix TFT array including a plurality of pixel circuits having a storage capacitor according to the present invention, a storage capacitor and a data line are connected to the storage capacitor in each of the plurality of pixel circuits. And a gate line for controlling a switching operation of the switching transistor, and the plurality of pixel circuits include at least first, second, third, and fourth pixel circuits, and the measurement method includes: After measuring the charge of the storage capacitor of the first pixel circuit after a predetermined hold time has elapsed after charging, the charge characteristic is measured for the storage capacitor of the third pixel circuit that has not yet been charged. In addition, after measuring the charge of the storage capacitor of the second pixel circuit after a predetermined holding time has elapsed after charging, charge characteristics are measured on the storage capacitor of the fourth pixel circuit that is not yet charged. And then charging, and then measuring the charge of the storage capacitor of the third pixel circuit after the predetermined holding time has elapsed, and then holding the fourth pixel circuit after the predetermined holding time has elapsed The main feature is that it includes the step of measuring the charge of the capacitor.

  In the above aspect, the present invention performs charge characteristic measurement on each holding capacitor of the first and second pixel circuits before the step of measuring with the first pixel circuit after a predetermined holding time has elapsed, and thereafter Before the step of charging and then charging the storage capacitors of the first and second pixel circuits, the first and second pixel circuits are assigned to the first pixel group, and the third and fourth The method further includes the step of assigning the pixel circuit to the second pixel group.

In the step of assigning the pixel circuit in the first aspect to the pixel group, the present invention is such that the first pixel circuit is connected to the first data line and the first gate line, and the second pixel circuit is The third pixel circuit is assigned to be connected to the first data line and the second gate line adjacent to the first gate line, and the third pixel circuit is connected to the second data line adjacent to the first data line. And the fourth pixel circuit includes a mode in which the fourth pixel circuit is assigned to be connected to the second data line and the second data line.

  According to the present invention, in the step of assigning the pixel circuit to the pixel group, the first pixel circuit is connected to the first data line and the first gate line, and the second pixel circuit is The third pixel circuit includes a first data line, a second data line adjacent to the first data line, and a second gate line adjacent to the first gate line. The fourth pixel circuit is connected to the third data line and the first gate line, which is connected to the third gate line adjacent to the first gate line and opposite to the second gate line. An aspect of assigning to be connected is also included.

  Furthermore, according to the present invention, in the step of assigning the pixel circuit to the pixel group, the first pixel circuit is connected to the first data line and the first gate line, and the second pixel circuit is The third pixel circuit is adjacent to the first data line, and is assigned to be connected to the second data line adjacent to the first data line and the second gate line adjacent to the first gate line. The fourth pixel circuit is connected to the first data line and the second gate line, and is connected to the third data line and the first gate line on the opposite side of the second data line. A mode of assigning as described is also included.

  Furthermore, according to the present invention, when any one of the first, second, third, and fourth pixel circuits is charged, the charging is performed until the charge of the charged pixel circuit is measured. Another pixel circuit connected to the gate line connected to the pixel circuit that is connected also includes a mode in which neither charging nor measurement is performed.

  Furthermore, according to the present invention, when any one of the first, second, third and fourth pixel circuits is measured, the other pixel circuits connected to the data line connected to the measured pixel circuit are charged. Also included is an embodiment that is not.

  Furthermore, in another aspect of the present invention, there is provided a method for measuring an active matrix TFT array including a plurality of pixel circuits each having a storage capacitor. Each of the plurality of pixel circuits includes a storage capacitor and a storage capacitor. A switching transistor for connecting the data line; a gate line for controlling a switching operation of the switching transistor; and a plurality of pixel circuits including at least first, second, third, and fourth pixel circuits, The measurement method includes assigning a predetermined number of pixel circuits from the plurality of pixel circuits to the first and second pixel groups, measuring the charge characteristics of each of the pixel circuits of the first pixel group, and then charging, The charge is measured from one of the pixel circuits of the first pixel group, the charge characteristic of one of the pixel circuits of the second pixel group is measured, and then charged. Performing for each pixel circuit in the group, and then measuring the charge from each pixel circuit in the second pixel group, wherein in each of the assigning steps, each pixel circuit in each of the first and second pixel groups is A pixel circuit connected to a data line or a gate line connected to a pixel circuit that has been assigned a different gate line and has been subjected to charge measurement, and is another pixel circuit connected to the gate line that has not yet been charged The main feature is that each pixel circuit of the first and second pixel groups is assigned so that the pixel circuit is charged next.

  In the present invention described above, the allocation in each of the first and second pixel groups in the allocation step is performed such that each pixel circuit is allocated not only to the gate line but also to the data line, and the charge measurement is completed. When charging a data circuit connected to a pixel circuit or a pixel circuit connected to a gate line, a pixel circuit that is not charged with another pixel circuit connected to the data line or the gate line is selected and then charged. Includes a mode in which the pixel circuits of the first and second pixel groups are allocated.

  Furthermore, in the above-described present invention, the TFT array includes a mode in which a bidirectional shift register is provided. In the above, the charge characteristic measurement means that the storage capacitor is charged and the storage capacitor is immediately measured. In addition, the charge characteristic measurement includes charging the storage capacitor and measuring the charge of the storage capacitor before a predetermined holding time elapses.

  Further, according to another aspect of the present invention, there is provided a method for measuring an active matrix TFT array including a plurality of pixel circuits each having a storage capacitor, wherein each of the plurality of pixel circuits includes a storage capacitor and the storage capacitor. A switching transistor for connecting the data line to the gate, and a gate line for controlling the switching operation of the switching transistor. The plurality of pixel circuits include at least first, second, third and fourth pixel circuits. The measurement method measures the charge of the storage capacitor of the first pixel circuit after a predetermined holding time has elapsed after charging, and then charges the storage capacitor of the third pixel circuit that has not yet been charged, And then charge the storage capacitor, and then measure the charge of the storage capacitor of the second pixel circuit after a predetermined retention time has elapsed after charging, and have not yet been charged. Charge the storage capacitor of the fourth pixel circuit, measure the charge of the storage capacitor, charge the storage capacitor, and then charge the storage capacitor of the third pixel circuit after the predetermined holding time has elapsed. The main feature is the step of measuring the charge, and then measuring the charge of the storage capacitor of the fourth pixel circuit after the predetermined retention time has elapsed.

By using the first and second aspects of the present invention, the test can be performed at a high speed when the charge characteristic and the retention characteristic of the retention capacitor included in each pixel circuit of the TFT array of the active matrix display panel are tested.
By using the third to twelfth aspects of the present invention, the charge characteristic and the retention characteristic of the retention capacitor included in each pixel circuit of the TFT array can be performed at high speed and with high accuracy.

  The best mode for carrying out the present invention will be described below with reference to FIGS.

FIG. 1 shows a block diagram of a TFT array measuring apparatus 100 according to the present invention.
In the following description, each pixel circuit of the TFT array is simply referred to as a “pixel”.

  The TFT array 102 includes a plurality of pixels (typically, a part of which is provided with reference numerals 156, 158, and 160), a gate line 152 by a V shift register 142, and an H shift register 140. By selecting the data line 154, a voltage defined by the data line is written to a specific pixel. The H shift register 140 and the V shift register 142 have CLK_H (128), CLK_V (148), pulse input terminals Start_H (130), Start_V (146), shift direction terminals Dir_H (126), Dir_V (150) as clock signal terminals. ) And enable terminals ENB_V (149).

  Each shift register shifts the signal applied to the pulse input terminal in the direction defined by the signal applied to the shift direction terminal according to the clock signal applied to the clock signal terminal. Here, the operation of the H shift register 140 and the V shift register 142 is schematically shown in FIGS. 2 and 3, respectively, and the operation thereof will be described.

Referring to FIG. 2, the H shift register 140 includes U shift registers HSR ₁ to HSR _U including HSR _m 1402. The H shift register 140 shifts the logic high signal given to the pulse input terminal Start_H 130 in the direction specified by the Dir_H terminal 126 by the number of clock signals given to the clock terminal CLK_H (128). The relay (1404 in this case) connected to the shift register (in this case HSR _m 1402) that stores the high signal is closed, and as a result, the signal applied to the Data terminal 124 is connected to the data line 154 (in the example of the figure). D _m ). In this way, the data lines that are not selected are opened.
Some H shift registers include an enable terminal. In this case, the designated relay 1404 is closed only when the enable terminal is logic high.
In some H shift registers, unselected data lines are connected to the ground potential.

Next, referring to FIG. 3, the V shift register 142 includes V shift registers VSR ₁ to VSR _V including VSR _n 1502. The V shift register 142 shifts the logic high signal given to the pulse input terminal Start_V146 by the number of clock signals given to the clock terminal CLK_V (148) in the direction specified by the Dir_V terminal 150. Then, a logic high signal is output from the shift register VSR _n 1502, and a logic high signal is output from the AND circuit 1504 connected to the output of the VSR _n 1502 only when the logic high signal is applied to the enable terminal ENB_V (149). The signal is buffered and amplified by the buffer 1506, and the ON voltage Von is output to the gate line G _n 152.
On the other hand, the shift register that is not selected outputs a logic low signal, which is buffered and amplified by the buffer, and as a result, the off voltage Voff is output to the unselected gate line.
Note that some V shift registers do not include the enable terminal ENB_V (149). In that case, the AND circuit 1504 does not exist, and the ON voltage Von is output to the gate line only by selecting the shift register. The

  Returning to FIG. 1, a power source terminal 124 of the H shift register 140 is connected in series with a variable voltage source 122 for applying a voltage to a selected data line and a charge meter 110 for measuring the amount of charge moved through the data line. It is connected.

Each pixel of the TFT array 102, for example, as shown in the pixel 158, are connected by a line 162 (G _n the case of the pixel 158) a predetermined gate line, as well as predetermined data line (the case of the pixel 158 D _m ) and line 164.

  Note that unless otherwise specified, in this specification, “writing” to a pixel or a storage capacitor means “charging” the storage capacitor of the pixel, and “reading” from the pixel or the storage capacitor means The term “discharges charge and measures the amount of charge” from the storage capacitor of the pixel is used.

The TFT array 102 used for the test according to the present invention is a display panel for liquid crystal or EL, and can be applied to a display panel before formation of liquid crystal or EL. The present invention can also be applied to a display panel after liquid crystal or EL is formed.
As shown in FIG. 4A, each pixel has a structure in which a gate and a source are connected to a gate line G _n (152) and a data line D _m (154), respectively. Connected to the connected pixel selection transistor Q1 (182) and the drain terminal thereof, the storage capacitor C1 (184) for storing the output voltage of the transistor Q1 between the common power supply V1 (188) and the drain thereof. The pixel driving circuit 186 is provided.

  In the case of a liquid crystal display panel, as shown in FIG. 4B, the pixel drive circuit only has an ITO electrode terminal 190 for forming liquid crystal.

  In the case of an EL display panel, as shown in FIG. 4C, the pixel driving circuit 186 includes a current driving transistor Q2 (192), an ITO electrode terminal 194, and an EL driving power source V2 (196). ). An EL can be formed on the ITO electrode terminal 194 and connected to any signal line. It should be noted that there is no hindrance in the measurement of the charge characteristics and retention characteristics of the storage capacitor, regardless of whether EL is formed on the ITO electrode terminal 194 or not.

Next, the measurement algorithm of the present invention will be described with reference to FIG. In this specification, the i-th pixel of the j-th pixel group is expressed as P _{j, i} , the gate line of the pixel is expressed as G _{j, i} , and the data line is expressed as D _{j, i} . It should be noted that the length of the horizontal axis in this figure represents the approximate time width relationship and does not reflect the exact ratio.
First, paying attention to the storage capacitor of _{the first} pixel P _{j, 1} of the j-th pixel group in the present invention, writing of the charge characteristic test is started at time t ₆ . Next, reading at the charge characteristic test from the same pixel is started at time t ₇ after the writing time WC has elapsed. Further, writing in the retention characteristic test is started on the same pixel at time t ₈ after the read time RC has elapsed. Next, reading at the holding characteristic test is started for the second pixel P _j−1,2 of the _j− 1th pixel group at time t ₉ after the writing time WH has elapsed. It should be noted that the pixel P _j−1,2 has been subjected to a charge characteristic test in advance and a holding characteristic test has been written therein, and the holding time H has elapsed. Next, when the reading of P _j−1,2 ends at time t ₁₀ after the reading time RH has elapsed _, writing and reading in the charge characteristic test for _{the second} pixel P _{j, 2 of the jth} pixel group are performed. Then, writing in the holding characteristic test is started.
Here, the relationship between the writing time WC in the charge characteristic test and the writing time WH in the holding characteristic test is generally equal because both are the same as the writing operation to the normal pixel. The relationship between the readout time RC in the charge characteristic test and the readout time RH in the holding characteristic test is such that a coarser resolution may be measured in the charge characteristic test than in the holding characteristic test. There are many.
As shown in FIG. 5, the reading for the first pixel P _j−1,1 of the _j− 1th pixel group is time t prior to the writing of the charge characteristic test for the pixel P _{j, 1.} Began to ₅

In this way, the reading of the pixel in which the holding characteristic test was written in the immediately previous pixel group, the writing and reading of the charge characteristic test for the first time, and the writing of the pixel group in which the holding characteristic test is written are alternately performed. Since this can be done, the waiting time A ₁ as shown in FIG. 14 does not occur.
Thereafter, reading of the holding characteristic test, writing and reading of the charge measurement test, and writing of the holding characteristic test are performed for all the pixels in the two groups. From the waiting time A ₃ after elapse of time t ₁₁ fractional occurring in relation to the retention time, already the first pixel P _{j, 1} of the retention characteristic tests of the j-th pixel group holding time H has elapsed already written Is read out. At time t ₁₂ of the later reading time RH course of holding characteristic test, it starts writing charge characteristic test of the first pixel of the next (j + 1) th pixel group P _{j + 1,1.}
Here, the number S of pixels in one pixel group is represented by S = H / (WC + RC + WH + RH), and the number of all pixel groups is represented by T.

Since the shift register is used to select the gate line and the data line between each pixel, when writing to a certain pixel is actually finished, the optimum moving direction to the position of the next pixel is selected by Dir_H 126 and Dir_V 150. The test apparatus controls (not shown in FIG. 1) so as to perform a shift operation by the clock necessary for moving to the target pixel. Therefore, it is necessary to design a measurement timing in consideration of the time margin of this shift operation. However, since the operation clock of the shift register is sufficiently shorter than the writing time or reading time in the above-described charge characteristic test and holding characteristic test, the time required for pixel selection control in the entire display panel can be sufficiently short. The effect on the entire test time is small.
In addition, since the pixels for writing and reading in the charge characteristic test and writing in the holding characteristic test are the same, a shift operation is not necessary between these operations. Therefore, in performing these two types of tests alternately, It avoids taking extra time.

Next, the algorithm introduced in FIG. 5 will be described in more detail with reference to FIG. FIG. 6 schematically shows the relationship between the writing time / reading time and the waiting time of the charge characteristic test and the holding characteristic test from the test start (node S) to the test end (node E). The horizontal axis shows a rough magnitude relationship over time. In the following notation, for example, WC _1,2 indicates the time required for writing the charge characteristic test to the pixel P _1,2, and thus, the type of elapsed time and the position of the pixel are combined. .
A period from node S to node 1 indicates a period during which writing is performed on the first pixel group. In this case, since there is no pixel for reading the holding characteristic test in combination, a waiting time A _r (402, 410, 418) corresponding to this reading time is inserted between each writing. That is, after waiting for the period _Ar (402), the charge characteristic test write WC _1,1 (404) is performed on the first pixel of the first pixel group, and the charge characteristic test read RC _1,1 (406) is performed. And hold characteristic test write WH _1,1 (408), wait for period A _r (410), and perform charge special test write WC _1,2 (412) to the second pixel of the first pixel group. The holding characteristic test write WH _{1, S} (424) to the last pixel of the first pixel group is repeated, and the fractional waiting time A ₃ (426) is awaited.

Next, between the node 1 and the node 2, the read operation of the holding characteristic test of each pixel of the pixel group in which the holding time H has passed in advance, and the writing and reading of the charge characteristic test to each pixel of the new pixel group And a period in which a series of operations of writing in the holding characteristic test are alternately performed. That is, after the writing has been performed in advance and the holding time has elapsed, the holding characteristic test reading RH _j−1,1 (428) of the first pixel of the j−1th pixel group is performed, and the jth pixel group Write WC _{j, 1} (430) of charge characteristic test to the first pixel, read RC _{j, 1} (432) of charge characteristic test, and write WH _{j, 1} (434) of holding characteristic test , Read out the holding characteristic test RH _j-1,2 (436) to the second pixel of the j−1th pixel group, and write the charge characteristic test WC to the second pixel of the jth pixel group WC _{j, 2} (438) is repeated, and the holding characteristic test read RH _{j-1, S} (444) and the holding characteristic test write WH _{j, S} (450) are performed for the last pixel of both groups. A fractional period A ₃ Wait for (452) and reach node 2.

Between the last node 2 and node E, there is no pixel for newly writing the charge characteristic test and the holding characteristic test, so a waiting time A _w (456, 460) corresponding thereto is inserted instead. That is, the holding characteristic test is read out to the first pixel of the T-th pixel group, which is the last pixel group, RH _{T, 1} (454), _Aw wait (456), and the T-th pixel group the second read RH retention characteristic tests of the pixel _{T, 2} performed (458), a _w waiting (460), by repeating that, RH reading retention characteristic tests for the last pixel T _{of, S} (464) is performed, node E is reached, and the test is terminated. Note that the number of pixels of the last pixel group may be less than S in relation to the number of pixels of the display panel, and in this case, the above algorithm can be appropriately corrected to cope with it.
Further, based on the algorithm shown in FIG. 6, even before the node 2 is reached, a pixel group having less than S pixels is provided, and a waiting time is required for a write or read cycle of a pixel group in which no S pixels exist. It may be possible to make corrections as appropriate, such as changing to provide.

Next, the algorithm shown in FIG. 6 will be described in more detail using the flowcharts of FIGS. In FIG. 7, when the program is started in step 910, a variable i indicating a pixel number in the pixel group is initialized to 1 in step 914. Then wait for the waiting time A _r corresponding to the read time of the pixel in step 916, performs the charge characteristics test writing and reading the i-th pixel of the first pixel group at step 917, the first pixel in step 918 Write the retention characteristic test to the i-th pixel of the group, and in step 920, determine whether it has been done for all S pixels in the first pixel group. If not, increment the variable i in step 922. Step 916 and subsequent steps are repeated. On the other hand, if S has been performed, a waiting time A _{3 is} waited at step 924. As described above, node 1 is reached from node S in FIG.

In step 926, a variable j indicating the pixel group number to be written is initialized to 2, and the jth pixel group is selected for writing and the j-1th pixel group is selected for reading. In step 930, the variable i is initialized to 1, and in step 932, the holding characteristic test is read for the i-th pixel of the j−1-th pixel group, and the charge characteristic of the i-th pixel of the j-th pixel group is read. The test is written and read, and the holding characteristic test is written. In step 934, it is determined whether or not S groups have been completed for both groups. If the result is No, the variable i is incremented in step 938 and the processing is repeated from step 932. If the result is Yes, the waiting time A ₃ waiting at step 936, at step 940, if the variable j is T-1, i.e. determines whether reading of all the pixels of the T-1 th group is completed. If the result is No, the variable j is incremented at step 942 and the process is repeated from step 930. As described above, the node 1 is reached from the node 1 in FIG.

If the result of step 940 is Yes, the variable j is set to T in step 944, the variable i is initialized to 1, and the holding characteristic test is read for the i-th pixel of the T-th pixel group in step 946. wait for writing equivalent time A _w in step 948. In step 950, it is determined whether the measurement has been completed for all the pixels in the T-th pixel group. If NO, the variable i is incremented in step 952, and the processing is repeated from step 946. If yes, the process ends at step 954.

  Next, step 932 will be described as a more detailed flowchart with reference to FIG. Details of steps 917 and 918 and step 946 are omitted because they can be easily understood by replacing a part of FIG. 8 with a waiting time.

First, it should be noted that the output voltage of the variable voltage source 122 can output the write voltage Vw and the read voltage Vr, and is initially set to Vr. As an example, the write voltage Vw is 5V and the read voltage Vr is 0V. 8, when this routine starts in step 1010, in step 1012, selects the first data lines are connected by H shift register 140 to the pixel _{P j-1, i D j} -1, i, V selecting a gate line G _{j-1, i} of the shift register 142 is connected to the pixel P _{j-1, i.} As a result, the charge meter 110 and the variable voltage source 122 are connected to the pixel P _{j−1, i} via the H shift register 140.

Next, in step 1018, the enable terminal ENB_V is set to logic high for a predetermined period, and the gate line Gj _{-1, i} is set from the off voltage Voff to the on voltage Von for a predetermined period, and then returned to the off voltage Voff. As a result, the pixel selection transistor Q1 (182 in FIG. 4) of the pixel P _{j-1, i} is turned on for a predetermined period as the discharge time of the storage capacitor, and due to the balance with the potential difference of the data line D _{j-1, i} , Charge transfer occurs between the storage capacitor C1 (184 in FIG. 4) and the charge meter (110 in FIG. 1) via the transistor Q1 (182).

Next, in step 1020, the amount of charge moved through the data line D _{j-1, i} is measured by the charge meter 110. This completes the reading of the holding characteristic test for the pixel P _{j−1, i} .

Next, in step 1030, the data line D _{j, i} connected to the pixel P _{j, i} is selected by the H shift register 140 and the gate line G _j connected to the pixel P _{j, i} by the V shift register 142. _{, i} is selected. In step 1032, the output voltage of the variable voltage source 122 is set to the write voltage Vw, and the output of the data line D _{j, i} connected to the pixel P _{j, i} is set as the write voltage Vw. Next, at step 1034, the enable terminal ENB_V is set to logic high, and the gate line G _{j, i} is set from Voff to Von. Next, in step 1035, the process waits for a predetermined period as the charging time for the storage capacitor. Then to the off-voltage Voff gate line G _{j, i} outputted from the ON voltage Von at step 1036, in step 1037, and sets the voltage Vr read the output voltage of the variable voltage source 122, the data line D _{j, i} output of Is a read voltage Vr. This completes the writing of the charge characteristic test for the pixel P _{j, i} .
Next, in step 1038, the enable terminal ENB_V is set to logic high for a predetermined period, the gate line Gj _{, i} is set from the off voltage Voff to the on voltage Von for a predetermined period, and then returned to the off voltage Voff. As a result, the pixel selection transistor Q1 of the pixel P _{j, i} is turned on for a predetermined period as the discharge time of the storage capacitor, and between the storage capacitor C1 and the charge meter due to the balance with the potential difference of the data line D _{j, i.} Charge transfer occurs through transistor Q1.
Next, at step 1039, the charge meter 110 measures the amount of charge moved via the data line D _{j, i} . This completes the readout of the charge characteristic test for the pixel P _{j, i} .
Next, in step 1040, the output voltage of the variable voltage source 122 is set to the write voltage Vw, and the output of the data line D _{j, i} connected to the pixel P _{j, i} is set to the write voltage Vw. Next, at step 1042, the enable terminal ENB_V is set to logic high, and the gate line G _{j, i} is set from Voff to Von. Next, in step 1044, a predetermined period is waited as a charging time for the storage capacitor. Next, in step 1046, the output of the gate line G _{j, i} is changed from the on voltage Von to the off voltage Voff. In step 1048, the output voltage of the variable voltage source 122 is set to the read voltage Vr, and the output of the data line D _{j, i} is output. Is a read voltage Vr. This completes the writing of the holding characteristic test for the pixel P _{j, i} . Finally, at step 1050, the operation of this routine is terminated.

  Next, a method of selecting pixels to be read / written in the holding characteristic test, that is, a method of determining a pixel group (pixel array), which is applied to the measurement algorithm of the present invention, will be described with reference to FIGS.

  For the sake of explanation, the position of each pixel is expressed using X and Y coordinates where the upper left corner of the display panel is 1. For example, in FIG. 9, pixel (3, 1) is represented as a pixel labeled “3a”, ie, labeled. Further, for the labels on the pixels, the first digit represents the pixel group number, and the second digit represents the pixel order within the pixel group. For example, pixel (3, 1) in FIG. 9 is labeled “3a”, which represents the first pixel in the third pixel group. In FIG. 9, each pixel of the third pixel group is assigned in order from the pixel 3a (3, 1) to the pixel 3S (3S). The size of the display panel will be described as U × V where the number of data lines is U and the number of gate lines is V.

  FIG. 9 shows an example of an allocation method that makes the pixel selection operation for writing and reading in the holding characteristic test simple and fast. The first pixel group starts from the pixel (1, 1) and selects S pixels from the top to the bottom. The next pixel group is the next column to the right and the pixel (2, 1) is the starting point. Pixel groups are assigned to all the pixels of the display panel in the order of selecting S pixels below. In this method, as described in step 932 of FIG. 7, when reading is performed with the i-th pixel of the j-1th pixel group and then writing is performed with the i-th pixel of the j-th pixel group, Since the gate lines need only be the same gate line, it is only necessary to select one adjacent data line. Therefore, the algorithm is simple and the time required for moving the target pixel is short.

  As another variation of this method, in the above allocation method, the next pixel group can be selected to the left of the current pixel group. Also, pixel groups can be assigned by assuming that the upper and lower and left and right ends of the display panel are connected cyclically.

  As yet another variation of this method, the pixel selection direction in each pixel group is not from top to bottom, but from bottom to top, and the position of the pixel group in the next order is the way to select pixels in the previous pixel group. Accordingly, if it is from bottom to top, the next pixel group can be selected to the right or left of the previous pixel group.

FIG. 10 and FIG. 11 show an embodiment according to an allocation method for realizing high-precision measurement.
FIG. 10A shows a method of shifting (+1, +1) in the X and Y directions as a movement amount for selecting a pixel in the pixel group, and shifting the movement amount (0, -1) between the pixel groups. A method of selecting a pixel array for each pixel group is schematically shown. As the pixels of the first pixel group, only the first four pixels of the S pixels are illustrated here, but the pixel (1, 1) is used as a starting point in the lower right direction as 1a to 1d. select. The second pixel group is selected as indicated by 2a to 2d starting from the pixel (1, V). Here, it should be noted that the upper and lower and left and right coordinates of the display panel are respectively selected as being connected to the cyclic.

  Similarly, in FIG. 10B, as another embodiment of the present invention, the movement amount within the pixel group is the upper right direction of (+1, −1), and the movement amount between the pixel groups is (0, +1). ) Shows a selection method in which the start pixel moves downward by one pixel.

  As still another embodiment of the present invention, FIG. 10C shows the movement amount in the pixel group in the lower left direction of (−1, +1), and the movement amount between the pixel groups is (0, −1). ) Shows a selection method in which the start pixel moves upward by one pixel at a time.

  FIG. 10D shows still another embodiment of the present invention. In FIG. 10D, the movement amount in the pixel group is the upper left direction of (−1, −1), and the movement amount between the pixel groups is (0, +1). ) Shows a selection method in which the start pixel moves downward by one pixel.

  The movement amounts of the H shift register and the V shift register when selecting a pixel by the four methods shown in FIG. Here, the signal line number of the data line is indicated by D, and the gate line number is indicated by G. When the shift direction of each shift register is selected by the shift direction input terminals (Dir_H, Dir_V) from the shift amounts shown here, the required clocks CLK_H, CLK_V are input, and a cyclic operation is performed. Is also input to the pulse input terminals Start_H and Start_V to operate the shift register, thereby selecting a pixel. From this table, it can be understood that the four methods shown in FIG. 10 require a minimum amount of movement between pixels and contribute to shortening the test time.

FIG. 11 shows how to select a pixel group different from the four methods shown in FIG.
In FIG. 11A, the movement amount for selecting a pixel in the pixel group is (+1, +1), which is the same as in FIG. 10A, and is in the lower right direction. However, the movement amount between the pixel groups is (−1, 0). The selection method in which the start pixel moves leftward one pixel at a time is shown. Again, note that the top and bottom and left and right coordinates of the display panel are each selected as being cyclic.

  Similarly, in FIG. 11B, as another embodiment of the present invention, the movement amount within the pixel group is the upper right direction of (+1, −1), and the movement amount between the pixel groups is (−1, −1). 0) shows a selection method in which the start pixel moves leftward by one pixel at a time.

  As still another embodiment of the present invention, FIG. 11C shows the movement amount within the pixel group in the lower left direction of (−1, +1), and the movement amount between the pixel groups is (+1, 0). The selection method in which the start pixel moves rightward by one pixel is shown.

  As still another embodiment of the present invention, FIG. 11D shows the movement amount in the pixel group is the upper left direction of (−1, −1), and the movement amount between the pixel groups is (+1, 0). ) Shows a selection method in which the start pixel moves downward by one pixel.

  In the four systems of FIG. 11 as well, it is possible to consider the movement amount of the H shift register and the movement amount of the V shift register similar to those in Table 1 above, and the movement amount between pixels so as to contribute to shortening the test time from now on. Will be understood to be minimal.

Next, the reason why high-accuracy measurement can be realized by the method according to FIGS. 10 and 11 will be described. FIG. 12 shows a pixel circuit having different data lines but different gate lines. Here, consider a case where the charge charged in the storage capacitor C1d of the lower pixel selected by the gate line G _n 1154 and the data line D _m 1150 is measured. The read voltage Vr is applied to the data line D _m, the ON voltage Von is applied to the gate line G _n 1154, as a result, stored in the storage capacitor C1d charges, transistor Q1d by the voltage Vr of the data line D _m Discharge through.

Here, considering the pixel selection transistor Q1c of a pixel having a common data line and different gate lines, the pixel selection transistor Q1c is in an off state because the gate line G _n-1 (1152) is Voff, but its off resistance Leak current. In particular, if the storage capacitor C1c is charged and waiting for the storage time to elapse, the potential difference between the source and drain of the pixel selection transistor Q1c is Vw−Vr, which is very large. Accordingly, the leakage current also increases. If the pixel selection transistor Q1c has been measured, the leakage current is very small because the potential difference between the source and drain is zero. That is, unlike the gate line data line in common, and the sum of the leakage current flowing as the data line D _m is large pixels that are waiting for the holding time to pass already charging increases. Therefore, the measurement value of the charge transfer amount changes depending on the measurement order within the pixel group. It should be noted that these are not limited to adjacent pixels but apply to all of a plurality of pixels having a common data line.

In the embodiment shown in FIG. 10 and FIG. 11, in order to solve the above problems, pixels are selected as an array for each pixel group as follows. First, regarding the selection of pixels, the following two points must be observed.
A1) The gate line of the charged pixel must not be selected until the holding time has elapsed.
A2) Other pixels connected to the data line of the pixel to be measured must not be charged.

In other words, the selection rule is as follows.
B1) For each pixel in the pixel group, each pixel is selected so that the gate line and the data line are different from each other.
B2) After a certain pixel is measured, a pixel having a common data line or gate line may be charged. However, the pixel to be charged must not have a common data line or gate line for any other pixel that holds the charged charge.

  Considering the embodiment of FIG. 10 and FIG. 11 in turn, any of the embodiments described in these figures satisfy the rules of B1 and B2, and do not bring about the inconvenience as shown in FIG. It will be understood.

  Next, another embodiment of a method for determining a pixel group (pixel arrangement) in a holding characteristic test, which is applied to the measurement algorithm of the present invention, will be described with reference to FIG.

  Here, in the above-described examination of FIG. 12, even if the data lines are charged so as to be held redundantly for a certain period in the holding capacity of a plurality of common pixels, unlike the method of selecting the pixels as shown in FIG. Even if there are a plurality of pixels connected to a common data line and holding a charge, if the number is not sufficiently small compared to the selection of the pixels in FIG. We focused on the fact that it can be measured with high accuracy to the extent that there is no practical problem.

That is, as shown in FIG. 15, the number of adjacent data lines used in one pixel group is limited to a predetermined number, and pixels connected to the predetermined number of data lines are pixels according to the following two rules. Select.
C1) The gate line of the charged pixel must not be selected until the holding time has elapsed.
C2) Select pixels so that the number of pixels holding charged charges connected to each data line is as small as possible.

  That is, as a method for selecting a pixel group that satisfies the above rules C1 and C2, an example of a selection method when the number R of data lines to be used is four based on FIG. One pixel group starts with pixel (1, 1) as a starting point, basically shifts (+1, +1) in the X and Y directions as the amount of movement for pixel selection, and finishes assigning to the R data lines to be used Then, (0, + (i × R)) (where i is an integer equal to or greater than 1) is shifted with respect to the starting point, and then (+ 1, + 1) is repeated. .

  In this way, the number of pixels having the same data line and overlapping the holding period is S / R (S / 4 in this example) with respect to the number S of pixels in one pixel group. Since the amount of leakage current due to the common data line is reduced, it is possible to measure with relatively high accuracy.

  The embodiment of FIG. 15 can be applied to (B) to (D) of FIG. 10 and (A) to (D) of FIG.

  This embodiment is applicable to the following cases, although the measurement accuracy is somewhat worse. That is, the present invention can be applied to a display panel in which the total number U of data lines of the display panel is smaller than the number S of pixels in one pixel group, that is, U <S. Further, in FIG. 1, the H shift register 140 for selecting the data lines of the display panel is configured by using a plurality of multiplexers, etc., so that there is a delay in selecting data lines up to a predetermined number R. However, when selecting a data line of a predetermined number R or more, it is suitable for a case where the delay time becomes too large to be ignored.

  As described above, the charge characteristic test and the retention characteristic test method of the storage capacitor of the active array matrix according to the present invention have been described with examples, but these are disclosed for the purpose of illustration. It should be noted that the present invention is not limited. Various modifications may be made, as will be readily understood by those skilled in the art. For example, although an example in which no waiting time is provided between the writing operation and the reading operation has been described in the charge characteristic test, a waiting time smaller than the holding time may be provided. Further, a method of moving more than 1 can be considered as the moving amount of the pixels in the pixel group, and the start pixel can be set at a place other than the end of the display panel. Furthermore, as an element applied to the test, it can also be applied to the measurement of the storage capacitor characteristics of an electroluminescence display panel of a method other than that shown in FIG.

  Note that in the present invention, a display panel in which the H shift register and / or the V shift register can be shifted in both directions has been described. However, the H shift register and / or the shift panel can be selected by sufficiently considering a margin for pixel selection time. The present invention can also be implemented for a display panel of a shift register in which the V shift register shifts only in a single direction.

  In addition, the present invention is not limited to the H shift register and V shift register included in the TFT array shown in FIG. 1, and the shift register may be arranged outside or inside the TFT array. Can be applied.

  Furthermore, the quality of the storage capacitor according to the present invention can be fed back to the previous stage of the TFT array manufacturing process and used to improve the quality of the process.

1 is a block diagram of a test circuit according to the present invention. FIG. 2 is a block diagram showing a circuit of an H shift register 140 in FIG. 1. FIG. 2 is a block diagram showing a circuit of a V shift register 142 in FIG. 1. It is a block diagram explaining the pixel circuit used as a test object by this invention. It is a timing chart explaining the test by this invention. It is a schematic diagram for demonstrating the sequence of the test shown in FIG. It is a flowchart explaining one of the Examples of this invention. It is a flowchart explaining in detail a part of the flowchart of FIG. FIG. 4 is a schematic diagram showing how to select a pixel group as an explanation of an embodiment of the present invention. As another explanation of the embodiment of the present invention, it is a schematic diagram showing another way of selecting a pixel group. FIG. 14 is a schematic diagram showing still another way of selecting a pixel group as another description of the embodiment of the present invention. It is a circuit diagram for demonstrating the effect by the method of FIG.10 and FIG.11. It is a block diagram of the testing apparatus by the test method of a prior art. It is a timing chart explaining the test method based on a prior art. It is a schematic diagram which shows another way of selecting a pixel group as another Example of this invention.

Explanation of symbols

100 TFT array measuring device 102 TFT array 110 Charge meter 122 Variable voltage source 124 Data terminal 126, 150 Shift direction terminal 128, 148 Clock signal terminal 130, 146 Pulse input terminal 140 H shift register 142 V shift register 149 Enable terminal 152 Gate line 154 Data line 156, 158, 160 Pixel circuit 162, 164 Connection line

Claims (13)

A method of measuring an active matrix TFT array including a plurality of pixel circuits having a storage capacitor, wherein each of the plurality of pixel circuits is for switching to connect the storage capacitor and a data line to the storage capacitor. A transistor, and a gate line that controls a switching operation of the switching transistor, wherein the plurality of pixel circuits include at least first, second, third, and fourth pixel circuits, and the measurement method includes:
A charge characteristic measurement is performed on the storage capacitor of the third pixel circuit that has not yet been charged after measuring the charge of the storage capacitor of the first pixel circuit after a predetermined holding time has elapsed after charging.
After measuring the charge of the holding capacitor of the second pixel circuit after a predetermined holding time has elapsed after charging, charge characteristics are measured on the holding capacitor of the fourth pixel circuit that has not been charged, and then charged.
Measuring the charge of the holding capacitor of the third pixel circuit after the predetermined holding time has elapsed;
A measuring method comprising: measuring a charge of a storage capacitor of the fourth pixel circuit after the predetermined holding time has elapsed. Before the step of measuring with the first pixel circuit after the predetermined holding time has passed, charge characteristics are measured on the holding capacitors of the first and second pixel circuits, and then charged.
Prior to the step of charging the storage capacitors of the first and second pixel circuits, the first and second pixel circuits are assigned to a first pixel group, and the third and fourth pixel circuits are assigned to the first and second pixel circuits. The measurement method according to claim 1, further comprising a step of assigning to the second pixel group. Assigning the pixel circuit to a pixel group;
The first pixel circuit is connected to a first data line and a first gate line, and the second pixel circuit is adjacent to the first data line and the first gate line. Assigned to be connected to the second gate line,
The third pixel circuit is connected to a second data line adjacent to the first data line and the first gate line, and the fourth pixel circuit is connected to the second data line. The measurement method according to claim 2, wherein allocation is performed so as to be connected to the second data line. Assigning the pixel circuit to a pixel group;
The first pixel circuit is connected to a first data line and a first gate line, and the second pixel circuit includes a second data line adjacent to the first data line; Assigned to be connected to a second gate line adjacent to the first gate line;
The third pixel circuit is connected to the first data line and a third gate line adjacent to the first gate line and opposite to the second gate line, and The measurement method according to claim 2, wherein the pixel circuit is assigned so as to be connected to the second data line and the first gate line. Assigning the pixel circuit to a pixel group;
The first pixel circuit is connected to a first data line and a first gate line, and the second pixel circuit includes a second data line adjacent to the first data line; Assigned to be connected to a second gate line adjacent to the first gate line;
The third pixel circuit is connected to the third data line adjacent to the first data line and on the opposite side of the second data line, and the first gate line, and 3. The measurement method according to claim 2, wherein the pixel circuit is assigned so as to be connected to the first data line and the second gate line. 4. When any one of the first, second, third and fourth pixel circuits is charged, the charged pixel circuit is not charged until the charge of the charged pixel circuit is measured. 6. The measuring method according to claim 1, wherein the other pixel circuit connected to the connected gate line is neither charged nor measured. When any one of the first, second, third, and fourth pixel circuits is measured, another pixel circuit connected to the data line connected to the measured pixel circuit is not charged. The measuring method according to claim 6. A method of measuring an active matrix TFT array including a plurality of pixel circuits having a storage capacitor, wherein each of the plurality of pixel circuits is configured to connect the storage capacitor and a data line to the storage capacitor. A switching transistor; and a gate line that controls a switching operation of the switching transistor. The plurality of pixel circuits include at least first, second, third, and fourth pixel circuits.
A predetermined number of pixel circuits are assigned to the first and second pixel groups from the plurality of pixel circuits,
Charge characteristics of each pixel circuit of the first pixel group are measured, and then charged.
For each pixel circuit of both pixel groups, the charge is measured from one of the pixel circuits of the first pixel group, the charge characteristic of one of the pixel circuits of the second pixel group is measured, and then charged. Done
Measuring charge from each pixel circuit of the second pixel group;
In the assigning step, in each of the first and second pixel groups, the pixel circuits are assigned such that the gate lines are different from each other,
A pixel circuit connected to a data line or a gate line connected to a pixel circuit for which charge measurement has been completed, and another pixel circuit connected to the gate line, which has not yet been charged, is charged next. And measuring each pixel circuit of the first and second pixel groups. The assignment in each of the first and second pixel groups in the assigning step is such that each pixel circuit assigns not only a gate line but also a data line to each other,
When charging a pixel circuit connected to a data line or a gate line connected to a pixel circuit for which charge measurement has been completed, select a pixel circuit that is not charged with another pixel circuit connected to the data line or the gate line. 9. The measuring method according to claim 8, wherein the pixel circuits of the first and second pixel groups are assigned so as to be charged next.   The measurement method according to claim 1, wherein the TFT array includes a bidirectional shift register.   11. The measurement method according to claim 1, wherein charge characteristic measurement is performed by charging the storage capacitor and immediately measuring the charge of the storage capacitor.   11. The measurement method according to claim 1, wherein the charge characteristic measurement includes charging the storage capacitor and measuring the charge of the storage capacitor before the predetermined holding time elapses. . A method of measuring an active matrix TFT array including a plurality of pixel circuits having a storage capacitor, wherein each of the plurality of pixel circuits is for switching to connect the storage capacitor and a data line to the storage capacitor. A transistor, and a gate line that controls a switching operation of the switching transistor, wherein the plurality of pixel circuits include at least first, second, third, and fourth pixel circuits, and the measurement method includes:
Measuring the charge of the holding capacitor of the first pixel circuit after a predetermined holding time has elapsed after charging, charging the holding capacitor of the third pixel circuit not yet charged, and measuring the charge of the holding capacitor; Then charge the holding capacity,
Measuring the charge of the holding capacitor of the second pixel circuit after a predetermined holding time has elapsed after charging, charging the holding capacitor of the fourth pixel circuit that has not been charged, and measuring the charge of the holding capacitor; Then charge the holding capacity,
Measuring the charge of the holding capacitor of the third pixel circuit after the predetermined holding time has elapsed;
A measuring method comprising: measuring a charge of a storage capacitor of the fourth pixel circuit after the predetermined holding time has elapsed.

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