JP2007228156A - Movement detection processing apparatus and method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a movement detection processing apparatus capable of preventing the reduction of a processing speed and the increase of power consumption. <P>SOLUTION: A searching object block storing RAM 12 and a reference block storing RAM 14 are connected to an address generation circuit 16. The pixel data of a searching object block and the pixel data of a reference block are inputted to an absolute difference value calculation circuit 24 in accordance with an address signal and an absolute difference value is calculated. A maximum value detection circuit 42 detects a maximum value of these stored values and outputs area information indicating an area corresponding to the maximum value and a clock signal to an address generation circuit 16. An accumulative operation circuit 32 calculates the sum of absolute difference values for one block from the absolute difference values, outputs the calculated summed absolute difference value (SAD) to an SAD value comparing circuit 52, and when a state that the SAD value is not minimum is detected, generates a reset signal 54 and interrupts the absolute difference value calculation of the block being processed at present. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a motion detection processing apparatus and method for performing motion search processing by encoding moving images.

  2. Description of the Related Art In recent years, in motion picture encoding technology, a motion detection technology has been developed that increases the encoding efficiency by obtaining a change from a past frame (reference frame) with respect to the current frame and encoding it as a motion vector. Yes. At the time of decoding, the current frame is restored from information on the motion vector and the reference frame.

  This motion detection is performed by searching a reference frame in order to search for a variation from the reference frame with respect to a search target block of 8 pixels × 8 pixels arranged in a current frame indicating an image of the current frame. Set. Next, by searching for a block having the same shape as the search target block within this search range, the variation of the target block is expressed as a motion vector.

  As a method for searching for blocks having the same shape, a method called a sum of absolute differences is used. It is as follows when expressed in mathematical formulas.

ここで、P1（x,y）は現在フレームの探索対象ブロックにおける（x,y）位置における画素値を示し、P2（x,y）は参照フレームの参照ブロックにおける（x、y）位置における画素値を示し、ＳＡＤはこれら画素値の差分絶対値和である。

Here, P1 (x, y) indicates a pixel value at the (x, y) position in the search target block of the current frame, and P2 (x, y) indicates a pixel at the (x, y) position in the reference block of the reference frame. SAD is the sum of absolute differences of these pixel values.

  The above equation (1) is applied to a method of taking the absolute difference value of the pixel values at the same position in the blocks and accumulating them. When the SAD value is large, it means that the difference between the blocks is large, and it can be seen that the shapes of the images in the blocks are different. A block having the smallest SAD value in the search range can be recognized as a block having the same shape.

  As a configuration for performing such processing, for example, a search target block storage RAM having a 64-byte memory area for storing block image data of 8 pixels × 8 pixels, and an 8-bit value pixel in the reference block storage RAM, for example. Data is input, and addresses generated from the address generation circuit are simultaneously given to these RAMs. This is because the pixel values at the same position in the search target block and the reference block are output from both RAMs.

  The address generation circuit horizontally scans the pixel positions in the block every 8 pixels in the horizontal direction and sequentially sub-scans in the vertical direction to generate addresses that are similarly horizontally scanned.

  The pixel value read from the search target block storage RAM and the reference block storage RAM by this address is the difference absolute value calculation circuit for calculating the difference absolute value | P1 (x, y) −P2 (x, y) | Is input. The calculated difference absolute value is input to the accumulation operation circuit to obtain the sum of one block, and the SAD value comparison circuit detects the block having the smallest SAD value.

  In order to reduce the amount of calculation, a certain threshold value is set in the SAD value comparison circuit, and if the calculation result in the accumulation calculation circuit exceeds this threshold value, the accumulation calculation is interrupted and the calculation for the next reference block is performed. There is a case to move to.

In the invention described in the conventional document 1, the sum of absolute differences between two images separated in time series is calculated, and when the calculation result exceeds a predetermined threshold, the calculation in the narrow range search window is terminated. However, there is no disclosure that starts the sum operation from a large absolute difference value.
Japanese Patent Laid-Open No. 10-271514

  However, the above-described conventional configuration has a problem that the amount of calculation is so large that it cannot be processed by a general CPU or the power consumption becomes very large even if it can be processed.

  Therefore, dedicated hardware for performing the difference absolute value sum calculation is provided in the CPU or as another hardware accelerator, or when the SAD value exceeds a certain threshold, the calculation for the block is interrupted. Even if a technique such as this is used, in most cases, there is a problem that the processing speed is reduced and the power consumption is increased to become a bottleneck.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a motion detection processing apparatus and method that can prevent a decrease in processing speed and an increase in power consumption.

  In order to solve the above-described problem, the present invention stores first memory means for storing pixel data of a search target block on which motion search processing is performed, and pixel data relating to a reference block indicating the past of the search target block. A second memory means, an address generating means for supplying the same address to the first and second memory means, and a difference absolute value based on the pixel data designated by the address in the first and second memory means. Difference absolute value calculation means for calculating and outputting, accumulation calculation means for accumulating the difference absolute values to obtain the difference absolute value sum, difference absolute value sum comparison means for detecting the minimum value from the difference absolute value sum, difference absolute The difference absolute value storage means for holding the value output from the value calculation means, and the maximum value among the values held by the difference absolute value storage means is detected and corresponds to the maximum value A maximum value detecting means for detecting area information indicating rear, and the address generating means divides the block to be processed into a plurality of areas when starting the motion search process, and each of the divided areas has a predetermined value. Generates an address for reading each pixel data at the position, and the maximum value detection means identifies the area where the difference absolute value is the maximum value among the divided areas, and starts the difference absolute value sum calculation from the area having the maximum value It is characterized by making it.

  Further, in order to solve the above-described problem, the present invention uses pixel data specified by the same address in both the search target block subjected to motion search processing and the past reference block of the search target block. A difference absolute value calculation step for calculating a difference absolute value, a cumulative calculation step for accumulating the difference absolute value to obtain a difference absolute value sum, a difference absolute value sum comparison step for detecting a minimum value from the difference absolute value sum, Area information indicating the area corresponding to the maximum value while detecting the maximum value among the values stored in the difference absolute value storage process that holds the value output from the difference absolute value calculation process and the difference absolute value storage process The address is divided into a plurality of areas when the motion search process is started, and the address is divided into a plurality of areas. It is an address that specifies raw data, and the maximum value detection step identifies the area where the difference absolute value is the maximum value among the divided areas, and starts the difference absolute value sum calculation from the area having the maximum value. Features.

  ADVANTAGE OF THE INVENTION According to this invention, the motion detection processing apparatus which can prevent the fall of processing speed and the increase in power consumption is provided. For example, it can be expected that the increase of the accumulated value is accelerated from the feature of the image in the natural world. For example, in the difference absolute value sum comparing means, the calculation is performed by comparing with a certain threshold value or the minimum value of the accumulated difference value until then. Since the abort process can be performed and the decision to abort can be advanced, the processing speed can be improved and the power consumption can be reduced.

  Embodiments of a motion detection processing apparatus and method according to the present invention will now be described in detail with reference to the accompanying drawings. Referring to FIG. 1, there is shown an embodiment of a motion search circuit to which the present invention is applied. In the following description, portions that are not directly related to the present invention are not shown and described, and reference numerals of signals are represented by reference numerals of connection lines that appear.

  As shown in the figure, the motion search circuit 10 includes, for example, a search target block storage RAM 12 and a reference block storage RAM 14 each having a 64-byte memory area for storing 8 × 8 pixel block image data. Have. The search target block storage RAM 12 is a memory for storing pixel data (P1 (x, y)) of the search target block, and the reference block storage RAM 14 is a pixel data (P2 (x, y) of the reference block. ), And these memories may have the same size and the same configuration. Both the address signal output from the output 18 of the address generation circuit 16 are input to the search target block storage RAM 12 and the reference block storage RAM 14 at the same timing.

  The search target block storage RAM 12 and the reference block storage RAM 14 output pixel data at addresses corresponding to the address signal 18 to outputs 20 and 22, respectively. These outputs 20 and 22 are connected to a difference absolute value calculation circuit 24.

  The difference absolute value calculation circuit 24 is a circuit for calculating the difference absolute value (| P1 (x, y) −P2 (x, y) |) of input pixel data, and the calculation result is output to outputs 26 and 28. Output. The output 26 of the difference absolute value calculation circuit 24 is connected to the difference absolute value storage register 30 and the output 28 is connected to the accumulation calculation circuit 32.

  The difference absolute value storage register 30 is provided for 4 bytes so as to hold the difference absolute values for four locations among the 64 difference absolute values in the 8 × 8 pixel block.

  FIG. 2 shows an 8 × 8 pixel block 200 in which pixel addresses “0” to “63” are arranged. The block 200 of 8 × 8 pixels is divided into four areas, that is, a first area 202, a second area 204, a third area 206, and a fourth area 208, and the difference absolute value storage register 30 has one location from each of the areas 202 to 208. Holds the absolute difference value. The output 40 of the absolute difference storage register 30 is connected to the maximum value detection circuit 42.

  The maximum value detection circuit 42 detects the maximum value among the four values stored in the absolute difference storage register 30 and outputs to the output 44 area information indicating in which area the maximum value was included. Output. This output 44 is connected to the address generation circuit 16. Further, the maximum value detection circuit 42 outputs a clock signal to the output 45 and supplies it to the address generation circuit 16. The maximum value detection circuit 42, when two or three difference absolute values of the detected plurality of difference absolute values take the same value and are the maximum value, the difference between these maximum values. The area information of the area to which any of the absolute values belongs may be output. In addition, when the plurality of detected absolute difference values are all the same value, the process can be started immediately from any area.

  The cumulative calculation circuit 32 calculates the sum of one block from the difference absolute value calculated by the difference absolute value calculation circuit 24, and outputs the calculated difference absolute value sum (SAD) to the output 50. The output 50 is connected to the SAD value comparison circuit 52.

  The SAD value comparison circuit 52 detects whether or not the SAD value is the minimum, and if it detects that the SAD value is not the minimum even during the accumulation, it generates a reset signal 54 and outputs it to the output 54. Output. The difference absolute value calculation of the block currently being processed is interrupted by this reset signal.

  Referring to FIG. 3, the order of address signals output from the address generation circuit 16 for the 8 × 8 pixel block 200 shown in FIG. 2 is shown. The pixel addresses “0” to “63” are stored in the search target block storage RAM 12 and the reference block storage RAM 14.

  An 8 × 8 pixel block 200 is divided into four areas, a first area 202, a second area 204, a third area 206, and a fourth area 208. Note that the four division is an example, and may be divided into a plurality of other division numbers. The address generation circuit 16 accesses each area in the order indicated by the arrows in FIG. In this case, the address generation circuit 16 outputs an address signal 18 having a 6-bit value to each of the areas 202 to 208 as shown in FIGS. An example of the internal configuration of the address generation circuit 16 for generating the address signal 18 is shown in FIG.

  The address generation circuit 16 in this embodiment divides a 6-bit address into 2 bits. The address generation circuit 16 includes generation circuits 800 to 808 that generate the 2-bit numerical value. The generation circuits 800 to 808 are respectively supplied with the area information 44, the clock 45, and the reset signal 54, and output the generated 2-bit numerical values to the outputs 810 to 818, respectively.

  The generation states of 2-bit addresses output from the generation circuits 800 to 808 are shown in FIGS. 9 to 13 show state transition diagrams of the generation circuits 800 to 808, respectively. The numerical values enclosed in circles indicate the values that are output from the outputs OUT810 to 818 when in this state. The output 810 of the generation circuit 802 is connected to the bit connection circuit 820. Outputs 812 and 814 of the generation circuits 802 and 804 are connected to the inputs B and A of the selection circuit 830, respectively. Outputs 816 and 818 of the generation circuits 806 and 808 are connected to the inputs B and A of the selection circuit 832 respectively.

  The selection circuits 830 and 832 are selector circuits that select values input to the inputs A and B, respectively, according to area information input to the input 44. Specifically, one selection circuit 830 selects a value to be input to the input A side when the area information 44 indicates the first area or the third area, and the area information 44 indicates the second area or the second area. When four areas are shown, the value input to the input B side is selected. The other selection circuit 832 selects a value input to the input A side when the area information 44 indicates the first area or the second area, and the area information 44 indicates the third area or the fourth area. If so, select the value to be input to the input B side. The selection circuits 830 and 832 output the selected values to outputs 840 and 842, respectively. These outputs 840 and 842 are connected to the bit connection circuit 820.

  The bit concatenation circuit 820 sets the output 810 of the generation circuit 800 to bits 1 and 0, the output 840 of the selection circuit 830 to bits 3 and 2, and the output 842 of the selection circuit 832 to bits 5 and 4, The 6-bit address signal 18 is generated by concatenating the values. This bit connection circuit 820 forms the output of the address generation circuit 16.

  As described above, the addresses shown in FIGS. 4 to 7 are obtained by combining the numerical values output from the generation circuits 800 to 808 based on the area information of the first area 202 to the fourth area 208.

  With the above configuration, the operation of the motion search circuit 10 will be described with reference to FIG. First, when the reset signal 54 is released to enter an operation state (time t1), the maximum value detection circuit 42 outputs area information 44 for switching the first area 202 to the fourth area 208 every clock (S1400). Since the generation circuits 800 to 808 after the reset release are in the initial state, the address generation circuit 16 switches the addresses “0”, “4”, and the like by switching the area information 44 in the order of the first area 202 to the fourth area 208. The address signal 18 is sequentially output in the order of “32” and “36” (S1402). These addresses indicate the upper left positions in the respective areas 202 to 208.

  The data at the position indicated by the address signal 18 is output from the search target block storage RAM 12 and the reference block storage RAM 14, and the absolute difference is calculated by the absolute value calculation circuit 24 every minute. Is passed to the difference absolute value storage register 30 and the cumulative arithmetic circuit 32. The maximum value detection circuit 42 detects the maximum value of the four values stored in the difference absolute value storage register 30 (S1404), and uses the area information 44 when the detected value is output as the address generation circuit. At the same time, the clock 45 that has been stopped is driven (S1406).

  The address generation circuit 16 continuously outputs the address for the area where the maximum difference absolute value was included by the clock 45 and the area information 44 (S1408), and the difference absolute value calculation circuit 24 in that area The difference absolute value is calculated (S1410), and the difference absolute value is accumulated in the accumulation operation circuit 32 (S1412).

  Also in this embodiment, as shown in FIG. 15, when the SAD value during the calculation exceeds a predetermined threshold (timing T1, T2) or exceeds the minimum value up to that point, the calculation for the block is aborted. Reduce the amount of computation.

  As described above, according to the above-described embodiment, the 8 × 8 pixel block is divided into a plurality of, for example, four parts, and the difference absolute value calculation is first performed on the pixel data of each area, and the calculation is continued from the area having the maximum value. Continue to accumulate. As a feature of the image, the neighborhood of the pixel value at a certain position tends to have a similar value, and the low frequency component is dominant, so the area having the maximum absolute value of the difference is accumulated first, In addition, the first four absolute difference calculations performed to identify the area having the maximum value are also accumulated to obtain the SAD value. For this reason, as shown in FIG. 9, it is possible to accelerate the increase in the accumulated value with a small computation overhead, and therefore, it is possible to advance the timing at which the computation is aborted. As a result, the processing amount for performing the motion detection process can be reduced, the processing capability can be improved, and the power consumption can be reduced.

  Next, a second embodiment to which the present invention is applied will be described with reference to FIG. The motion search circuit 1600 according to the present embodiment is similar to that shown in FIG. Unlike the embodiment shown in FIG. 1, the other configuration may be the same as that of the embodiment shown in FIG.

  The SAD value evaluation circuit 1602 compares the sum of absolute differences (SAD) at one location in each of the four divided areas with a preset value. The SAD value evaluation circuit 1602 first compares the SAD value for each pixel data in each area with a preset threshold value in order to determine the four divided areas 202 to 208 (FIG. 2). The SAD value evaluation circuit 1602 generates an enable interrupt signal 1604 when the SAD value is smaller than the threshold value. The SAD value evaluation circuit 1602 outputs the generated interrupt signal to the output 1604, and this output is connected to the maximum value detection circuit 1606.

  The maximum value detection circuit 1606 in this embodiment has the same function as that of the maximum value detection circuit 42 shown in FIG. 1. When the enable interrupt signal 1604 is input, the maximum value detection operation is stopped and the area information For example, a signal indicating the first area is immediately output, and calculation for calculating the sum of absolute differences in the motion search circuit 1600 is started.

  In the present embodiment, when the search target block and the reference block are the same, the SAD value calculation calculation is not interrupted halfway and the SAD value calculation is performed up to the last block over the entire block. In this case, since the same result is obtained from any of the four divided areas, the maximum value detection process for determining the area is not required, and the calculation can be started from any area.

  As described above, according to the present embodiment, the maximum value detection process can be interrupted by the interrupt signal 1604 when the SAD value for each pixel data in each of the four divided areas is smaller than a preset threshold value. As a result, the latency required for maximum value detection can be eliminated. This latency can be minimized when processing is performed by a dedicated circuit in the configuration shown in FIG. If the same processing is performed using general-purpose RISC, etc., the latency may increase for maximum value detection, so by adding interrupt processing in the above embodiment, unnecessary maximum value detection processing is canceled. As a result, the processing speed can be improved and the power consumption can be reduced.

  In the first embodiment shown in FIG. 1, as the internal configuration of the address generation circuit 16, a configuration is shown in which addresses obtained by dividing a 6-bit address by two bits are separately generated and the divided information is connected. However, the present invention is not limited to this. For example, an offset value (“4” in the second area, “32” in the third area, In the case of an area, a configuration in which “36” is added may be adopted.

  In the first embodiment, a configuration for processing a block of 8 × 8 pixels is illustrated. However, the present invention is not limited to this. For example, the present invention can also be applied to a block of 16 × 16 pixels, which is an MPEG 4 processing unit. It is.

  Regarding the area division method, the block is divided into 4 × 4 pixel blocks and the upper left pixel of each block is calculated in order to obtain the maximum difference absolute value. However, the present invention is not limited to this. The number of area divisions, the division method, the pixel position for obtaining the maximum value, and the like are not limited to the above embodiment.

It is a block diagram of a motion search circuit to which the present invention is applied. It is a figure which shows dividing | segmenting the block of 8x8 drawing. It is a figure which shows the order of the address with respect to the divided | segmented block. It is a figure which shows the address of a 1st area. It is a figure which shows the address of a 2nd area. It is a figure which shows the address of a 3rd area. It is a figure which shows the address of a 4th area. It is a block diagram which shows the structural example of an address generation circuit. It is a state transition diagram of a generation circuit. It is a state transition diagram of a generation circuit. It is a state transition diagram of a generation circuit. It is a state transition diagram of a generation circuit. It is a state transition diagram of a generation circuit. It is a timing chart which shows operation | movement of a motion search circuit. It is a figure which shows the example of an abort timing of a calculation. It is a block diagram which shows the other Example of a motion search circuit.

Explanation of symbols

10 Motion search circuit
12 Search target block storage RAM
14 Reference block storage RAM
16 Address generation circuit
24 Difference absolute value calculation circuit
30 Difference absolute value storage register
32 Cumulative operation circuit
42 Maximum value detection circuit
52 SAD value comparison circuit

Claims (4)

First memory means for storing pixel data of a search target block to be subjected to motion search processing;
Second memory means for storing pixel data relating to a reference block indicating the past of the search target block;
Address generating means for supplying the same address to the first and second memory means;
Difference absolute value calculating means for calculating and outputting a difference absolute value based on the pixel data designated by the address in the first and second memory means;
Accumulating calculation means for accumulating the difference absolute value to obtain a difference absolute value sum;
Difference absolute value sum comparison means for detecting a minimum value from the difference absolute value sum;
Difference absolute value storage means for holding a value output from the difference absolute value calculation means;
A maximum value detecting means for detecting area information indicating an area corresponding to the maximum value, as well as detecting the maximum value among the values held by the absolute difference storage means;
The address generation unit divides a processing target block into a plurality of areas when starting a motion search process, and generates addresses for reading pixel data at predetermined positions in each of the divided areas,
The maximum value detecting means identifies an area having a maximum difference absolute value among the divided areas, and starts a difference absolute value sum calculation from the area having the maximum value. .   2. An apparatus according to claim 1, wherein said apparatus is connected to an output of said cumulative calculation means and generates an interrupt signal indicating that a maximum value detection process is unnecessary based on said sum of absolute differences. The evaluation means generates the interrupt signal when the difference absolute value sum for one piece of pixel data in each area divided into a plurality is smaller than a predetermined threshold, and performs a maximum value detection process. A motion detection processing device characterized by being interrupted. A difference absolute value calculation step of calculating a difference absolute value using pixel data designated by the same address in both the search target block subjected to motion search processing and the past reference block of the search target block; ,
A cumulative calculation step of accumulating the absolute difference value to obtain a differential absolute value sum;
A difference absolute value sum comparison step of detecting a minimum value from the difference absolute value sum;
A difference absolute value storage step for holding a value output from the difference absolute value calculation step;
A maximum value detecting step for detecting area information indicating an area corresponding to the maximum value, as well as detecting the maximum value among the values held in the difference absolute value storing step,
The address is an address that divides the search target block and the reference block into a plurality of areas when starting the motion search process, and specifies pixel data in each of the plurality of areas;
The maximum value detecting step identifies an area having a maximum difference absolute value among the divided areas, and starts a difference absolute value sum calculation from the area having the maximum value. .   The method according to claim 1, further comprising an evaluation step of generating an interrupt signal indicating that a maximum value detection process is unnecessary based on the sum of absolute differences obtained in the cumulative calculation step. The evaluation step generates the interrupt signal and interrupts the maximum value detection process when the difference absolute value sum for one pixel data in each area divided into a plurality is smaller than a predetermined threshold value. A motion detection processing method characterized by the above.

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