JP2007228052A - Reconfiguration data control circuit, and reconfiguration data control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a CPU load for rewriting configuration information, and to avoid useless rewriting of the configuration information. <P>SOLUTION: An input data controller 10 separates an input data into a header part and a data part. A header analyzer 20 analyzes the separated header part, and extracts a necessary configuration information memory address for the input data. When it is not possible to extract, the input data controller deletes the data part concerned. From the configuration information memory address, a configuration information controller 30 decides whether or not the configuration information corresponding to the input data exists in a reconfigurable integrated circuit unit 50. When the configuration information does not exist in the reconfigurable integrated circuit, the configuration information controller loads the corresponding configuration information from a configuration information memory 40 to the reconfigurable integrated circuit unit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to reconfiguration data control, and more particularly to a reconfiguration data control circuit and a reconfiguration data control method for writing configuration information to a reconfigurable integrated circuit unit.

  In recent years, logic circuits having reconfigurable integrated circuit units have become widespread, and the configuration information can be rewritten so that the data input to the reconfigurable integrated circuit unit can be processed by the data input to the logic circuit. The form to use is increasing.

  With this input data, in order to rewrite the configuration information so that the input data can be processed by the reconfigurable integrated circuit unit, the control CPU (Central Processing Unit) is used to analyze the input data, and the analyzed data A method is used in which relevant configuration information is loaded from a configuration information memory and written to a reconfigurable integrated circuit unit.

  However, the process of rewriting this reconfiguration information is too heavy for the CPU to ignore.The CPU analyzes the input data, calculates the configuration information from the analysis results, loads the configuration information from the configuration information memory, and configures it. There is a demand to reduce the performance of a series of operations such as writing information to a reconfigurable integrated circuit unit.

  In addition, when the input data is in various formats, the configuration information of the reconfigurable integrated circuit unit is written many times, and the overhead is so large that it cannot be ignored even when viewed from the whole processing of the logic circuit. It has become. Even when various input data are randomly input, it is desired that configuration information writing of a reconfigurable integrated circuit unit does not frequently occur.

  In order to solve such a problem, a reconfiguration control device having a function such as a DMA device is provided in a reconfiguration target arithmetic device, and the CPU needs to reconfigure the hardware of the arithmetic device For example, a technique is known in which another task is executed after a hardware reconfiguration instruction is issued until an operation completion notification is received from the arithmetic device (see, for example, Patent Document 1). When receiving the hardware reconfiguration instruction, the reconfiguration controller reads a configuration information word for hardware reconfiguration from the system memory and loads it into the configuration information register.

  In addition, for a circuit in which at least a part of the region where the circuit is to be reconfigured has a previous circuit that has been reconfigured before and the processing is being performed, the circuit overlaps with the previous circuit region. Divide the data for reconstruction into non-overlapping parts, reconfigure the non-overlapping parts in parallel with the processing of the previous circuit, and reconfigure the overlapping parts after the processing of the previous circuit is completed This technique is also known (see, for example, Patent Document 2). Header information is added to the processing data for reconfiguration, and reconfiguration control corresponding to the header information is performed.

Japanese Unexamined Patent Publication No. 2004-070869 (pages 5-6, FIG. 1) JP 2001-320271 A (Pages 6-7)

  However, in the technique described in Patent Document 1 described above, loading and writing operations of configuration information from the memory are performed by a hardware reconfiguration command from a host device such as a CPU, and the switching control of the configuration is performed by the CPU. Therefore, there is a problem that overhead for reconfiguration still remains.

  Further, in the technique described in Patent Document 2 described above, reconfiguration is performed based on the analyzed header information. However, even if processing data for reconfiguration that should not be input to the system is input, means for eliminating it is lacking. There is a problem that unnecessary configuration information may be written.

  Accordingly, an object of the present invention is to provide a reconfiguration data control circuit and a reconfiguration data control method that eliminate the overhead of the CPU for reconfiguration.

  Another object of the present invention is to provide a reconfiguration data control circuit and a reconfiguration data control method that avoid writing useless configuration information.

  The reconfiguration data control circuit of the present invention is a reconfiguration data control circuit for writing configuration information to a reconfigurable integrated circuit unit (50 in FIG. 1). 40), a data part to be processed in the integrated circuit unit, and an input data control part (10 in FIG. 1) that separates input data into a header part for designating configuration information for the data part and stores the data part When the header part is input from the input data control unit and analyzed, and the stored header data is found to match the header part, the configuration information memory address that is the storage address of the configuration information in the configuration information memory is determined. The header analysis unit (20 in FIG. 1) to be output and the configuration information memory address input from the header analysis unit correspond to the configuration information written in the integrated circuit unit. When the configuration information memory address does not correspond to any of the configuration information memory addresses, the configuration information control unit (30 in FIG. 1) loads the configuration information on the configuration information memory address input from the header analysis unit from the configuration information memory and writes it to the integrated circuit unit. ).

  Specifically, the header analysis unit (20 in FIG. 1) includes an input data analysis memory (23 in FIG. 3) that stores header data associated with the configuration information memory address, and searches the input data analysis memory to search the input data analysis memory. Detection is performed.

  In addition, when the detection cannot be performed in the header analysis unit (20 in FIG. 1), the input data control unit deletes the stored data unit.

  Further, the integrated circuit unit (50 in FIG. 1) is composed of an independently operable integrated circuit bank, and configuration information can be written for each integrated circuit bank.

  The configuration information control unit (30 in FIG. 1) also accesses the configuration information memory address of the configuration information written in the integrated circuit unit, the number of the destination integrated circuit bank, and the access to this configuration information by the input data. An LRU table (34 in FIG. 4) that stores a list of count values is provided. If there is a matching configuration information memory address as a result of searching the LRU table, the count value is incremented and the integration is performed. Output the circuit bank number to the input data control unit, and if there is no matching configuration information memory address, write the configuration information to the integrated circuit bank with the lowest count value and enter the number of the integrated circuit bank to write to The output to the data control unit, and the input data control unit outputs the integrated circuit unit corresponding to the integrated circuit bank number input from the configuration information control unit. The data portion is output to an input signal line to the network.

  The reconfiguration data control method of the present invention is a reconfiguration data control method in the reconfiguration data control circuit, wherein the input data control unit separates the input data into a header part and a data part, and the input data analysis part includes When the separated header part is analyzed and the stored header data is found to match the header part, the configuration information memory address that is the storage address of the configuration information in the configuration information memory is output to the configuration information control unit When the stored header data does not detect a match with the header portion, the input data control unit deletes the data portion, and the configuration information control unit starts loading and writing the configuration information. The configuration information control unit determines whether the configuration information of the configuration information memory address input from the input data analysis unit has been written to the integrated circuit unit. Determining, when the configuration information has been written to the integrated circuit unit, the input data control unit outputting the data portion to the integrated circuit unit, and when the configuration information has not been written to the integrated circuit unit The input data control unit waits for completion of writing and outputs the data unit to the integrated circuit unit.

  The first effect of the present invention is that since the reconfiguration data control circuit has a complete hardware configuration, the intervention of the CPU for the reconfiguration can be eliminated and overhead can be eliminated.

  The second effect of the present invention is that, if there is no header data that matches the header portion of the input data in the input data analysis memory, the input data control portion is configured to delete the data portion from the FIFO. This means that it is possible to avoid rewriting information and to prevent the data part that should not be input from being input to the integrated circuit unit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of configuration]
Referring to FIG. 1, a reconfiguration data control circuit according to an embodiment of the present invention is shown together with an integrated circuit unit 50. The integrated circuit unit 50 is configured by the configuration information supplied from the reconfiguration data control circuit and processes data. The integrated circuit unit 50 is divided into M integrated circuit banks that can operate independently, and each integrated circuit bank can be reconfigured in N ways.

  The reconfiguration data control circuit includes an input data control unit 10, a header analysis unit 20, a configuration information control unit 30, and a configuration information memory 40, and has a complete hardware configuration without a CPU. The configuration information memory 40 stores N pieces of configuration information in advance. Here, there is a relationship of M <N. Since the configuration information memory address is associated with the header portion of the input data, the header portion can designate any of N pieces of configuration information.

  Input data to be randomly input to the input data control unit 10 includes a data part to be processed in the integrated circuit unit 50 and a header part for designating configuration information for the data part. The input data control unit 10 separates the input data into a data part and a header part, and outputs the data part to the integrated circuit unit and the header part to the header analysis part 20. The integrated circuit bank in the integrated circuit unit that is the output destination of the data portion is designated by the configuration information control unit 30.

  The header analysis unit 20 analyzes the header part input from the input data control unit 10. As a result, when the stored header data that matches the header portion is detected, the configuration information memory address that is the storage address of the configuration information in the configuration information memory 40 is output to the configuration information control unit 30.

  The configuration information control unit 30 performs LRU management of the configuration information, and when the configuration information memory address is input from the header analysis unit 20, it matches one of the configuration information memory addresses corresponding to the configuration information written in the integrated circuit unit 50. Do or search. As a result, if they match, the write destination integrated circuit bank number is output to the input data control unit 10. On the other hand, if they do not match, the configuration information on the configuration information memory address input from the header analysis unit 20 is loaded from the configuration information memory 40 and written to the integrated circuit bank that is least frequently used. Then, the write destination integrated circuit bank number is output to the input data control unit 10.

  The input data control unit 10 outputs the data part to the integrated circuit bank of the integrated circuit bank number input from the configuration information control unit 30. The integrated circuit unit 50 processes the data portion of the input data in the state (re) configured as described above.

  Next, the input data control unit 10, the header analysis unit 20, and the configuration information control unit 30 will be described in detail with reference to FIGS.

  FIG. 2 shows details of the input data control unit 10, which is composed of a data separation unit 11, a FIFO management unit 12, and a FIFO group 13. The FIFO group 13 includes M FIFOs, and each of the FIFO1 to FIFOM can store a data portion. The number of FIFOs matches the number of integrated circuit banks in the integrated circuit unit 50. The data separation unit 11 separates the input data into a data part and a header part, and outputs the data part to the FIFO management part 12 and the header part to the header analysis part 20.

  The FIFO management unit 12 allocates one of the free FIFOs in the FIFO group 13 and writes the data unit. Then, the assigned FIFO number is output to the header analysis unit 20. When there is no header data that matches the header part based on the analysis result of the header part in the header analysis part 20, the FIFO management part 12 deletes the data part from the FIFO of the FIFO number input from the header analysis part 20. When the integrated circuit bank number to which the configuration information is written is input from the configuration information control unit 30, the data section is output from the FIFO of the FIFO number to the input signal line to the integrated circuit unit 50 corresponding to the integrated circuit bank number.

  FIG. 3 shows details of the header analysis unit 20, which includes an analysis memory search unit 21, a memory address output unit 22, and an input data analysis memory 23. In the input data analysis memory 23, header data for designating N pieces of configuration information stored in the configuration information memory 40 is registered in advance. The analysis memory search unit 21 sequentially reads the input data analysis memory 23, and searches for a header part input from the input data separation unit 11 of the input data control unit.

  As a result, if there is matching header data, the memory address output unit 22 configures the address used when searching as the configuration information memory address, along with the FIFO number input from the FIFO management unit 12 of the input data control unit 10. Output to the information control unit 30. On the other hand, if there is no matching header data, the FIFO number input from the input data control unit 10 is returned to the FIFO management unit 12 of the input data control unit 10.

  FIG. 4 shows details of the input data analysis memory 23. In the input data analysis memory 23, a header portion of input data that can be input to the reconfigurable integrated circuit unit 50 is registered in advance as header data. The header data 1 to N correspond to the memory addresses 1 to N of the configuration information memory 40, respectively. Therefore, the configuration information registered in the configuration information memory 40 corresponds to the header data 1 to N registered in the input data analysis memory 23, respectively.

  FIG. 5 shows details of the configuration information control unit 30, which is composed of an LRU table management unit 31, a bank number output unit 32, a configuration information read / write unit 33, and an LRU table 34. As shown in FIG. 6, the LRU table 34 includes a configuration information memory address of configuration information written in the integrated circuit unit 50, a write destination integrated circuit bank number, and a count of accesses to this configuration information by input data. Stores a list with values.

  The LRU table management unit 31 searches the LRU table 34 for the configuration information memory address input from the memory address output unit 22 of the header analysis unit 20. As a result, when there is a hit, the LRU table management unit 31 increments the count value of the LRU table 34. The bank number output unit 32 outputs the integrated circuit bank number corresponding to the configuration information memory address and the FIFO number input from the header analysis unit 20 to the input data control unit 10. In this way, by managing the configuration information obtained by analyzing input data using LRU processing, the reconfigurable integrated circuit unit can behave like a cache, and it depends on loading and writing of configuration information. Can reduce overhead.

  On the other hand, in the case of a mishit, the configuration information read / write unit 33 loads the configuration information on the configuration information memory address input from the header analysis unit 20 from the configuration information memory 40, and the count value in the LRU table 34 is the smallest. The configuration information is written to the integrated circuit bank having the integrated circuit bank number. Then, the LRU table management unit 31 overwrites the configuration information memory address of the LRU table 34 with the configuration information memory address input from the header analysis unit 20. The bank number output unit 32 outputs the integrated circuit bank number and the FIFO number input from the header analysis unit 20 to the input data control unit 10.

[Description of operation]
The operation of the reconfiguration data control circuit configured as described above will be described with reference to the time chart of FIG. Here, the first input data, the second input data, and the third input data are sequentially input, the configuration information for the first input data having the header portion “1” is not present in the LRU table 34, and the header portion is “2”. It is assumed that the configuration information for the second input data “” and the third input data having the header part “3” exists in the LRU table 34.

  In time zone T1, the input data control unit 10 assigns the FIFO with the number “1” to the first input data, and the data part obtained by separating the first input data has the FIFO number “1”. Written to FIFO. Also, the FIFO number “1” and the header part (referred to as “1”) are output to the header analysis unit 20.

  In time zone T2, the input data control unit assigns the FIFO with the number “2” to the second input data, and the data portion obtained by separating the second input data is the FIFO with the FIFO number “2”. Written to Also, the FIFO number “2” and the header part (“2”) are output to the header analysis unit 20.

  The header analysis unit 20 sequentially reads the input data analysis memory 23, and searches for header data that matches the header part “1” input from the input data control unit 10 in the time zone T1. As a result, since there is matching header data, the memory address used when the header data is searched is output to the configuration information control unit 30 as the configuration information memory address “1”. At this time, the FIFO number “1” input from the input data control unit 10 in the time zone T1 is also accompanied.

  In time zone T3, the input data control unit assigns the FIFO with the number “3” to the third input data, and the data portion obtained by separating the third input data is the FIFO with the FIFO number “3”. Written to Also, the FIFO number “3” and the header part (referred to as “3”) are output to the header analysis unit 20.

  The header analysis unit 20 sequentially reads the input data analysis memory 23 and searches for header data that matches the header part “2” input from the input data control unit 10 in the time zone T2. As a result, since there is matching header data, the memory address used when the header data is searched is output to the configuration information control unit 30 as the configuration information memory address “2”. At this time, the FIFO number “2” input from the input data control unit 10 in the time zone T2 is also accompanied.

  The configuration information control unit 30 sequentially reads the LRU table 34 and searches for the configuration information memory address “1” input in the time zone T2. Since the configuration information memory address “1” does not exist in the LRU table 34 under the initial assumption, the configuration information control unit 30 outputs the configuration information “1” to the integrated circuit unit 50 and starts writing.

  The output destination integrated circuit bank at this time corresponds to the integrated circuit bank having the smallest count value in the LRU table 34. As a result, the configuration information is written to the integrated circuit bank that is least frequently used.

  In the time zone T4, the header analysis unit 20 sequentially reads the input data analysis memory 23 and searches for header data that matches the header portion “3” input from the input data control unit 10 in the time zone T3. As a result, since matching header data exists, the memory address used when searching for the header data is output to the configuration information control unit 30 as the configuration information memory address “3”. At this time, the FIFO number “3” input from the input data control unit 10 in the time zone T3 is also accompanied.

  The configuration information control unit 30 sequentially reads the LRU table 34 and searches for the configuration information memory address “2” input in the time zone T3. Since the configuration information memory address “2” exists in the LRU table 34 by the initial assumption, the integrated circuit bank number “2” and the FIFO number “2” are output from the configuration information control unit 30 to the input data control unit 10. . Then, the count value paired with the configuration information memory address “2” is incremented.

  Since the writing of the configuration information “1” to the integrated circuit unit 50 started in the time zone T3 has not been completed, the configuration information “1” is continuously sent from the configuration information control unit 30 even in this time zone. Is output. Therefore, the output of the integrated circuit bank number “1” and the FIFO number “1” to the input data control unit 10 is suspended.

  In the time zone T5, the configuration information control unit 30 sequentially reads the LRU table 34 and searches for the configuration information memory address “3” input in the time zone T4. Since the configuration information memory address “3” exists in the LRU table 34 by the initial assumption, the integrated circuit bank number “3” and the FIFO number “3” are output from the configuration information control unit 30 to the input data control unit 10. . Then, the count value paired with the configuration information memory address “3” is incremented. Since the writing of the configuration information “1” started in the time zone T3 to the integrated circuit unit 50 continues until the end of the time zone T5, the configuration information “1” is continuously accumulated from the configuration information control unit 30 in this time zone. Output to the circuit unit 50.

  Further, the input data control unit 10 uses the integrated circuit unit corresponding to the integrated circuit bank number “2” as the data part stored in the FIFO with the FIFO number “2” input from the configuration information control unit 30 in the time zone T4. Output to the input signal line to 50. As a result, the data portion of the second input data is processed by the integrated circuit unit 50 configured by the configuration information specified by the header portion of the second input data.

  In time zone T6, the writing of configuration information “1” started from time zone T3 ended with the end of time zone T5. Therefore, the reserved FIFO number “1” and integrated circuit bank number “1” are the configuration information. The data is output from the control unit 10 to the input data control unit 10.

  Further, the input data control unit 10 uses the integrated circuit unit corresponding to the integrated circuit bank number “3” as the data part stored in the FIFO with the FIFO number “3” input from the configuration information control unit 30 in the time zone T5. Output to the input signal line to 50. As a result, the data portion of the third input data is processed by the integrated circuit unit 50 configured by the configuration information specified by the header portion of the third input data.

  In the time zone T7, the input data control unit 10 corresponds to the integrated circuit bank number “1” for the data portion in which the FIFO with the FIFO number “1” input from the configuration information control unit 30 in the time zone T6 is stored. Output to the input signal line to the integrated circuit unit 50. As a result, the data portion of the first input data is processed by the integrated circuit unit 50 configured by the configuration information specified by the header portion of the first input data.

  The above is the case where header data that matches the header portion of any input data exists in the input data analysis memory 23 of the header analysis unit 20. However, if there is no matching header data, the header analysis unit 20 returns the FIFO number input from the input data control unit 10 to the input data control unit 10. The input data control unit 10 deletes the data part stored in the FIFO having this FIFO number. In this way, it is possible to prevent the data portion that should not be input from being input to the integrated circuit unit 50 in advance.

  Further, since the stored contents of the input data analysis memory 23 and the configuration information memory 40 are associated in advance, the address of the input data analysis memory 23 in which the header data matches the header data in the header analysis unit 20 is the same as the configuration information memory address. can do.

  In addition, since the LRU table 34 is provided in the configuration information control unit 30 and the input status in the reconfigurable integrated circuit unit 50 is managed by the LRU processing, the rarely input data can be reconfigured. It can be driven out of the circuit, and can be brought close to a state in which rewriting of configuration information does not occur frequently.

  Further, even when the configuration information is rewritten by the configuration information control unit 30, the reconfigurable integrated circuit unit 50 has a bank configuration, so that the integrated circuit bank other than the integrated circuit bank in which the rewriting has occurred is provided. The data portion for can perform data processing.

The block diagram which shows the structure of embodiment of the reconfiguration | reconstruction data control circuit of this invention Block diagram showing details of input data control unit 10 Block diagram showing details of header analysis unit 20 Block diagram showing an example of data in the input data analysis memory 23 Block diagram showing details of configuration information control unit 30 Block diagram showing example data in LRU table 34 Timing chart showing an operation example of the reconfiguration data control circuit of the present invention

Explanation of symbols

10 Input data controller
11 Input data separator
12 FIFO manager
13 FIFO group
20 Input data analysis section
21 Analysis memory search part
22 Memory address output section
23 Input data analysis memory
30 Configuration information control unit
31 LRU table management department
32 Bank number output section
33 Configuration information read / write section
34 LRU table
40 Configuration information memory
50 integrated circuit units

Claims (6)

In a reconfiguration data control circuit that writes configuration information to a reconfigurable integrated circuit unit,
A configuration information memory in which the configuration information is stored in advance;
A data portion to be processed in the integrated circuit unit; an input data control portion for separating the input data into a header portion for designating configuration information for the data portion and storing the data portion;
When the header part is input from the input data control unit and analyzed, and when the stored header data matches the header part, the configuration information memory address which is the storage address of the configuration information in the configuration information memory is determined. Header analysis unit to output,
When the configuration information memory address input from the header analysis unit does not correspond to any of the configuration information memory addresses corresponding to the configuration information written in the integrated circuit unit, the configuration information memory address input from the header analysis unit A reconfiguration data control circuit comprising a configuration information control unit that loads the above configuration information from the configuration information memory and writes the configuration information into the integrated circuit unit.   2. The header analysis unit includes an input data analysis memory storing the header data associated with the configuration information memory address, and performs the detection by searching the input data analysis memory. Reconfiguration data control circuit.   3. The reconfigured data control circuit according to claim 1, wherein when the detection by the header analysis unit is not possible, the input data control unit deletes the stored data unit.   4. The integrated circuit unit according to claim 1, wherein the integrated circuit unit includes an integrated circuit bank that can operate independently, and configuration information can be written to each integrated circuit bank. Reconfiguration data control circuit. The configuration information control unit stores a list of the configuration information memory address of the configuration information written in the integrated circuit unit, the number of the destination integrated circuit bank, and the count value of access to the configuration information by the input data. With an LRU table
As a result of searching the LRU table, when there is a matching configuration information memory address, incrementing the count value and outputting the integrated circuit bank number to the input data control unit;
When there is no matching configuration information memory address, writing the configuration information to the integrated circuit bank having the lowest count value, and outputting the number of the integrated circuit bank to which the write is performed to the input data control unit;
5. The reconfiguration data control according to claim 4, wherein the input data control unit outputs the data unit to an input signal line to the integrated circuit unit corresponding to the integrated circuit bank number input from the configuration information control unit. circuit. A reconstruction data control method in the reconstruction data control circuit according to claim 1,
The input data control unit separating the input data into a header part and a data part;
When the input data analysis unit analyzes the separated header portion and detects the stored header data that matches the header portion, a configuration information memory address that is a storage address of the configuration information in the configuration information memory Output to the configuration information control unit, and when the stored header data does not detect a match with the header unit, the input data control unit deletes the data unit,
The configuration information control unit starts loading and writing configuration information;
The configuration information control unit determines whether the configuration information of the configuration information memory address input from the input data analysis unit has been written to the integrated circuit unit;
When the configuration information has been written to the integrated circuit unit, the input data control unit outputs the data unit to the integrated circuit unit;
The reconfiguration includes the step of waiting for completion of writing of the configuration information when the configuration information has not been written to the integrated circuit unit, and the input data control unit outputting the data unit to the integrated circuit unit Data control method.

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