JP2007227701A - Ferroelectric memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory excellent in operation characteristics in low voltage drive. <P>SOLUTION: The ferroelectric memory includes a memory cell MC having a ferroelectric capacitor Cf. When application voltage is assumed to be Vapp between both electrodes of a ferroelectric capacitor Cf and counter voltage of the ferroelectric capacitor Cf is assumed to be Vc, Vc/Vapp is 0.4 or more and 0.8 or less. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory.

  Ferroelectric memories have been proposed as semiconductor memories. Ferroelectric memory has features such as non-volatility, high-speed writing / reading, and low power consumption, and is one of the promising candidates for next-generation non-volatile memory.

By the way, as the driving voltage of the ferroelectric memory is lowered, there are increasing problems that the read margin of retained data is lowered and that an error of retaining reverse data occurs in an imprint test. In addition, it has been common knowledge that a ferroelectric memory is driven with a voltage that can obtain a residual polarization amount of 90% of the residual polarization amount at the time of saturation, as shown in Patent Document 1 or Non-Patent Document 1. In other words, it has been common knowledge to drive at a voltage more than three times the coercive voltage. However, in low voltage driving, if the coercive voltage is lowered to 1/3 or less of the driving voltage, the decrease (depolarization) of the polarization holding amount at 0 V increases, so that low voltage driving by simply reducing the coercive voltage is difficult.
JP 2000-156471 A Shinzo Sakuma and Takahashi Hayashi, "Ferroelectric memory for ultra-low voltage operation for portable devices", Oki Technical Review, Oki Electric Industry Co., Ltd., April 2002, No. 190, p. 36-39

  An object of the present invention is to provide a ferroelectric memory that is excellent in operating characteristics in low voltage driving.

(1) A ferroelectric memory according to an aspect of the present invention includes:
Having a memory cell including a ferroelectric capacitor;
When the applied voltage Vapp between the electrodes of the ferroelectric capacitor is Vc and the coercive voltage of the ferroelectric capacitor is Vc, Vc / Vapp is in the range of 0.4 to 0.8.

  According to this, Vc / Vapp is conventionally 1/3 or less, whereas under the above conditions, Vc / Vapp is set to a range of 0.4 or more and 0.8 or less. According to the above conditions, a relatively large Pr / Ps ratio can be secured in low-voltage driving. That is, since a large amount of polarization necessary for data retention can be secured, the operating characteristics of the ferroelectric memory can be improved.

(2) In this ferroelectric memory,
When the saturation polarization amount of the ferroelectric capacitor is Ps, the residual polarization amount when the ferroelectric capacitor is saturated is Pr, and σ = Vc / log ((Ps + Pr) / (Ps−Pr)), σ / Vapp may be in the range of 0.2 or less.

  According to this, at least 70% required as the ratio of Pr / Ps can be satisfied.

(3) In this ferroelectric memory,
Furthermore, σ / Vapp may be in the range of 0.12 or less.

  According to this, even if the hysteresis curve is shifted by imprinting, the ratio of Pr / Ps can be maintained at 70% or more.

(4) In this ferroelectric memory,
The ferroelectric material of the ferroelectric capacitor includes at least one of lead titanate and lead zirconate, has a tetragonal structure, and may have a (111) orientation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1A is a diagram illustrating an example of a ferroelectric memory according to the present embodiment, and FIG. 1B is a circuit diagram of the ferroelectric memory in FIG. 1A. (C) is a figure which shows an example of a hysteresis curve.

  First, the configuration and operation of the ferroelectric memory according to the present embodiment will be described.

  The ferroelectric memory 100 has a plurality of memory cells MC formed on the semiconductor substrate 10, and each memory cell MC is separated by an element isolation region 50. Each memory cell MC includes a (for example, n-channel) MOS transistor Tr and a ferroelectric capacitor Cf. Specifically, the MOS transistor Tr has a gate connected to the word line WL, a source 20 connected to the bit line BL, and a drain 22 connected to one end of the ferroelectric capacitor Cf via the plug 30. . The ferroelectric capacitor Cf includes first and second electrodes 40 and 42 and a ferroelectric film 44 provided between both electrodes, and the first electrode 40 at one end is interposed through the plug 30. The second electrode 44 at the other end is connected to the plate line PL. In the example shown in FIG. 1A, an interlayer insulating film 52 is provided on a semiconductor substrate 10 on which a MOS transistor Tr or the like is formed, and a ferroelectric capacitor Cf is provided on the interlayer insulating film 52. .

  Note that the memory cell is not limited to the 1T1C type structure illustrated in FIGS. 1A and 1B, and a 2T2C type, FET type, or the like can be applied.

  When writing logic “1” and “0” data in this memory cell MC, a drive voltage Vapp (or −Vapp) is applied between both electrodes of the ferroelectric capacitor Cf. Specifically, a selection voltage is applied to the word line WL to turn on the MOS transistor Tr, and a voltage of Vapp (or -Vapp) is applied between the bit line BL and the plate line PL. For example, when writing logic “0”, 0 V is applied to the bit line BL and Vapp is applied to the plate line PL. On the other hand, when writing logic “1”, Vapp is applied to the bit line BL and 0 V is applied to the plate line PL.

  Even if the applied voltage is removed, that is, the word line WL is not selected and the MOS transistor Tr is turned off, the data written in this way remains in the residual polarization (Pr or -Pr shown in FIG. 1C). ).

  When reading data from the memory cell MC, a selection voltage is applied to the word line WL to turn on the MOS transistor Tr, and Vapp is applied to the plate line PL. As a result, the amount of charge corresponding to the data stored in the ferroelectric capacitor Cf is released to the bit line BL. That is, different charge amounts are discharged to the bit line BL depending on the logic “0” or “1”, and the voltage appearing on the bit line BL is amplified by the sense amplifier, so that the read operation can be performed.

  In the operation of a ferroelectric memory, it is generally known that the driving voltage is three times or more the coercive voltage because the hysteresis curve of the ferroelectric capacitor is surely saturated. For example, referring to FIG. 1C, the absolute value of the driving voltage (maximum value of applied voltage) of the ferroelectric capacitor Cf is Vapp, and the coercive voltage (the amount of polarization is 0) of the ferroelectric capacitor Cf. Vc / Vapp is 1/3 or less, where Vc is the absolute value of the voltage at the time. On the other hand, it is desired to realize low voltage driving from the viewpoint of reduction of power consumption, etc. In this case, if the coercive voltage is decreased in proportion to the driving voltage, that is, Vc / Vapp is 1/3 in the low voltage driving. If it is as follows, the data retention performance of the memory is inferior, and the operation of the ferroelectric memory becomes unstable.

  Here, the relationship between Vapp, Vc, and σ indicating the squareness of the hysteresis curve will be considered with reference to FIGS. Note that σ = Vc / log ((Ps + Pr) / (Ps−Pr)), where Ps is the absolute value of the saturation polarization amount of the ferroelectric capacitor, and Pr is the residual polarization amount of the ferroelectric capacitor. Is the absolute value of.

  FIG. 2 is a diagram showing a change in the hysteresis curve of the ferroelectric capacitor when Vc is changed, and FIG. 3 is a diagram showing a change in the hysteresis curve when σ is changed.

  FIG. 2 shows the difference in hysteresis curves when Vc / Vapp = 0.2, 0.5, 0.8 when fixed at σ / Vapp = 0.15. According to this, when Vc / Vapp is small (when Vc / Vapp = 0.2), the residual polarization amount of the ferroelectric capacitor remains only about 50% with respect to the saturation polarization amount Ps, and the data retention performance is high. It turns out that it is low. On the other hand, when Vc / Vapp is large (when Vc / Vapp = 0.8), saturation polarization cannot be reached at Vapp in low voltage driving, that is, polarization inversion cannot be completely achieved at Vapp. Recognize. From the above, the remanent polarization amount becomes small if Vc / Vapp is too small or too large. Therefore, in order to improve the data retention performance, it is necessary to select Vc having an appropriate size with respect to Vapp. In this respect, in the case of Vc / Vapp = 0.5, the residual polarization quantity of the ferroelectric capacitor remains at a high ratio with respect to the saturation polarization quantity Ps, and the polarization is almost completely reversed at the drive voltage Vapp. It can be seen that the data retention performance is excellent.

  On the other hand, FIG. 3 shows the difference in hysteresis curve when σ / Vapp = 0.15, 0.25 and 0.35 when Vc / Vapp = 0.5 is fixed. According to this, it can be seen that as σ increases, the voltage required for complete polarization reversal increases, and the saturation of the hysteresis curve when taking a certain Vapp is worsened. That is, in low voltage driving, as σ increases, the residual polarization decreases, so it is necessary to suppress σ as small as possible.

  Next, the relationship between Vapp, Vc, and σ based on Pr / Ps will be considered with reference to FIGS. Here, FIG. 4 is a diagram showing ranges of σ / Vapp and Vc / Vapp where Pr / Ps ≧ 0.7, and FIG. 5 is a diagram when 20% imprint is present in FIG. is there.

The saturation polarization amount Ps is determined by the ferroelectric material of the ferroelectric capacitor. For example, when the ferroelectric material is a (111) highly oriented tetragonal lead zirconate titanate material on a platinum electrode. Typical Ps is about 30 μC / cm ² . According to the International Semiconductor Technology Roadmap (ITRS), it is said that the amount of switching charge required in the future is 40 μC / cm ² . Therefore, if 2Ps = 60 μC / cm ² , 2Pr / 2Ps = 40/60 = 67% is necessary to secure a switching charge amount of 2Pr = 40 μC / cm ² or more. Considering this, when looking at the ranges of σ / Vapp and Vc / Vapp where 2Pr is 70% or more of 2Ps, according to FIG. Furthermore, it can be seen that σ / Vapp is included in the entire range when 0.2 or less.

  On the other hand, the ferroelectric capacitor has a problem of Vc shift due to the imprint phenomenon, but it is known that Vc typically shifts about 20% of Vapp at present. Considering this, when the range of σ / Vapp and Vc / Vapp where 2Pr is 70% or more of 2Ps when 20% imprint is assumed, according to FIG. 5, Vc / Vapp is 0. It can be seen that it is 4 or more and 0.8 or less, and that σ / Vapp is included in a wide range when it is 0.12 or less. More preferably, Vc / Vapp is not less than 0.4 and not more than 0.7, and σ / Vapp is not more than 0.12 and is included in the entire range.

  From the above, in a ferroelectric memory driven at a low voltage, Vc / Vapp is in the range of 0.4 or more and 0.8 or less, preferably σ / Vapp is 0.2 or less, more preferably σ. When / Vapp is in the range of 0.12 or less, the operating characteristics can be improved. Further, by satisfying the above conditions, it is possible to suppress reverse data retention errors due to imprinting as much as possible in low voltage driving.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1A is a diagram illustrating an example of a ferroelectric memory according to the present embodiment, and FIG. 1B is a circuit diagram of the ferroelectric memory in FIG. 1A. (C) is a figure which shows an example of a hysteresis curve. It is a figure which shows the change of the hysteresis curve of a ferroelectric capacitor at the time of changing Vc. It is a figure which shows the change of the hysteresis curve at the time of changing (sigma). It is a figure which shows the range of (sigma) / Vapp and Vc / Vapp which are Pr / Ps> = 0.7. FIG. 5 is a diagram when 20% imprint is performed in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Source 22 ... Drain 30 ... Plug 40 ... 1st electrode 44 ... Ferroelectric film 44 ... 2nd electrode 50 ... Element isolation region 52 ... Interlayer insulating film 100 ... Ferroelectric memory

Claims (4)

Having a memory cell including a ferroelectric capacitor;
When the applied voltage between both electrodes of the ferroelectric capacitor is Vapp and the coercive voltage of the ferroelectric capacitor is Vc, Vc / Vapp is 0.4 or more and 0.8 or less. Dielectric memory. 2. The ferroelectric memory according to claim 1, wherein
When the saturation polarization amount of the ferroelectric capacitor is Ps, the residual polarization amount when the ferroelectric capacitor is saturated is Pr, and σ = Vc / log ((Ps + Pr) / (Ps−Pr)), σ A ferroelectric memory in which / Vapp is in the range of 0.2 or less. The ferroelectric memory according to claim 2, wherein
Furthermore, a ferroelectric memory in which σ / Vapp is in a range of 0.12 or less. The ferroelectric memory according to any one of claims 1 to 3,
A ferroelectric memory, wherein the ferroelectric material of the ferroelectric capacitor includes at least one of lead titanate and lead zirconate, has a tetragonal structure, and has a (111) orientation.

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