JP2007226361A - Image forming apparatus, memory controller, program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve an image forming apparatus for efficiently preventing illegal data from being read. <P>SOLUTION: An image formation apparatus 1 is provided with an image memory 20 for storing image data; an ICU part 18 for writing and reading image data through a plurality of data buses to the image memory 20; and an image printing part 21 for forming an image corresponding to image data read from the image memory 20 by the ICU part 18. Furthermore, the image forming apparatus 1 is provided with a bus exchange processing part 19 for exchanging the connection destination of the plurality of data buses connecting the image memory 20 to the ICU part 18 after the ICU part 18 operates writs and reads the image data for one page. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory control device for writing / reading data to / from a memory. In particular, the present invention relates to an image forming apparatus for writing / reading image data to / from an image memory.

  Usually, a complex image forming apparatus having functions such as a fax machine and a scanner has an image memory for storing (storing) captured image data before printing.

  By the way, such image memory often stores confidential image data. Therefore, it is preferable that the image memory has a structure in which stored image data is not easily read even when the image memory is detached from the image forming apparatus by a third party and analyzed alone.

  In this regard, for example, Patent Document 1 and Patent Document 2 disclose a technique for converting the bit array of a data bus connected to an image memory and encrypting the image data.

In addition, image data that has already been formed is erased from the image memory so that the image data is not illegally read from the image memory.
JP 63-107352 (published May 18, 1987) JP 2000-29790 (released January 28, 2000)

  However, in the configurations of Patent Documents 1 and 2, the entire image memory is encrypted with the same encryption key. Therefore, if the encryption key is leaked for some reason, the entire image memory is decrypted. Further, the same image data can be read out any number of times by using the encryption key.

  Further, when erasing image data from the image memory by an application, since the data size of the image data is large, considerable time is required for the erasing process.

  The present invention has been made in view of the above-described problems, and an object thereof is to realize an image forming apparatus, a memory control apparatus, a program, and a recording medium that can efficiently prevent unauthorized data reading. There is.

  In order to solve the above problems, an image forming apparatus according to the present invention is connected to an image memory for storing image data and the image memory via a plurality of data buses. An image forming apparatus comprising: a memory control unit that writes and reads image data to and from an image memory; and an engine unit that forms an image corresponding to the image data read from the image memory by the memory control unit. A bus replacement unit that performs a bus replacement process for changing a connection destination between the image memory and the memory control unit is provided for each of the plurality of data buses at predetermined timings.

  According to the above configuration, the memory control unit writes and reads image data to and from the image memory via a plurality of data buses. The bus replacement means changes the connection destination between the image memory and the memory control means for the plurality of data buses at predetermined timings.

  As a result, when the image data written in the image memory before the above timing is read after the above timing, the data bus connection destination has been changed (that is, the data bus has been replaced), so that the data has been read out. Image data cannot be decoded. The processing for changing the connection destination of the data bus (bus replacement processing) takes less time than the conventional image data erasing processing by an application. Therefore, it is possible to prevent leakage of an image corresponding to image data in a short time.

  On the other hand, image data written in the image memory after the above timing can be read out in a decodable manner because the connection destination of the data bus is not changed.

  As described above, a part of the image data written in the image memory can be decoded, but the rest can be made undecipherable.

  In the conventional technique in which the entire image memory is encrypted with the same data bus replacement pattern, there is a problem that once the replacement pattern is leaked, all image data can be decrypted. However, as described above, according to the present invention, even if the current replacement pattern leaks, the image data written before the timing is still undecipherable. Further, by using a plurality of data bus replacement patterns, each of the plurality of image data can be encrypted in a different state and then written to the image memory. Therefore, the leakage of image data can be further prevented as compared with the conventional technique in which the entire image memory is encrypted with the same data bus replacement pattern.

  As described above, according to the above configuration, even if image data is illegally read out in a process that requires only a short time of changing the connection destination of the data bus (bus replacement process), the image data In addition to making the image unreadable, it is possible to further prevent the leakage of image data as compared with the prior art, so that illegal data reading can be efficiently prevented.

Specific examples of the timing include the following.
For example, the bus replacement unit performs the bus replacement process after the memory control unit writes and reads image data for one page. As a result, even if image data of a page before the current page is read from the image memory, it cannot be decoded.

  In addition, when there are a plurality of data bus replacement patterns, the data bus replacement pattern can be changed for each page. Therefore, even if the image data of one page can be decoded accidentally, The image data cannot be decoded. Therefore, it is possible to improve the security of a job composed of a plurality of pages.

  The bus replacement unit may perform the bus replacement process after the memory control unit writes and reads image data for one job. As a result, even if image data of a job prior to the current job is read from the image memory, it cannot be decoded. Further, as compared with the case where the bus replacement process is performed for each page as described above, the frequency of the bus replacement process is reduced, and the total time required for the bus replacement process can be shortened. Furthermore, after the job is completed, that is, when job processing is not performed, the bus replacement processing can be performed, and other processing in the image forming apparatus is not affected.

  The image forming apparatus according to the present invention further comprises security setting means for setting whether or not reading is necessary for each job, and the bus replacement means includes image data of a job set by the security setting means as unreadable. The bus replacement processing may be performed after the memory control means performs writing and reading of the above.

  According to the above configuration, the user can input to the security setting means whether or not each job can be read out. Then, after the processing of the job set by the security setting means as unreadable is completed, the bus replacement processing is performed. For this reason, even if the image data of the job set as unreadable is illegally read from the image memory, it cannot be decoded.

  In this case, since the bus replacement process is performed only when the read is set to be impossible, the total time required for the bus replacement process can be minimized.

  The bus replacement means may perform the bus replacement processing after the memory control means writes and reads image data for a predetermined amount of memory area. As a result, the connection destination of the data bus is changed for each predetermined amount of image data. Therefore, even if image data written in a memory area different from the memory area currently accessed by the memory control means is read from the image memory, it cannot be decoded.

  The image forming apparatus of the present invention further includes an address storage unit that stores an address in the image memory of image data on which an image is formed by the engine unit, and the bus replacement unit includes the address storage unit. When the access request for the address stored in is received, the bus replacement process may be performed.

  As a result, even if image data that has already been imaged is illegally read out from the image memory, the data bus is switched, so that it cannot be decoded. In this way, it is possible to reliably prevent unauthorized reading of image data on which an image has already been formed.

  Furthermore, in the image forming apparatus of the present invention, it is preferable that the bus replacement unit performs the bus replacement process in units of bits.

  According to the above configuration, even if the image data is illegally read from the image memory, the data is converted bit by bit, so that it cannot be easily decoded.

  Furthermore, in the image forming apparatus according to the present invention, the plurality of data buses are divided into a plurality of groups each having a predetermined number (an integer of 2 or more), and each group includes the bus replacement unit. The bus replacement unit may perform the bus replacement process for the data buses included in the corresponding group.

  For example, when there are a large number of data buses such as 32 bits, part of the image data may be decoded unless the data buses are complicatedly replaced. Specifically, when only 2 bits out of 32 bits are replaced, 30 bits are read normally. In such a case, part of the image data may be decoded. In order to avoid such a situation, when data buses are exchanged in a complicated manner, the exchange pattern becomes enormous, and the process for specifying the exchange pattern becomes complicated.

  However, according to the above configuration, the plurality of data buses are divided into a plurality of groups each having a predetermined number (an integer of 2 or more), and the bus replacement unit exists corresponding to each group. That is, the group and the bus replacement means have a one-to-one correspondence. Each bus replacement unit changes the connection destination of the data bus included in the corresponding group.

  That is, if the number of groups is L, the number of data buses included in the group (the above-mentioned predetermined number) is M, and the total number of data buses is N, then N = L × M.

  As a result, each bus replacement means replaces a predetermined number M (<N) of data buses, and thus the replacement pattern is smaller than the number of replacement patterns of all data buses. As a result, the replacement pattern designation process in each bus replacement unit is simplified.

  Furthermore, since each bus replacement means replaces the data buses of the corresponding group, all the data buses are replaced in a complicated manner. As a result, it is possible to prevent a part of the image data from being decipherable.

  In order to solve the above problems, the memory control device of the present invention is connected to the memory via a memory and a plurality of data buses. Memory control means for writing and reading data, and a bus for performing bus replacement processing for changing the connection destination between the memory and the memory control means for the plurality of data buses at predetermined timings And a replacement means.

  According to the above configuration, when data written in the memory before the timing is read after the timing, the read data cannot be decoded because the connection destination of the data bus is changed. The bus replacement process takes less time than the conventional image data erasure process by an application. Therefore, data leakage can be prevented in a short time.

  On the other hand, data written to the memory after the above timing can be read in a readable manner because the connection destination of the data bus is not changed.

  In the conventional technique in which the entire memory is encrypted with the same data bus replacement pattern, there is a problem that once the replacement pattern is leaked, all data can be decrypted. However, as described above, according to the present invention, even if the current replacement pattern is leaked, the data written before the timing is still undecipherable. Furthermore, by using a plurality of data bus replacement patterns, each of the plurality of data can be encrypted in a different state and then written to the memory. Therefore, data leakage can be further prevented as compared with the conventional technique in which the entire memory is encrypted with the same data bus replacement pattern.

  As described above, according to the above-described configuration, even if data is illegally read out, the data can be made undecipherable and the leakage of data can be further prevented by a process that requires only a short time such as a bus replacement process. Therefore, illegal data reading can be efficiently prevented.

  The information processing apparatus may be realized by a computer. In this case, a program that causes the information processing apparatus to be realized by the computer by causing the computer to operate as the respective means, and a computer-readable program that records the program. Various recording media are also within the scope of the present invention.

  An image forming apparatus according to the present invention is connected to an image memory for storing image data and the image memory via a plurality of data buses, and the image data is transmitted to the image memory using the data bus. In an image forming apparatus comprising a memory control means for writing and reading data, and an engine unit for forming an image corresponding to the image data read from the image memory by the memory control means, for each predetermined timing, For the plurality of data buses, there are provided bus replacement means for performing a bus replacement process for changing a connection destination between the image memory and the memory control means.

  Thereby, when the image data written in the image memory before the timing is read after the timing, the read image data cannot be decoded because the connection destination of the data bus is changed. The bus replacement process takes less time than the conventional image data erasure process by an application. Therefore, it is possible to prevent leakage of an image corresponding to image data in a short time. As a result, illegal reading of data can be efficiently prevented.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.

  FIG. 1 is a block diagram illustrating an internal configuration of an image forming apparatus 1 according to the present embodiment. As illustrated in FIG. 1, the image forming apparatus 1 includes a CPU 11, a main memory 12, a ROM 13, a system controller 14, and an I / O unit 15, hard disk drive (HDD) 16, compression / decompression unit (CODEC) 17, ICU (image control unit) unit 18, bus replacement processing unit 19, image memory 20, and image printing unit 21.

  The CPU 11 performs processing according to a program recorded in the ROM 13 and controls each block in the image forming apparatus 1.

  The main memory 12 is a memory used when the CPU 11 performs calculations and the like. The system controller 14 is a chip set that manages the exchange of data generated among the CPU 11, the main memory 12, the ROM 13, and other blocks.

  An I / O (Input / Output) unit is an interface for connecting to an external device, such as a LAN board or USB. The I / O unit 15 acquires image data (print data) from an external device such as a personal computer.

  A hard disk drive (HDD) 16 is a storage device. In this embodiment, image data input from an external device via the I / O unit 15 and compressed by the compression / decompression unit 17 is temporarily stored. To do.

  The compression / decompression unit 17 performs compression / decompression processing of image data.

  The ICU unit 18 controls the flow of data among the compression / decompression unit 17, the bus replacement processing unit 19, the image memory 20, and the image printing unit 21 in accordance with an instruction from the CPU 11.

  Specifically, the ICU unit 18 causes the compression / decompression unit 17 to compress the image data received from the system controller 14. The compressed data is stored in the HDD 16 in response to an instruction from the CPU 11. Then, the ICU unit 18 sequentially reads the compressed image data stored in the HDD 16 in accordance with an instruction from the CPU 11, and performs decompression processing in the compression / decompression unit 17. Then, the ICU unit 18 controls the image memory 20 by the memory control signal and writes the decompressed image data to the image memory 20. At this time, the ICU unit 18 designates an address for writing image data through the memory address bus, and outputs the image data to be written through the memory data bus (hereinafter simply referred to as the data bus). The image data is written into the image memory 20 via the bus replacement processing unit 19.

  The ICU unit 18 sequentially reads out the image data written in the image memory 20 in accordance with an instruction from the CPU 11 and causes the image printing unit 21 to perform a printing process.

  The bus replacement processing unit 19 switches the connection between the data bus from the ICU unit 18 and the data bus from the image memory 20. In other words, the bus replacement processing unit determines the connection destination between the image memory 20 and the ICU unit 18 for a plurality of data buses (four in this case) connecting the image memory 20 and the ICU unit 18. The bus replacement process to be changed (replaced) is performed. The bus replacement processing unit 19 includes a register unit 22 and a bus swap unit 23.

  FIG. 2 is a diagram illustrating an internal configuration of the bus replacement processing unit 19. As shown in FIG. 2, the bus swap unit 23 includes 4-bit data buses 24a-0 to 24a-3 of bit0,..., Bit3 on the ICU unit 18 side, and bit0,. Switches 25-1 to 25-4 and switches 26-1 to 26-4 for switching the connection with the 4-bit data buses 24 b-0 to 24 b-3 are provided.

  The switches 25-1 to 25-4 are used for writing, that is, when image data is transmitted from the data bus 24a-0 to 24a-3 on the ICU side to the data bus 24b-0 to 24b-3 on the image memory 20 side. This switch is effective (low impedance). The switches 25-1 to 25-4 change the connection destination between the image memory 20 and the ICU unit 18 for the data bus at the time of writing.

  Further, the switches 26-1 to 26-4 transmit image data from the data bus 24b-0 to 24b-3 on the image memory 20 side to the data buses 24a-0 to 24a-3 on the ICU side at the time of reading. This switch is effective (low impedance) when The switches 26-1 to 26-4 change the connection destination between the image memory 20 and the ICU unit 18 for the data bus at the time of reading.

  The register unit 22 stores the setting conditions for the replacement operation in the bus swap unit 23 transmitted from the ICU unit 18. The register unit 22 receives a CS / RD / WR control signal, a local address bus, a local data bus, and a clock from the ICU unit 18.

  The CS / RD / WR control signal is a chip select signal for designating a chip and a signal indicating whether the access is read or write.

  The local address bus signal is a 1-bit signal that designates an RD / WR bus pattern register, which will be described later, and is output from the ICU unit 18 to the register unit 22 at a timing set in the register unit 22.

  The local data bus signal indicates a 5-bit WR bus pattern register value and an RD bus pattern register value indicating a bus swap pattern, and a 1-bit RW bit register value. The WR bus pattern register value is a bus pattern register value used at the time of writing, and the RD bus pattern register value is a bus pattern register value used at the time of reading.

  When the RW bit register value is “0”, the bus swap unit 23 turns off the switches 25-1 to 25-4 (high impedance), and when the RW bit register specification is “1”, the switch 26-1 is written. ˜4 is off (high impedance).

  Further, when the RW bit register value is “1”, the bus swap unit 23 controls the switches 25-1 to 25-4 according to the WR bus pattern register value set in the register unit 22, and the ICU side The connection destinations of the data buses 24a-0 to 3 and the data buses 24b-0 to 3 on the image memory 20 side are switched. Similarly, when the RW bit register specification is “0”, the bus swap unit 23 controls the switch according to the RD bus pattern register value set in the register unit 22, and the data bus 24 a on the ICU side. The connection destinations of −0 to 3 and the data bus 24b-0 to 3 on the image memory 20 side are switched.

  FIG. 3 is a table showing the correspondence between the WR / RD bus pattern register value and the connection destination replacement pattern between the image memory 20 and the ICU unit 18 for the four data buses of bits 0 to 3. . The bus swap unit 23 stores the table shown in FIG. 3 in advance, reads a bus pattern (replacement pattern) corresponding to the WR / RD bus pattern register value set in the register unit 22 from the table, and reads the bus The switches 25-1 to 4 and 26-1 to 4 are controlled so as to form a pattern.

  The image memory 20 is a volatile memory, and temporarily stores image data before an image is formed by the image printing unit 21.

  The image printing unit 21 is a printer engine, and forms an image corresponding to the image data sent from the ICU unit 18 on a recording medium such as paper.

(Flow of write / read processing for image memory)
Next, the flow of image data writing (writing) / reading (reading) processing to the image memory 20 in the image forming apparatus 1 will be described with reference to the flowchart shown in FIG.

  First, when the image forming apparatus 1 is activated, the ICU unit 18 sets the WR / RD bus pattern register value of the register unit 22 to the initial value N in accordance with an instruction from the CPU 11 (S1). For example, the initial value N is “00000” (bus pattern No. 0) shown in FIG.

  At this time, when the HDD 16 stores the image data input from the I / O unit 15, the system controller 14 stores the image data in the main memory 12.

  Next, the CPU 11 determines whether image data (print data) is stored in the main memory 12 (S2). If the image data is not stored in the main memory 12 (No in S2), the process of S2 is repeated again.

  When the image data is stored in the main memory 12 (Yes in S2), the CPU 11 determines whether or not the image memory 20 has a free space (S3).

  If there is free space in the image memory 20 (Yes in S3), the ICU unit 18 sets the RW bit register of the register unit 22 to “1” in accordance with an instruction from the CPU 11. The bus swap unit 23 sets all the switches 26-1 to 4-4 used at the time of reading according to the RW bit register “1” set in the register unit 22 to high impedance. Further, the bus swap unit 23 controls the switches 25-1 to 25-4 so that a bus pattern (see FIG. 3) corresponding to the WR bus pattern register value is obtained (S4). Here, since the WR bus pattern register value is “00000”, the data bus connection destinations of bit 0, 1, 2, 3 on the ICU unit 18 side are bit 0, 1, 2, 3 on the image memory 20 side. Data bus.

  Next, the system controller 14 reads out image data from the main memory 12 and outputs it to the ICU unit 18 in accordance with an instruction from the CPU 11. The ICU unit 18 controls the image memory 20 by the memory control signal after the expansion processing by the compression / expansion unit 17 and writes the image data (print data) to the image memory 20 via the bus swap unit 23 (S5). ).

  Next, in accordance with an instruction from the CPU 11, the ICU unit 18 adds 1 to the WR bus pattern register value of the register unit 22 for each page (S6).

  That is, on the second page, since the WR bus pattern register value is “00001”, the connection destination of each data bus of bit 0, 1, 2, 3 on the ICU unit 18 side is bit 0, 1 on the image memory 20 side. , 3 and 2 data buses. That is, bit2 and bit3 are interchanged.

  Thereby, the image data of the first page is written according to the bus pattern (see FIG. 3) corresponding to the WR bus pattern register value “00000”, and the image data of the second page is set to the WR bus pattern register value “00001”. Data is written according to the corresponding bus pattern (see FIG. 3). Specifically, the image data of the second page is converted into data in which the values of bit 2 and bit 3 are interchanged and stored in the image memory 20. In this way, the image data of all pages is stored in the image memory 20.

  Thus, since the image data is written into the image memory 20 via the bus swap unit 23, the data is exchanged between bits according to the bus pattern (see FIG. 3) corresponding to the WR bus pattern register value. It will be.

  Thereafter, the CPU 11 determines whether or not the image printing unit 21 can print out (S7). Specifically, the CPU 11 determines whether or not the image printing unit 21 has completed warming up for a predetermined time. If printing output is not possible (No in S7), the process returns to S2.

  On the other hand, when printing output is possible (No in S7), the ICU unit 18 sets the RW bit register “0” in the register unit 22 in accordance with an instruction from the CPU 11. When the RW bit register “0” is set in the register unit 22, the bus swap unit 23 sets the write switches 25-1 to 25-4 to high impedance. Further, the bus swap unit 23 sets the read switches 26-1 to 26-4 so that the bus pattern (see FIG. 3) according to the RD bus pattern register value (here, the initial value N = “00000”) is obtained. Control (S8).

  Thereafter, the ICU unit 18 designates an address using a memory address bus, and reads image data from the designated address via the bus swap unit 23. The ICU unit 18 outputs the read image data to the image printing unit 21 to form an image (S9).

  Next, the ICU unit 18 adds 1 to the RD bus pattern register value of the register unit 22 for each page in accordance with an instruction from the CPU 11 (S10).

  As a result, the image data of the first page is read according to the bus pattern (see FIG. 3) corresponding to the RD bus pattern register value “00000”, and the image data of the second page is read by the RD bus pattern register value “00001”. The data is read in accordance with the bus pattern corresponding to (see FIG. 3). Specifically, the image data of the second page stored in the image memory 20 is converted into data in which the values of bit2 and bit3 are interchanged and read. However, as described above, when the image data of the second page is written into the image memory 20, the original image data is converted into data in which the values of bit2 and bit3 are interchanged. Therefore, at the time of reading, the values of bit2 and bit3 are interchanged again, and can be read as original image data. In this way, the image data of all pages is read from the image memory 20.

  Thereafter, the ICU unit 18 determines whether there is image data (print data) that has not been subjected to image formation processing (print processing) in the image printing unit 21 in the image memory 20 in accordance with an instruction from the CPU 11. (S11). If image data that has not undergone image formation processing exists in the image memory 20, the process returns to S7. On the other hand, if there is no image data that has not undergone image formation processing in the image memory 20, the process returns to S2.

  As described above, the bus replacement processing unit 19 sets the same bus pattern for each page when writing (writing) image data and when reading (reading) image data. Therefore, image data can be normally read by performing writing and reading via the bus replacement processing unit 19.

  On the other hand, even if the image data that has been subjected to image formation processing written in the image memory 20 is illegally read, the WR bus pattern register value for writing the image data to the image memory 20 and the current RD bus pattern The register value does not match. For this reason, even if image data that has undergone image formation processing is read from the image memory 20, it is read in an indecipherable state in which values are exchanged between bits, and the image leaks to a third party. Disappears.

(Bus swap timing)
In the above description, the bus replacement processing unit 19 changes (replaces) the connection destination between the ICU unit 18 and the image memory 20 for four data buses of bits 0 to 3 for each page (bus). It has been described as performing a replacement process. However, the timing of switching the connection destination of the data bus is not limited to this. FIG. 5 is a diagram illustrating various modified examples of the timing of switching the connection destination of the data bus.

  (Modification 1) The bus replacement processing unit 19 replaces the connection destination of the data bus for each job. That is, the ICU unit 18 may add 1 to the RW / RD bus pattern register value stored in the register unit 22 for each job in accordance with an instruction from the CPU 11. In this case, the frequency of the bus replacement process is reduced as compared with the case where the bus replacement process is performed for each page. For this reason, the time required for replacing the data bus can be shortened. Further, since the bus replacement process is performed after the job is completed, the bus replacement process can be performed when the job process is not performed, and other processes in the image forming apparatus 1 are not affected.

  (Modification 2) The connection destination of the data bus may be changed after the writing / reading process of the image data of the job that has received an instruction that reading is impossible.

  In this case, the ICU unit 18 is provided with a security setting unit that prompts the user to input whether or not to set unreadable for each job, and sets unreadable according to the user input. Note that the security setting unit may perform a setting that disables reading via an external device such as a personal computer. For example, the security setting unit may acquire a flag indicating whether reading is impossible together with the image data from the external device, analyze the flag, and set the reading disabled.

  The ICU unit 18 then stores the WR / RD bus pattern register stored in the register unit 22 when the writing / reading process of the image data of the job set to be unreadable by the security setting unit to the image memory 20 is completed. Change the value. As a result, the WR bus pattern register value at the time of writing the image data set as unreadable to the image memory 20 does not match the current RD bus pattern register value. For this reason, even if an unauthorized person reads out image data of a job set to be unreadable from the image memory 20 or reads out print data for which security settings have been made, the value is exchanged between bits. Is possible.

  Further, since the data bus connection destination is changed only when the writing / reading processing of the job for which reading is disabled is completed, the time required for the data bus replacement processing can be minimized.

  (Modification 3) The ICU unit 18 may change the WR / RD bus pattern register value stored in the register unit 22 in accordance with the address information specified by the memory address bus.

  For example, when the ICU unit 18 designates a predetermined value (“000000H”, “100000H”, “200000H”..., Shown in FIG. 5) as the memory address bus, the WR / Change the RD bus pattern register value. In other words, the ICU unit 18 changes the WR / RD bus pattern register value for each predetermined amount of memory area or for each predetermined amount of image data.

  Further, the ICU unit 18 may include an address storage unit that stores an address of an area in the image memory 20 in which image data in which the image forming process in the image printing unit 21 is completed is written. That is, after outputting the image data to the image printing unit 21, the ICU unit 18 stores the address where the image data was written in the address storage unit. The ICU unit 18 may change the RD bus pattern register value stored in the register unit 22 only when receiving an access request for the address stored in the address storage unit. As a result, even if there is unauthorized access to image data that has undergone image formation processing, it cannot be read in a decipherable state.

(Modification of bus swap unit)
In the above description, an example in which the data bus is 4 bits has been described. However, in recent years, there are some having a large processing capability such as 32 bits for high-speed correspondence. In this case, the connection pattern between each 32-bit data bus on the ICU unit 18 side and each 32-bit data bus on the image memory 20 side is enormous. For this reason, the number of bits indicating the WR / RD bus pattern register value increases.

  In addition, when the connection destinations of two data buses of 32 bits are interchanged with each other, since 30 bits are not interchanged, most of them can be decoded and information leakage may occur.

  Therefore, when the number of bits of the data bus is large, as shown in FIG. 6, it is preferable to provide sub-bus swap units 23-1 to 8 for every predetermined number of bits (4 bits in FIG. 6). Each of the sub-bus swap units 23-1 to 23-8 has the same configuration as that of the bus swap unit 23 shown in FIG. Then, each of the sub bus swap units 23-1 to 23-8 changes the connection destination of the four data buses according to the WR / RD bus pattern register value set in the register unit 22. The bus pattern is the same as in FIG.

  For example, in the sub-bus swap unit 23-2 corresponding to bit 4-7, bit 4-7 corresponds to bit 0-3, the data buses 24a-4 to 7 of bits 4 to 7 on the ICU side, and the image memory 20 side The connection with the data buses 24b-4 to 7 of the bits 4 to 7 is switched. When the WR / RD bus pattern register value is “00001”, the sub-bus swap unit 23-2 switches the connection between the bit 6 data bus on the ICU side and the bit 7 data bus on the image memory 20 side.

  Thus, by dividing 32 bits into 4 bits and switching the data bus connection for each 4 bits, the WR / RD bus pattern register value can be indicated by a low bit. Furthermore, since most of the 32 bits are replaced, even if image data is read out illegally, most of it cannot be decoded.

  As described above, the image forming apparatus 1 according to the present embodiment is connected to the image memory 20 that stores image data and the image memory 20 via a plurality of data buses (data buses). Are used to form an image corresponding to the image data read from the image memory 20 by the ICU unit (memory control means) 18 for writing and reading image data to and from the image memory 20. An image printing unit (engine unit) 21 is provided. Further, the image forming apparatus 1 includes a bus replacement processing unit (bus replacement unit) 19 that performs a bus replacement process for changing a connection destination between the image memory 20 and the ICU unit 18 for the plurality of data buses. Is provided.

  Thereby, when the image data written in the image memory 20 before the timing is read after the timing, the data bus connection destination is changed (that is, the data bus is replaced). The image data cannot be deciphered. The data bus replacement process takes less time than the conventional image data erasure process by an application. Therefore, it is possible to prevent leakage of an image corresponding to image data in a short time.

  On the other hand, the image data written in the image memory 20 after the above timing can be read out in a decodable manner because the connection destination of the data bus is not changed.

  As described above, a part of the image data written in the image memory 20 can be decoded, but the rest can be made undecipherable. Further, by making a plurality of bus patterns (replacement patterns) of the data bus (in the case of the above embodiment, 24 patterns: see FIG. 3), each of the plurality of image data is encrypted in a different state, and then the image memory 20 can be written. As a result, it is possible to prevent leakage of image data to a high degree as compared with the conventional technique in which the entire image memory 20 is encrypted with the same data bus replacement pattern.

  As described above, according to the above configuration, even if image data is illegally read out in a process that requires only a short time of changing the connection destination of the data bus (bus replacement process), the image data Since the image data can be made unreadable and leakage of image data can be highly prevented, illegal data reading can be efficiently prevented.

Specific examples of the timing include the following.
For example, the bus replacement processing unit 19 performs the bus replacement processing after the ICU unit 18 has written and read image data for one page. As a result, even if the image data of the page before the current page is read from the image memory 20, it cannot be decoded.

  Further, since there are 24 bus patterns, the bus patterns can be different for each page. Therefore, even if the image data of one page can be decoded accidentally, the image data of another page cannot be decoded. Therefore, it is possible to improve the security of a job composed of a plurality of pages.

  The bus replacement processing unit 19 may perform the bus replacement processing after the ICU unit 18 has written and read image data for one job. As a result, even if image data of a job prior to the current job is read from the image memory 20, it cannot be decoded. Further, as compared with the case where the bus replacement process is performed for each page as described above, the frequency of the bus replacement process is reduced, and the total time required for the bus replacement process can be shortened.

  Further, the image forming apparatus 1 may include a security setting unit (not shown) (security setting unit) that sets whether or not reading is necessary for each job. The bus replacement processing unit 19 may perform the bus replacement processing after the ICU unit 18 writes and reads the image data of the job set as unreadable by the security setting unit.

  According to the above configuration, the user can input to the security setting unit whether or not each job can be read out. Then, after the processing of the job set by the security setting unit as unreadable is completed, the data bus is replaced. For this reason, even if the image data of the job set to be unreadable is illegally read from the image memory 20, it cannot be decoded.

  In this case, since the bus replacement process is performed only when the read is set to be impossible, the total time required for the bus replacement process can be minimized.

  The bus replacement processing unit 19 may perform the bus replacement processing after the ICU unit 18 has written and read out image data for a predetermined amount of memory area. As a result, the connection destination of the data bus is changed for each predetermined amount of image data. Therefore, even if image data written in a memory area different from the memory area currently accessed by the ICU unit 18 is read from the image memory 20, it cannot be decoded.

  The image forming apparatus 1 further includes an address storage unit that stores the address in the image memory 20 of the image data on which the image is formed by the image printing unit 21, and the bus replacement processing unit 19 includes the address storage unit. The bus replacement process may be performed when an access request for an address stored in the unit is received.

  As a result, even if image data that has already been imaged is illegally read out from the image memory 20, the data bus is replaced, and therefore it cannot be decoded. In this way, it is possible to reliably prevent unauthorized reading of image data on which an image has already been formed.

  Furthermore, it is preferable that the bus replacement processing unit 19 performs the bus replacement processing in units of bits.

  According to the above configuration, even if the image data is illegally read out from the image memory 20, the data is converted bit by bit and cannot be easily decoded.

  Further, the plurality of data buses are divided into a plurality of groups each having a predetermined number (an integer of 2 or more), and the image forming apparatus 1 has a sub-bus swap unit (bus replacement unit) 23-1 for each group. -8, and each of the sub-bus swap units 23-1 to 23-8 may perform the bus replacement process on the data buses included in the corresponding group.

  That is, the number of groups is L (8 in FIG. 6), the number of data buses included in the group is M (4 in FIG. 6), and the total number of data buses is N (32 in FIG. 6). In this case, N = L × M.

  As a result, each of the sub-bus swap units 23-1 to 23-8 replaces a predetermined number M (<N) of data buses. Here, the number of M data bus replacement patterns is smaller than the number of bus patterns of all data buses. As a result, the bus pattern designation process in each of the sub-bus swap units 23-1 to 23-8 is simplified.

  Furthermore, since each of the sub-bus swap units 23-1 to 8 performs the above-described bus replacement process for the corresponding group of data buses, all the data buses are replaced in a complicated manner. As a result, it is possible to prevent a part of the image data from being decipherable.

  In the above embodiment, the image forming apparatus is described as an example. The features of the present invention are the ICU unit 18, the bus replacement processing unit 19, and the image memory 20 in the above embodiment. A memory control device including these blocks is not limited to an image forming apparatus, and can be incorporated into an information processing apparatus that needs to prevent data leakage.

  That is, the memory control device of the present invention is connected to the image memory (memory) 20 and the image memory via a plurality of data buses, and an ICU unit for writing and reading data using the data buses. 18 and a bus replacement processing unit 19 that changes a connection destination between the image memory 20 and the ICU unit 18 for the plurality of data buses at predetermined timings.

  As a result, even if the data is illegally read out in a short process such as a bus replacement process, the data can be made undecipherable and data leakage can be highly prevented. Data reading can be efficiently prevented.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  In the above description, the CPU 11 controls each block in accordance with a program stored in the ROM 13. However, an object of the present invention is to provide a recording medium in which a program code (execution format program, intermediate code program, source program) of a program of the image forming apparatus 1 which is software that realizes the above-described functions is recorded so as to be readable by a computer. This can also be achieved by supplying the image forming apparatus 1 and reading and executing the program code recorded on the recording medium by the computer (or CPU 11 or MPU).

  Examples of the recording medium include a tape system such as a magnetic tape and a cassette tape, a magnetic disk such as a floppy (registered trademark) disk / hard disk, and an optical disk such as a CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  The image forming apparatus 1 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Also, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

(Supplementary information)
A memory control device according to the present invention is a memory data destruction system having a bus swap circuit for swapping a data bus when a memory controller accesses an arbitrary memory area. Thereby, not all memory data is destroyed, but only unnecessary data can be destroyed (cannot be read). The image forming apparatus of the present invention uses the above memory data destruction system, Swap the data bus at any timing. Thus, by swapping the data bus at an arbitrary replacement timing, it is possible to destroy data in the memory at a timing that does not affect the operation of the apparatus.

In the above-described image forming apparatus, the data bus can be swapped every page printing. As a result, it is possible to reliably disable reprinting of the same page by swapping the data bus for each page printing. In the above image forming apparatus, the data bus is swapped at the timing when one job is completed. be able to. As a result, the data bus swap process for each page when printing a plurality of pages can be omitted by swapping the data bus at the end of one job.

  In the image forming apparatus described above, the data bus can be swapped at the end of the security job. As a result, if you want to destroy only the security job data, swapping the data bus only at the end of the security job and not swapping the data bus at the end of other jobs saves the time required for swapping other than the security job. it can.

  Further, the image forming apparatus of the present invention uses the above memory data destruction system to swap the data bus only when accessing the processed memory area. Thus, only the processed data can be destroyed by swapping the data bus only when accessing the processed (printed) memory area.

  In the image forming apparatus, an arbitrary memory area is swapped using address information. Thus, by using the address information, it is possible to limit and destroy an arbitrary memory area (an area where processed data is present) without destroying data in all memory areas.

  In the image forming apparatus, the data bus is swapped only in the memory area in units of one page. By swapping the data bus only in the memory area of one page unit, the image data can be destroyed in units of one page, so that the image data in the memory can always be destroyed.

  Alternatively, in the image forming apparatus described above, the data bus is swapped only in the memory area in units of 1 job. By swapping the data bus only in the memory area of 1 job unit, when printing multiple pages, it is possible to destroy the data after printing all pages, and the data bus is swapped when there is no job. Does not affect.

  In the image forming apparatus, the unit for swapping the data bus is a bit unit. Thereby, it is possible to make the print result unrecognizable.

  The image forming apparatus according to the present invention includes a plurality of bus swap circuits according to the number of bits of the data bus in the memory data destruction system. Thus, a system corresponding to the number of bits of the data bus can be constructed by configuring a plurality of bus swap circuits.

  The present invention can prevent leakage of data without erasing processed data. Therefore, the present invention can be applied to prevent leakage of image data that has already been formed in a multifunction peripheral or printer that sequentially forms input images on a recording medium or the like.

1 is a block diagram illustrating a configuration of an image forming apparatus according to an exemplary embodiment. FIG. 4 is a circuit diagram illustrating an internal configuration of a bus replacement processing unit included in the image forming apparatus when the number of bits is 4; It is a figure which shows a bus swap pattern. 6 is a flowchart showing a flow of processing for writing (writing) / reading (reading) image data with respect to an image memory. It is a figure explaining the modification of the replacement timing of a bus pattern. It is a circuit diagram which shows the internal structure of a bus replacement | exchange process part in the case of 32 bits.

Explanation of symbols

1 Image forming apparatus 11 CPU (memory control means)
12 Main memory 13 ROM
14 System Controller 15 I / O Unit 16 Hard Disk Drive (HDD)
17 Compression / Expansion Unit 18 ICU Unit (Memory Control Unit)
19 Bus replacement processing part (bus replacement means)
20 Image memory (memory)
21 Image printing part 22 Register part (bus replacement means)
23 Bus swap section (bus replacement means)
23-1-8 Sub-bus swap section (bus replacement means)
24a-0 to 31 Data bus (ICU side)
24b-0 to 31 data bus (image memory side)
25-1 to 4 and 26-1 to 4 switches

Claims (11)

An image memory for storing image data;
Memory control means connected to the image memory via a plurality of data buses, and writing and reading image data to and from the image memory using the data bus;
An image forming apparatus comprising: an engine unit that forms an image corresponding to the image data read from the image memory by the memory control unit;
An image comprising: a bus replacement unit that performs a bus replacement process for changing a connection destination between the image memory and the memory control unit for each of the plurality of data buses at a predetermined timing. Forming equipment.   The image forming apparatus according to claim 1, wherein the bus replacement unit performs the bus replacement process after the memory control unit writes and reads image data for one page.   The image forming apparatus according to claim 1, wherein the bus replacement unit performs the bus replacement process after the memory control unit writes and reads image data for one job. For each job, it has security setting means to set whether or not reading is necessary,
2. The bus replacement unit according to claim 1, wherein the bus replacement unit performs the bus replacement process after the memory control unit performs writing and reading of image data of a job set as unreadable by the security setting unit. Image forming apparatus.   The image forming apparatus according to claim 1, wherein the bus replacement unit performs the bus replacement process after the memory control unit writes and reads image data for a predetermined amount of memory area. An address storage unit for storing an address in the image memory of image data on which an image has been formed by the engine unit;
The image forming apparatus according to claim 1, wherein the bus replacement unit performs the bus replacement process when receiving an access request for an address stored in the address storage unit.   The image forming apparatus according to claim 1, wherein the bus replacement unit performs the bus replacement process in units of bits. The plurality of data buses are divided into a plurality of groups every predetermined number (an integer of 2 or more),
Each group has the bus replacement means,
The image forming apparatus according to claim 1, wherein each bus replacement unit performs the bus replacement process on a data bus included in the corresponding group. Memory,
Memory control means connected to the memory via a plurality of data buses, and writing and reading data to and from the memory using the data bus;
Memory control comprising bus replacement means for performing bus replacement processing for changing a connection destination between the memory and the memory control means for the plurality of data buses at each predetermined timing. apparatus.   A program for operating the image forming apparatus according to any one of claims 1 to 8, wherein the program causes a computer to function as each of the above units.   The computer-readable recording medium which recorded the program of Claim 10.

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