JP2007218968A - Plasma display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display apparatus which protects electronic components from excessive pulse-like current generated when starting the apparatus. <P>SOLUTION: An electrode driving part comprises: a diode D16 and a resistor R13; a diode D13 and a resistor R14; a diode D14 and a resistor R15; a diode D15 and a resistor R16; a diode D11 and a resistor R17; and a bootstrap circuit connecting a diode 12 and a resistor 18 in series therewith, wherein all or some of these resistors are wire wound resistors. Moreover, a resistor R20 is inserted between a write-in bias voltage generation circuit 73 and each scanning driver 76, and this resistor R20 is a wire wound resistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plasma display device which is an image display device using a plasma display panel.

  In a plasma display panel (hereinafter referred to as “panel”), a pair of panel substrates, a front panel substrate and a rear panel substrate, are arranged to face each other so that a discharge space is formed between both substrates, and a rare gas is formed in the discharge space. Is sealed and the periphery is sealed. A plurality of display electrodes composed of scan electrodes and sustain electrodes are formed on the front panel substrate, and a plurality of data electrodes are formed on the rear panel substrate in a direction orthogonal to the display electrodes. A discharge cell which is a unit light emitting region is formed at the three-dimensional intersection. By applying a voltage having a predetermined waveform to the display electrode and the data electrode of the panel configured as described above and selectively generating a discharge in each discharge cell, the phosphor layer formed in each discharge cell Light is emitted by the discharge, whereby a desired image is displayed from the panel.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. The image is displayed.

Since the plasma display apparatus performs an image display operation using such a driving method, a high voltage is applied to the electrode driving unit that supplies a driving signal having a high voltage driving voltage waveform to each electrode of the panel or the electrode driving unit. It has a high voltage power supply to supply. In addition, in order to stably supply a drive signal to each electrode from the electrode drive unit or to prevent excessive current from flowing, for example, a resistor or the like is used as a current limiting element between the electrode drive unit and the electrode. There has been proposed a technique for inserting and stabilizing the plasma display device, or preventing accidental damage to electronic components due to power-on or abnormal discharge (for example, see Patent Document 1). Moreover, as a resistor to be inserted as a current limiting element between such an electrode driving unit and an electrode, a resistor having a medium power or higher is usually used particularly when dealing with an excessive current or the like. . As one specific example of a resistor used for such a purpose, a metal oxide film resistor having a high heat resistance corresponding to medium power or higher has been conventionally used.
Japanese Patent Laying-Open No. 2005-10788

  However, when a metal oxide film resistor is used to cope with an excessive current due to abnormal driving operation, as in the conventional example, in order to suppress such an electric current depending on the excessive current amount. There was a problem that there was a high possibility that the resistor itself would generate heat or even be damaged.

  That is, since the metal oxide film resistor as described above is easy to process, the resistance value is adjusted by trimming the resistor surface into a coil shape or the like. As described above, the resistance value of the metal oxide film resistor can be set easily, but the trimming surface tends to become non-uniform due to such trimming. It was easy to be low. In particular, since the plasma display device displays an image by applying a high voltage pulse to a large number of electrodes as described above, a transient inrush current is generated every time the device is turned on, or due to a high voltage pulse. There is a possibility that a current including a peak current of a large current is generated constantly. In such a plasma display device, if a metal oxide film resistor with low reliability is used, for example, a large current flows in a non-uniform portion of the resistor surface, and the resistor surface is locally damaged. Such damage may cause destruction of the entire resistor, and as a result, it may cause inconvenience such as the plasma display device not operating properly.

  The present invention has been made in view of these problems. Even if an excessive current flows through the electrode driving unit or a resistor used in a bootstrap circuit that supplies a power supply voltage to the electrode driving unit, It is an object of the present invention to provide a plasma display device capable of protecting the resistor itself and electronic components such as an IC and a semiconductor connected to the resistor without inconvenience.

  In order to solve the above-described problems, the plasma display apparatus of the present invention includes a substrate on which a plurality of scan electrodes and sustain electrodes are formed, and a substrate on which a plurality of data electrodes are formed so as to be orthogonal to the scan electrodes and sustain electrodes. And a plasma display panel having discharge cells formed therein, and an electrode driving unit for driving the scan electrode, the sustain electrode, and the data electrode, and the electrode driving unit includes a diode and a resistor. And a bootstrap circuit for supplying a power supply voltage, and the resistor is a wound resistor using a wound resistance wire.

  Further, the plasma display device of the present invention has a substrate in which a plurality of scan electrodes and sustain electrodes are formed and a substrate in which a plurality of data electrodes are formed so as to be orthogonal to the scan electrodes and sustain electrodes. A plasma display panel having discharge cells; a scan electrode driver for driving the scan electrodes; a sustain electrode driver for driving the sustain electrodes; and a data electrode driver for driving the data electrodes. In addition, the scan electrode driver includes a write bias voltage generation circuit that generates a write bias voltage to the scan electrode in the write period, and a scan pulse voltage that generates a scan pulse voltage to the scan electrode in the write period The write bias voltage is supplied from the generation circuit and the write bias voltage generation circuit, and the scan pulse voltage is supplied from the scan pulse voltage generation circuit. A plurality of scan driver circuits that switch the applied write bias voltage and scan pulse voltage at a predetermined timing and apply them to the respective scan electrodes, and resistors connected between the write bias voltage generation circuit and the scan driver circuit And a resistor connected between the write bias voltage generation circuit and the scan driver circuit is a wound resistor using a wound resistance wire.

  According to the present invention, the resistor used in the electrode driving unit and the bootstrap circuit that supplies the power source voltage to the electrode driving unit is a winding resistor that has high reliability and can limit the inflow of a pulsed signal. Therefore, in the unlikely event that an excessive current flows through the electrode driving unit or the resistor used in the bootstrap circuit that supplies power to the electrode driving unit, the resistor itself and the electrons connected to the resistor Since the components can be protected without inconvenience, a plasma display device having high quality and high reliability can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of the panel of the plasma display device in accordance with the exemplary embodiment of the present invention. The panel 10 is configured such that a glass front substrate 21 and a rear substrate 31 are arranged to face each other and a large number of discharge cells are formed therebetween. On the front substrate 21, a plurality of scanning electrodes 22 and sustaining electrodes 23 constituting a display electrode pair are formed in parallel with each other. A dielectric layer 24 is formed so as to cover the scan electrodes 22 and the sustain electrodes 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 covered with an insulating layer 33 are provided on the back substrate 31, and a grid-like partition wall 34 is provided on the insulating layer 33. A phosphor layer 35 is provided on the surface of the insulator layer 33 and the side surfaces of the partition walls 34. The front substrate 21 and the rear substrate 31 are arranged to face each other so that the scan electrode 22, the sustain electrode 23, and the data electrode 32 intersect, and discharge cells are formed at respective positions where the electrodes intersect. For example, a mixed gas of neon and xenon is sealed in the discharge cell as a discharge gas. Note that the structure of the panel 10 is not limited to that described above, and for example, a structure having a stripe-shaped partition instead of the cross-shaped partition 34 may be used.

  FIG. 2 is an electrode array diagram of panel 10 used in the embodiment of the present invention. In the row direction, n scan electrodes SCN1 to SCNn (scan electrode 22 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 23 in FIG. 1) are arranged, and m data electrodes DD1 to DD1 are arranged in the column direction. DDm (data electrode 32 in FIG. 1) is arranged. A discharge cell is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode DDj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  As a method for driving each electrode as shown in FIG. 2, a method of performing gradation display by combining a subfield to emit light after dividing one field period into a plurality of subfields. Such a method is called a subfield method, and this embodiment will be described with reference to a configuration example in which each electrode is driven based on such a subfield method.

  FIG. 3 is a block diagram of the plasma display device according to the embodiment of the present invention. The plasma display device 100 includes a panel 10, an image signal processing unit 42, a data electrode driving unit 43, a scanning electrode driving unit 44, a sustain electrode driving unit 46, and a timing generation unit 48. The image signal processing unit 42 converts the image signal sig into image data indicating light emission / non-light emission for each subfield of each discharge cell. The data electrode driving unit 43 converts the image data for each subfield into a signal corresponding to each data electrode 32 and drives each data electrode 32. The scan electrode driver 44 supplies a predetermined drive voltage waveform to each scan electrode 22 to drive each scan electrode 22. The sustain electrode driver 46 supplies a predetermined drive voltage waveform to each sustain electrode 23 to drive each sustain electrode 23. The data electrode driving unit 43, the scan electrode driving unit 44, and the sustain electrode driving unit 46 constitute an electrode driving unit for driving the scan electrode, the sustain electrode, and the data electrode. The timing generator 48 generates various timing signals for controlling the drive voltage waveform of each electrode driver based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies the timing signals to each electrode driver.

  FIG. 4 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the exemplary embodiment of the present invention. As shown in FIG. 4, in the present plasma display device, one field period is constituted by a plurality of subfields including an initialization period, a writing period, and a sustain period based on the subfield method. Further, in this plasma display device, the discharge cell is selectively caused to emit light by applying a drive signal having a drive voltage waveform as shown in FIG. 4 to the data electrode, the scan electrode, and the sustain electrode for each subfield. Perform gradation display.

  FIG. 5 is a circuit diagram showing a configuration of scan electrode driving unit 44 of the plasma display device in accordance with the exemplary embodiment of the present invention. Next, the configuration of the scan electrode drive unit 44 that generates the drive voltage waveform as shown in FIG. 4 will be described.

  As shown in FIG. 5, scan electrode driving unit 44 includes initialization voltage generation circuit 50, scan electrode side sustain pulse generation circuit (hereinafter, referred to as “sustain pulse generation circuit” as appropriate) 60, and scan pulse generation circuit 70. With. Initialization voltage generation circuit 50 generates a drive signal to the scan electrode in the subfield initialization period. Sustain pulse generation circuit 60 generates a drive signal to the scan electrode in the sustain period of the subfield. Scan pulse generation circuit 70 generates drive signals for the scan electrodes in the subfield writing period, and also generates drive signals generated by initialization voltage generation circuit 50, sustain pulse generation circuit 60, and scan pulse generation circuit 70. Is applied to each of the scan electrodes SCN1 to SCNn of the panel 10 as a scan electrode drive signal to drive the scan electrodes.

  Further, scan electrode driver 44 supplies logic power supply 151 for supplying power supply voltage Vcc to a driver for generating a timing signal to initialization voltage generating circuit 50, sustain pulse generating circuit 60, and scan pulse generating circuit 70; An initialization power supply 153 that supplies a power supply voltage Vset for generating an initialization voltage waveform to the initialization voltage generation circuit 50, and a sustain pulse that supplies a power supply voltage Vsus for generating a sustain pulse to the sustain pulse generation circuit 60 Power supply 152 for power supply, power supply voltage 154 for supplying a power supply voltage Vscn for generating a write bias voltage in the write period to scan pulse generating circuit 70, and power supply voltage Vad for generating a scan pulse are scanned. A scan pulse power supply 155 supplied to the pulse generation circuit 70 is further provided.

  In particular, scan electrode driver 44 in the present embodiment synthesizes and switches the high-voltage drive voltage waveforms generated by initialization voltage generation circuit 50, sustain pulse generation circuit 60, and scan pulse generation circuit 70. As a result, the scan electrode drive signal as shown in FIG. 4 is generated. In order to generate such a high-voltage complicated drive voltage waveform, the plasma display apparatus is usually configured to operate some circuits in a floating state. In this embodiment mode, in order to supply the power supply voltage to the circuit in the floating state, the power supply voltage is supplied to the circuit in the floating state by using a technique called a bootstrap method. Such a bootstrap system can be realized with a configuration in which a capacitor and a capacitor are charged from a power supply that is not in a floating state, and this charging voltage is used as a power supply for a high-side circuit that is in a floating state.

  The initialization voltage generation circuit 50 supplies a timing signal to the Miller integration circuit 51 and the Miller integration circuit 52, the Miller integration circuit 51, the Miller integration circuit 52, and the like that generate the scan electrode drive signal having the initialization voltage waveform in the initialization period. A half-bridge driver 54 and a driver 55 are provided. The signal output from the initialization voltage generation circuit 50 is supplied to the reference potential A that is the reference potential of the scan pulse generation circuit 70.

  Miller integrating circuit 51 raises reference potential A of scan pulse generating circuit 70 in a ramp shape to generate an upward ramp waveform of the initialization voltage waveform, and Miller integrating circuit 52 drops reference potential A in a ramp shape. Generates a down-slope waveform of the initialization voltage waveform. Further, an FET (field effect transistor) Q12 provided between the Miller integrating circuit 51 and the Miller integrating circuit 52 switches between the rising slope waveform and the falling slope waveform of the initialization voltage waveform. By such an operation, the scan electrode drive signal in the initialization period as shown in FIG. 4 is generated. In order to generate such a ramp waveform, Miller integrating circuit 51 comprises FET Q11, capacitor C15 and resistor R11, and Miller integrating circuit 52 comprises Miller integrating circuit comprising FET Q13, capacitor C18 and resistor R12. .

  In the initialization voltage generating circuit 50, the half bridge driver 54 for driving the FET Q11 and the FET Q12 is supplied with a driving voltage from the logic power supply 151 to the high voltage side of the half bridge driver 54, that is, the high side driving circuit by the bootstrap method. Is supplied. In order to configure a bootstrap circuit based on such a bootstrap system, the initialization voltage generation circuit 50 includes a resistor R14, a diode D13, and a capacitor C14. That is, the power supply voltage Vcc from the logic power supply 151 is charged to the capacitor C14 on the positive side via the resistor R14 and the diode D13 and on the negative side via the FET Q15, and this charged voltage is the floating state of the half bridge driver 54. It is used as a driving voltage for the high side driving circuit. Similarly, the initialization voltage generation circuit 50 includes a resistor R15, a diode D14, and a capacitor C13, which also constitute a bootstrap circuit. That is, the power supply voltage Vcc from the logic power supply 151 is charged to the capacitor C13 on the positive side via the resistor R14, the diode D13, the resistor R15 and the diode D14, and on the negative side via the FET Q12 and the FET Q15. Is also used as a driving voltage for the high-side driving circuit in which the half-bridge driver 54 is in a floating state. Further, the initialization voltage generating circuit 50 includes a resistor R16, a diode D15, and a capacitor C16, and these also constitute a bootstrap circuit. That is, the power supply voltage Vset of the initialization power supply 153 is also charged to the capacitor C16 via the resistor R16 and the diode D15 on the positive side and the FET Q15 on the negative side by the bootstrap method. This charged voltage is used as a power source for Miller integrating circuit 51.

  Further, the initialization voltage generation circuit 50 includes a bypass capacitor C17 of a logic power supply 151 as a power supply of a driver 55 that drives the FET Q13.

  Next, sustain pulse generating circuit 60 includes FET Q14 and FET Q15 for generating a sustain pulse, and half bridge driver 64 for supplying a timing signal to FET Q14 and FET Q15. In response to the control by the timing signal from the half-bridge driver 64, the FET Q14 turns on and off the output of the sustain pulse voltage Vsus, and the FET Q15 turns on and off the output of the ground potential, whereby the sustain pulse generation circuit 60 outputs the ground potential and the voltage Vsus. A sustain pulse alternating with and is output. The driving voltage is supplied from the logic power supply 151 to the high-side drive circuit in the floating state of the half-bridge driver 64 from the logic power supply 151 to the half-bridge driver 64 that drives the FET Q14 and the FET Q15. In order to configure such a bootstrap circuit, sustain pulse generation circuit 60 includes resistor R13, diode D16, and capacitor C19. That is, the power supply voltage Vcc from the logic power supply 151 is charged to the capacitor C19 on the positive side via the resistor R13 and the diode D16 and on the negative side via the FET Q15, and this charged voltage is charged to the high side of the half bridge driver 64. This is used as a driving voltage for the driving circuit. Further, the sustain pulse generation circuit 60 includes a bypass capacitor C10 of the logic power supply 151 as a drive voltage for the low-voltage side of the half-bridge driver 64, that is, the low-side drive circuit. Sustain pulse generation circuit 60 may further include a power recovery circuit 69 that reduces the switching loss by utilizing LC resonance with the electrode capacitance of the panel when the sustain pulse is switched.

  Next, scan pulse generating circuit 70 generates FET Q23 for connecting reference potential A to scan pulse voltage Vad under control of driver 74, and write bias voltage Vscn to scan electrodes SCN1 to SCNn in the write period. The output write bias voltage generation circuit 73 generates a scan pulse signal that is switched from the write bias voltage Vscn to the scan pulse voltage Vad at a predetermined timing and is superimposed on the write bias voltage, and is applied to the scan electrodes SCN1 to SCNn. Each scan driver circuit (hereinafter referred to as a scan driver) 76 that supplies a scan pulse signal is provided. The driver 74 and the FET Q23 constitute a scan pulse voltage generation circuit that generates the scan pulse voltage Vad to the scan electrodes SCN1 to SCNn in the writing period.

  In the scan pulse generation circuit 70, each scan driver 76 is supplied with a driving voltage from the logic power supply 151 to each scan driver 76 by a bootstrap method. In order to configure such a bootstrap circuit, the scan pulse generation circuit 70 includes a resistor R17, a diode D11, and a capacitor C11. That is, the power supply voltage Vcc from the logic power supply 151 is charged to the capacitor C11 on the positive side via the resistor R17 and the diode D11 and on the negative side via the FETQ12 and FETQ15, and this charged voltage is supplied to each scan driver 76. Used as a driving voltage. Further, the scan pulse generation circuit 70 includes a resistor R18, a diode D12, and a capacitor C12, which also constitute a bootstrap circuit. That is, the power supply voltage Vscn of the write bias power supply 154 is also charged to the capacitor C12 via the resistor R18 and the diode D12 on the positive side and the FETQ12 and FETQ15 on the negative side according to the bootstrap method. This charged voltage is used as a power source for the write bias voltage generation circuit 73.

  In the scan pulse generation circuit 70, a write bias voltage generation circuit 73 outputs a driver 75 that outputs a timing signal indicating a write period, and a write bias voltage Vscn in the write period according to the timing signal of the driver 75. FETQ20 and FETQ21 for switching to output are provided. The FET Q20 turns on and off the output of the power supply voltage Vscn of the write bias power supply 154, and the FET Q21 turns on and off the output of the voltage of the reference potential A. With such a configuration, the write bias voltage generation circuit 73 outputs the write bias voltage Vscn in the write period, and outputs the voltage of the reference potential A in a period other than the write period, via the resistor R20. A write bias voltage Vscn is supplied to each scan driver 76.

  By the way, since the diode used for the bootstrap system described above is connected to a high voltage, there is a possibility that the diode may be destroyed when the power is turned on or an apparatus malfunctions. Therefore, in the plasma display device of this embodiment, in each bootstrap circuit, as described above, the diode D16 and the resistor R13, the diode D13 and the resistor R14, the diode D14 and the resistor R15, and the diode D15 and the resistor R16. A diode and a resistor are connected in series like a diode D11 and a resistor R17, and a diode D12 and a resistor R18. That is, in the plasma display device of the present embodiment, such a resistor is connected in series with a diode as a current limiting element, so that even when a high voltage is temporarily generated in the bootstrap circuit, This prevents inconveniences such as an excessive current flowing through the diode or an excessive voltage being applied, thereby destroying the diode. In addition, an excessive current flows between the write bias voltage generation circuit 73 and each scan driver 76 due to an abnormality of the apparatus, etc., thereby destroying the FET Q20 and the FET Q21. Inconvenience may occur. For this reason, in the plasma display device of the present embodiment, a resistor R20 as a current limiting element is inserted between the write bias voltage generation circuit 73 and each scan driver 76. Even if an excessive current that flows backward from the scan driver 76 due to an abnormality of the scan electrode or the like is generated, the amount of the current is suppressed, and the breakdown of the write bias voltage generation circuit 73 is prevented.

  Furthermore, if a transient inrush current occurs every time the device power is turned on, or if an excessive current flows due to an abnormality in the device, the current also flows through these resistors. However, if they were easily affected by such an excessive current, there was a possibility that these resistors would cause an abnormality of the device. In order to eliminate such inconvenience, in the plasma display device of the present embodiment, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, and the resistor R20, A winding resistor using a wound resistance wire is used.

  Hereinafter, a driving operation in each subfield of the plasma display apparatus configured as described above will be described.

  First, in the initializing period of the first subfield shown in FIG. 4, a voltage of 0 volt is applied from the sustain electrode driver 46 to the sustain electrodes SUS1 to SUSn, and the voltage is applied using the Miller integrating circuit 51 of the scan electrode driver 44. A ramp voltage that gradually rises from Vi1 toward voltage Vi2 is applied to reference potential A. At this time, the FET Q12 is turned off, and each scan driver 76 is controlled to supply the voltage of the reference potential A to each of the scan electrodes SCN1 to SCNn. Then, as shown in FIG. 4, a ramp voltage that gradually increases from voltage Vi1 to voltage Vi2 is applied to scan electrodes SCN1 to SCNn. Thereafter, the voltage Ve is applied from the sustain electrode driver 46 to the sustain electrodes SUS1 to SUSn, and the FET Q12 is turned on in the scan electrode driver 44, and the voltage is gradually increased from the voltage Vi3 to the voltage Vi4 using the Miller integrating circuit 52. A descending ramp voltage is applied to the reference potential A. Thus, a ramp voltage that gradually decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SCN1 to SCNn via each scan driver 76. Then, a weak initializing discharge is generated in each discharge cell, and wall charges necessary for the subsequent address operation are formed on each electrode. Note that as the operation in the initialization period, as shown in the initialization period of the second subfield in FIG. 4, it is only necessary to apply a ramp voltage that gradually falls to scan electrodes SCN1 to SCNn.

  Next, in the writing period, first, in the scan electrode driving unit 44, the FET Q23 of the scan pulse generating circuit 70 is turned on, and the reference potential A of the scan pulse generating circuit 70 is set to the scan pulse voltage Vad. At this time, in the write bias voltage generation circuit 73, the driver 75 outputs a switching signal corresponding to the timing signal indicating the writing period to the FET Q20 and its inverted signal to the FET Q21. Thereby, in the writing period, the FET Q20 is turned on and the FET Q21 is turned off, and a voltage higher than the reference potential A by the writing bias voltage Vscn is output from the writing bias voltage generation circuit 73 and supplied to the resistor R20. Is done.

  Thus, in the writing period, the scan pulse voltage Vad is supplied to the reference potential A, and the write bias voltage Vscn is supplied from the write bias voltage generation circuit 73 to each scan driver 76 via the resistor R20. It becomes a state. At the same time, at the start of the write period, each scan driver 76 selects the supplied write bias voltage Vscn and outputs this write bias voltage Vscn to scan electrodes SCN1 to SCNn. As a result, a voltage obtained by adding the voltage Vscn to the reference potential A, that is, a write bias voltage Vscn as shown in FIG. 4 is applied to the scan electrodes SCN1 to SCNn via the respective scan drivers 76. Next, only the scan driver 76 corresponding to the scan electrode SCN1 in the first row selects the reference potential A of the supplied scan pulse voltage Vad. As a result, the scan pulse voltage Vad that is negative with respect to the write bias voltage Vscn is applied to the scan electrode SCN1 in the first row. At this time, a positive write pulse voltage Vd is applied to the data electrode 32 corresponding to the discharge cell to emit light using the data electrode driver 43. Then, an address discharge is generated in the discharge cells in the first row to which the scan pulse voltage Vad and the write pulse voltage Vd are simultaneously applied, and an address operation for accumulating wall charges in the scan electrode SCN1 and the sustain electrode SUS1 is performed.

  Next, the scan driver 76 in the first row returns to select the write bias voltage Vscn, and the scan driver 76 corresponding to the scan electrode SCN2 in the second row selects the reference potential A of the scan pulse voltage Vad. Control to do. As a result, the scan pulse voltage Vad is applied to the scan electrode SCN2 in the second row. At this time, the write pulse voltage Vd is applied to the data electrode 32 corresponding to the discharge cell to emit light. Then, in the second row discharge cells to which the scan pulse voltage Vad and the write pulse voltage Vd are simultaneously applied, an address discharge occurs, and an address operation is performed. The above address operation is repeated until the discharge cell in the n-th row, and an address discharge is selectively generated in the discharge cells to emit light to form wall charges.

  In the subsequent sustain period, a voltage of 0 volt is applied from sustain electrode driver 46 to sustain electrodes SUS1 to SUSn. The scan electrode driver 44 controls each scan driver 76 to select the reference potential A, turns off the FET Q23, turns on the FET Q12 and the FET Q14, and applies the voltage Vsus to the scan electrodes SCN1 to SCNn. To do. When sustain pulse voltage Vsus is applied to scan electrodes SCN1 to SCNn in this way, a sustain discharge occurs in the discharge cells that have caused the address discharge, and light is emitted. Next, the FET Q14 of the scan electrode driver 44 is turned off, the FET Q15 is turned on to apply a voltage of 0 volt to the scan electrodes SCN1 to SCNn, and the sustain pulse voltage Vsus is applied from the sustain electrode driver 46 to the sustain electrodes SUS1 to SUSn. Apply. Then, in the discharge cell in which the sustain discharge has occurred, the sustain discharge occurs again to emit light. Thereafter, similarly, the necessary number of sustain pulses are alternately applied to scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn to cause the discharge cells to emit light with a predetermined luminance.

  In the subsequent subfield, the discharge cell is caused to emit light by repeating the same operation as that of the subfield described above, and an image is displayed.

  By performing the operations of the scan electrode driving unit 44, the sustain electrode driving unit 46, and the data electrode driving unit 43 as described above, the driving voltage waveform as shown in FIG. 4 is applied to each electrode. The discharge cell corresponding to the image is caused to emit light, and the image is displayed on the panel.

  As described above, the driving operation in the case where the plasma display apparatus operates without abnormality has been mainly described. Next, regarding the mechanism in which an excessive pulsed current is generated during the driving operation in the plasma display apparatus, An example will be described.

  For example, when one output terminal of each scan driver 76 is destroyed due to a short circuit or the like, the power supply line of the power supply voltage Vcc from the logic power supply 151 may be shorted to lower the power supply voltage. . When such a situation occurs, the power supply voltage Vcc is commonly supplied to the other scan drivers 76 that have not been destroyed, so the power supply voltage Vcc applied to the scan drivers 76 that have not been destroyed also decreases. Then, the normal scanning driver 76 also does not operate, and the internal switching circuit does not operate. In this state, if a sustain pulse is applied to sustain electrodes SUS1 to SUSn in the sustain period, the output of scan driver 76 is passed through the interelectrode capacitance between scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn. Sustain pulse voltage Vsus is applied. Then, an excessive pulse-like current flows backward in the direction of the write bias voltage generation circuit 73 through the switching circuit in the operation stop state in each scan driver 76 that is not destroyed.

  If such an abnormal state continues, the temperature of the FET Q21 in which excessive current is concentrated rapidly rises, and if the temperature rise at this time is too large, the FET Q21 may be destroyed. Further, as a mechanism of occurrence of an abnormality, not only the malfunction example of the scan driver 76 described above, but also, for example, logic for generating timing signals such as a driver 74, a driver 75, a driver 55, a half bridge driver 54, or a half bridge driver 64. It may also be caused by malfunction or failure of the circuit. Further, when such an abnormality occurs, a high voltage is temporarily generated in the bootstrap circuit, and an excessive current flows through the diode, thereby possibly destroying the diode.

  In order to prevent such inconvenience, as described above, in the plasma display device of the present embodiment, the resistor R20 as a current limiting element is provided between the write bias voltage generation circuit 73 and each scan driver 76. Inserting. Further, in each bootstrap circuit, diode D16 and resistor R13, diode D13 and resistor R14, diode D14 and resistor R15, diode D15 and resistor R16, diode D11 and resistor R17, and diode D12 and resistor R18. Are connected in series.

  However, since a large current also flows through these resistors provided to limit the current, these resistors themselves may also generate heat abnormally. At this time, if the resistor surfaces of these resistors themselves are non-uniform, as described above, a large current flows through the non-uniform portions of the resistor surfaces, and the resistor surfaces are locally damaged. The damage may cause destruction of the entire resistor, and as a result, it may cause inconvenience such as the plasma display device not operating properly.

  For this reason, the plasma display device of this embodiment uses these resistors R13, R14, R15, R16, R17, R18 and R20 as winding resistors, This suppresses damage and destruction of the resistor itself due to excessive current. In other words, a wound resistor has a configuration in which a metal resistor wire is wound around a winding frame as a resistor, and high-frequency characteristics are not good due to such a coil shape, but, for example, a trimming process such as a metal oxide film resistor is performed. Since the processing is not performed, the resistor is uniform. For this reason, winding resistors are more reliable than metal oxide film resistors, etc., and even if excessive current flows through such winding resistors, they can suppress damage and destruction of the resistors themselves, As a result, it is possible to prevent inconveniences such as the protection function in the plasma display device not operating properly.

  In the plasma display device of the present embodiment, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, and the resistor R20, which are the winding resistors, The high frequency characteristics are not important because they are inserted into the power supply line that supplies the power. On the other hand, since the plasma display device displays an image by applying a high voltage pulse to a large number of electrodes, when an abnormality occurs in the device, a write bias voltage generation circuit is used as in the above-described abnormality occurrence mechanism. There is a high possibility that a pulsed excessive current flows into an electronic component such as the diode 73 or the diode of each bootstrap circuit, or a pulsed excessive voltage is applied. Therefore, by inserting the resistor R20, which is a winding resistor having an inductive component depending on the coil shape, between the write bias voltage generation circuit 73 and each scan driver 76, the induction of this winding resistor is performed. It is possible to suppress an excessive pulse-like current from flowing into the write bias voltage generation circuit 73 due to the component. That is, since the pulsed current containing a large amount of high-frequency components can be limited by utilizing the characteristics of the winding resistor, which inherently has poor high-frequency characteristics, the protection effect on the write bias voltage generation circuit 73 can be enhanced. it can. Similarly, in each bootstrap circuit, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, and a resistor R18, which are winding resistors having an inductive component depending on the coil shape, By connecting in series with the corresponding diodes, the inductive component of this winding resistor can suppress excessive current and voltage in the form of pulses, so it is possible to increase the protection effect on the diode in the bootstrap circuit. .

  In the above description, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, and the resistor R20 in the scan electrode driving unit 44 are examples of winding resistors. However, some of these resistors may be wound resistors. For example, a winding resistor may be provided in the bootstrap circuit provided in the sustain electrode driving unit 46 or the data electrode driving unit 43. The structure which is provided may be sufficient.

  As described above, the plasma display device of the present invention includes the diode D16 and the winding resistor R13, the diode D13 and the winding resistor R14, and the diode D14 and the winding resistance in each bootstrap circuit of the scan electrode driving unit 44. The resistor R15, the diode D15 and the winding resistor R16, the diode D11 and the winding resistor R17, and the diode D12 and the winding resistor R18 are connected in series. Further, a winding resistor R20 is inserted between the write bias voltage generation circuit 73 and each scan driver 76. In the plasma display device of the present invention, an excessive current flows through the resistors used in the write bias voltage generation circuit 73 of the scan electrode drive unit 44 and the bootstrap circuit that supplies the power supply voltage by this configuration. Even so, these resistors are highly reliable and are wound resistors that can limit the inflow of pulsed signals, so that the resistors themselves and the electronic components connected to the resistors can be protected without inconvenience. Accordingly, a plasma display device having high quality and high reliability can be provided.

  The present invention provides a plasma display device having high quality and high reliability, which can protect electronic components from an abnormal phenomenon without any inconvenience even if an abnormality occurs in an electrode driving unit. As it can, its industrial applicability is extremely high.

1 is an exploded perspective view of a panel in a plasma display device according to an embodiment of the present invention. Panel arrangement of panels in the plasma display device Block diagram of the plasma display device Drive voltage waveform diagram applied to each electrode of panel in the plasma display device Circuit diagram of scan electrode driver in the plasma display device

Explanation of symbols

10 Plasma display panel (panel)
DESCRIPTION OF SYMBOLS 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Dielectric layer 25 Protective layer 31 Back substrate 32 Data electrode 33 Insulator layer 34 Partition 35 Phosphor layer 42 Image signal processing part 43 Data electrode drive part 44 Scan electrode drive part 46 Sustain electrode Drive unit 48 Timing generation unit 50 Initialization voltage generation circuit 51, 52 Miller integration circuit 54, 64 Half bridge driver 55, 74, 75 driver 60 Scan electrode side sustain pulse generation circuit (sustain pulse generation circuit)
69 Power Recovery Circuit 70 Scan Pulse Generation Circuit 73 Write Bias Voltage Generation Circuit 76 Scan Driver Circuit (Scan Driver)
DESCRIPTION OF SYMBOLS 100 Plasma display apparatus 151 Power supply for logic 152 Power supply for sustain pulse 153 Power supply for initialization 154 Power supply for writing bias 155 Power supply for scan pulse

Claims (2)

A plasma display panel having discharge cells formed therein by disposing a substrate on which a plurality of scan electrodes and sustain electrodes are formed and a substrate on which data electrodes are formed so as to be orthogonal to the scan electrodes and the sustain electrodes. And an electrode driver for driving the scan electrode, the sustain electrode, and the data electrode,
The electrode driving unit includes a bootstrap circuit for connecting a diode and a resistor in series, supplying a power supply voltage, and the resistor is configured by a wound resistor using a wound resistance wire. A characteristic plasma display device. A plasma display panel having discharge cells formed therein by disposing a substrate on which a plurality of scan electrodes and sustain electrodes are formed and a substrate on which data electrodes are formed so as to be orthogonal to the scan electrodes and the sustain electrodes. A scan electrode driver for driving the scan electrode, a sustain electrode driver for driving the sustain electrode, and a data electrode driver for driving the data electrode,
The scan electrode driving unit includes:
A write bias voltage generation circuit for generating a write bias voltage to the scan electrode in the write period;
A scan pulse voltage generation circuit for generating a scan pulse voltage to the scan electrode in the writing period;
The write bias voltage is supplied from the write bias voltage generation circuit, the scan pulse voltage is supplied from the scan pulse voltage generation circuit, and the supplied write bias voltage and the scan pulse voltage are set at a predetermined timing. A plurality of scan driver circuits which are switched and applied to the respective scan electrodes;
A resistor connected between the write bias voltage generation circuit and the scan driver circuit;
The plasma display device, wherein the resistor connected between the write bias voltage generation circuit and the scan driver circuit is formed by a wound resistor using a wound resistance wire.

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