JP2007214762A - Mixed transmission method and device for atm cell and ethernet packet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mixed transmission method and a device for ATM cells and Ethernet packets that never make transmission efficiency worse. <P>SOLUTION: A communication device which accommodates ATM and Ethernet structures and performs switching operation based upon information described in ATM cells or Ethenet packets is provided with a transmitting means of transmitting the ATM cells while regarding the ATM cells as Ethernet packets of 53-byte fixed length. Consequently, the transmission efficiency can not be made worse. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a mixed transmission method and apparatus for ATM cells and Ethernet packets, and more particularly, in a transitional environment in which ATM communication apparatuses and Ethernet (registered trademark of Fuji Xerox) are mixed, ATM cells and Ethernet packets are simultaneously transmitted. The present invention relates to a communication method and apparatus that enable communication.

  In recent years, the transition from ATM to Ethernet has progressed. However, since the transition from ATM communication environment to Ethernet communication environment involves cost and effort, there are many cases in which ATM communication devices are used as they are. A communication environment is required.

  FIG. 10 shows a conventional mixed accommodation technique of ATM cells and Ethernet packets. 125 μs is one section, and there are a header part (PCBd) 1, an ATM cell accommodation part (“Pure” ATM cells section) 2, and a GEM data accommodation part (TDM & data fragments over GEM section) 3. The header part 1 contains information such as how many cells are accommodated in the ATM cell accommodation part 2, GEM data head position, effective data length, and the like. The ATM cell accommodation unit 2 accommodates N ATM cells. The GEM data storage unit 3 stores Ethernet packets that are further encapsulated.

As a conventional technique of this type, a fixed-length frame is set on the uplink, and this frame is further divided into a plurality of uplink subframes so that uplink signals of different signal formats are accommodated in separate uplink subframes. This technique is known (see, for example, Patent Document 1).
Japanese Unexamined Patent Publication No. 2000-92011 (paragraphs 0024 to 0031, FIG. 1)

  In the conventional technique described above, when ATM cells and Ethernet packets are mixed and transmitted, capsulation must be performed, and a problem arises in that transmission efficiency deteriorates due to the addition of headers. In addition, when the transition from ATM to Ethernet is completely completed, the interface processing unit (hereinafter abbreviated as IF) that performs mixed transmission has a format that is incompatible with Ethernet, and therefore cannot be connected to other devices. The problem that it cannot be used occurs.

Further, when ATM cells and Ethernet packets are mixed and transmitted, there arises a problem that ATM cells and Ethernet packets cannot be distinguished as they are.
Also, in a communication device that contains ATM cells and Ethernet packets together, when switching, when switching for ATM cells, when switching functions for ATM cells, switching for Ethernet packets Has a problem in that the configuration is complicated because switching functions for Ethernet packets are required.

  Furthermore, in a communication apparatus that accommodates ATM cells and Ethernet packets together, when priority control is performed, a priority control function for ATM cells and a priority control function for Ethernet packets are required, and the configuration becomes complicated.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a mixed transmission method and apparatus for ATM cells and Ethernet packets that do not deteriorate transmission efficiency.

(1) The invention according to claim 1 is a communication apparatus that accommodates ATM and Ethernet, and performs switching based on the information described in the ATM cell or Ethernet packet. The ATM cell is a 53-byte fixed Ethernet packet. It is characterized by the fact that transmission is carried out by assuming that.
(2) The invention according to claim 2 is characterized in that ATM cells and Ethernet packets are separated and detected by data length and error detection from data on a physical medium in which ATM cells and Ethernet packets are mixed. And
(3) The invention according to claim 3 is a search that accommodates a physical medium in which ATM cells and Ethernet packets are mixed and switches both ATM cells and Ethernet packets and uses Ethernet and ATM as entries. Switching is performed by referring to the table.
(4) The invention according to claim 4 is characterized in that when both ATM cells and Ethernet packets are switched, priority control is performed by priority classification common to ATM cells and Ethernet packets.
(5) The invention according to claim 5 is a communication device that accommodates ATM and Ethernet, and performs switching based on information described in the ATM cell or Ethernet packet. It is characterized in that a transmission means for performing transmission is provided.

(1) According to the invention described in claim 1, ATM cells and Ethernet packets can be mixedly transmitted without deteriorating transmission efficiency. In addition, it is possible to make the device usable even after Ethernet migration is completed by providing compatibility with Ethernet.
(2) According to the invention described in claim 2, it is possible to realize identification and separation of ATM cells and Ethernet packets.
(3) According to the invention described in claim 3, the switching function can be shared and the configuration of the switching function can be simplified.
(4) According to the invention described in claim 4, the priority control function can be shared, and the configuration of the priority control function can be simplified.
(5) According to the invention described in claim 5, ATM cells and Ethernet packets can be mixedly transmitted without deteriorating transmission efficiency. In addition, it is possible to make the device usable even after Ethernet migration is completed by providing compatibility with Ethernet.

(First embodiment)
FIG. 1 is an explanatory diagram of ATM cell / Ethernet packet mixed transmission according to the present invention. The IFG 11 indicates an inter-frame gap (Inter Frame Gap), and the preamble 12 indicates a pattern for detecting the head of the frame. These patterns are obtained by applying Ethernet technology. By placing these patterns before the ATM cell 13 or the Ethernet packet 14, the ATM cell can be regarded as an Ethernet packet with a fixed 53 bytes and transmitted. This enables mixed transmission of ATM cells and Ethernet packets.

  Here, the preamble 12 has a pattern in which “10101010” of 7 bytes is continuous and the last 1 byte is “10101011”. When the end is not “10” but “11”, it indicates that an ATM cell or an Ethernet packet starts from the next byte.

  FIG. 2 is a diagram showing an ATM cell format. An ATM cell is composed of 53 bytes of information, and consists of a header portion 17 and an information field 18. In the header portion 17, VPI is a virtual path identifier, VCI is a virtual channel identifier, PT is a payload type, CLP is cell loss priority indication, and HEC is header portion error control.

  FIG. 3 is a diagram showing the format of an Ethernet packet. FIG. 4 is an explanatory diagram of each part of the Ethernet packet format. Reference numeral 21 denotes a PA (preamble), which is a signal bit string used for establishing synchronization, the bit string is “10101010...”, And the last byte is “10101011”. PA is composed of 8 bytes. Reference numeral 22 denotes a MAC-DA (Destination Address), which is composed of 6 bytes.

  Reference numeral 23 denotes a MAC-SA (Source Address), which is composed of 6 bytes. Reference numeral 24 denotes a tag protocol identifier (TPID: tag protocol identifier). By default, “0x8100” indicating a VWAN tag is inserted. The TPID 24 is composed of 2 bytes. Reference numeral 25 denotes a Tag Control Identifier (TCI: tag control information), which is composed of 2 bytes. The TCI 25 includes pri25a3 bits, CFI25b1 bits, and VID25c12 bits. pri25a is a priority bit indicating a priority of 3 bits. The CFI 25b is a 1-bit canonical format identifier. VID is a 12-bit identifier for identifying VLAN (VWAN).

  Reference numeral 26 denotes Type / Length (length of the data portion), excluding padding (dummy data). Reference numeral 27 denotes a Data area, which indicates upper protocol data. Reference numeral 28 denotes a frame check sequence (FCS: frame check sequence), which is an error check code CRC-32. The FCS 28 is composed of 4 bytes. The TPID 24 and the TCI 25 constitute a VWAN and a VLAN. VLAN is an extension tag assigned by a user defined in IEEE802.1Q, and VWAN is an extension tag assigned to a normal carrier, although the contents are the same as VLAN.

  According to the first embodiment, ATM cells and Ethernet packets can be mixedly transmitted without deteriorating transmission efficiency. In addition, it is possible to make the device usable even after Ethernet migration is completed by providing compatibility with Ethernet.

(Second embodiment)
FIG. 5 is a block diagram showing an embodiment of the present invention, and shows the flow of identification / separation of ATM cells and Ethernet packets. The transmission medium 31 is a physical medium such as an optical fiber or a twisted pair wire. The physical interface unit 32 is configured by an optical module or the like, and converts an optical signal into an electrical signal. The physical interface unit 32 is connected to the ATM / Ether mixed compatible physical unit 33. In the ATM / Ether mixed compatible physical unit 33, 33a is a clock recovery / link-up control unit that performs reception clock regeneration and link-up control with the opposite device based on the electrical signal.

  Reference numeral 33b denotes a head detection unit that detects the head of an ATM cell or an Ethernet packet based on the preamble. The output of the head detection unit 33b enters an S / P (serial / parallel) conversion unit 34 and is converted into parallel data. The output of the S / P conversion unit 34 enters the ATM / Ether mixed MAC 35. In the ATM / Ether mixed MAC 35, 35a is a packet length detector for detecting the length of the extracted ATM cell or Ethernet packet.

  Based on the detected length information, if it is 64 bytes or more, it is determined as an Ethernet frame, and the FCS error detection unit 35b detects the FCS error. Then, an Ethernet packet is output from the FCS error detection unit 35b. If the detected length information is 53 bytes, it is determined as an ATM cell, and the HEC error detection unit 35c detects the HEC error. Then, an ATM cell is output from the HEC error detection unit 35c.

As described above, the ATM cell and the Ethernet can be separated by detecting the data length and performing the error check.
(Third embodiment)
In order to make the switching function of ATM cells and Ethernet packets common, it is necessary to make the search table that is the basis for executing switching common. FIG. 6 is a diagram illustrating a configuration example of a search table. The search table 41 is composed of a plurality of entries. As shown in the figure, Ethernet entries and ATM entries are mixed. Each entry includes a search key portion and an output port list corresponding to the search key portion.

  Reference numeral 42 denotes the contents of the Ethernet entry. 42a is an E / A area indicating whether the entry is for Ethernet or ATM, 42b is a registered MAC address, 42c is a registered VWAN value, 42d is a registered VLAN value, and 43 is an entry An output port list that determines the output destination of the packet that matches is shown.

  If the packet is an Ethernet packet, a table search is performed to check whether there is an entry that matches the MAC-DA value and the VWAN / VLAN VID value in the switching target packet. If there is a matching entry in the table, the output port list associated with the entry is referred to obtain port information to be output.

  44 shows the contents of the ATM entry. 44a is an E / A area indicating whether the entry is for Ethernet or ATM, 44b is a registered VPI value, 44c is a registered VCI value, and 45 is an output that determines an output destination of a packet that matches the entry It is a port list. If it is an ATM cell, a table search is performed to determine whether there is an entry that matches the VPI / VCI value in the cell header. If there is a matching entry in the table, the output port list associated with the entry is referred to obtain port information to be output.

  In order to make the search table common to the ATM cell and the Ethernet packet, the switching table is made common by making the Ethernet VWAN correspond to the ATM VPI and the Ethernet VLAN correspond to the VCI of the ATM cell. In addition, areas (E / A areas 42a and 44a in the figure) are provided so that it can be identified whether the entry is for ATM or Ethernet. With this configuration, the ATM cell header portion and the Ethernet header portion are associated with each other, so that switching using the same search table is possible without using separate tables.

(Fourth embodiment)
A method for realizing common ATM cell priority control and Ethernet packet priority control will be described. In order to perform priority control in ATM, a method is adopted in which priority is determined by a request from a terminal during call control. Thus, a certain priority class is assigned to the VPI / VCI value in the ATM cell header.

  On the other hand, in the case of Ethernet, priority classification is performed by looking at priority information of eight levels in the priority field of the packet length VWAN / VLAN-TAG. This priority information is given by the terminal or the switching device on the way.

  Next, a method for realizing common priority assignment in an environment in which ATM cells and Ethernet packets are mixed will be described. In order to standardize the priority assignment, the priority in Ethernet and the priority in ATM are reassigned as a mixed class. FIG. 7 is an explanatory diagram of priority class integration. Reference numeral 51 denotes an Ethernet class, and 52 denotes an ATM class. In this example, the number of Ethernet classes is 8, and the number of ATM classes is 8. This is reclassified as a mixed class 53. For example, in FIG. 7, the Ethernet class 51 and the ATM class 52 are allocated in the descending order of priority, and the Ethernet class 51 and the ATM class 52 are shared.

  According to this embodiment, ATM cells and Ethernet packets can be mixedly transmitted without deteriorating transmission efficiency. In addition, it is possible to make the device usable even after Ethernet migration is completed by providing compatibility with Ethernet.

  FIG. 8 is a block diagram showing a configuration example of a switch device that accommodates both ATM and Ethernet. Reference numeral 60 denotes an ATM / Ether mixed compatible switch. Signals from ATM compatible devices and Ethernet compatible devices enter their respective interfaces. That is, a signal from the ATM compatible device enters the ATM IF unit 61, and a signal from the Ethernet compatible device enters the Ethernet IF 62. Reference numeral 64 denotes a mixed IF unit that connects ATM / Ethernet mixed compatible devices.

  63 is a switch for switching ATM cells or IF packets between IFs. The ATM / Ether mixed compatible switch 60 includes three types of IFs 61, 62, and 64 and a switch 63 that switches between ATM cells / Ethernet packets input from them. The ATMIF 61, the Ethernet IF 62, and the mixed IF unit 64 usually have a plurality of ports to accommodate a plurality of physical lines. The mixed IF unit 64 outputs ATM / Ether mixed data and is connected to an ATM / Ether mixed compatible device.

  FIG. 9 is a block diagram showing a specific configuration example of the switch device of the present invention. The same components as those in FIG. 8 are denoted by the same reference numerals. In the figure, 71 is a transmission medium for transmitting ATM cells, 72 is a transmission medium for transmitting Ethernet packets, and 73 is a transmission medium for transmitting ATM cell and Ethernet packet mixed signals. As these transmission media, for example, an optical fiber or a twisted pair wire is used. Reference numeral 60 denotes an ATM / Ethernet mixed compatible switch.

  The ATM IF unit 61 is composed of three blocks. Reference numeral 61a denotes a physical interface such as optical MDL. Reference numeral 61b denotes an ATM-compatible physical unit. Reference numeral 61c denotes an ATM MAC unit. In the input direction, the ATM cell input to the physical IF unit 61a is converted from light to an electrical signal, and the ATM physical unit 61b performs clock recovery, S / P conversion, link control, cell synchronization / cell extraction, etc. It is recognized as an ATM cell. Next, HEC error detection and the like are performed by the ATM MAC unit 61c.

  In the output direction, the ATM cell from the switch unit 63 passes through the ATM MAC unit 61c as it is, P / S converted by the ATM physical unit 61b, passed to the physical IF unit 61a, and passed through the transmission medium 71 as an optical signal. Are sent out.

  The Ethernet IF unit 62 includes three blocks. Reference numeral 62a denotes a physical IF unit such as an optical MDL. Reference numeral 62b denotes an Ethernet physical unit. 62c shows the Ethernet MAC. In the input direction, the Ethernet packet input to the physical IF unit 62a is converted from light to an electrical signal, and the Ethernet physical unit 62b performs clock recovery, S / P conversion, link control, 5B → 4B conversion based on the IEEE protocol, and packet extraction. Etc., and is recognized as an Ethernet packet.

  The Ethernet MAC unit 62c performs length check, FCS error detection, and the like. In the output direction, the Ethernet packet from the switch unit 63 passes through the Ethernet MAC unit 62c as it is, and the Ethernet physical unit 62b performs processing such as 4B → 5B code conversion, P / S conversion, and preamble addition, and the physical IF unit 62a. And is transmitted as an optical signal via the transmission medium 72.

  The switch unit 63 is composed of four blocks. Reference numeral 63a denotes a switch body that performs switch control. A buffer 63b is constituted by a memory or the like that temporarily accommodates ATM cells and Ethernet packets. 63c is a search table for searching for a destination port from information of an ATM cell header or Ethernet packet header and determining a switching path based on the result (see FIG. 6). In the case of ATM, 63d is a signaling control unit that determines a switching path and classification according to a signaling request from a terminal. In the case of Ethernet, path setting and classification are performed by VWAN in the packet.

  The mixed IF unit 64 is composed of three blocks. Reference numeral 64a denotes a physical IF unit such as an optical MDL. Reference numeral 64b denotes an ATM / Ethernet mixed compatible physical unit. Reference numeral 64c denotes a physical IF unit.

  In the input direction, the ATM / Ethernet mixed data input to the physical IF unit 64c is converted from light to an electrical signal, and the clock / recovery, S / P conversion, link control, 5B → 4B is performed in the ATM / Ethernet mixed compatible physical unit 64b. Code conversion, packet / cell extraction processing, and the like are performed, and it is recognized as a mixture of ATM cells / Ethernet packets. A length check is performed in the physical IF unit 64a.

  If it is 53 bytes, it is regarded as an ATM cell, HEC error detection is executed, and if normal, it is passed to the switch unit 63. If the length is 64 bytes or more, it is regarded as an Ethernet packet, FCS error detection is performed, and if it is normal, it is passed to the switch unit 63. In the output direction, the Ethernet packet from the switch unit 63 passes through the physical IF unit 64a as it is, and 4B → 5B code conversion, P / S conversion, preamble addition processing, etc. are performed in the ATM / Ethernet mixed correspondence physical unit 64b. It is passed to the physical IF unit 64c and sent as an optical signal to the transmission line via the transmission medium 73.

  Here, since the format on the transmission path is Ethernet, it is possible to use an existing Ethernet compatible physical unit as it is as the ATM / Ethernet mixed compatible physical unit 64b. Further, when only the Ethernet is used in the future, it is only necessary to process the ATM cell, so that when the ATM is completely replaced, it can be used as the Ethernet accommodating IF.

  Conventionally, transmission is basically either ATM cell transmission or Ethernet packet transmission, and when trying to mix, either or both must be encapsulated, and transmission efficiency has been reduced by adding headers. . Also, due to the encapsulation, the original format is incompatible with either ATM / Ethernet, making it difficult to connect to other devices. According to the present invention, ATM cells and Ethernet packets can be mixed and transmitted without performing encapsulation. In addition, since it is compatible with Ethernet, even if the ATM cell is completely replaced with Ethernet, the device can be used as it is, and seamless transition is possible.

It is explanatory drawing of the ATM cell Ethernet packet mixed transmission by this invention. It is a figure which shows an ATM cell format. It is a figure which shows the format of an Ethernet packet. It is explanatory drawing of each part of an Ethernet packet format. It is a block diagram which shows one embodiment of this invention. It is a figure which shows the structural example of a search table. It is explanatory drawing of integration of a priority class. It is a block diagram which shows the structural example of a switch apparatus. It is a block diagram which shows the specific structural example of the switch apparatus of this invention. It is explanatory drawing of a prior art.

Explanation of symbols

60 ATM / Ethernet mixed compatible switch unit 61 ATM IF unit 61a Physical IF unit 61b ATM physical unit 61c ATM MAC unit 62 Ethernet IF unit 62a Physical IF unit 62b Ether physical unit 62c Ether MAC unit 63 Switch unit 63
63a Switch body 63b Buffer 63c Search table 63d Signaling control unit 64 Mixed IF unit 64a ATM / Ether mixed compatible MAC unit 64b ATM / Ether mixed compatible physical unit 64c Physical IF unit 71 Transmission medium 72 Transmission medium 73 Transmission medium

Claims (5)

In a communication device that accommodates ATM and Ethernet, and performs switching based on information described in an ATM cell or Ethernet packet,
A mixed transmission method for ATM cells and Ethernet packets, wherein the ATM cells are regarded as 53-byte fixed Ethernet packets and transmitted.   2. An ATM cell and an Ethernet according to claim 1, wherein the ATM cell and the Ethernet packet are separated and detected by detecting the data length and error from the data on the physical medium in which the ATM cell and the Ethernet packet are mixed. Packet transmission method. When a physical medium in which ATM cells and Ethernet packets are mixed is accommodated and both ATM cells and Ethernet packets are switched,
2. The method for mixed transmission of ATM cells and Ethernet packets according to claim 1, wherein switching is performed by referring to one search table having Ethernet and ATM cells as entries. When a physical medium in which ATM cells and Ethernet packets are mixed is accommodated and both ATM cells and Ethernet packets are switched,
2. The method of mixed transmission of ATM cells and Ethernet packets according to claim 1, wherein priority control is performed by priority classification common to ATM cells and Ethernet packets. In a communication device that accommodates ATM and Ethernet, and performs switching based on information described in an ATM cell or Ethernet packet,
A mixed transmission apparatus for ATM cells and Ethernet packets, characterized in that transmission means for performing transmission by regarding an ATM cell as a 53-byte fixed Ethernet packet is provided.

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