JP2007214410A - Stress managing method of self standing thin film and stencil-mask manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stress managing method of a self standing thin film for a stencil mask capable of maintaining a high pattern-position accuracy, and to provide a manufacturing method of the stencil mask. <P>SOLUTION: In the stress managing method of a self standing thin film for a stencil mask, an SOI substrate 30 is prepared comprising an Si single-crystal supporting substrate 11, an intermediate oxide-film layer 21, and an Si single-crystal thin-film layer 31. Further, impurities (P (phosphorus), B (boron), etc.) for adjusting the stresses of thin films are introduced into the Si single-crystal thin-film layer 31 of the SOI substrate 30. Moreover, the SOI substrate 30a is created having the Si single-crystal thin-film layer 31a having the introduced impurities for adjusting the stresses. Subsequently, a resistance measuring device 210 and a four-probe measurement head 211 of a stress measuring apparatus 200 are so used as to measure the resistance value of the Si single-crystal thin-film layer 31a having the introduced impurities for adjusting the stresses. Furthermore, the measured resistance values are taken into an operational processor 220 to indicate the stresses of the Si single-crystal thin-film layer 31a by converting the resistance values into the stresses. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a stress management method for a self-supporting thin film of a stencil mask used in an electron beam projection exposure method and a method for manufacturing a stencil mask.

  In recent years, with the miniaturization of semiconductor integrated circuits, research and development such as electron beam lithography has been actively performed as a manufacturing technique thereof. The stencil mask has a structure in which a transfer stencil pattern is formed on a free-standing thin film, and is used as a mask for these lithography techniques.

  Specifically, among the lithography techniques, as a method corresponding to miniaturization of semiconductors, a method called cell projection exposure method using electron beam or block exposure method, LEEPL (Low Energy Electron Projection Lithography), EPL (Electron Projection Lithography) ) The electron beam projection exposure method called the method has been developed. In addition to this, mask blanks having the same level of free-standing thin film are also used in the cell projection method, e-beam method, etc. due to the demand for miniaturization of the stencil pattern.

In the EPL method or the LEEPL method, as shown in FIG. 6, the circuit pattern is transferred to the sensitive substrate 330 on which the resist layer 331 is formed using a stencil mask 320.
In the stencil mask 320, a stencil (opening) 322 for forming a circuit pattern is provided in a self-supporting membrane 321 having a thickness that scatters or absorbs an electron beam, and the electron beam passes through the stencil (opening) 322. Electron beam projection exposure for transmitting the circuit pattern onto the sensitive substrate 330 is performed.

In the stencil mask 310 used in the EPL method or the LEEPL method, as shown in FIG. 5, in order to increase the rigidity of the free standing thin film 312, the free standing thin film 312 has a side of about 1 to 5 mm by a beam (strut) 311 or a bulk portion. A rectangular thin film is often used.
As the material of the self-supporting thin film 312, single crystal silicon is used as a material that is uniform and has few defects. Although the thickness of the free-standing thin film 312 may be 5 to 20 μm, it is often about 3 μm or less in consideration of deterioration of workability of the high aspect pattern accompanying the miniaturization of the stencil pattern 313.

An SOI substrate (silicon on insulator) is used for manufacturing a stencil mask having such a free-standing thin film. Since the SOI substrate uses single crystal silicon for the thin film layer, a thin film with few defects can be formed, and the intermediate oxide film layer is used as an etching stopper layer when etching the support substrate or the single crystal silicon thin film layer. be able to.
Furthermore, when the Smart-Cut method or the ELTRAN method is used, an SOI substrate with a thin film layer having a thickness variation of 5% or less can be obtained, so that highly accurate stencil pattern dimension control is possible.

Since the intermediate oxide film layer of the SOI substrate is formed by a thermal oxidation method, it has a compressive stress of about 300 MPa. Therefore, when a self-supporting thin film is formed, the stress of the self-supporting thin film becomes a compressive stress and bends depending on the thickness of the intermediate oxide film layer and the single crystal silicon thin film layer.
Therefore, it is necessary to perform stress control so as to give a strain so that the self-supporting thin film has a tensile stress and further so that the self-supporting thin film is stretched. For the stress control of this single crystal silicon thin film layer, a method of introducing impurities such as phosphorus and boron having an atomic diameter smaller than that of silicon is used. By controlling the phosphorus concentration in the single crystal silicon thin film layer, the stencil pattern A transfer mask blank and a transfer mask that can easily suppress warpage and pattern deformation have been proposed (see, for example, Patent Document 1).

However, excessive impurity concentration causes strong tensile stress and deteriorates the positional accuracy of the stencil pattern. Therefore, in order to suppress the stencil pattern in a free standing thin film of about 1 mm × 1 mm to a positional accuracy of 10 nm or less, it is about 0 to 10 MPa. Tensile stress is required. Here, the position accuracy is a variation 3σ of a difference between a design coordinate and an actual measurement coordinate in an arbitrary region, for example, a self-supporting thin film.
The pattern density in the membrane is uneven, and in the case of a line pattern, the internal stress is 10 MPa or less, and the positional deviation caused by the stress can be suppressed to about 10 nm.
Further, in the hole pattern, the positional deviation due to stress can be suppressed to about 4 nm.

  The relationship between the concentration of impurities introduced into the single crystal silicon thin film layer and the internal stress depends on the substrate conditions such as the type of impurity, the thickness of the single crystal silicon thin film layer and the intermediate oxide film layer, and the manufacturing conditions of the single crystal silicon thin film layer and the SOI substrate. Therefore, it is necessary to investigate the relationship between the impurity concentration and the internal stress for each substrate condition and determine the optimum impurity concentration corresponding to the necessary internal stress of the free-standing thin film.

  In addition, the internal stress of the single crystal silicon thin film layer can be measured by the bulge method for measuring the internal stress from the relationship between the pressure applied to the single crystal silicon thin film layer and the amount of deformation after the single crystal silicon thin film layer is formed. Measure the amount of displacement due to the stress of the stencil pattern position coordinates in the single crystal silicon thin film layer with a position coordinate measuring instrument with a measurement accuracy of about 5 nm. Further, there is a position coordinate measurement method for determining the internal stress by comparing the displacement amount with the analysis result by the finite element method.

  By the above method, a stencil mask can be manufactured by forming a single crystal silicon thin film layer having an arbitrary internal stress for each substrate condition.

In order to maintain the transfer accuracy of the stencil mask, it is necessary to manage the stress of the self-supporting thin film and to measure the thin film stress.
However, in the stress measurement by the bulge method, after adjusting the stress of the thin film, the SOI substrate is processed to form a self-supporting thin film, and the SOI substrate must be mechanically held to apply pressure. There is a problem in that damage such as cracking or cracking occurs.
Further, the resonance frequency measurement method also has a problem that the SOI substrate and the free-standing thin film are damaged because it is necessary to mechanically hold the SOI substrate after the free-standing thin film is formed and apply vibration to the free-standing thin film.

  In addition, there is a problem in the stress adjustment process, and when the impurity concentration is low and the tensile stress is low, there is a problem that it is difficult to additionally introduce impurities into the self-supporting thin film.

There is also a position coordinate measurement method, but it is necessary to form a stencil pattern for stress confirmation after forming a self-supporting thin film, which not only increases the number of processes, but also has a low impurity concentration and low tensile stress. There is a problem that additional installation cannot be performed.
JP 2002-261003 A

The present invention has been devised in view of the above problems, and an object of the present invention is to provide a stress management method for a stencil mask free-standing thin film and a method for manufacturing a stencil mask that can maintain high-precision pattern position accuracy.

  In order to achieve the above object in the present invention, first, in claim 1, stress is applied to the Si single crystal thin film layer of the SOI substrate having the Si single crystal support substrate, the intermediate oxide film layer, and the Si single crystal thin film layer. This is a self-supporting thin film stress management method characterized by managing the stress of the self-supporting thin film by measuring the resistance value of the Si single crystal thin film layer after introducing the adjusting impurities.

According to a second aspect of the present invention, there is provided a method for manufacturing a stencil mask, comprising at least the following steps.
(A) A step of preparing an SOI substrate having a Si single crystal supporting substrate, an intermediate oxide film layer, and a Si single crystal thin film layer.
(B) A step of introducing impurities for stress adjustment into the Si single crystal thin film layer.
(C) A step of measuring the resistance of the Si single crystal thin film layer into which the stress adjusting impurity is implanted, and manufacturing an SOI substrate having the stress adjusted Si single crystal thin film layer.
(D) A step of patterning the Si single crystal thin film layer of the SOI substrate whose stress is adjusted.
(E) A step of patterning the Si single crystal support substrate of the SOI substrate to form a support frame and a beam.

According to the stress management method of the self-supporting thin film of the present invention, since the internal stress of the self-supporting thin film can be measured by measuring the resistance of the Si single crystal thin film layer, the yield is obtained without causing damage such as contamination or cracking of the self-supporting thin film. A good stencil mask can be provided.
Further, since no mechanical holding is required, there is no damage to the SOI substrate.
In addition, since it is not necessary to make a self-supporting thin film for dummy measurement and the internal stress of the self-supporting thin film can be evaluated immediately before processing, the number of substrates to be input can be set to the minimum necessary, which can contribute to the reduction of material costs.

Hereinafter, embodiments of the present invention will be described.
According to the first aspect of the present invention, an impurity for stress adjustment is introduced into the Si single crystal thin film layer of the SOI substrate having the Si single crystal support substrate, the intermediate oxide film layer, and the Si single crystal thin film layer, and then the Si single crystal thin film is introduced. This is a stress management method for a self-supporting thin film in which the stress of the self-supporting thin film is managed by measuring the resistance value of the layer.
FIG. 1 shows a measuring device that measures the resistance value of a Si single crystal thin film layer 31a into which a stress adjusting impurity is introduced, converts the resistance value into stress by an arithmetic device 220, and measures the stress of the Si single crystal thin film layer 31a. It is a schematic block diagram which shows an example.

A method for managing the stress of the self-supporting thin film using the stress measuring apparatus 200 shown in FIG. 1 will be described.
First, an SOI substrate 30 including a Si single crystal support substrate 11, an intermediate oxide film layer 21, and a Si single crystal thin film layer 31 is prepared (see FIG. 2A).

Next, an impurity for thin film stress adjustment is introduced into the Si single crystal thin film layer 31 of the SOI substrate 30 to produce an SOI substrate 30a having the Si single crystal thin film layer 31a into which the stress adjustment impurity is introduced (FIG. 2B). )reference).
As impurities, P (phosphorus), B (boron), etc. can be used, and they can be introduced using a thermal diffusion method or ion implantation method, but sufficient annealing is performed to suppress the impurity concentration distribution in the film thickness direction. It is desirable.

Next, the resistance value of the Si single crystal thin film layer 31a into which the stress adjusting impurity is introduced is measured using the resistance measuring device 210 and the four-end needle measuring head 211 of the stress measuring apparatus 200 shown in FIG. In consideration of the possibility of damage such as scratches due to contact with the four-end needle measuring head 211, it is desirable to extract a portion that does not become a self-supporting thin film and measure a plurality of locations in the SOI substrate.
The resistance value measured by the resistance measuring device 210 is taken into the arithmetic processing unit 220, converted into stress, and the stress of the Si single crystal thin film layer 31a is displayed.

Here, the relationship between the sheet resistance of the Si single crystal thin film layer 31a and the internal stress is experimentally investigated in advance by using a bulge method, a resonance frequency measurement method, or the like for Si single crystal thin film layers having different impurity concentrations. It is registered in the processing device 220 in advance.
Therefore, the internal stress can be easily obtained by the arithmetic processing unit 220 by measuring the sheet resistance of the Si single crystal thin film layer 31a with a four-end needle resistance measuring machine.

For example, P (phosphorus) is used as an impurity in an SOI substrate 30 composed of a 725 μm thick Si single crystal support substrate 11, a 1.0 μm thick intermediate oxide film layer 21, and a 2.0 μm thick Si single crystal thin film layer 31. An example of the relationship between the sheet resistance and the internal stress of the introduced Si single crystal thin film layer 31a is shown in FIG.
From FIG. 3, in order to obtain a free-standing thin film of 15 MPa or less, the sheet resistance value needs to be in the range of about 4-7 Ω / □.

Here, as for the sheet resistance and internal stress of the Si single crystal thin film layer 31a into which the impurity concentration is introduced, desired values are not always obtained in one operation.
If the sheet resistance is 7Ω / □ or more, it is determined that the impurity concentration is insufficient and the impurity concentration needs to be added, and the impurity introduction step is performed again.
When the sheet resistance is 4 Ω / □ or less, it is determined that the internal stress is higher than 15 MPa because the impurity concentration is too high, and it is used as a high-stress free-standing thin film for a mask for other purposes.

Further, B (boron) is added as an impurity to the SOI substrate 30 composed of the 725 μm-thick Si single crystal support substrate 11, the 1.0 μm-thick intermediate oxide film layer 21, and the 2.0 μm-thick Si single crystal thin film layer 31. An example of the relationship between the sheet resistance and the internal stress of the introduced Si single crystal thin film layer 31a is shown in FIG.
From FIG. 4, in order to obtain a free-standing thin film of 0 to 15 MPa, the sheet resistance value needs to be in the range of about 30 to 60 Ω / □.
The mask pattern produced here is a hole system, and the positional deviation due to stress must be suppressed to 10 nm or less. Since the internal stress of the membrane is expected to be about 6 nm at 15 MPa, the misalignment caused by the stress can be made 10 nm or less by using a self-supporting thin film of 15 MPa or less.

  The setting example of the appropriate internal stress range of 0 to 15 MPa is merely an example, and the required internal stress of the free standing thin film depends on the specifications of the mask to be manufactured. Depends on position accuracy specifications.

Hereinafter, a method for manufacturing a stencil mask using the SOI substrate 30a having the stress-adjusted i single crystal thin film layer 31a will be described.
First, a resist layer is formed on the stress-adjusted Si single crystal thin film layer 31a, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 41 (see FIG. 2C).

Next, by dry etching using SF ₆ gas or the like, the Si single crystal thin film layer 31a is etched using the resist pattern 41 as a mask, and further ashing treatment is performed using oxygen plasma or the like, so that the Si single crystal thin film layer 31a The stencil 32 is formed at a predetermined position (see FIG. 2D).

  Next, a resist layer having a thickness of several tens of μm is formed on the Si single crystal support substrate 11, and a series of patterning processes such as pattern exposure and development are performed to form a window resist pattern 42 (FIG. 2E). reference).

Next, the Si single crystal support substrate 11 is etched by dry etching using the window resist pattern 42 as a mask.
Here, the etching process of the Si single crystal support substrate 11 is performed by performing etching with a high aspect ratio (etching depth / opening dimension) when a process combining etching with a fluorine-based gas and a protective film deposition step with a fluorocarbon-based gas is used. Can do.

  Next, after the window resist pattern 42 is removed by an ashing process using oxygen plasma or the like, a part of the intermediate oxide film layer 21 is etched with an HF solution, and then washed with ammonia overwater or buffered hydrofluoric acid. The beam 11a is produced, and the stencil mask 100 having the self-supporting thin film 31a whose stress is adjusted can be obtained. (See FIG. 2 (e)).

In addition, when the distance between adjacent free-standing thin films such as an EPL mask is short, it is necessary to etch the Si single crystal support substrate 11 by dry etching. However, the distance between the free-standing thin films is sufficiently large as in a cell projection mask. If permitted, a wet etch such as KOH may be used.
In the case of wet etching, after forming a pattern mask for a thin film window with a nitride film or the like, 30 wt% KOH is heated to 80 ° C., and a part of the Si single crystal support substrate 11 is removed to the intermediate oxide film layer by wet etching. After that, a part of the intermediate oxide film layer is further etched with a 5 wt% buffered HF solution, and washed with ammonia overwater or buffered hydrofluoric acid to obtain a stencil mask.

  First, an SOI substrate 30 having a diameter of 200 mm comprising a 725 μm thick Si single crystal support substrate 11, a 1 μm thick intermediate oxide film layer 21 and a 2.0 μm thick Si single crystal thin film layer 31 was prepared (FIG. 2A). reference).

  Next, a thin-film stress adjusting impurity made of P (phosphorus) is introduced into the Si single crystal thin film layer 31 of the SOI substrate 30 by an ion implantation method, and the Si single crystal thin film layer 31a into which the stress adjusting impurity is introduced is provided. An SOI substrate 30a was manufactured (see FIG. 2B).

  Next, the resistance value of the Si single crystal thin film layer 31a into which the stress adjusting impurity was introduced was measured using the resistance measuring device 210 and the four-end needle measuring head 211 of the stress measuring apparatus 200 shown in FIG. The resistance value is 4.2Ω / □, and the measured resistance value is taken into the arithmetic processing unit 220 and converted into stress. The expected stress of the Si single crystal thin film layer 31a after the formation of the membrane is 11 MPa. It was.

Next, an electron beam sensitive resist (PMMA (polymethylmethacrylate based positive resist)) is applied on the stress-adjusted Si single crystal thin film layer 31a to form a 500 nm thick resist layer, and 120 μC / cm ^The resist pattern 41 was formed by performing electron beam exposure with an electron beam dose of ² and performing a series of patterning processes such as development (see FIG. 2C).

Next, a resist pattern 41 is formed by dry etching using a fluorocarbon-based gas.
As a mask, the Si single crystal thin film layer 31a was etched and further subjected to ashing with oxygen plasma to form a stencil 32 at a predetermined position of the Si single crystal thin film layer 31a (see FIG. 2D).

  Next, a resist layer having a thickness of 50 μm was formed on the Si single crystal support substrate 11, and a series of patterning processes such as pattern exposure and development were performed to form a window resist pattern 42 (see FIG. 2E). .

Next, using the window resist pattern 42 as a mask, the Si single crystal support substrate 11 was etched by dry etching using a fluorocarbon-based gas.
Further, a part of the Si single crystal support substrate 11 was removed up to the intermediate oxide film layer 21 with an etching solution in which 30 wt% KOH was heated to 80 ° C.

  Further, a part of the intermediate oxide film layer 21 is etched with a 5 wt% buffered HF solution, washed with ammonia-hydrogen peroxide or buffered hydrofluoric acid, and used for the EPL method having the self-supporting thin film 31a whose stress is adjusted to 11 MPa. A beamed stencil mask 100a was obtained. (See FIG. 2 (e)).

  First, an SOI substrate 30 having a diameter of 200 mm comprising a 725 μm thick Si single crystal support substrate 11, a 0.2 μm thick intermediate oxide film layer 21, and a 2.0 μm thick Si single crystal thin film layer 31 was prepared (FIG. 2 ( a)).

  Next, a thin film stress adjusting impurity made of B (boron) is introduced into the Si single crystal thin film layer 31 of the SOI substrate 30 by an ion implantation method, and the Si single crystal thin film layer 31a into which the stress adjusting impurity is introduced is provided. An SOI substrate 30a was manufactured (see FIG. 2B).

  Next, the resistance value of the Si single crystal thin film layer 31a into which the stress adjusting impurity was introduced was measured using the resistance measuring device 210 and the four-end needle measuring head 211 of the stress measuring apparatus 200 shown in FIG. The resistance value was 64Ω / □, and the measured resistance value was taken into the arithmetic processing unit 220 and converted into stress. The expected stress of the Si single crystal thin film layer 31a was about 8 MPa.

Next, an electron beam sensitive resist (PMMA (polymethylmethacrylate based positive resist)) is applied on the stress-adjusted Si single crystal thin film layer 31a to form a 500 nm thick resist layer, and 120 μC / cm ^The resist pattern 41 was formed by performing electron beam exposure with an electron beam dose of ² and performing a series of patterning processes such as development (see FIG. 2C).

  Next, by dry etching using a fluorocarbon-based gas, the Si single crystal thin film layer 31a is etched using the resist pattern 41 as a mask, and further, an ashing process using oxygen plasma is performed, so that a predetermined Si single crystal thin film layer 31a is formed. A stencil 32 was formed at the position (see FIG. 2D).

  Next, a resist layer having a thickness of 50 μm was formed on the Si single crystal support substrate 11, and a series of patterning processes such as pattern exposure and development were performed to form a window resist pattern 42 (see FIG. 2E). .

Next, using the window resist pattern 42 as a mask, the Si single crystal support substrate 11 was etched by dry etching using a fluorocarbon-based gas.
Further, a part of the Si single crystal support substrate 11 was removed up to the intermediate oxide film layer 21 with an etching solution in which 30 wt% KOH was heated to 80 ° C.

  Further, an EPL method having a self-supporting thin film 31a whose stress is adjusted to 9.1 MPa by etching a part of the intermediate oxide film layer 21 with a 5 wt% buffered HF solution, cleaning with ammonia overwater or buffered hydrofluoric acid. The stencil mask with beam 100b used for the above was obtained. (See FIG. 2 (e)).

It is a schematic block diagram which shows an example of the stress measuring apparatus of a self-supporting thin film. (A)-(e) is typical structure sectional drawing which shows one Example of the manufacturing method of the stencil mask of this invention to process order. It is explanatory drawing which shows the relationship between the sheet resistance and stress of the Si single crystal thin film layer which introduce | transduced P (phosphorus) as an impurity for stress adjustment. It is explanatory drawing which shows the relationship between the sheet resistance and stress of the Si single crystal thin film layer which introduce | transduced B (boron) as an impurity for stress adjustment. (A) is a schematic plan view which shows an example of the stencil transfer mask used by EPL method or LEEPL method. (B) is a schematic cross-sectional view taken along line A-A ′ of (a). (C) is the schematic structure sectional drawing which expanded the B section of (b). It is explanatory drawing which shows the state which is pattern-transferring to the sensitive board | substrate using a transfer mask.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Si single crystal support substrate 11a ... Beam 21 ... Intermediate oxide film layer 30, 30a ... SOI substrate 31 ... Si single crystal thin film layer 31a ... Si single crystal thin film layer in which impurities for stress adjustment are introduced (Self-supporting thin film)
32 ... Stencil 41 ... Resist pattern 42 ... Window resist pattern 100, 100a, 100b ... Stencil mask 200 ... Stress measuring device 210 ... Resistance measuring device 211 ... 4 Probe measuring head 220 ... Arithmetic processing apparatus

Claims (2)

  After introducing an impurity for stress adjustment into the Si single crystal thin film layer of the SOI substrate having the Si single crystal support substrate, the intermediate oxide film layer, and the Si single crystal thin film layer, the resistance value of the Si single crystal thin film layer is measured. A method for managing stress in a free-standing thin film, characterized by managing stress in the free-standing thin film. The manufacturing method of the stencil mask characterized by comprising the following processes at least.
(A) A step of preparing an SOI substrate having a Si single crystal supporting substrate, an intermediate oxide film layer, and a Si single crystal thin film layer.
(B) A step of introducing impurities for stress adjustment into the Si single crystal thin film layer.
(C) A step of measuring the resistance of the Si single crystal thin film layer into which the stress adjusting impurity is implanted, and manufacturing an SOI substrate having the stress adjusted Si single crystal thin film layer.
(D) A step of patterning the Si single crystal thin film layer of the SOI substrate whose stress is adjusted.
(E) A step of patterning the Si single crystal support substrate of the SOI substrate to form a support frame and a beam.

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