JP2007214397A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent disconnection caused by the flow of an excessive electric current in specified wiring by equalizing the current flowing in each kind of wiring concerning a semiconductor integrated circuit for feeding power with the plurality of layers of wiring in order to increase a current capacity. <P>SOLUTION: The source diffusion layer 6b of a MOSFET 6 is connected to second layer metallic power feeding wiring 2c through the use of two mutually independent current routes. One current route is the route to the second layer metallic power feeding wiring 2c via a contact plug 4a, a first layer metallic layer 1c, an inter-metallic layer plug 5a, a second layer metallic wiring 2a, and a second layer metallic draw wiring 2b. The other current route is the route to the second layer metallic power feeding wiring 2c via a contact plug 4b, a first metallic wiring 1a, a first metallic draw wiring 1b, and an inter-metallic layer plug 5b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a metal wiring structure for supplying power to a circuit in the semiconductor integrated circuit.

  In a silicon integrated circuit, the current flowing through a transistor increases in accordance with the demand for higher operation speed as the transistor becomes finer. Thus, the metal wiring connecting the transistors becomes thinner with the miniaturization of the transistors, but since the current flowing through the transistors increases, the amount of current flowing per unit cross-sectional area of the wiring tends to increase as the degree of integration increases. is there. Due to such an increase in the current of the wiring, there arises a problem that the wiring is disconnected due to an excessive current flowing through the wiring. For example, as shown in FIG. 12, the source diffusion layer 6b of the MOSFET 6 having the gate electrode 6a, the source diffusion layer 6b, and the drain diffusion layer 6c includes a contact plug, a first layer metal wiring 1a, and a first layer metal lead-out wiring 1b. The first layer metal lead-out line 1b is narrower than the first layer metal feed line 1e, and there is a risk of disconnection at this portion.

In order to solve this problem, it is effective to reduce the current density by increasing the cross-sectional area of the wiring. As a method for this, as shown in FIG. 13, the source diffusion layer 6b is made to have a first-layer metal power supply wiring through a wider first-layer metal wiring 1a and first-layer metal lead-out wiring 1b than in the case shown in FIG. There is a method of drawing out to 1e. However, this method has a problem that the degree of integration is lowered instead of preventing disconnection. For example, as shown in FIG. 14, in the case of laying out a large number of transistors side by side, the distance between the transistors must be increased by the width of the lead-out wiring 1b, and the degree of integration decreases. In this case, since the width of the power supply wiring 1e does not affect the distance between the transistors, it can be made wider than the lead-out wiring 1b, and the risk of disconnection is small.
As another solution, as shown in FIG. 15, a method using two or more metal wiring layers to substantially prevent the wiring from being disconnected by increasing the thickness of the wiring has been proposed. ing. In FIG. 15, the source diffusion layer 6b is connected to the second-layer power supply wiring 2c through the contact plug 4a, the first-layer metal wiring 1a, the first-layer metal lead-out wiring 1b, and the metal interlayer plug 5b. 4a, the metal interlayer plug 5a, the second layer metal wiring 2a, and the second layer metal lead-out wiring 2b are connected to the second layer power supply wiring 2c. Such a method of supplying power by using two layers of metal wiring is disclosed in Patent Documents 1 and 2, for example.
Japanese Patent Laid-Open No. 01-243543 JP 2004-096118 A

The method of increasing the width of the wiring has a problem that the degree of integration decreases. In addition, in the structure in which the wiring is multi-layered, it is difficult to flow a current uniformly to the wiring of each layer, and there is a problem that the current is concentrated only in a part of the metal wiring layers and disconnection occurs. For example, in the circuit of FIG. 15, the current path passing through the first layer metal wiring 1a has a lower resistance value than the current path passing through the second layer metal wiring 2a, and thus the current flowing through the first layer metal lead wiring 1b. Becomes larger than the current flowing through the second-layer metal lead-out wiring 2b, and the first-layer metal lead-out wiring 1b is easily disconnected.
An object of the present invention is to solve the above-described problems of the prior art, and an object of the present invention is to prevent disconnection of power supply wiring in a miniaturized and highly densified semiconductor integrated circuit. That is.

  In order to achieve the above object, according to the present invention, a semiconductor region provided on a semiconductor substrate or an alloy layer provided on the semiconductor region and a metal power supply wiring or a metal ground wiring are electrically connected. In the semiconductor integrated circuit, there is provided a semiconductor integrated circuit, wherein the semiconductor region or the alloy layer and the metal power supply wiring or the metal ground wiring are connected by at least two mutually independent current paths. .

  According to the present invention, resistance values of a plurality of current paths can be equalized, so that a current can be made to uniformly flow through the wirings of the respective current paths, and disconnection of the wirings can be prevented. In addition, disconnection can be prevented without increasing the wiring width around the element such as a transistor, so that the degree of integration of the semiconductor integrated circuit can be improved.

  1A and 1B are diagrams for explaining an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line AA. In the present embodiment, the source diffusion layer 6b of the MOSFET 6 having the gate electrode 6a, the source diffusion layer 6b, and the drain diffusion layer 6c and the second-layer metal power supply wiring 2c are connected by two independent current paths. Yes. One current path is a path from the contact plug 4a, the first layer metal layer 1c, the metal interlayer plug 5a, the second layer metal wiring 2a, and the second layer metal lead-out wiring 2b to the second layer metal feed wiring 2c. The other current path is a path that reaches the second layer metal power supply wiring 2c through the contact plug 4b, the first layer metal wiring 1a, the first layer metal lead-out wiring 1b, and the metal interlayer plug 5b. Here, the second layer metal power supply wiring 2c is a wide wiring, and in the drawing, the metal interlayer plug 5b connecting the first layer metal lead-out wiring 1b and the second layer metal power supply wiring 2c is Although only one is shown, it is actually connected by many conductive plugs, and both are connected to a low resistance.

  The current path connecting the source diffusion layer 6b and the second-layer metal power supply wiring 2c has a resistance value between the source diffusion layer 6b and the contact plugs 4a and 4b because the high resistance portion of both paths is the source diffusion layer 6b. The difference is small and the current flowing through both paths is almost the same. That is, since the current flowing through the first layer metal lead-out wiring 1b and the second layer metal lead-out wiring 2b can be made uniform, disconnection of the wiring can be prevented.

  2A and 2B are diagrams schematically showing a conventional wiring structure, in which FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along the line AA. In FIG. 2, the same reference numerals are given to the same parts as those in FIG. 1, and therefore, the duplicated explanation is omitted. In the conventional example shown in FIG. 2, the current path via the contact plug 4a is shown. Is divided into two parts where the contact plug 4a contacts the first layer metal wiring 1a, and branches into two parts where the metal interlayer plug 5a contacts the second layer metal wiring 2a. The wiring 1a is branched into two at locations where the wiring 1a contacts the metal interlayer plug 5b. Further, the current path passing through the contact plug 4b is branched into two at the place where the contact plug 4b contacts the first layer metal wiring 1a. In general, since the resistance of the metal interlayer plug is higher than that of the metal wiring, the current flowing from the contact plug 4a to the metal interlayer plug 5a in FIG. 1 is increased from the contact plug 4a to the first layer metal wiring 1a side. Flowing. This also occurs when the current branches to the metal interlayer plug 5c and the first layer metal wiring 1a. For this reason, more current flows in the path of the first layer metal lead-out wiring 1b than in the path of the second layer metal lead-out wiring 2b, and the currents in both paths become uneven.

This will be made clearer by comparing the currents of the paths in the structures of FIGS. Here, FIGS. 1 and 2 are approximated by circuits as shown in FIGS. 3 and 4, respectively. 3 and 4,
Rsi1, Rsi2: Source diffusion layer resistance
Rcon1, Rcon2: Contact plug resistance
Rm11, Rm12: Resistance of first layer metal wiring (including lead wiring)
Rm21, Rm22: Resistance of second layer metal wiring (including lead wiring)
Rvia1, Rvia2, Rvia3: Resistance of metal interlayer plug. Here, the current flowing between the terminal IN of the diffusion layer and the terminal OUT of the second layer metal power supply wiring is calculated by a circuit simulator. At this time
Rsi1 = Rsi2 = 50Ω
Rcon1 = Rcon2 = 1Ω
Rm11 = Rm12 = 0.2Ω
Rm21 = Rm22 = 0.2Ω
Rvia1 = Rvia2 = 1Ω
Rvia3 = 0.01Ω
Assume that Table 1 shows currents Im12 and Im22 flowing through the resistors Rm12 (first-layer lead-out wiring) and Rm22 (first-layer lead-out wiring) when a voltage of 1 V is applied between IN and OUT, respectively.

From Table 1, it can be seen that in the conventional system, a current nearly three times as large as that of the Rm22 side, that is, the second layer lead-out line 2b flows in the Rm12 side, that is, the first layer lead-out line 1b. Therefore, in the conventional method, there is a high risk of disconnection in the first layer lead wiring 1b. On the other hand, in the present invention, the total current flowing through Rm12 and Rm22 is about 0.7% smaller than the conventional method, but the current flowing through both is almost equal, so the risk of disconnection of one wiring is lower than the conventional method. .

FIG. 5 is a graph showing a change in the ratio of Im12 and Im22 when the resistances Rsi1 and Rsi2 of the source diffusion layer are changed. Here, Rsi1 = Rsi2 = Rsi. As shown in the figure, it can be seen that at any resistance value of Rsi, Im12 / Im22 of the present invention is closer to 1 than Im12 / Im22 of the conventional method, and current flows evenly. In particular, when Rsi1 and Rsi2 are 10Ω or more and the resistance of the source diffusion layer is higher than the resistance of the metal layer, contact plug, and metal interlayer plug portion, Im12 / Im22 of the present invention is almost 1, and it can be seen that a great effect is obtained. .
Although the wiring between the semiconductor region such as the diffusion layer and the power supply wiring has been described above, the present invention can be similarly applied to the wiring connecting the semiconductor region and the ground wiring.

6A and 6B are diagrams showing Embodiment 1 of the present invention, in which FIG. 6A is a plan view and FIG. 6B is a cross-sectional view taken along the line AA. In FIG. 6, the same reference numerals are given to the same parts as those in FIG. In this embodiment, a Ti silicide layer 6d is formed on the source diffusion layer 6b made of silicon. In this embodiment, the source diffusion layer 6b is connected to the second layer metal power supply wiring 2c via the Ti silicide layer 6d via the two lines of wiring. Even in this case, the resistance of the two lines of wiring The difference between the values can be reduced, and a current that is equalized can be supplied to both.
In this embodiment, a Ti silicide layer is formed on a diffusion layer made of silicon, but the diffusion layer may be germanium, a mixed crystal of silicon and germanium, or the like in addition to silicon. The metal alloy may be an alloy of silicon, germanium, a semiconductor such as a mixed crystal of silicon and germanium, and titanium, cobalt, tungsten, nickel, or the like.

  FIGS. 7A and 7B are a plan view and a cross-sectional view showing a second embodiment of the present invention. In the present embodiment, two systems of current paths are formed using the first layer metal wiring. The path A reaches the first layer power supply wiring 1e from the diffusion layer 7 via the contact plug 4a and the first layer metal wiring 1a, and the path B passes from the diffusion layer 7 to the contact plug 4b and the first layer metal. The first layer power supply wiring 1e is reached via the wiring 1d. The two paths are independent from each other and are not connected to portions other than the first layer power supply wiring 1e. In this circuit, the resistances of both paths are substantially determined by the resistance value in the diffusion layer 7 and the resistance values of the contact plugs 4a and 4b, and can be approximately the same, and the currents flowing in both paths can be made approximately equal. it can. Therefore, the risk of disconnection of any one of the wires can be reduced.

  8A and 8B are a plan view and a cross-sectional view showing a third embodiment of the present invention. In this embodiment, the diffusion layer 7 is connected to the second layer power supply wiring 2c by two paths A and B having the first layer to the second layer wiring, but the both paths do not have an overlapping portion. The path A reaches the second layer power supply wiring 2c from the diffusion layer 7 via the contact plug 4a, the first layer metal layer 1c, the metal interlayer plug 5a, and the second layer metal wiring 2a. The layer 7 reaches the second layer power supply wiring 2c via the contact plug 4b, the first layer metal wiring 1a, the metal interlayer plug 5b, and the second layer metal wiring 2d and the metal interlayer plug 5b. The two paths are independent from each other and are not connected at portions other than the second layer power supply wiring 2c. In this circuit, the resistance of both paths is almost determined by the resistance value of the diffusion layer 7 and the resistance values of the contact plugs 4a and 4b and the metal interlayer plugs 5a and 5b, and can be almost the same, and flows through both paths. The currents can be approximately equal.

  9A and 9B are diagrams showing Embodiment 4 of the present invention, in which FIG. 9A is a plan view and FIG. 9B is a cross-sectional view taken along the line AA. In this embodiment, the collector diffusion layer 8c of the bipolar transistor 8 having the emitter diffusion layer 8a, the base diffusion layer 8b, and the collector diffusion layer 8c is connected to the second-layer metal power supply wiring 2c through two current paths. However, the two current paths are formed to overlap. The path A is routed from the collector diffusion layer 8c through the contact plug 4a, the first layer metal layer 1c, the metal interlayer plug 5a, the second layer metal wiring 2a, and the second layer metal lead-out wiring 2b. The path B reaches the second layer power supply wiring 2c from the collector diffusion layer 8c through the contact plug 4b, the first layer metal wiring 1a, the first layer metal lead-out wiring 1b, and the metal interlayer plug 5b. Yes. The two paths are independent from each other and are not connected at portions other than the second layer power supply wiring 2c. In this circuit, the resistance of both paths is almost determined by the resistance value in the collector diffusion layer 8c and the resistance values of the contact plugs 4a and 4b and the metal interlayer plugs 5a and 5b, and can be approximately the same. The flowing currents can be made approximately equal.

  10A and 10B are diagrams showing Embodiment 5 of the present invention, in which FIG. 10A is a plan view and FIG. 10B is a cross-sectional view taken along the line AA. In the present embodiment, the source diffusion layer 6b of the MOSFET 6 is connected to the third layer metal power supply wiring 3c via three current paths, but the three current paths are formed so as to overlap. The path A leads from the source diffusion layer 6b to the contact plug 4a, the first layer metal layer 1f, the metal interlayer plug 5a, the second layer metal layer 2e, the metal interlayer plug 5d, the third layer metal wiring 3a and the third layer metal. The third layer power supply wiring 3c is reached via the wiring 3b, and the path B1 extends from the source diffusion layer 6b to the contact plug 4b, the first layer metal layer 1c, the metal interlayer plug 5b, the second layer metal wiring 2a, The second layer metal lead wiring 2b and the metal interlayer plug 5e are reached to the third layer power supply wiring 3c, and the path B2 is connected from the source diffusion layer 6b to the contact plug 4c, the first layer metal wiring 1a, and the first layer metal. It reaches the third layer power supply wiring 3c via the lead wiring 1b, the metal interlayer plug 5c, the second layer metal lead wiring 2b, and the metal interlayer plug 5e. Here, the route A is independent of the routes B1 and B2, and the route B1 and the route B2 reach the second layer lead-out wiring 2b and are integrated as the route B. That is, the path A is not connected to the paths B1 and B2 at portions other than the third layer power supply wiring 3c. Further, the path B1 and the path B2 are independent until reaching the contact portion with the second layer lead-out wiring 2b of the metal interlayer plug 5e immediately below the third layer power supply wiring 3c. In this circuit, the resistance of each path is substantially determined by the resistance value in the source diffusion layer 6b and the resistance value of the contact plug and the metal interlayer plug, and can be made substantially the same. Can be equal.

  11A and 11B are views showing Embodiment 6 of the present invention, in which FIG. 11A is a plan view and FIG. 11B is a cross-sectional view taken along the line AA. In the present embodiment, the source diffusion layer 6b of the MOSFET 6 is connected to the second-layer metal power supply wiring 2c via four current paths, but the four current paths are two on the source diffusion layer. It is integrated into one route. The four current paths are formed so as to overlap each other. The paths A1 and A2 reach the second layer metal wiring 2a from the source diffusion layer 6b via the contact plugs 4a and 4b, the first layer metal layer 1c, and the metal interlayer plugs 5a and 5b, and are integrated into the path A. The second layer power supply wiring 2c is reached via the second layer metal wiring 2a and the second layer metal lead-out wiring 2b, and the paths B1 and B2 are routed from the source diffusion layer 6b to the first via the contact plugs 4c and 4d. It reaches the layer metal wiring 1a and is integrated into the path B, and reaches the second layer power supply wiring 2c via the first layer metal wiring 1a, the first layer metal lead-out wiring 1b, and the metal interlayer plug 5c. Here, the routes A1 and A2 are independent of the routes B1 and B2, and the routes B1 and B2 are independent of the routes A1 and A2. In this circuit, the resistance of each path is substantially determined by the resistance value in the source diffusion layer 6b and the resistance value of the contact plug and the metal interlayer plug, and can be made substantially the same. Can be equal. Therefore, since the current densities of the path A and the path B can be made similar, the risk of disconnection of one of the wirings is reduced.

  Although preferred embodiments and examples of the present invention have been described above, the present invention is not limited to these embodiments and examples, and appropriate modifications can be made without departing from the scope of the present invention. Is. For example, in the embodiments, the power supply to the source diffusion layer and the collector diffusion layer has been described. However, the present invention is not limited to these regions, and the power supply to other regions may be used. Moreover, said Example can be combined suitably. For example, the alloy layers can be formed on the diffusion layers of Examples 2 to 6 by combining Examples 2 to 6 and Example 1.

The top view and sectional drawing which show one embodiment of this invention. The top view and sectional drawing of a prior art example. The equivalent circuit schematic of one embodiment of this invention. The equivalent circuit diagram of a prior art example. The graph showing the relationship between the effect of this invention and diffusion layer resistance. The top view and sectional drawing of Example 1 of this invention. The top view and sectional drawing of Example 2 of this invention. The top view and sectional drawing of Example 3 of this invention. The top view and sectional drawing of Example 4 of this invention. The top view and sectional drawing of Example 5 of this invention. The top view and sectional drawing of Example 6 of this invention. The top view of a prior art example. The top view at the time of extending the wiring width in a prior art example. The top view at the time of extending a wiring width and arranging the transistors in parallel in the conventional example. Sectional drawing at the time of making wiring into a multilayer in a prior art example.

Explanation of symbols

1a, 1d First layer metal wiring 1b First layer metal lead wiring 1c, 1f First layer metal layer 1e First layer metal feed wiring 2a, 2d Second layer metal wiring 2b Second layer metal lead wiring 2c Second layer metal Power supply wiring 2e Second layer metal layer 3a Third layer metal wiring 3b Third layer metal lead-out wiring 3c Third layer metal power supply wiring 4a, 4b, 4c, 4d Contact plugs 5a, 5b, 5c, 5d, 5e Metal interlayer plug 6 MOSFET
6a gate electrode 6b source diffusion layer 6c drain diffusion layer 6d Ti silicide layer 7 diffusion layer 8 bipolar transistor 8a emitter diffusion layer 8b base diffusion layer 8c collector diffusion layer

Claims (8)

In a semiconductor integrated circuit in which a semiconductor region provided on a semiconductor substrate or an alloy layer provided on the semiconductor region and a metal power supply wiring or a metal ground wiring are electrically connected, the semiconductor region or the alloy layer and the A semiconductor integrated circuit, wherein the metal power supply wiring or the metal ground wiring is connected by at least two mutually independent current paths. Each current path connecting between the semiconductor region or the alloy layer and the metal power supply wiring or the metal ground wiring uses one layer of metal wiring, and does not use metal wiring of other layers. The semiconductor integrated circuit according to claim 1. 3. The semiconductor integrated circuit according to claim 2, wherein the current paths of the respective layers are formed so as to overlap each other. Between the semiconductor region or the alloy layer and the metal power supply wiring of the nth (n is an integer of 2 or more) layer or the metal ground wiring of the nth layer via the metal wiring of the nth layer. The current path via the n-th layer metal wiring is connected to the contact plug from the semiconductor region or the alloy layer and (n-1) metal interlayer plugs and n-th layer formed immediately above the contact plug. A current path passing through the metal wiring of the k-th [k is an integer of 1 to (n−1)] layer is formed from the semiconductor region or the alloy layer on the contact plug and directly above the metal wiring. The (k-1) metal interlayer plugs, the k-th layer metal wiring and the (n−k) metal interlayer plugs directly below the metal power supply wiring or the metal ground wiring, Metal 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit reaches a wiring line. 2. The metal wiring of the same layer is used for each current path connecting between the semiconductor region or the alloy layer and the metal power supply wiring or the metal ground wiring. Semiconductor integrated circuit. Between the metal wiring and the semiconductor region or the alloy layer, a plurality of contact plugs or a plurality of contact plugs and one or a plurality of metal interlayer plugs formed on each of the plurality of contact plugs The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected via The semiconductor region is formed of silicon, germanium or a mixed crystal of silicon and germanium, and the alloy layer is formed of silicon, germanium or a mixed crystal of silicon and germanium and an alloy of titanium, cobalt, tungsten or nickel. The semiconductor integrated circuit according to claim 1, wherein: 8. The semiconductor integrated circuit according to claim 1, wherein the semiconductor region is one of a source region or a drain region of a MOSFET, or a collector region or an emitter region of a bipolar transistor.

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